FM24CL04B

FM24CL04B RAMTRON | Alldatasheet

Document overview

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• PDF pages: 12

Technical content

Features

4K bit Ferroelectric Nonvolatile RAM

• Organized as 512 x 8 bits
• High Endurance 1014 Read/Writes
• 38 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface
• Up to 1 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz Low Power Operation
• 2.7V to 3.65V operation
• 100 µA Active Current (100 kHz)
• 3 µA (typ.) Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin “Green”/RoHS SOIC (-G)

Description

The FM24CL04B is a 4-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 38 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24CL04B performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data polling. The FM24CL04B is capable of supporting 10 14 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24CL04B ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM24CL04B provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24CL04B is available in an industry standard 8- pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration Pin Names Function A1-A2 Device Select Address 1 and 2 SDA Serial Data/Address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage

Ordering Information

FM24CL04B-G “Green”/RoHS 8-pin SOIC FM24CL04B-GTR “Green”/RoHS 8-pin SOIC, Tape & Reel NC VSS VDD WP SCL SDA

Figure 1. Block Diagram edges. A pull-up resistor is required. input also incorporates a Schmitt trigger input for improved noise immunity. all addresses may be written. This pin is internally pulled down.

Rev. 1.3 Feb. 2011 Page 8 of 12 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +5.0V VIN Voltage on any signal pin with respect to V SS -1.0V to +5.0V and VIN < VDD+1.0V * TSTG Storage Temperature -55°C to + 125°C TLEAD Lead Temperature (Soldering, 10 seconds) 260° C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 3.5kV 1.25kV 250V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 2.7 3.3 3.65 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 100 170 300 µA µA µA ISB Standby Current 3 6 µA 2 ILI Input Leakage Current ±1 µA 3 ILO Output Leakage Current ±1 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.3 V VIL Input Low Voltage -0.3 0.3 V DD V VOL Output Low Voltage @ IOL = 3.0 mA 0.4 V RIN Input Resistance (WP, A2, A1) For VIN = VIL (max) For VIN = VIH (min) KΩ MΩ VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A1, A2 pins. 4. This parameter is periodically sampled and not 100% tested. 5. The input pull-down circuit is strong (40KΩ) when the input voltage is below VIL and much weaker (1MΩ) when the input voltage is above VIH.

Rev. 1.3 Feb. 2011 Page 9 of 12 AC Parameters (TA = -40° C to + 85° C, VDD = 2.7V to 3.65V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 1 tF Input Fall Time 300 300 100 ns 1 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 3V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing Power Cycle Timing (TA = -40°C to +85°C, VDD = 2.7V to 3.65V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU Power Up (V DD min) to First Access (Start condition) 10 - ms tPD Last Access (Stop condition) to Power Down (V DD min) 0 - µs tVR V DD Rise Time 30 - µs/V 1 tVF V DD Fall Time 100 - µs/V 1 Notes 1. Slope measured at any point on VDD waveform.

Rev. 1.3 Feb. 2011 Page 10 of 12 AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing Write Bus Timing Data Retention Symbol Parameter Min Max Units Notes TDR @ +85ºC 10 - Years @ +80ºC 19 - Years @ +75ºC 38 - Years 3.6V Output 1100 Ω 100 pF

Rev. 1.3 Feb. 2011 Page 11 of 12 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters Legend: XXXXXX= part number, P= package type (G=SOIC) R=rev code, LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24CL04B, “Green” SOIC package, Year 2010, Work Week 49 FM24CL04BG A00002G1 RIC1049 XXXXXXXP RLLLLLLL RICYYWW

Rev. 1.3 Feb. 2011 Page 12 of 12

Revision History

1.0 11/10/2010 Initial Release 1.1 12/20/2010 Changed V IH (max) spec to VDD+0.3V. 1.2 1/31/2011 Added ESD ratings. 1.3 2/15/2011 Changed t PU and tVF spec limits.