FM24C64

FM24C64_05 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 12

Technical content

Features

64K bit Ferroelectric Nonvolatile RAM

• Organized as 8,192 x 8 bits
• High Endurance 1 Trillion (1012) Read/Writes
• 45 Year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface
• Up to 1 MHz maximum bus frequency
• Direct hardware replacement for EEPROM
• Supports legacy timing for 100 kHz & 400 kHz Low Power Operation
• 5V operation
• 150 µA Active Current (100 kHz)
• 10 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC (-S)
• “Green” 8-pin SOIC (-G)

Description

The FM24C64 is a 64-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24C64 performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately. The FM24C64 is capable of supporting 10 12 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24C64 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writes with less overhead for the system. The FM24C64 provides substantial benefits to users of serial EEPROM, yet these benefits are available in a hardware drop-in replacement. The FM24C64 is available in an industry standard 8-pin SOIC package using a two-wire protocol. The specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration VSS VDD WP SCL SDA Pin Names Function A0-A2 Device Select Address SDA Serial Data/address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage 5V

Ordering Information

FM24C64-G “Green” 8-pin SOIC

Figure 1. FM24C64 Block Diagram match the corresponding bits contained in the device address. edges. A pull-up resistor is required. input also incorporates a Schmitt trigger input for improved noise immunity.

detail in the interface section below. high endurance as compared with EEPROM. vulnerable to noise during much of the cycle. prevent incorrect operation. users but is described in this section. device on the bus that is being controlled is a slave. The FM24C64 always is a slave device. Electrical Specifications section. Figure 2. Typical System Configuration

Figure 3. Data Transfer Protocol high. All operations must end with a Stop condition. aborted by asserting a Start condition at any time. ready the FM24C64 for a new operation. not change while SCL is high. SDA signal low to acknowledge receipt of the byte. is a No-Acknowledge and the operation is aborted.

1010 A 2 A 1 A 0 R / W

Figure 4. Slave Address requires two bytes. The first is the MSB (upper byte). a single read or write operation. transfer occurs MSB (most significant bit) first. counter will wrap from 1FFFh to 0000h. write can occur immediately following a write. increment if writes are attempted to these addresses. SS) will deactivate this feature. WP should not be left floating.

Rev. 3.0 Mar. 2005 8 of 12 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any signal pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V * TSTG Storage temperature -55°C to + 125°C TLEAD Lead temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Machine Model (JEDEC Std JESD22-A115-A) 4kV 250V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 115 400 150 500 1.2 µA µA mA ISB Standby Current 1 10 µA 2 ILI Input Leakage Current ±1 µA 3 ILO Output Leakage Current ±1 µA 3 VIL Input Low Voltage -0.3 0.3 V DD V VIH Input High Voltage 0.7 V DD V DD + 0.5 V VOL Output Low Voltage @ IOL = 3 mA 0.4 V VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. 4. This parameter is characterized but not tested.

Rev. 3.0 Mar. 2005 9 of 12 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 1 tF Input Fall Time 300 300 100 ns 1 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested.

Rev. 3.0 Mar. 2005 10 of 12 AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing SCL SDA StopStart Valid Data bit 7 from FM24C64 Data bit 6 from FM24C64 Start Valid Acknowledge to FM24C64 Data bits 5-0 from FM24C64 tSU:STA tR tF tBUF tHIGH 1/fSCL tLOW tAA tDH tSU:DAT tSP tHD:DAT tSP Write Bus Timing SCL SDA StopStart Valid Data/Address bit 7 to FM24C64 Start Valid Acknowledge from FM24C64 tSU:STO Data/Address bit 6 to FM24C64 Data/Address bit 5-0 to FM24C64 tHD:STA tSU:DAT tHD:DAT tAA Data Retention (VDD = 4.5V to 5.5V, +85° C) Parameter Min Units Notes Data Retention 45 Years 5.5V Output 1700 Ω 100 pF

Rev. 3.0 Mar. 2005 11 of 12 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°-8 ° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24C64, Standard SOIC package, Year 2004, Work Week 39 FM24C64-S A40003S RIC0439 XXXXXXX-P LLLLLLL RICYYWW

Rev. 3.0 Mar. 2005 12 of 12

Revision History

0.1 10/4/99 Initial Release 1.0 12/7/99 Changed to Preliminary status. 1.1 7/2/00 Removed Endurance chart. 2.1 1/22/02 Changed to Production status. Added clarification to package standard and changed package name to SOIC. 2.2 4/26/02 Changed endurance from 10 10 to 10 12 cycles. Rewrote Data Retention and Endurance section. Changed storage temp range -55 to +125 C. Removed Data Retention note. 2.3 8/5/03 Removed DIP package option. 2.4 3/17/04 Added “green” package. Updated package drawing. 3.0 3/29/05 Changed Data Retention spec. Added ESD and package MSL ratings. New rev. number to comply with new scheme.