FM24C256

FM24C256_05 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 12

Technical content

Features

256Kbit Ferroelectric Nonvolatile RAM

• Organized as 32,768 x 8 bits
• High Endurance 10 Billion (1010) Read/Writes
• 45 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface
• Up to 1 MHz Maximum Bus Frequency
• Supports Legacy Timing for 100 kHz & 400 kHz Low Power Operation
• 5V Operation
• 200 µA Active Current (100 kHz)
• 100 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin EIAJ SOIC
• “Green” Packaging Option

Description

The FM24C256 is a 256-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The FM24C256 performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. In addition, the product offers write endurance orders of magnitude higher than EEPROM. Also, FRAM exhibits much lower power during writes than EEPROM since write operations do not require an internally elevated power supply voltage for write circuits. These capabilities make the FM24C256 ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows more frequent data writing with less overhead for the system. The FM24C256 is available in a 8-pin EIAJ SOIC package using an industry standard two-wire protocol. Specifications are guaranteed over an industrial temperature range of -40°C to +85°C. Pin Configuration VSS VDD WP SCL SDA Pin Names Function A0-A2 Device Select Address SDA Serial Data/Address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage 5V

Ordering Information

FM24C256-SE 8-pin EIAJ SOIC FM24C256-G “Green” 8-pin EIAJ SOIC NOTE: Top side part marking is “FM24C256-S” whereas “FM24C256-SE” is used only for ordering.

Figure 1. Block Diagram low, all addresses may be written. This pin is internally pulled down. for falling edges. An external pull-up resistor is required. input also incorporates a Schmitt trigger input for improved noise immunity.

Figure 3. Data Transfer Protocol when a Stop is asserted, the operation will be aborted. read) in order to assert a Stop condition. aborted by asserting a Start condition at any time. ready the FM24C256 for a new operation. Start condition prior to performing another operation. not change while SCL is high. SDA signal low to acknowledge receipt of the byte. is a No-Acknowledge and the operation is aborted. operation so that the part can be addressed again. the receiver sends Acknowledges (and clocks). indicates a read operation, and a 0 indicates a write.

1010 A 2 A 1 A 0 R / W

Figure 4. Slave Address

Rev 3.1 May 2005 Page 5 of 12 Addressing Overview After the FM24C256 (as receiver) acknowledges the device address, the master can place the memory address on the bus for a write operation. The address requires two bytes. The first is the MSB (upper byte). Since the device uses only 15 address bits, the value of the upper bits is a “don’t care”. Following the MSB is the LSB (lower byte) with the remaining eight address bits. The address value is latched internally. Each access causes the latched address value to be incremented automatically. The current address is the value that is held in the latch, either a newly written value or the address following the last access. The current address will be held as long as power remains or until a new value is written. Reads always use the current address. A random read address can be loaded by beginning a write operation as explained below. After transmission of each data byte, just prior to the acknowledge, the FM24C256 increments the internal address latch. This allows the next sequential byte to be accessed with no additional addressing externally. After the last address (7FFFh) is reached, the address latch will roll over to 0000h. There is no limit to the number of bytes that can be accessed with a single read or write operation. Data Transfer After the address information has been transmitted, data transfer between the bus master and the FM24C256 can begin. For a read operation the FM24C256 will place 8 data bits on the bus then wait for an Acknowledge from the master. If the Acknowledge occurs, the FM24C256 will transfer the next sequential byte. If the Acknowledge is not sent, the FM24C256 will end the read operation. For a write operation, the FM24C256 will accept 8 data bits from the master then send an acknowledge. All data transfer occurs MSB (most significant bit) first. Memory Operation The FM24C256 is designed to operate in a manner very similar to other 2-wire interface memory products. The major differences result from the higher performance write capability of FRAM technology. These improvements result in some differences between the FM24C256 and a similar configuration EEPROM during writes. The complete operation for both writes and reads is explained below. Write Operation All writes begin with a device address, then a memory address. The bus master indicates a write operation by setting the LSB of the device address to a 0. After addressing, the bus master sends each byte of data to the memory and the memory generates an acknowledge condition. Any number of sequential bytes may be written. If the end of the address range is reached internally, the address counter will wrap from 7FFFh to 0000h. Unlike other nonvolatile memory technologies, there is essentially no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay on the bus. The entire memory cycle occurs in less time than a single bus clock. Therefore, any operation including a read or write can occur immediately following a write. Acknowledge polling, a technique used with EEPROMs to determine if a write has completed is unnecessary and will always return a ready condition. Internally, an actual memory write occurs after the th data bit is transferred. It will be complete before the Acknowledge is sent. Therefore, if the user desires to abort a write without altering the memory contents, this should be done using a Start or Stop condition prior to the 8 th data bit. The FM24C256 uses no page buffering. The memory array can be write protected using the WP pin. Pulling the WP pin high will write-protect all addresses. The FM24C256 will not acknowledge data bytes that are written when WP is active. In addition, the address counter will not increment if writes are attempted to these addresses. Setting WP low will deactivate this feature. WP is internally pulled down. The state of WP should remain stable from the Start command until the address is complete. Figure 5 and 6 below illustrate both a single-byte and multiple-write.

Rev 3.1 May 2005 Page 8 of 12 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Voltage on V DD with respect to VSS -1.0V to +7.0V VIN Voltage on any signal pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V * TSTG Storage Temperature -55°C to + 125°C TLEAD Lead temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Machine Model (JEDEC Std JESD22-A115-A) 4kV 400V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 200 500 1.2 µA µA mA ISB Standby Current 100 µA 2 ILI Input Leakage Current 10 µA 3 ILO Output Leakage Current 10 µA 3 VIH Input High Voltage 0.7 V DD V DD + 0.5 V 4 VIL Input Low Voltage -0.3 0.3 V DD V 4 VOL Output Low Voltage @ IOL = 3 mA 0.4 V RIN Address Input Resistance (WP, A2-A0) For VIN = VIL (max) For VIN = VIH (min) KΩ MΩ VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP, A2-A0 pins. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is strong (20KΩ ) when the input voltage is below VIL and weak (1MΩ ) when the input voltage is above VIH. This resistance is characterized and not tested.

Rev 3.1 May 2005 Page 9 of 12 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V, CL = 100 pF unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold 0 0 0 ns tSU:DAT Data In Setup 250 100 100 ns tR Input Rise Time 1000 300 300 ns 1 tF Input Fall Time 300 300 100 ns 1 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD 5.5V Output 1700 Ω 100 pF

Rev 3.1 May 2005 Page 10 of 12 Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:D AT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention (VDD = 4.5V to 5.5V, +85° C) Parameter Min Units Notes Data Retention 45 Years

Rev 3.1 May 2005 Page 11 of 12 Mechanical Drawing 8-pin EIAJ SOIC Pin 1 5.23 ±0.10 0.05 0.25 1.78 2.00 0.36 0.50 1.27 0.10 mm 0.51 0.76 0.19 0.25 0°- 8° Recommended PCB Footprint 9.30 0.651.27 2.15 5.00 All dimensions in millimeters. Legend: XXXXXX= part number LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week FM24C256, “Green” EIAJ SOIC package, Year 2004, Work Week 50 FM24C256-G A40003S1 RIC 0450 FM24C256, Standard EIAJ SOIC package (-SE) RIC FM24C256-S (Lot Code and Date Code on backside of package) XXXXXXX-G LLLLLLL RIC YYWW RIC XXXXXXX-S

Rev 3.1 May 2005 Page 12 of 12

Revision History

1.0 4/10/01 Initial Release 1.1 9/28/01 Changed Idd and Isb specifications. Changed test load to 1700 ohms to reflect 3mA VOL test condition. 1.2 1/31/02 Updated package drawing and dimensions. Rewrote description of the internal memory architecture and endurance section. 1.3 2/3/04 Added “part marking” note to Ordering Information (pg 1). 3.0 2/16/05 Added “green” packaging option. Added ESD and package MSL ratings. Changed storage temperature. New rev. number and 1 st page footer to comply with updated scheme. Changed Data Retention spec. 3.1 5/5/05 Clarified Package Marking Scheme text and drawings.