FM24C16C RAMTRON | Alldatasheet
Document overview
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Technical content
Features
16K bit Ferroelectric Nonvolatile RAM Organized as 2,048 x 8 bits High Endurance (1012) Read/Write Cycles 36 year Data Retention at +75C NoDelay™ Writes Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface Up to 1MHz maximum bus frequency Direct hardware replacement for EEPROM Supports legacy timing for 100 kHz & 400 kHz Low Power Operation 5V operation 100 A Active Current (100 kHz) 4 A (typ.) Standby Current Industry Standard Configuration Industrial Temperature -40 C to +85 C 8-pin “Green”/RoHS SOIC (-G)
Description
The FM 24C16C is a 16 -kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memor y or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for 36 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. The F M24C16C performs write operations at bus speed. No write delays are incurred. Data is written to the memory array in the cycle after it has been successfully transferred to the device. The next bus cycle may commence immediately without the need for data p olling. The FM 24C16C is capable of supporting 10 12 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM 24C16C ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows the system to write data more frequently, with less system overhead. The FM24C16C provides substantial benefits to users of serial EEPROM, and these benefits are available as a hardware drop -in replacement. The FM 24C16C is available in an industry standard 8 -pin SOIC package and uses a familiar two-wire protocol. The specifications are guaranteed over the ind ustrial temperature range from -40°C to +85°C. Pin Configuration Pin Names Function SDA Serial Data/Address SCL Serial Clock WP Write Protect VSS Ground VDD Supply Voltage
Ordering Information
FM24C16C-G “Green”/RoHS 8-pin SOIC FM24C16C-GTR “Green”/RoHS 8-pin SOIC, Tape & Reel NC NC NC VSS VDD WP SCL SDA
Figure 1. Block Diagram output driver includes slope control for falling edges. A pull-up resistor is required. the falling edge and clocked-in on the rising edge. all addresses may be written. This pin is internally pulled down.
FM24C16C - 16Kb 5V I2C F-RAM Rev. 1.1 May 2011 Page 8 of 12 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to VSS -1.0V to +7.0V VIN Voltage on any signal pin with respect to VSS -1.0V to +7.0V and VIN < VDD+1.0V * TSTG Storage Temperature -55C to +125C TLEAD Lead Temperature (Soldering, 10 seconds) 260 C VESD Electrostatic Discharge Voltage - Human Body Model (AEC-Q100-002 Rev. E) - Charged Device Model (AEC-Q100-011 Rev. B) - Machine Model (AEC-Q100-003 Rev. E) 2.5kV 1.25kV 100V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions abov e those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 100 200 400 ISB Standby Current 4 10 A 2 ILI Input Leakage Current ±1 A 3 ILO Output Leakage Current ±1 A 3 VIL Input Low Voltage -0.3 0.3 VDD V VIH Input High Voltage 0.7 VDD VDD + 0.3 V VOL Output Low Voltage @ IOL = 3 mA 0.4 V RIN Input Resistance (WP pin) For VIN = VIL (max) For VIN = VIH (min) VHYS Input Hysteresis 0.05 VDD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 2. SCL = SDA = VDD. All inputs VSS or VDD. Stop command issued. 3. VIN or VOUT = VSS to VDD. Does not apply to WP pin. 4. This parameter is characterized but not tested. 5. The input pull-down circuit is strong (40K) when the input voltage is below VIL and much weaker (1M) when the input voltage is above VIH.
FM24C16C - 16Kb 5V I2C F-RAM Rev. 1.1 May 2011 Page 9 of 12 AC Parameters (TA = -40 C to + 85 C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 s tHIGH Clock High Period 4.0 0.6 0.4 s tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 s tBUF Bus Free Before New Transmission 4.7 1.3 0.5 s tHD:STA Start Condition Hold Time 4.0 0.6 0.25 s tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 s tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 s tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 The speed-related specifications are guaranteed characteristic points from DC to 1 MHz. 2 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25 C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. Power Cycle Timing VDD min.VDD SDA,SCL tVR tPDtPU tVF Power Cycle Timing (TA = -40C to +85C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Units Notes tPU Power Up (VDD min) to First Access (Start condition) 1 - ms tPD Last Access (Stop condition) to Power Down (VDD min) 0 - s tVR VDD Rise Time 30 - s/V 1 tVF VDD Fall Time 100 - s/V 1 Notes 1. Slope measured at any point on VDD waveform.
FM24C16C - 16Kb 5V I2C F-RAM Rev. 1.1 May 2011 Page 10 of 12 AC Test Conditions Equivalent AC Load Circuit Input Pulse Levels 0.1 VDD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 VDD Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:DAT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention Symbol Parameter Min Max Units Notes TDR @ +85ºC 10 - Years @ +80ºC 18 - Years @ +75ºC 36 - Years 5.5V Output 1700 100 pF
FM24C16C - 16Kb 5V I2C F-RAM Rev. 1.1 May 2011 Page 11 of 12 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 0.40 1.27 0.19 0.25 - 8 Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXXXX= part number, P= package type R=rev code, LLLLLLL= lot code RIC=Ramtron Int‟l Corp, YY=year, WW=work week Example: FM24C16C, “Green” SOIC package, Year 2010, Work Week 49 FM24C16C-G A00002G1 RIC1049 XXXXXXX-P RLLLLLLL RICYYWW
FM24C16C - 16Kb 5V I2C F-RAM Rev. 1.1 May 2011 Page 12 of 12
Revision History
1.0 3/22/2011 Initial Release 1.1 5/20/2011 Added ESD ratings.