FM24C16A

FM24C16A_05 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 12

Technical content

Features

16K bit Ferroelectric Nonvolatile RAM

• Organized as 2,048 x 8 bits
• High Endurance (1012) Read/Write Cycles
• 45 year Data Retention
• NoDelay™ Writes
• Advanced High-Reliability Ferroelectric Process Fast Two-wire Serial Interface
• Up to 1MHz maximum bus frequency
• Direct hardware replacement for EEPROM Low Power Operation
• 5V operation
• 150 µA Active Current (100 kHz)
• 10 µA Standby Current Industry Standard Configuration
• Industrial Temperature -40° C to +85° C
• 8-pin SOIC (-S)
• “Green” 8-pin SOIC (-G)

Description

The FM24C16A is a 16-kilobit nonvolatile memory employing an advanced ferroelectric process. A ferroelectric random access memory or FRAM is nonvolatile and performs reads and writes like a RAM. It provides reliable data retention for over 45 years while eliminating the complexities, overhead, and system level reliability problems caused by EEPROM and other nonvolatile memories. Unlike serial EEPROMs, the FM24C16A performs write operations at bus speed. No write delays are incurred. The next bus cycle may commence immediately without the need for data polling. The FM24C16A is capable of supporting 10 12 read/write cycles, or a million times more write cycles than EEPROM. These capabilities make the FM24C16A ideal for nonvolatile memory applications requiring frequent or rapid writes. Examples range from data collection where the number of write cycles may be critical, to demanding industrial controls where the long write time of EEPROM can cause data loss. The combination of features allows the system to write data more frequently, with less system overhead. The FM24C16A provides substantial benefits to users of serial EEPROM, and these benefits are available as a hardware drop-in replacement. The FM24C16A is available in an industry standard 8-pin SOIC and uses a two-wire protocol. The specifications are guaranteed over the industrial temperature range from -40°C to +85°C. Pin Configuration Pin Names Function SDA Serial Data/Address SCL Serial Clock WP Write Protect VDD Supply Voltage 5V VSS Ground

Ordering Information

FM24C16A-G “Green” 8-pin SOIC VSS SDA SCL NC WP VDD NC NC

Figure 1. Block Diagram output driver includes slope control for falling edges. A pull-up resistor is required. the falling edge and clocked-in on the rising edge. all addresses may be written. This pin is internally pulled down.

Rev 3.0 Mar. 2005 Page 8 of 12 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +7.0V VIN Voltage on any signal pin with respect to V SS -1.0V to +7.0V and VIN < VDD+1.0V * TSTG Storage Temperature -55°C to +125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 4kV 1kV 300V Package Moisture Sensitivity Level MSL-1 * Exception: The “VIN < VDD+1.0V” restriction does not apply to the SCL and SDA inputs. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. DC Operating Conditions (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Main Power Supply 4.5 5.0 5.5 V IDD VDD Supply Current @ SCL = 100 kHz @ SCL = 400 kHz @ SCL = 1 MHz 115 400 800 150 500 1000 µA µA µA ISB Standby Current 1 10 µA 2 ILI Input Leakage Current ±1 µA 3 ILO Output Leakage Current ±1 µA 3 VIL Input Low Voltage -0.3 0.3 V DD V VIH Input High Voltage 0.7 V DD V DD + 0.5 V VOL Output Low Voltage @ IOL = 3 mA 0.4 V RIN Input Resistance (WP pin) For VIN = VIL (max) For VIN = VIH (min) KΩ MΩ VHYS Input Hysteresis 0.05 V DD V 4 Notes 1. SCL toggling between VDD-0.3V and VSS, other inputs VSS or VDD-0.3V. 4. 3. VIN or VOUT = VSS to VDD. Does not apply to WP pin. 5. 4. This parameter is characterized but not tested. 6. 5. The input pull-down circuit is strong (50KΩ ) when the input voltage is below VIL and much weaker (1MΩ ) when the input voltage is above VIH.

Rev 3.0 Mar. 2005 Page 9 of 12 AC Parameters (TA = -40° C to + 85° C, VDD = 4.5V to 5.5V unless otherwise specified) Symbol Parameter Min Max Min Max Min Max Units Notes fSCL SCL Clock Frequency 0 100 0 400 0 1000 kHz 1 tLOW Clock Low Period 4.7 1.3 0.6 µs tHIGH Clock High Period 4.0 0.6 0.4 µs tAA SCL Low to SDA Data Out Valid 3 0.9 0.55 µs tBUF Bus Free Before New Transmission 4.7 1.3 0.5 µs tHD:STA Start Condition Hold Time 4.0 0.6 0.25 µs tSU:STA Start Condition Setup for Repeated Start 4.7 0.6 0.25 µs tHD:DAT Data In Hold Time 0 0 0 ns tSU:DAT Data In Setup Time 250 100 100 ns tR Input Rise Time 1000 300 300 ns 2 tF Input Fall Time 300 300 100 ns 2 tSU:STO Stop Condition Setup 4.0 0.6 0.25 µs tDH Data Output Hold (from SCL @ VIL) 0 0 0 ns tSP Noise Suppression Time Constant on SCL, SDA 50 50 50 ns Notes : All SCL specifications as well as start and stop conditions apply to both read and write operations. 1 The speed-related specifications are guaranteed characteristic points from DC to 1 MHz. 2 This parameter is periodically sampled and not 100% tested. Capacitance (TA = 25° C, f=1.0 MHz, VDD = 5V) Symbol Parameter Max Units Notes CI/O Input/Output Capacitance (SDA) 8 pF 1 CIN Input Capacitance 6 pF 1 Notes 1 This parameter is periodically sampled and not 100% tested. AC Test Conditions Input Pulse Levels 0.1 V DD to 0.9 VDD Input rise and fall times 10 ns Input and output timing levels 0.5 V DD Equivalent AC Load Circuit 5.5V Output 1700 Ω 100 pF

Rev 3.0 Mar. 2005 Page 10 of 12 Diagram Notes All start and stop timing parameters apply to both read and write cycles. Clock specifications are identical for read and write cycles. Write timing parameters apply to slave address, word address, and write data bits. Functional relationships are illustrated in the relevant data sheet sections. These diagrams illustrate the timing parameters only. Read Bus Timing tSU:SDA Start tR tF Stop Start tBUF tHIGH 1/fSCL tLOW tSP tSP Acknowledge tHD:DAT tSU:D AT tAA tDH SCL SDA Write Bus Timing tSU:STO Start Stop Start Acknowledge tAA tHD:DAT tHD:STA tSU:DAT SCL SDA Data Retention (VDD = 4.5V to 5.5V, +85° C) Parameter Min Units Notes Data Retention 45 Years

Rev 3.0 Mar. 2005 Page 11 of 12 Mechanical Drawing 8-pin SOIC (JEDEC Standard MS-012 variation AA) Pin 1 4.90 ±0.10 0.10 0.25 1.35 1.75 0.33 0.51 1.27 0.10 mm 0.25 0.50 45° 0.40 1.27 0.19 0.25 0°-8 ° Recommended PCB Footprint 7.70 0.651.27 2.00 3.70 Refer to JEDEC MS-012 for complete dimensions and notes. All dimensions in millimeters. Legend: XXXX= part number, P= package type LLLLLLL= lot code RIC=Ramtron Int’l Corp, YY=year, WW=work week Example: FM24C16A, Standard SOIC package, Year 2004, Work Week 39 FM24C16A-S A40003S RIC0439 XXXXXXX-P LLLLLLL RICYYWW

Rev 3.0 Mar. 2005 Page 12 of 12

Revision History

0.1 6/26/02 Initial Release 2.0 7/23/03 Changed to Production status. 2.1 3/17/04 Added “green” package. Updated package drawing. 3.0 3/29/05 Changed Data Retention spec. Added ESD and package MSL ratings. Added pcb footprint drawing. New rev. number and 1 st page footer to comply with new scheme.