FM20L08

FM20L08_07 RAMTRON | Alldatasheet

Document overview

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• PDF pages: 14

Technical content

Features

1Mbit Ferroelectric Nonvolatile RAM

• Organized as 128Kx8
• Unlimited Read/Write Cycles
• NoDelay™ Writes
• Page Mode Operation to 33MHz
• Advanced High-Reliability Ferroelectric Process SRAM Replacement
• JEDEC 128Kx8 SRAM pinout
• 60 ns Access Time, 350 ns Cycle Time System Supervisor
• Low Voltage monitor drives external /LVL signal
• Write protects memory for low voltage condition
• Software programmable block write protect (-TG1 only) Superior to Battery-backed SRAM Modules
• No battery concerns
• Monolithic reliability
• True surface mount solution, no rework steps
• Superior for moisture, shock, and vibration
• Resistant to negative voltage undershoots Low Power Operation
• 3.3V +10%, -5% Power Supply
• 22 mA Active Current Industry Standard Configurations
• Industrial Temperature -40° C to +85° C
• 32-pin “Green”/RoHS TSOP (-TG)

Description

The FM20L08 is a 128K x 8 nonvolatile memory that reads and writes like a standard SRAM. A ferroelectric random access memory or FRAM is nonvolatile, which means that data is retained after power is removed. It provides data retention for over 10 years while eliminating the reliability concerns, functional disadvantages, and system design complexities of battery-backed SRAM (BBSRAM). Fast write timing and unlimited write endurance make FRAM superior to other types of memory. In-system operation of the FM20L08 is very similar to other RAM devices and can be used as a drop-in replacement for standard SRAM. Read and write cycles may be triggered by /CE or simply by changing the address. The FRAM memory is nonvolatile due to its unique ferroelectric memory process. These features make the FM20L08 ideal for nonvolatile memory applications requiring frequent or rapid writes in the form of an SRAM. The FM20L08 includes a voltage monitor function that monitors the power supply voltage. It asserts an active-low signal that indicates the memory is write- protected when V DD drops below a critical threshold. When the /LVL signal is low, the memory is protected against an inadvertent access and data corruption. The FM20L08 also features software-controlled write protection (-TG1 only). The memory array is divided into 8 uniform blocks, each of which can be individually write protected. Device specifications are guaranteed over the industrial temperature range -40°C to +85°C. Pin Configuration

Ordering Information

FM20L08-60-TG 60 ns access, 32-pin “Green”/RoHS TSOP FM20L08-60-TG1 60 ns access, 32-pin “Green”/RoHS TSOP with software Write Protect A11 A13 WE DNU A15 VDD LVL A16 A14 A12 OE A10 CE DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0

Figure 1. Block Diagram mode read and write operations. low. The entire address is latched internally on the falling edge of chip enable. Subsequent changes to the A(2:0) address inputs allow page mode operation. latches a new column address for fast page mode write cycles. available. Deasserting /OE high tri-states the DQ pins. DQ(7:0) I/O Data: 8-bit bi-directional data bus for accessing the FRAM array. operating limits, the /LVL signal will be pulled high. DNU - Do Not Use: This pin should be left unconnected.

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 3 of 14 Functional Truth Table /CE /WE A(16:3) A(2:0) Operation H X X X Standby/Idle ↓ H V V Read L H No Change Change Page Mode Read L H Change V Random Read ↓ L V V /CE-Controlled Write L ↓ X V /WE-Controlled Write 2 L ↓ No Change V Page Mode Write 3 ↑ X X X Starts Precharge Notes: 1) H=Logic High, L=Logic Low, V=Valid Address, X=Don’t Care. 2) /WE-controlled write cycle begins as a Read cycle and A(16:3) is latched then. 3) Addresses A(2:0) must remain stable for at least 15 ns during page mode operation. 4) For write cycles, data-in is latched on the rising edge of /CE or /WE, whichever comes first.

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 4 of 14 Overview The FM20L08 is a bytewide FRAM memory logically organized as 131,072 x 8 and is accessed using an industry standard parallel interface. All data written to the part is immediately nonvolatile with no delay. The device offers page mode operation which provides higher speed access to addresses within a page (row). An access to a different page requires that either /CE transitions low or the upper address A(16:3) changes. Memory Operation Users access 131,072 memory locations with 8 data bits each through a parallel interface. The FRAM array is organized as 8 blocks each having 2048 rows. Each row has 8 column locations, which allows fast access in page mode operation. Once an initial address has been latched by the falling edge of /CE, subsequent column locations may be accessed without the need to toggle /CE. When /CE is deasserted high, a precharge operation begins. Writes occur immediately at the end of the access with no delay. The /WE pin must be toggled for each write operation. Read Operation A read operation begins on the falling edge of /CE. The falling edge of /CE causes the address to be latched and starts a memory read cycle if /WE is high. Data becomes available on the bus after the access time has been satisfied. Once the address has been latched and the access completed, a new access to a random location (different row) may begin while /CE is still low. The minimum cycle time for random addresses is t RC. Note that unlike SRAMs, the FM20L08’s /CE-initiated access time is faster than the address cycle time. The FM20L08 will drive the data bus only when /OE is asserted low and the memory access time has been satisfied. If /OE is asserted prior to completion of the memory access, the data bus will not be driven until valid data is available. This feature minimizes supply current in the system by eliminating transients caused by invalid data being driven onto the bus. When /OE is inactive, the data bus will remain hi-Z. Write Operation Writes occur in the FM20L08 in the same time interval as reads. The FM20L08 supports both /CE- and /WE-controlled write cycles. In both cases, the address is latched on the falling edge of /CE. In a /CE-controlled write, the /WE signal is asserted prior to beginning the memory cycle. That is, /WE is low when /CE falls. In this case, the device begins the memory cycle as a write. The FM20L08 will not drive the data bus regardless of the state of /OE as long as /WE is low. Input data must be valid when /CE is deasserted high. In a /WE-controlled write, the memory cycle begins on the falling edge of /CE. The /WE signal falls some time later. Therefore, the memory cycle begins as a read. The data bus will be driven if /OE is low, however it will hi-Z once /WE is asserted low. The /CE- and /WE-controlled write timing cases are shown on page 11. In the Write Cycle Timing 2 diagram, the data bus is shown as a hi-Z condition while the chip is write-enabled and before the required setup time. Although this is drawn to look like a mid-level voltage, it is recommended that all DQ pins comply with the minimum V IH/VIL operating levels. Write access to the array begins on the falling edge of /WE after the memory cycle is initiated. The write access terminates on the rising edge of /WE or /CE, whichever comes first. A valid write operation requires the user to meet the access time specification prior to deasserting /WE or /CE. Data setup time indicates the interval during which data cannot change prior to the end of the write access (/WE or /CE high). Unlike other truly nonvolatile memory technologies, there is no write delay with FRAM. Since the read and write access times of the underlying memory are the same, the user experiences no delay through the bus. The entire memory operation occurs in a single bus cycle. Data polling, a technique used with EEPROMs to determine if a write is complete, is unnecessary. Page Mode Operation The FM20L08 provides the user fast access to any data within a row element. Each row has eight column locations. An access can start anywhere within a row and other column locations may be accessed without the need to toggle the /CE pin. For page mode reads, once the first data byte is driven onto the bus, the column address inputs A(2:0) may be changed to a new value. A new data byte is then driven to the DQ pins. For page mode writes, the first write pulse defines the first write access. While /CE is low, a subsequent write pulse along with a new column address provides a page mode write access. Precharge Operation The precharge operation is an internal condition in which the state of the memory is prepared for a new access. Precharge is user-initiated by driving the /CE signal high. It must remain high for at least the minimum precharge time t PC.

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 5 of 14 Supply Voltage Monitor An internal voltage monitor circuit continuously checks the V DD supply voltage. When V DD is below the specified threshold V TP, the monitor asserts the /LVL signal to an active-low state. The FM20L08 locks out access to the memory when V DD is below the trip voltage. This prevents the system from accessing memory when V DD is too low and inadvertently corrupting the data. The /LVL signal should not be used as a system reset signal because the system host may attempt to write data to the FM20L08 below its specified operating voltage. The /LVL pin may be used as a status indicator that the memory is locked out. On power up, the /LVL signal will begin in a low state signifying that V DD is below the VTP threshold. It will remain low as long as V DD is below that level. Once VDD rises above VTP, a hold-off timer will begin creating the delay t PULV. Once this delay has elapsed, the /LVL signal will go high or inactive. At this time the memory can be accessed. The memory is ready for access prior to t PU as shown in the Electrical Specifications section. The /LVL signal will remain high until V DD drops below the threshold. Software Write Protection (Applies only to “-TG1” device. The –TG device does not have this Write Protect feature. See Ordering Information on page 1) The 128Kx8 address space is divided into 8 sectors (blocks) of 16Kx8 each. Each sector can be individually software write-protected and the settings are nonvolatile. A unique address and command sequence invokes the write protection mode. To modify write protection, the system host must issue six read commands and two write commands. The specific sequence of read addresses must be provided in order to access to the write protect mode. Following the read address sequence, the host must write a data byte that specifies the desired protection state of each sector. For confirmation, the system must then write the complement of the protection byte immediately following the protection byte. Any error that occurs including read addresses in the wrong order, issuing a seventh read address, or failing to complement the protection value will leave the write protection unchanged. The write-protect state machine monitors all addresses, taking no action until the write-protect read/write sequence occurs. During the address sequence, each read will occur as a valid operation and data from the corresponding addresses will be driven onto the data bus. Any address that occurs out of sequence will cause the software protection state machine to start over. After the address sequence is completed, the next operation must be a write cycle. The data byte contains the write-protect settings. This value will not be written to the memory array, so the write address is ignored. Rather the byte will be held pending the next cycle, which must be a write of the data complement to the protection settings. If the complement is correct, the write protect settings will be updated. If not, the process is aborted and the address sequence starts over. The data value written after the correct six addresses will not be entered into memory. The protection data byte consists of 8-bits, each associated with the write protect state of a sector. Setting a bit to 1 write protects the corresponding sector; a 0 enables writes for that sector. The following table shows the write-protect sectors with the corresponding bit that controls the write-protect setting. Write Protect Sectors – 16K x8 blocks Sector 7 1FFFFh – 1C000h Sector 6 1BFFFh – 18000h Sector 5 17FFFh – 14000h Sector 4 13FFFh – 10000h Sector 3 0FFFFh – 0C000h Sector 2 0BFFFh – 08000h Sector 1 07FFFh – 04000h Sector 0 03FFFh – 00000h The write-protect address sequence follows: 1. 05555h * 2. 1AAAAh 3. 03333h 4. 1CCCCh 5. 100FFh 6. 0FF00h 7. 1AAAAh 8. 1CCCCh 9. 0FF00h 10. 00000h * If /CE is low entering the sequence, then an address of 00000h must precede 05555h. The address sequence provides a very secure way of modifying the protection. The correct address sequence has a 1 in 5 x 10 30 chance of occurring accidentally. A flow chart of the entire write protect operation is shown in Figure 2. As mentioned above, write-protect settings are nonvolatile. The factory default is unprotected.

Figure 2. Write-Protect State Machine

Figure 3. Use of Pullup Resistor on /CE

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 8 of 14 Electrical Specifications Absolute Maximum Ratings Symbol Description Ratings VDD Power Supply Voltage with respect to V SS -1.0V to +5.0V VIN Voltage on any signal pin with respect to V SS -1.0V to +5.0V and VIN < VDD+1V TSTG Storage Temperature -55°C to +125°C TLEAD Lead Temperature (Soldering, 10 seconds) 300° C VESD Electrostatic Discharge Voltage - Human Body Model (JEDEC Std JESD22-A114-B) - Charged Device Model (JEDEC Std JESD22-C101-A) - Machine Model (JEDEC Std JESD22-A115-A) 3kV 750V 200V Package Moisture Sensitivity Level MSL-2 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only, and the functional operation of the device at these or any other conditions above those listed in the operational section of this specification is not implied. Exposure to absolute maximum ratings conditions for extended periods may affect device reliabilit y. DC Operating Conditions (TA = -40° C to +85° C, VDD = 3.3V +10%, -5% unless otherwise specified) Symbol Parameter Min Typ Max Units Notes VDD Power Supply 3.135 3.3 3.63 V IDD V DD Supply Current - 22 mA 1 ISB Standby Current – CMOS - 25 µA 2 VTP V DD trip point to assert (deassert) /LVL 2.7 - 3.0 V 3 ILI Input Leakage Current ±1 µA 4 ILO Output Leakage Current ±1 µA 4 VIH Input High Voltage 2.2 V DD + 0.3 V VIL Input Low Voltage -0.3 0.6 V VOH Output High Voltage ( IOH = -1.0 mA) 2.4 - V VOL Output Low Voltage ( IOL = 2.1 mA) - 0.4 V 5 Notes 3. This is the VDD trip voltage at which /LVL is asserted or deasserted. When VDD rises above VTP, /LVL will be deasserted after satisfying tPULV. When VDD drops below VTP, /LVL will be asserted after satisfying tPDLV. 4. VIN, VOUT between VDD and VSS. 5. For the /LVL pin, the test condition is IOL = 80 µA when VDD is between 3.135V and 1.2V. The state of the /LVL pin is not guaranteed when VDD is below 1.2V.

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 9 of 14 Read Cycle AC Parameters (TA = -40° C to +85° C, CL = 30 pF, VDD = 3.3V +10%, -5% unless otherwise specified) -60 Symbol Parameter Min Max Units Notes tRC Read Cycle Time 350 - ns tCE Chip Enable Access Time - 60 ns tAA Address Access Time - 350 ns tOH Output Hold Time 50 - ns tAAP Page Mode Address Access Time - 25 ns tOHP Page Mode Output Hold Time 5 - ns tCA Chip Enable Active Time 60 - ns tPC Precharge Time 290 - ns tAS Address Setup Time (to /CE low) 5 - ns tAH Address Hold Time (/CE-controlled) 60 - ns tOE Output Enable Access Time - 10 ns tHZ Chip Enable to Output High-Z - 15 ns 1 tOHZ Output Enable High to Output High-Z - 15 ns 1 Write Cycle AC Parameters (TA = -40° C to +85° C, VDD = 3.3V +10%, -5% unless otherwise specified) -60 Symbol Parameter Min Max Units Notes tWC Write Cycle Time 350 - ns tCA Chip Enable Active Time 60 - ns tCW Chip Enable to Write Enable High 60 - ns tPC Precharge Time 290 - ns tPWC Page Mode Write Enable Cycle Time 30 - ns tWP Write Enable Pulse Width 15 - ns tAS Address Setup Time (to /CE low) 5 - ns tAH Address Hold Time (/CE-controlled) 60 - ns tASP Page Mode Address Setup Time (to /WE low) 5 - ns tAHP Page Mode Address Hold Time (to /WE low) 15 - ns tWLC Write Enable Low to /CE High 25 - ns tWLA Write Enable Low to A(16:3) Change 25 - ns tAWH A(16:3) Change to Write Enable High 350 - ns tDS Data Input Setup Time 20 - ns tDH Data Input Hold Time 0 - ns tWZ Write Enable Low to Output High Z - 15 ns 1 tWX Write Enable High to Output Driven 5 - ns 1 tWS Write Enable to /CE Low Setup Time 0 - ns 1,2 tWH Write Enable to /CE High Hold Time 0 - ns 1,2 Notes 1 This parameter is characterized but not 100% tested. 2 The relationship between /CE and /WE determines if a /CE- or /WE-controlled write occurs. Power Cycle Timing (TA = -40° C to +85° C, VDD = 3.3V +10%, -5% unless otherwise specified) Symbol Parameter Min Max Units Notes tPULV Power Up to /LVL Inactive Time (V TP to /LVL high) 0 5 ms tPDLV Power Down to /LVL Active Time (V TP to /LVL low) 0 15 µs tPU Power Up (/LVL high) to First Access Time 0 - µs tPD Last Access (/CE high) to Power Down (V DD min) 0 - µs tVR V DD Rise Time 50 - µs/V 1 tVF V DD Fall Time 100 - µs/V 1 Notes 1 Slope measured at any point on VDD waveform.

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 10 of 14 Data Retention (VDD = 3.3V +10%, -5%) Parameter Min Max Units Notes Data Retention 10 - Years Capacitance (TA = 25° C , f=1 MHz, VDD = 3.3V) Symbol Parameter Min Max Units Notes CI/O Input/Output Capacitance (DQ) - 8 pF 1 CIN Input Capacitance - 6 pF 1 Notes 1. This parameter is characterized and not 100% tested. AC Test Conditions Input Pulse Levels 0 to 3V Input rise and fall times 3 ns Input and output timing levels 1.5V Output Load Capacitance 30 pF Read Cycle Timing 1 (/CE low, /OE low) A(16:0) DQ(7:0) tRC tOH tAA tOH Read Cycle Timing 2 (/CE-controlled) CE A(16:0) OE DQ(7:0) tAS tCE tCA tPC tOE tOHZ tHZ tAH

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 11 of 14 Page Mode Read Cycle Timing Although sequential column addressing is shown, it is not required. Write Cycle Timing 1 (/WE-Controlled, /OE low) Write Cycle Timing 2 (/CE-Controlled) NOTE: See Write Operation section for detailed description (page 4).

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 12 of 14 Write Cycle Timing 3 (/CE low) Page Mode Write Cycle Timing CE A(16:3) WE tCA tPC DQ(7:0) tCW A(2:0) Col 0 Col 1 Data 0 Col 2 tAS tDS Data 1 tWP tDH Data 2 OE tAHP tPWC tWLC tASPtAH Although sequential column addressing is shown, it is not required. Power Cycle Timing

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 13 of 14 Mechanical Drawing 32-pin Shrunk TSOP-I (8.0 x 13.4 mm) All dimensions in millimeters Legend: XXXXXX= part number, SP= speed/package/temp/write-protect R=rev code, YY=year, WW=work week, LLLLLL= lot code Examples: “Green” TSOP package, Industrial temp, B rev., Year 2006, Work Week 44, Lot 60011TG Without Write-Protect feature With Write-Protect feature RAMTRON RAMTRON FM20L08-60TG FM20L08-60G1 B064460011TG B064460011TG RAMTRON XXXXXXX-SP RYYWWLLLLLL

FM20L08 - Industrial Temp. Rev. 1.72 May 2007 Page 14 of 14

Revision History

0.6 1/30/04 Added Vdd fall time spec. Changed Power Cycle Timing diagram. Added t AWH Write Timing spec. Added typ value to VTP in DC Operating table. Changed software write-protect scheme. Changed /LVL to Output-only pin. Modified Block Diagram, Pin Description and DC Operating tables. Modified package drawing title. 0.61 5/20/04 Changed t WX, tAAP, and tAWH specs. Added tAH to Write Cycle parameters table. Changed input rise/fall time AC test condition. Changed tVF units. Added “green” package. 0.7 9/3/04 Reduced to one speed grade and changed to -60 speed grade. Supply voltage 3.3V +10%, -5%. Temp range 0 to +85C. 0.8 12/20/04 Temp range -40 to +85C. Changed AC timing parameters. Changed part number/ordering information. 1.0 3/25/05 Changed to Preliminary status. 1.1 5/23/05 Added “green” packaging option. Added marking scheme. 1.2 6/6/05 Removed –T packaging option. 1.3 8/15/05 Changed address setup and I DD specs. Added tVR parameter. Added note about /CE high during power cycles. Modified Power Cycle timing diagram and added timing parameters. Removed references to the use of /LVL as a system reset signal. Changed temperature limits. 1.4 10/18/05 Changed I SB. Changed VTP limits. Added note to Power Cycle Timing table. Rewrote text describing use of pullup resistor. 1.5 2/9/06 Order device with or without software WP. Changed t PULV to 5ms. Added ESD and MSL ratings. 1.6 6/12/06 Changed specs to industrial temperature. Devices with date codes 0605 thro ugh 0620 comply with this datasheet revision. 1.7 8/21/06 Changed I SB spec. Updated ESD ratings. Removed Note 2 from Power Cycle Timing table. Devices with date codes 0624 and beyond comply with this datasheet revision. 1.71 4/9/07 Changed Package Marking Scheme. Updated ESD machine model and MSL ratings. 1.72 5/10/07 Added pcb footprint to package drawing.