FAMP0417CAX-W70E FIDELIX | Alldatasheet

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FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 FMP0417CAx-W70E Customer Fidelix Co., Ltd.

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FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 Document Title 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM

Revision History

PreliminaryFeb.21st, 2008Generated new datasheet0.0 RemarkDraft dateHistoryRevision No.

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 256K x 16 bit Super Low Power and Low Voltage Full CMOS RAM PIN DESCRIPTION Do Not Use DNUData Inputs/OutputsI/O1~I/O16 Core PowerVCCLow Power Modes/ZZ Lower Byte(I/O 1~8)/LBAddress InputsA0~A17 Upper Byte(I/O9~16)/UBWrite Enable Input/WE GroundVSSOutput Enable Input/OE I/O PowerVCCQChip Select Input/CS FunctionNameFunctionName

FEATURES

  • Process Technology : Full CMOS
  • Organization : 256K x 16
  • Power Supply Voltage : 2.7~3.3V
  • Three state output and TTL Compatible
  • Separated I/O power(VCCQ) & Core power(VCC)
  • Automatic power-down when deselected PRODUCT FAMILY ISB1 (CMOS Standby Current) ICC2 ICC1 Max.Typ. 25mA Max.Typ. Max.Typ.Min. 70uA3.0 Typ.Max. 30uA15mA3mA1.5mA70ns3.32.7Extended (-25~85’C)FMP0417CAx-W70E Operating Voltage (V) f = fmaxf = 1MHz Power Dissipation SpeedOperating TemperatureProduct Family FUNCTIONAL BLOCK DIAGRAM Precharge circuit.Clk gen. VCC VSS Memory arrayRow Addresses I/O Circuit Column select Data cont Data cont Column Addresses Data cont Control Logic /CS /ZZ /OE /WE /UB /LB I/O9~I/O16 I/O1~I/O8 Row select 1. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at Vcc = Vcc (typ) and TA = 25C. 2. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER
  • Low Power & Page Modes FMP0417CA1 : support the PASR/DPD function FMP0417CA2 : support the Direct DPD function FMP0417CA4 : support the PASR/DPD/PAGE function FMP0417CA5 : support the Direct DPD/PAGE function
  • Page read/write operation by 16 words (FMP0417CA4, FMP0417CA5)
  • DPD mode by using MRS only (FMP0417CA1, FMP0417CA4)
  • Direct DPD mode when /ZZ goes low (FMP0417CA2, FMP0417CA5)

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 PRODUCT LIST Wafer, 70ns, VCC=3.0V, VCCQ=3.0VFMP0417CAx-W70E FunctionPart Name Extended Temperature Products(-25~85’C) FUNCTIONAL DESCRIPTION ABSOLUTE MAXIMUM RATINGS1) ’C-25 to 85TAOperating Temperature ’C-65 to 150TSTGStorage temperature W1.0PDPower Dissipation V-0.2 to 3.6VccVoltage on Vcc supply relative to Vss V-0.2 to Vcc+0.3VVIN, VOUTVoltage on any pin relative to Vss UnitRatingsSymbolItem 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for Industria lp e r i o d s may affect reliability. RECOMMENDED DC OPERATING CONDITIONS1) -0.23) 0.8VCCQ 2.7 2.7 Min FMP0417CAx 0.2VCCQ VCC+0.22) 3.3 3.3 Max VVCCSupply voltage VVILInput low voltage VVIHInput high voltage VVSSGround VVCCQI/O operating voltage UnitSymbolItem Note : 1.TA=-25 to 85’C, otherwise specified. 2. Overshoot : Vcc+1.0V in case of pulse width≤20ns. 3. Undershoot : -1.0V in case of pulse width≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. 1. F=FBGA, G=FBGA(Pb-Free), H=FBGA(Pb-Free & Halogen Free), W=WAFER Direct DPD2)DeselectedHigh-ZHigh-ZX1)X1)X1)X1)LX1) ActiveWord WriteDinDinL L ActiveUpper Byte WriteDinHigh-ZLH ActiveLower Byte WriteHigh-ZDinHL LX1) ActiveWord ReadDoutDoutLL ActiveUpper Byte ReadDoutHigh-ZLH ActiveLower Byte ReadHigh-ZDoutHL HL HL ActiveOutput DisabledHigh-ZHigh-ZLX1)HHH ActiveOutput DisabledHigh-ZHigh-ZX1)LHHH L StandbyDeselectedHigh-ZHigh-ZHHX1)X1)HX1) Low Power Modes3)DeselectedHigh-ZHigh-ZX1)X1)X1)X1)LH StandbyDeselectedHigh-ZHigh-ZX1)X1)X1)X1)HH PowerModeI/O9-16I/O1-8/UB/LB/WE/OE/ZZ/CS 1. X means don’t care.(Must be low or high state) 2. In case of FMP0417CA2 & FMP0417CA5 product 3. In case of FMP0417CA1 & FMP0417CA4 product

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 DC AND OPERATING CHARACTERISTICS 1. Capacitance is sampled, not 100% tested. CAPACITANCE1) (f=1MHz , TA=25’C) Max Min pFVIO=0VCIOInput/Output capacitance pFVIN=0VCINInput capacitance UnitTest ConditionSymbolItem uA70--/CS≥VCC-0.2V, /ZZ≥VCC-0.2V, Other inputs=0~VCCISB1Standby Current(CMOS) uA10--/ZZ≤0.2V, Other inputs=0~VCC, No refresh(DPD)ISB0 Low Power Modes uA55--/ZZ≤0.2V, Other inputs=0~VCC, ¼ refresh area selectionISB0a uA60--/ZZ≤0.2V, Other inputs=0~VCC, ½ refresh area selectionISB0b uA70--/ZZ≤0.2V, Other inputs=0~VCC, All refresh area selectionISB0c uA1--1/CS=VIH, /ZZ=VIH, /OE=VIH or /WE=VIL, VIO=VSS to VCCILOOutput leakage current uA1--1VIN=VSS to VCCILIInput leakage current mA31.5-Cycle time=1us, 100%duty, IIO=0mA, /CS≤0.2V, /ZZ=VIH, VIN≤0.2V or VIN≥VCC-0.2VICC1 Average operating current V0.2VCCQIOL=0.5mAVOLOutput low voltage mA2515-Cycle time=Min, IIO=0mA, 100% duty, /CS=VIL, /ZZ=VIH, VIN=VIL or VIHICC2 V0.8VCCQIOH=-0.5mAVOHOutput high voltage 0.3 Max Typ Min mA/CS=VIH, /ZZ=VIH, Other inputs=VIH or VILISBStandby Current(TTL) UnitTest ConditionsSymbolItem AC Input/Output Reference Waveform NOTE: 1. AC test inputs are driven at VCCQ for a logic 1 and VSS for a logic 0. Input rise and fall times (10% to 90%) < 1.6ns. 2. Input timing begins at VCCQ/2. 3. Output timing ends at VCCQ/2. AC Output Load Circuit DUT 50Ω 30pF Test Point VCCQ/2 Test Points VCCQ/23VCCQ/2 2 VCCQ VSS Input1 Output

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 AC CHARACTERISTICS(VCC=2.7V~3.3V, Extended product : T A=-25 to 85’C) 1. /CS High Pulse Width is defined by /CS or (/UB and /LB) because /UB & /LB can make standby mode when /UB=High and /LB=High. Maximum Cycle Time Page Mode Address Access Time Page Mode Cycle Time ns-25tPC Page ns25-tPAA ns20k-tMRC ns-10tCP/CS High Pulse Width ns-5tOWEnd Write to Output Low-Z ns-0tDHData Hold from Write Time ns-20tDWData to Write Time Overlap ns50tWHZWrite to Output High-Z ns-0tWRWrite Recovery Time ns-50tWPWrite Pulse Width ns-60tBW/UB, /LB Valid to End of Write ns-60tAWAddress Valid to End of Write ns-0tASAddress Set-up Time ns-60tCWChip Select to End of Write ns20K70tWCWrite Cycle Time Write ns-5tOHOutput Hold from Address Change ns50tOHZOutput Disable to High- Z Output ns50tBHZ/UB, /LB Disable to High- Z Output ns50tHZChip Disable to High- Z Output ns-5tOLZOutput Enable to Low-Z Output 70ns ns-10tBLZ/UB, /LB Enable to Low-Z Output ns-10tLZChip Select to Low-Z Output ns70-tBA/UB, /LB Access Time ns25-tOEOutput Enable to Valid Output ns70-tCOChip Select to Output ns70-tAAAddress Access Time ns20K70tRCRead Cycle Time Read MaxMin UnitsSymbolParameter List

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 Power Up Sequence 1. Apply Power 2. Maintain stable power for a minimum of 200us with /CS=V IH Standby Mode State Machines Standby Mode Characteristics Initial State Standby Mode Active Mode Low Power Modes 1 (4M/2M/1M bits) Power On /CS=VIL /ZZ=VIH /CS=VIH (or/and /UB=/LB=VIH) /ZZ=VIH /CS=VIH /CS=VIH, /ZZ=VIL /CS=VIL, /ZZ=VIH /UB or/and /LB=VIL Low Power Modes 2 (Data Invalid) Wait 200us /CS=VIH, /ZZ=VIL /CS=VIH, /ZZ=VIL /CS=VIH /ZZ=VIL /CS=VIL /ZZ=VIH /CS=VIH, /ZZ=VIH 055 (ISB0a)¼v a l i d 060 (ISB0b)½v a l i d 20010 (ISB0)Invalid Low Power Modes 070 (ISB0c)valid 070 (ISB1)ValidStandby Mode Memory Cell Data Wait Time(us)Standby Current(uA)

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 READ CYCLE (2) (/ZZ=/WE=VIH) 1. tHZ and tOHZ are defined as the ti me at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. Address tAA tCO tBA tOE tOH tOLZ tBLZ tLZ Data ValidHigh-Z tHZ tBHZ tOHZ /CS /UB, /LB /OE Data Out tRC READ CYCLE (1) (Address controlled,/CS=/OE=VIL, /ZZ=/WE=VIH, /UB or/and /LB=VIL) Address Data Out tRC Previous Data Valid Data Valid tAA tOH 1. tHZ and tOHZ are defined as the ti me at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 4. In case page address skew is over 3ns, tPAA will be out of spec. PAGE READ CYCLE (/ZZ=/WE=VIH, 16 words access) A0~A3 tAA tCO tBA tOE High-Z tHZ tBHZ tOHZ /CS /UB, /LB /OE Data Out tRC A4~A17 tOH tPC tPC tPC tPC tPC tPC tPC tPAA tPAA tPAA tPAA tPAA tPAA tPAA tLZ tBLZ tOLZ Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid tMRC

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 WRITE CYCLE (2) (/CS controlled, /ZZ=VIH) Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2)tAS(3) tAW WRITE CYCLE (3) (/UB, /LB controlled, /ZZ=VIH) 1. A write occurs during the overlap (tWP) of lo w /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneou sly asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. Address /CS /UB, /LB /WE Data Out tWC tWR(4) tBW tWP(1) High-Z High-Z Data Valid tDW tDH Data in tCW(2) tAW tAS(3) WRITE CYCLE (1) (/WE controlled, /ZZ=VIH) Address /CS /UB, /LB /WE Data Out tWC tCW(2) tWR(4) tAW tBW tWP(1) tAS(3) High-Z High-Z Data Undefined Data Valid tDW tDH tOWtWHZ Data in

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 1. A write occurs during the overlap (tWP) of lo w /CS and /WE. A write begins when /CS goes low and /WE goes low with asserting /UB or /LB for single byte operation or simultaneou sly asserting /UB and /LB for double byte operation. A write ends at the earliest transition when /CS goes high and /WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the /CS going low to end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS or /WE going high. 5. Do not access device with cycle timing shorter than tRC(tWC) for continuous periods > 20us. 6. In case page address is over 3ns, write to the invalid address can occur. PAGE WRITE CYCLE (Address controlled, /ZZ=VIH) A4~A17 /CS /UB, /LB /WE Data Out tAS(3) High-Z Data Undefined Data Valid tDW tOW tWHZ Data in A0~A3 tWC tPC tPC tPC tPC tPC tPC tPC High-Z tDH Data Valid tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW tDH tDW Data Valid Data Valid Data Valid Data Valid Data Valid Data Valid tMRC

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 LOW POWER MODES 1. Mode Register Set A0A1A2A3A4A17 ~ A5 Array Refresh AreaHalf SelectionArray On/Off on /ZZ ZZ Enable/Disable0 /ZZ Enable/Disable DPD Disable (Default)1 Deep Power Down Enable0 TypeA4 Array On/Off on /ZZ Reduced Memory Size Mode1 Partial Array Refresh Mode (Default)0 TypeA3 Note: If the register is written to enable the Deep Power Down, the part will go into Deep Power Down during the following time that /ZZ is driven low and there is no MRS update. When /ZZ is driven high, all of the register settings will return to default state for the part (i.e. full array refresh, Deep Power Down Disabled). Note: The RMS(Reduced Memory Size) mode is enabled after /ZZ goes high and remains enabled after /ZZ goes high. To change to a different mode, the mode register will have to be rewritten. Half Selection (Top / Bottom) Top1 Bottom (Default)0 TypeA2 Array Refresh Area RFU10 ½A r r a y01 ¼A r r a y1 Full Array (Default)0 TypeA0 2. MRS Update Address /CS /UB, /LB /WE tWC tWR(4) tBW tWP(1) tCW(2)tAS(3) tAW /ZZ tZZWE Register Write Start Register Write Complete Register Update Complete The register update take place on the rising edge of /ZZ. Once the register is updated, the next time /ZZ goes low, without any updates to the register starting within the tZZWE max time of 1us, the part will refresh the array selected. The data bus is a don’t care When /ZZ is low during the register updates.

FMP0417CAx-W70E CMOS LPRAM Revision 0.0 Feb. 2008 2Mb128Kbx1620000h-3FFFFh1/2101 1Mb64Kbx1630000h-3FFFFh1/4111 4Mb256Kbx1600000h-3FFFFhFull00X 2Mb128Kbx1600000h-1FFFFh1/2100 1Mb64Kbx1600000h-0FFFFh1/4110 DensitySizeAddressRefresh SectionA1,A0A2 Partial Array Refresh Mode (A3=0, A4=1) Reduced Memory Size Mode (A3=1, A4=1) 3. Deep Power Down Mode Entry/Exit 4. Address Information tZZmin tR /CS /UB, /LB /WE tWC tWR(4) tBW tWP(1) tCW(2) tAS(3) tAW /ZZ tZZWE Register Write(DPD) Deep Power down start Deep Power down exit Next Cycle 2Mb128Kbx1620000h-3FFFFh1/2101 1Mb64Kbx1630000h-3FFFFh1/4111 2Mb128Kbx1600000h-1FFFFh1/2100 1Mb64Kbx1600000h-0FFFFh1/4110 DensitySizeAddressRefresh SectionA1,A0A2 us-10Low Power Mode TimetZZmin us-200Operation Recovery TimetR(Deep Power Down Mode only) us10ZZ low to Write Enable LowtZZWE UnitsMaxMinDescriptionParameter