ES5120 CYRUSTEK | Alldatasheet
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１． GENERAL DESCRIPTION The ES5120 is a 3 3/4 digit measurement system which combines integrating analog-to-digital converter, frequency counter,and logic level tester in either 40-pin DIP package or 44-pin QFP package ． The high level of integration permits ES5120-based instruments to deliver higher pe rformance and more features while actually reducing parts count. With a maximum range of 3999 counts, the ES 5120 provides 10 times greater resolution in the 200m V to 400mV range than traditional 3 1/2 digit mete rs. An autozero cycle guarantees a zero reading with a 0V input. CMOS Processing reduces analog input bias current to on ly 1PA. Rollover error, th e difference in readings for equal magnitude but opposite polarity input signals, is less than ± 1 Count. Differential reference inputs permit ratiometric measurem ents for ohms or bridge transducer applications. The ES5120's frequency counter opti on simplifies design of an instrument which is well suited to both analog and digital troubleshooting : voltage, current, and resistance measurements plus precise frequency measurements to 4 MHz (higher frequencies can be measured with an external pr escaler) and a simple logic probe. The frequency counte r will automatically adjust its range to match the input frequency, over a four decade range.
Two logic level measurement inputs permit a ES5120-based meter to function as a logic probe. When combined with ex t e r n a l level shifters, the ES5120 will display logic levels on the LCD display and also turn on a piezoelectri c buzzer when the measured logic level is low. Other ES5120 features simplify inst rument design and reduce parts count. On-chip decimal point driver s are included, as is a low battery detection annunciator. A pi ezoelectric buzzer can be controlled with an external switch or by the logic probe inputs. Two oscillator options are provided : A crystal can be used if high accuracy frequency meas urements are desired, or a simple RC option can be used for low-end instruments. A 'peak reading hold' input allows the ES5120 to retain the highest A-D or frequency readin g. This feature is useful in measuring motor starting current , maximum temperature, and similar applications. The ES5120 operates from a si ngle 9V battery, with typical power of 16mW. Packages incl ude a 40-pin DIP and 44-pin Flat Package.
２．FEATURES ■ Multiple-Function Measurement System z Analog to digital Converter z Frequency Counter z Logic Probe ■ Frequency Counter z Measures Input Frequency to 4 MHz z Autoranging Over Four Decade Range ■ Logic Probe Inputs z 2 LCD Annunciators z Buzzer Drive (with Two Types of Buzzer Frequencies, 5 KHz and 2.5KHz, for choice) ■ Peak Reading Hold with LCD Annunciator ■ 3 3/4 Digit(3999 Maximum) Resolution ■ Low Noise A-D Converter z Differential Inputs, 1 pA Bias Current z Differential Reference for Ratiometric Ohms z On-Chip Voltage Reference, 60 ppM/℃ Drift ■ No External LCD Drivers Required z Full 3 3/4 Digit Display z Displays "OL" for Input Overrange
z Three Decimal Point and Polarity Drivers z LCD Annunciator Drive z Adjustable LCD Drive Voltage ■ Low Battery Detect with LCD Annunciator ■ On Chip Buzzer Driv er and Control Input ■ Control Input Changes Full Scale Range by 10:1 ■ Data Hold Input ■ Underrange and Overrange Outputs ■ Multiple Package Options z 40-pin DIP Package z 44-pin Flat Package
３．TYPICAL APPLICATION 0.1μF
４．FUNCTIONAL BLOCK DIAGRAM
５．PIN ASSIGNMENT ES5120AZ ES5120BZ ES5120AQ ES5120BQ
６．PIN DESCRIPTION AND FUNCTION P i n N o . P i n N o . (40-pin (44-pin Flat Package) Pack age) Symbol Descrlption 1 40 L-E4 LCD segment drive for L("l ogic low"),polarity,and"e"segment of most significant digit (MSD) 2 41 AGD4 LCD segment drive for" a","g",and"d"segments of MSD 3 42 BC4P3 LCD segment drive for"b"and"c"segments of MSD and decimal point 3 4 43 HFE3 LCD segment drive for H("logi c high"), and"f"and"e"segment of 3rd LSD 5 44 AGD3 LCD segment drive for"a","g", and"d"segments of 3rd LSD 6 1 BC3P2 LCD segment drive for"b"and" c"segments of 3rd LSD and decimal point 2. 7 2 OFE2 LCD segment driver for"overra nge",and"f"and"e"segments of 2nd LS 8 3 AGD2 LCD segment drive for"a","g",and"d"segments of 2nd LSD. 9 4 BC2P1 LCD segment drive for"b"and" c"segments of 2nd LSD and decimal point 1. 10 5 PKFE1 LCD segment drive for "hold peak reading", and"f"and"e"segments of LSD 11 6 AGD1 LCD segment drive for"a","g",and"d"segments of LSD.
P i n N o . P i n N o . (40-pin (44-pin Flat Package) Package) Symbol Descrlption 12 7 BC1BT LCD segment drive for"b" and"c"segments of LSD and "low battery". 13 8 BP3 LCD backplane #3. 14 9 BP2 LCD backplane #2. 15 10 BP1 LCD backplane #1.
11 VDISP Sets peak LC D drive signal : VPEAK=(V+)-VDISP may also be set to
compensate for temperature vari ation of LCD crystal threshold voltage.(default: The VDISP pin is connected to DGND.) 16 12 DGND Internal logic digital ground , the logic "O" level. Nominally 4.7V below V＋ 17 13 ANNUNC Square wave output at th e backplane frequency, synchronized to BP1 ANNUNC can be used to control display annunciators. Connecting an LCD segment to ANNUNC turns it on; connecting it to its backplane turns it off. 18 14 LOGIC "Logic Mode" control input. When connected to V＋ the converter is in logic mode. The LCD disp lays "OL" and the decimal point inputs control the "high" and "l ow" annunciators. When the "low" annunciator is on, the buzzer will also be on. When unconnected or connected to DGND, the ES5120 is in the voltage frequency measurement mode. This pin has a 5 μA internal pulldown to DGND.
P i n N o . P i n N o . (40-pin (44-pin Flat Package) Pack age) Symbol Descrlption 19 15 RANGE/ FREQ Dual-purpose input.In voltage mode:When connected to V ＋; the FREQ integration time will be 200 counts instead of 2000 counts,and the LCD will display th e analog input divided by 10. In frequency mode, this pin is the frequency input. A digital signal applied to this pin will be meas ured with a one second timebase. There is an internal 5μA pulldown to DGND. 20 16 DP0/LO Dual-purpose input. Decima l Point select input for voltage measurements. In logic mode, connecting this pin to V ＋ will turn on "low" LCD segment. Th ere is an internal 5 μA pulldown to DGND in volts mode only. Decimal point logic: DP1 DP0 Decimal Point Selected
00 N o n e
01 D P 1
10 D P 2
11 D p 3
21 17 DP1/HI Dual-purpose input. Decima l Point select input for voltage measurements. In logic mode, connecting this pin to V ＋ will turn on the "high" LCD segment. There is an internal 5μA pulldown to DGND in volts mode only. 22 18 BUZOUT Buzzer output. Audio fre quency, 2.5K or 5.0K for choice determined by chip bonding, output which drives a piezo buzzer.
P i n N o . P i n N o . (40-pin (44-pin Flat Package) Pack age) Symbol Descrlption 23 19 BUZIN Buzzer control input. Connecting BUZIN to V ＋ turns the buzzer on. BUZIN is logically ORed(inter nally) with the "l ogic level low" input. There is an internal 5μA pulldown to DGND. 24 20 FREQ/ VOLTS V oltage or frequency measurement select input. When connected to DGND, the a-d converter function is active. When connected to V ＋ the frequency counter function is active. This pin has an internal 5μA pulldown to DGND. 25 21 PKHOLD Peak Hold input. Wh en connected to V ＋, the converter will only update the display if a new conver sion value is greater than the preceeding value. Thus, the peak reading will be stored and held indefinitely. When unconnected or connected to DGND, the converter will operate normally. This pin has an internal 5 μA pulldown to DGND. (Note : This pin may be with the function of EOC/HOLD which depends on chip bonding.) 22 UR Underrange output. This output will be high when the digital reading is 380 counts or less. 23 OR Overrange output. This output w ill be high when the analog signal input is greater than full scale. The LCD will di splay "OL" when the input is overranged.
P i n N o . P i n N o . (40-pin (44-pin Flat Package) Pack age) Symbol Descrlption 26 24 V- Negative supply connection. Co nnect to negative terminal of 9V battery. 27 25 COM Analog circuit ground reference point. Nominally 3.3V below V＋. 28 26 C REF + Positive connection for reference capacitor. 29 27 C REF - Negative connection for reference capacitor. 30 28 V REF + High differential reference input connection. 31 29 V REF - Low differential reference input connection. 32 30 V IN - Low analog input signal connection. 33 31 V IN + High analog input signal connection. 34 32 V BUFF Buffer output. Connect to integration resistor. 35 33 C AZ Autozero capacitor connection. 36 34 V INT Integrator output. Connect to integration capacitor.
35 EOC/
Bidirectional pin. Pulses low (i.e . from V+ to DGND) at the end of each conversion. If connected to V+ , conversions will continue but the display is not updated. 37 36 OSC1 Crystal oscillator (input) connection. 38 37 OSC2 Crystal oscillator (output) connection. 39 38 OSC3 RC oscillator connection. 40 39 V+ Positive power supply connection. Typically 9V .
７．ABSOLUTE MAXIMUM RATING Characteristic Rating Supply Voltage (V+ to V-) 1 2 V Analog Input Voltage (either input) V + to V- Reference Input Voltage (either input) V + to V- Digital Inputs DGND to V + Power Dissipation (plastic package) 800 mW Operating Temperature 0 ℃ to +70 ℃ Storage Temperature -65 ℃ to +160 ℃ Lead Temperature (soldering, 10 sec) 2 7 0 ℃ ※ Note ：There are ten pins for Analog section, such as COM, C REF +,CREF VREF +, VREF -, VIN +, VIN -, VBUFF, CAZ, and V INT and the others are related to Digital section.
８．ELECTRICAL CHARACTER ISTICS At V+=9V，fosc 40KHZ，TA=25℃ unless otherwise noted Characteristic Test Conditions Limit Units Zero Input Reading VIN＝0.0V Full-Scale=400.0mV -000.0 ±000.0 +0 00.0 Digital Reading Ratiometric Reading V IN=VREF VREF=200mV 1999 1999/ 2000
2000 Digital
(Max. deviation from best straight line fit) Full-Scale=400mV ± 0.2 Counts Roll-over Error -V IN=+VIN=390.0mV -1 ± 0.2 +1 Counts Common Mode Rejection Ratio VCM=± 1V, VIN=0V Full-Scale=400.0mV － 50 －μ V/V Noise VIN=0V, Full-Scale=400.0mV － 15 －μ Vp-p Zero Reading Drift VIN=0V 0℃≦TA≦70℃ － 0.2 1 μV/℃ Scale Factor Temperature Coefficient V IN=399.0mV 0℃≦TA≦70℃(Ext. Ref.= 0 ppm/℃ ppm/℃ Analog COMMON Voltage (with respect to V+) 25KΩ between Common and Positive Supply 3.15 3.3 3.45 V Analog COMMON Temperature Coefficient 25KΩ between Common and V 0℃≦TA≦70℃ － 30 ppm/℃ Back plane Drive Voltage(Peak To Peak) V+ to V-＝9V 4.5 5.0 5.5 V Supply Current (Does not include COMMON current) V IN＝0V － 1.2 1.7 mA
ELECTRICAL CHARACTERISTICS (contd.) Limit Characteristic Test Conditions Min. Typ. Max. Units Buzzer Freguency fosc = 40.0 KHz 5.0/2.5 KHz Counter Timebase Period fosc = 40.0 KHz 1 second Low Battery Flag Voltage V+ to V- 6.7 7.0 7.3 V Control pin Pulldown Current 5 μA Note 1:Two types of Buzzer Frequencies for choice determined by chip bonding. Limit Characteristic Test Conditions Min. Typ. Max. Units Input Low Voltage －－ DGND +1.5V V Input High Voltage V+ -1.5V －－ V Output, Low Voltage UR、OR、Outputs 1L=50uA －－ DGND +0.4V V Output High Voltage UR、OR Outputs 1N=50uA V+ -1.5V －－ V
９．TEST CIRCUIT
9.1 General Function Test
0.1μF
9.2 ICCQ Test
0.1u
１０．ERAL THEORY OF OPERATION
10.1 Analog Section :
In addition to the basic integrate and deintegrate dual slope phases discussed above, the ES5120 design incorporates an "Auto Zero" ph ase. The additional phase ensure that the integrator star ts at zero volts (even after a severe over-range conversion) and that all offset voltage errors (buffer amplif ier, integrator and compar- ator) are removed from the conversion. A true digital zero reading is assured without any external adjustments. A complete conversion consists of four distinct phases : (1) Auto Zero Phase (2) Signal Integrate Phase (3) Reference Deintegrate Phase (4) ADC SYSTEM Timing (1) Auto Zero Phase During the Auto Zero phase, the differential input signal is disconnected from the meas urement circuit by opening internal analog switches and th e internal nodes are shorted to Analog Common (0 volt ref.) to establish a zero input condition. Additional analog switches close a feedback loop around the integrator and comparator to permit
comparator offset voltage error compensation. A voltage established on C AZ then compensates for internal device offset voltages during the measurement cycle. The Auto Zero phase residual is typically 10 to 15μA. (2) Signal Integration Phase Upon completion of the Auto Zero phase, the Auto Zero loop is opened and the intern al differential inputs connect to V IN + and V IN -. The differential in put signal is then integrated for a fixed time pe riod, which in the ES5120 is 2000 counts (4000 clock period s). The externally set clock frequency is divided by two be fore clocking the internal counters. The integration time period is : 4 0 0 0 f o s c The differential input voltage must be within the device common-mode range when the converter and measured system share the same power supply common (ground). If the converter and measured system do not share the same power supply common as in ba ttery powered applications, V IN- should be tied to Analog Common. Polarity is determined at the end of signal integration phase. The sign bit is a "true polar ity" indication in that signals less than 1 LSB are correctly determined. This allows precision null detection whic h is limited only by device noise and Auto Zero residual offsets.
V VVI2000 (3) Reference Integrate (Deintegrate) Phase The reference capacitor, whic h was charged during the A u t o Z e r o p h a s e , i s c o n nected to the input of the integrating amplifier. The inte rnal sign logic ensures that the polarity of the reference vo ltage is always connected in the phase which is opposite to that of the input voltage. This causes the integrator to ramp back to zero at a constant rate which is determined by the reference potential. The amount of time required (T DEINT) for the integrating amplifier to reach zero is di rectly proportional to the amplitude of the voltage that was put on the integrating capacitor (VINT) during the integration phase : The digital reading displayed is : Digital Count ＝ (4) ADC System Timing The oscillator frequency is divi ded by 2 prior to clocking the internal decade count ers. Each phase of the measurement cycle has the following length : Auto Zero : 1999 to 5999 counts Signal Integrate : 2000 counts Deintegrate : 1 to 4001 counts REF INTINTINT DEINT V VCRT =
10.2 Frequency counter th eory of Operation :
In addition to serving as an analog to digital converter, the ES5120 internal counter can also function as a frequency counter, (Figure 5). In the counter mode, pulses at the RANGE/FREQ in put will be counted and displayed. The ES5120 frequency counter derives its timebase from the colck oscillator. The counter time base is : 4,000,000 Tcounter = Fosc Thus, the counter will operate with a 1 second timebase when a 40 kHz oscillator is used. The frequency counter accuracy is determined by the oscillator
accuracy. For accurate frequenc y measurements, a crystal oscillator is recommended. The frequency counter will automatically select the proper range. Autorange operation extends over four decades, from 3.999 kHz to 3.999 MHz. Decimal points are set automatically in the frequency mode, (Figure 6). The logic switching levels of the RANGE/FREQ input are CMOS levels. For best counter operation, an external buffer is recommended.
10.3 Logic Probe Theory of Operation :
This mode is selected when the LOGIC input is high. Two dual purpose pins, which norma lly control the decimal points, are used as logic inputs. Conne cting either input to a logic high level will turn on the correspondi ng LCD annunciator, Also when the "low " annunciator is on the buzzer will be on. As with the Frequency Counter input, external level shifters/buffers are recommende d for the logic probe inputs. (Fig.7)
When the logic probe fu nction is selected while FREQ/VOLTS is low (A/D mode). th e analog to digital converter will remain in the autozero mode. The LCD display will read "OL" and all decima l points will be off. (Fig. 6 - Display) If the logic probe is active while FREQ/VOLTS is high (counter mode) the frequency counter will continue to operate. The display will read "OL" but the decimal points will be visible. If the logic probe input is also conn ected to the RANGE/FREQ input, then bringing the LOGIC input low will immediately display the frequency at the logic probe input.
10.4 Selection of operating Mode
inputs. The control input truth table is shown in Table 1. Table 1. Control Input Truth Table
10.5 LCD Display
The ES5120 drives a triplex (m ultiplexed 3:1) liquid crystal display with three backplanes . The LCD display can include decimal points, polarity sign, and annuciators for overrange, peak hold, high and low logic levels, and low battery Fig. 8 shows the assignment of the display segments to the backplanes and the segment driv e lines. The back plane drive frequency is obtaine d by dividing the os cillator frequency by 240. 40-pin DIP Pin No 44-pin QFP Pin No BP1 BP2 BP3 14 0 L o w 〝―〞 E4 24 1 A 4 G 4 D 4 34 2 B 4 C 4 D P 3 44 3 H I G H F 3 E 3 54 4 A 3 G 3 D 3 6 1 B3 C3 DP2 7 2 OVER F2 E2 8 3 A2 G2 D2 9 4 B2 C2 DP1 10 5 PEAK F1 E1 11 6 A1 G1 D1 12 7 B1 C1 BATT 13 8 BP3 14 9 BP2 15 10 BP1 F i g . 8 L C D B ackplane and Segment Assignments
Backplane waveform are shown in Fig. 9. These appear on output BP1, BP2, and BP3. They remain the same regardless of the segments being driving. Other display output lines have waveforms that vary depending on the displays va lues. Fig. 10 shows a set of waveforms for the AGD outputs of one digit for several combinations of "ON" segments.
１１．包裝(Package) 44-pin QFP package