ES5136 CYRUSTEK | Alldatasheet
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3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) I、GENERAL DESCRIPTION The ES5136 combines analog section and digital section on a single monolithic CMOS integrated circuit to provide a high performance, very low power 3 1/2 –digit A/D converter. Each device includes a dual slope converter, inte rnal reference, seven segment decoders, display drivers, and clock. The ES5136 is designed to interface with a liquid crystal displa y and includes a back plane drive. The supply current is only 150 µA, very suitable for 9V battery operation. To built a high performance dig ital panel meter, ES5136 needs only few passive components and a LC D display. The true differential input and reference of ES5136 are vers atile and useful in all systems, and these give the designers an uncommon advantage to make the measurement of load cells, trai n gauges and other bridge type transducers. The ES5136 can be used as a pl ug-in replacement for the ES5106 in a wide variety of applica tions by changing only the passive components of the ES5106. The ES5136 differs from the ES5106 in that it includes lower power dissipation, improved temperature coefficient of analog common and scale factor, and the design of ZERO INTEGRATE phase to elim inate the overrange hangover and hysteresis.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) II、FEATURES *Pin compatible with ES5106. *Internal reference with low temperature drift *Direct LCD display drive *No additional active components required *Low input leakage current---1pA typical *Guaranteed zero reading for 0 volts input on all scales *Auto polarity indication *True differential input and reference *Internal clock circuit *Low power consumption III、APPLICATTONS *Digital panel meters *Digital multi-meters *Digital centigrade thermometer *pH meters *Capacitance meters
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) IV、PIN ASSIGNMENT
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) P I N A S S I G N M E N T NC NC TEST OSC3 NC OSC2 OSC1 AB4 POL BP NC REF HI REF LO CREF + CREF - COM IN HI IN LO AZ BUF INT ES5136Q 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) V、BLOCK DIAGRAM
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) VI、ABSOLUTE MAXIMUM RATING Lead Temperature(during soldering): At distance 1/16±1/32 inch(1.59±0.79mm)from case for 10S max +265 ℃ VII、ELECTRICAL CHARACTERISTICS AT TA = 25℃,V+ to V- = 9V , fcolock = 48Khz unless otherwise indicated. Refer to Fig.2. CHARACTERISTIC TEST CONDITIONS LIMITS MIN TVP MAX UNITS Zero Input Reading V IN=0.0V -000.0 ±000.0 +000.0 Digital Reading Ratiometric Reading V IN = VREF VREF = 100mV 999 999/1000 1000 Digital Reading ROLLOVER Error -VIN = +VIN≅200.0mV -1 ±0.2 +1 Counts Linearity Full Scale = 200mV or 2V -1 ±0.2 +1 Counts Common Mode Rejection Ratio VCM = ± 1V,VIN = 0V Full Scale = 200.0mV － 50 － µV/V Input Leakage Current V IN = 0V － 11 0 p A
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) ELECTRICAL CHARACTERISTICS(Contd.) LIMITS CHARACTERISTIC TEST CONDITIONS Min Typ Max Units Noise (P K-PK value not exceeded 95% of time) VIN = OV Full Scale = 200mV － 15 － µV Zero Reading Drift V IN = 0V 0℃<TA<70℃ － 0.2 － µV/℃ Scale Factor Temperature Coefficient VIN = 199.0mV 0℃<TA<70℃ (Ext. Ref.0 ppm/℃) － 15 ppm/℃ Supply Current (Does not include COMMON current) VIN = 0V (not 1) － 150 180 µA Analog COOMON Voltage (with respect to V+)
250 KΩ between
COMMON & V+ 2.8 3.0 3.2 V Temp. Coeff. of Analog COMMON (with respect to V+) COMMON & V+ － 50 75 ppm/℃ PK-PK Segment Drive Voltage V+ to V- = 9V 4 5 6 V PK-PK Backplane Drive Voltage V+ to V- = 9V 4 5 6 V Power Dissipation Capacitance VS. Clock Freq － 40 － pF Note 1:During auto zero phase, current is 10-20µA higher.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) VIII、TEST CIRCUIT
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) DX、FUNCTION DESCRIPTION A、Analog Section The Analog Section of the ES5136 is a dual slope converter, which is shown in Figure 1. The conversion takes place in four distinct phases. 1.Phase 1, Auto Zero (A/Z) During auto zero processing, the inte rnal A/Z switches are turned on. The errors in the analog components(offset voltage of buffer, integrator and comparator)will be automatically nulled out by shorting the input internally to COMMON a nd closing a feed back loop such that error information is stor ed on the auto-zero capacitor C AZ At the same time. the reference capacitor is charged to the reference voltage VREF. 2.Phase 2, Signal Integrate(INT) During signal integrating, the A/Z switches are opened and the INT switches are closed for 1,000 system clock pulses. The integrating capacitor will ramp up at a rate th at is proportional to input voltage VIN. At the end of this phase the pol arity of the integrated signal is determined. 3.Phase 3, Reference Deintegrate(DE) At the beginning of this phase, the input low is internally connected to COMMON and input high is switched from V IN to. VREF According to the polarity, the integrator will disc harge back toward zero. The nuber of system clock pulses counted be tween the beginning of this cycle and the time when the integrator output passes through zero is a digital measure of the magnitude of input voltage. Specifica lly the digital reading displayed is 1000(VIN/VREF).
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) 4.Phase 4, Zero Integrate (ZI) During zero integrating, the refere nce capacitor is charged to the reference voltage and input low is shorted to analog common. At the same time, a feedback loop is clos ed around the system to input high to cause the integrator output to return to zero so that the overrange hangover of the integral capacitor can be eliminated. 5.Differential Input The input voltage can be any differe ntial voltages, but must be within the common mode range of the i nput amplifier(buffer). The voltage range is from 0.5 volts below the pos itive supply to 1.0 volt above the negative supply. In this range the CMRR of the system is 86dB typical. Since the integrator swi ngs with the common mode voltage, it must be assured that the integrator output does not saturate. 6.Differential Reference The reference inputs are floating, and the only restriction on the applied voltage is that it should lie in the ra nge of the owner supply voltage of the converter. The roll- over voltage caused by the reference capacitor losing or gaining charge to stray capacity on its nodes is the main source of common mode e rror. In a large common mode condition, the reference capacitor wi ll gain extral charge(increase voltage)when deintegrates a positi ve signal but lose charge(decrease voltage)when deintegrates a negati ve input signal. The difference in reference for positive or negative i nput signal will gi ve a roll-over error. By selecting the referen ce capacitor large enough in comparison to the stray capacitance, this error can be held to less than 0.5 count for the worst case condition.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) 7. Analog COMMON The voltage between V+ and COMM ON is internally regulated at about 3.1 volts. Thus the COMMON pin can set the common mode voltage for battery operation or for any system where the input signals are floating with respect to the pow er supply. As a reference, the common voltage is adequate for many applications. When the total supply voltage is large enough to cause the zener to regulate(6.4V typical), the common voltage will have a low voltage coefficient(0.001%/%), low output impedance ( ≅10Ω), and a temperature coefficient typically less than 75ppm/℃. The on-chip reference has some limitations. If there is a large temperature variation, the referen ce temperature coefficient may not take over and cause some errors. The other limitation is when the total supply voltage is less than that wh ich will cause the zener to regulate, the common voltage will have a poor voltage coefficient. The problems are of course eliminated if an external refe rence is used, as shown in Figure 3.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) Figure 3:Using External reference During auto-zero and deintegrati ng, analog COMMON is used as the return of input low. If IN LO and COMMON are not connected to the same node, a common mode voltage may exist in the system and is taken care of by the excellent CMRR of the ES5136. When IN LO is set at a fi xed known voltage, COMMON should be tied to the same point of IN LO , thus the common mode voltage can be removed from the converter. The same holds true for the reference voltage. If reference can be refe renced to analog COMMON, it should be since this removes the common mode voltage from output stage of analog COMMON includes an N channel FET that can sink 30mA or more of current to hold the vol tage 3.1 volts below the positive supply . And there is only 1 µA of source current, so the COMMON may easily be tied to a more negative voltage thus over-riding the internal reference. 8. Digital Section The digital section of the ES5136 is shown in Figure 1. A large P channel source follower and a 6 volts zener diode form the internal digital ground of ES5136. This form ation is strong enough to absorb large capacitive currents when the back plane (BP) voltage is switched.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) 1. Test The TEST pin is connected to th e internal digital ground by a 500 Ω resistor. It has two functions. First, it can be used as the negative supply for externally generated segment driv ers such as decimal points or any other presentation on the LCD displa y. Figures 4(a) and (b) show such an application. The applied load curr ent should not be more than 1mA. Second, it is used as “lamp test”. When TEST is connected to V+(pull high)all segments will be turned on and the display should read-1888. The TEST pin will sink about 10mA under this cibdutuib. Figure4: Decimal point drivers Coution:In the lamp test mode, the segments output are no longer a square-wave but a constant DC vo ltage which may destroy the LCD display if left in this mode for extended periods.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) 2. System Clock Following three basic clocking arrangements can be used in the ES5136. a. An external oscillator connected to pin 40 b. A crystal between pins 39 and 40 c. An R-C oscillator using all three pins These arrangements are shown in Figure 5. Figure 5: Clock Circuits The clock frequency is divided by 4 prior to being us ed as the system clock. The system clock is then divi ded to form the four convert-cycle phases. They are signal integrate(1000 counts), reference deintegrate(0 to 2000 counts), zero integrator(11 counts to 140 counts) and auto-zero(910 to 2900 counts). When input signals are less than full scale, the unused portion of reference deinte grate and zero integrator is occupied by auto- zero. Thus a complete measure cycle is 4,000 cunts and is independent of input voltage. When the clock frequency is 48Khz , the conversion tate is 3 readings per second.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) To achieve maximum line frequency( 60Hz) noise reje ction, the signal integrate period should be an integral number of line frequency period. For 60Hz noise rejection, clock fr equency should be one of 24KHz, 120KHz, 80KHz, 60KHz, 48KHz, 34 2/7K Hz, etc. For 50Hz rejection, clock frequencies of 2000Khz, 100 KHz, 66 2/3KHz, etc. would be suitable. Note that 40Khz will reject both 50 and 60Hz. 3. Back Plane and Polarity The back plane(BP)frequency is the system clock frequency divided by 200. For 3 readings/sec conversion ra te, the BP frequency is a 60Hz square wave with a nominal amplit ude of 5 volts. The segments are driven at the same frequency and amplitude of BP, but out of phase when ON and in phase when OFF. In all cases negligible dc voltage exists across the segments. The polarity (POL ) indication is “ON” for negative input signals. X、COMPONENT VALUE SELECTION 1. Oscillator Components For all ranges of clock freque ncy a 50PF or 47PF capacitor is recommended and the approximate resist or values are given in the Table 2. Reference Voltage The relation ship between the full-scale input voltage and the reference voltage is :V IN (full-scale) = 2V REF,for 200mV full scale, the voltage applied between REF HI and REF LO should be set at 100/0mV. For 2V full scale, set reference voltage at 1.000V.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) 3. Integrating Resistor The output stage of the buffer amp lifier and the integrator have a quiescent current of 6 µA. They can supply drive current around 1 µA with negligible non-linearity. The inte grating resistor should be large enough to remain in this very linea r region over the input voltage range, but small enough that undue leakage requirements are not placed on the PC board. For 2V full scale, 1.8M Ω is near optimum and similarly 180KΩ for a 200mV scale. 4.Integrating Capacitor The value of integrating capacitor should be selected to give the maximum voltage swing that ensures tolerance build-up will not saturate the integrator swing(approx. 0.3V from either supply). When the analog COMMON is used as reference, a nominal ±2V full scale integrator swing is recommended. The value of CINT is 0.047 µF for 48Khz clock frequency , and is 0.15 µF for 16Khz clock frequency. If differe nt clock frequencies are used, the value of C INT should be changed in invers e proportion to maintain the same output swing. The integrating capacitor s hould be a low dielectric- loss type to prevent roll-over errors. Long te rm stability and temperature coefficient are unimportant since the dual slope tech nique cancels the effect of these variations. Polypropylene capacitors ha ve been found to work well; they have low dielectric loss characteristics and are inexpensive.
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) 5.Auto-Zero Capacitor Since much of the noise originates in the auto-zero loop, the size of the auto-zero capacitor has some influen ce on the noise of the converter, For 200mV full scale where noise is very important, a 0.33 µF capacitor is recommended. For 2V full scale, a 0.033 µF capacitor can increase the speed of recovery from overload and is adequate for noise on this scale. 6.Reference Capacitor A 0.1 µF reference capacitor is large enough to work well in most applications. When a large common mode voltage exists and a 200mV full scale is used, capacito r of large value is requ ired to prevent roll-over error. Generally 1.0 µF will hold the roll-over er ror to 0.5 count in this instance. CLOCK Freq. RC value 34 2/7Khz 40KHz 48KHz 50KHz 60KHz 66 2/3KHz R(C = 47PF) 280KΩ 240KΩ 200KΩ 190KΩ 160KΩ 140KΩ R(C = 47PF) 250KΩ 220KΩ 180KΩ 170KΩ 140KΩ 120KΩ Table 1: Resistor value VS. Clock Frequency
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) XI、APPLICATION CIRCUITS
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power)
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power)
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) XII、PHYSICAL DIMENSION
3 1/2 DIGIT A/D CONVERTER W/LCD(Low power) XII、PHYSICAL DIMENSION 44 pins QFP package size