ES5116 CYRUSTEK | Alldatasheet
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Technical content
Features
Guaranteedzeroreadingwithzeroinput Low inputleakagecurrent(1pA typical) InternalReferencewith low temperaturedrift C typically) Low noise(15uVp-p typical) DirectLCD displaydriver-no externalcompo- nentsrequired Differentialinputand voltagereference Precisionnulldetectionwithtruepolarityatzero Internalclockcircuit No additionalactive circuitsrequired Low BatteryIndication Display-Hold
Description
The ES5116 islow power monolithicCMOS 3 1/2digit LCD displayA/D converter. Itcontainsthe internal clock,voltagereference,seven-segment decoders,LCD displaydriversand a back planedriver. The improved internalzenerreferencevoltagecircuitgivestheanalog common a smalltemperaturecoefficientof C typically. The high accuracy characteristicsof the ES5116 performverylow linearityerrorand roll-over error. The highinputimpedance ( ) and low inputleakagecurrent(1pA typical)give theES5116 a good applicationinthefieldofhighimpedance circuit measurement.The differentialinputand referenceare suitableformeasuringbridgetransduceror ohms by usingratio-metricmethod. The dualslopeconversion techniquemak estheES5116 a good normal and com- mon mode rejectionratio.W itha suitableoscillatorfre- quency,theES5116 hasa highrejectionof50Hz, 60Hz and 400Hz linefrequency noise. W ithsinglepower supply,a few passive components and a LCD display, ES5116 can be builtas highperformancepanelmeter. ExistingDisplayhold,low batteryflag integrationand De-integrationarefouradditionalfeatures. A pplication 1. Digitalpanelmeters 2. Digitalmulti-meters 3. Thermometers 4. Capacitancemeters 5. pH meters 6. Photo-meters
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication Block Diagram
7 SECHEHT
f e a g d c b BAT LCD PHASE DRIVER LATCH MOEDS UNITSTENS 200 battery Low detect Low battery CONTROL LOGIC TO SWITCH DRIVERS FROM COMPARATOR OUTPUT + + PLANE BACK INTERNAL DIGITAL GROUND TEST Vin =1V OSC2OSC1 OSC3 CLOCK TYPICAL SECHEHT TO SECON 5mA 2mA OUTPUT DIGITAL GROUND LOGIC INT CINT ZERO AUTO RINT BUFFV+ 2.9V 6.2V CAZ INTEGRATOR SECTION DIGITAL TO COHPARATOR A.ZINPUT HIGH CREF- LOW INPUT A/Z DE(1) INT DEHDEH DEHDEHA/Z INT 10uA REF LO CAEF REF HICREF+ IN HI INLOCOMMON DISPLAY FONT 500 6.2V DINTINT A/Z CONTROLHOLD
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication Pin Assignment
1 QFP-44pin package
44 43 42 41 40 39 38 37 36 35 34 12 13 14 15 16 17 18 19 20 21 22 LB G 2 C 3 A 3 G 3 B P PO L A B 4 B 3 D EEN IN TEN TEST O S3 HO LD O S2 O S1 V + D 1 C 1 B 1 REFHI REFLO C+REF C-REF COMMON INHI INLO A.Z BUFF INT A 1 F1 G 1 E1 D 2 C 2 B 2 A 2 F2 E2 D 3 ES5116Q
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication
2 SSOP-48pin package
A .Z. B U FF IN T V - LB N C G 2 C 3 A 3 D EEN R EFH I N C R EFLO C -R EF C +R EF O S1 ES5116V 24 25 Pin Description PinNo. Symbol Type Description 1 DEEN O De-integrationstatusflag. 2 INTEN O Integrationstatusflag. 3 TEST I PullhightoV+ allLCD segments willbe activated. 4 OS3 – Crystaloscillatorconnection. 5 HOLD I Hold pin,pullhightoholddisplay. 6 OS2 – Crystaloscillatorconnection. 7 OS1 – Crystaloscillatorconnection. 8 V+ – Positive supplyvoltage.Connectingtobatterypositive terminal. 9 D1 O LCD segment line. 10 C1 O LCD segment line. 11 B1 O LCD segment line. 12 A1 O LCD segment line. 13 F1 O LCD segment line. 14 G1 O LCD segment line. 15 E1 O LCD segment line. 16 D2 O LCD segment line. 17 C2 O LCD segment line. 18 B2 O LCD segment line. 19 A2 O LCD segment line. continuedon nextpage
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication continuedfrom previouspage PinNo. Symbol Type Description 20 F2 O LCD segment line. 21 E2 O LCD segment line. 22 D3 O LCD segment line. 23 B3 O LCD segment line. 24 F3 O LCD segment line. 25 E3 O LCD segment line. 26 AB4 O LCD segment line. 27 POL O LCD segment line. 28 BP O LCD segment line. 29 G3 O LCD segment line. 30 A3 O LCD segment line. 31 C3 O LCD segment line. 32 G2 O LCD segment line. 33 LB O Low-batteryflag segment driver. 34 V - – Ne gative supplyvoltage.Connectingtobatterynegative terminal. 35 INT O Integrationcycleoutput. 36 B UFF O Integrationresistorconnectionforbufferoutput. 37 A.Z – Auto-zerocapacitorconnection. 38 INLO – Low analoginputsignalconnection. 39 INHI – High analoginputsignalconnection. 40 COMMON – Setthecommon-mode voltageforthesystem. 41 C+REF – Positive capacitorconnectionforon-chipDC-DC converter. 42 C-REF – Ne gative capacitorconnectionforon-chipDC-DC converter. 43 REF LO I Low differentialreferenceinputconnection. 44 REF HI I High differentialreferenceinputconnection. Note: 1. PinNo. ofQFP-44 pinpackage. AbsoluteMaximum Ratings Characteristic Rating SupplyVoltage( to ! ) 12V Analog InputVoltage(eitherinput) to ReferenceInputVoltage(eitherinput) to Clock Input TEST to Power Dissipation(plasticpackage) 800mW OperatingTemperature C to"# C StorageTemperature $% C to' C Lead Temperature(soldering,10sec) ( C ElectricalCharacteristics
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication Parameter Symbol TestCondition Min. Typ. Max. Units Zero InputReading – *),+.-/
0 Full-
Scale=200.0mV -000.0 12 +000.0 DigitalReading Ratio-metricReading – )54 = *687:9 , *687:9 =100mV 999 999/1000 1000 DigitalReading Linearity (Max.deviation from beststraightlinefit) – full-Scale=200mVor Full-Scale=2.000V -1 12 ( 1 Counts roll-overError – $; *)54 ="< *)54 = 200.0mV -1 12 ( +1 Counts Common Mode Rejection Ratio ? =1 1V, <)@4 =0V Full-Scale=200.0mV – 50 – uV/V Low batteryflag – V+ toV - 6.7 7.0 7.3 V Noise – )54 0CBEDFHGIG;$ JLK M GIN<-O( – 15 – uVp-p InputLeakage Current – *)54Q-R 0 – 1 10 pA Zero ReadingDrift – )54 0 , C<= SUT <= "#V C – 0.2 1 uV/ C Analog COMMON Voltage (withrespecttoV – 25K Between Common and Posi- tive Supply 2.8 3.0 3.2 V Analog COMMON Temper- atureCoefficient – 25K Between Common and C<=T A<= #V C – 60 75 ppm/ C Segment Drive Voltage – to =9V 4 5 6 V Back planeDrive Voltage – to 4 5 6 V Supply Current (Does not includeCOMMON current) FunctionalDescription
1 Analog Common
The COMMON pinisusedtosetthecommon-mode voltageforthesystemwhich theinputsignalsarefloating.Inmost of theapplications,INLO, REFLO and COMMON pinsareusuallyconnected.Itcan remove common-mode voltage concerns.Inotherapplications,INLO doesnotconnectwithCOMMON. The ES5116 generatesa common mode voltage, which has thehighCMRR (86dB typical.)Ne vertheless,itshouldbe caretopreventtheoutputof theintegratorfrom saturation. The COMMON pin isalsoused as a voltagereference.Itoutputsa voltagewhich isaround 2.9voltsbelow the positive supply.The COMMON voltagehasa low outputimpedanceof '& typically. The analogCOMMON isconnectedinternallytoan NMOS which can sink30mA. ThisNMOS willholdtheCOM- MON voltageat2.9voltswhen an externalloadattemptstopulltheCOMMON voltagetow ardthepositive supply.The sourcecurrentofCOMMON isonly10uA, so itiseasytopullCOMMON voltagetoa more negative voltage. When thetotalsupplyvoltageislarge enough tocausethezenertoregulate(>7V,)theCOMMON voltagewillhave a low temperaturecoefficientlessthan W P C typically.Thisvoltagecan be usedtogeneratethereferencevoltage.
2 Reference Voltage
Foran 1000 countsreading,theinputsignalmust be equaltothereferencevoltage.As a result,itrequirestheinputsignal be twicethereferencevoltagefora 2000 countsfull-scalereading.Thus,forthe200.0mV and 2.000V full-scale,the referencevoltageshouldequal100.0mV and 1.000V,Insome applicationsthefull-scaleinputvoltagemay be differentto 200 mV or2.000V.Forexample,inthe600 mV full-scaleapplications,thereferencevoltageshouldbe setto300 mV .
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication The differentialreferenceshouldbe usedduringthemeasurementofresistorby theratio-metricmethod and when a digitalreadingofzeroisdesiredforV inX- 0,a compensatingoffsetvoltagecanbe appliedbetweenCOMMON and INLO, and thevoltageofbeingmeasuredisconnectedbetweenCOMMON and INHI.
3 System T iming
The oscillatorfrequency isdividedby fourpriortoclockingtheinternaldecadecounters.The signalintegrationtakesa fixed 1000 countstimeperiodwhich isequalto4000 clockpulses.The back planedrive signalisderived by dividing oscillatorfrequency by 800.To mak e a maximum noiserejectionoflinefrequency(60Hz or50Hz,)thesignalintegration periodshouldbe a multipleof thelinefrequency period.For 60Hz-noiserejection,oscillatorfrequenciesof 120KHz, 80KHz, 60KHz, 48KHz, 40KHz, etc.shouldbe selected.For50Hz rejection,oscillatorfrequenciesof100KHz, 50KHz, 40KHz, etc.w ouldbe suitable. Forallrangesoffrequency Rosc shouldbe 100K ,Cosc isselectedfrom theapproximateequationf= 0.45/RC.For 48KHz clock(3reading/second),Cosc=100pF.
4 IntegratingResistor
The inputbufferamplifierand integratoraredesignedwithclassA outputstages.Theoutputstageidlingcurrentis100 uA. Both of them can supply20uA drive currentswithnegligiblelinearityerrors.The integratingresistorischosento remainlineardrive regionintheoutputstage.Itshouldnotbe so large thattheleakagecurrentof printedcircuitboard willinduceerrors.The recommended integratingresistorvalueforthe200 mV and 2 V full-scaleare47K and 470 K respectively.
5 IntegratingCapacitor
The integratingcapacitorshouldbe selectedtomaximize integratoroutputvoltageswing withoutcausingoutputsatura- tion.For 3 readings/second(48KHz clock,)a 0.22uFvalueof Y[Z]\\U^ issuggested.Ifa differentoscillatorfrequency is used,Y_Z]\\U^ must be changedininverseproportiontomaintainthenominal1 2V integratorswing. The integratingcapacitormust have low dielectricabsorptiontominimizeroll-overerror.An inexpensive polypropy- lenecapacitorisrecommented.
6 A uto-Zero Capacitor
The auto-zerocapacitorsizehas some influenceon systemnoise.A 0.47uFcapacitorisrecommended for200mV full scale.A 0.047uFcapacitorisadequatefor2V fullscaleapplications.A mylartypedielectriccapacitorisadequate.
7 Reference VoltageCapacitor
The referencevoltageusedtoramp theintegratoroutputvoltagebacktozeroduringthereferenceintegratecycleisstored on Y_\`badc . A 0.1uF valuecapacitorisacceptablewhen INLO isconnectedwith COMMON. A mylar typedielectric capacitorisadequate.
8 TEST
The TEST pinistiedtotheinternallygenerateddigitalgroundthrougha 500 resistor.Itspotentialis5V lessthanV+. The TEST pinloadshouldbe no more than1 mA. IfTEST ispulledhightoV+, allsegments plustheminus signwillbe actived. Itmay destroy theLCD displayas keepinginthismode forseveralminutes.
9 Segment Drivers
For 3 readings/second(48KHz clock)theBP frequency isa 60Hz squarew ave with a nominal amplitudeof 5V.The segments aredriven inthesame frequency/amplitude.They areinphasewithBP when thesegment shouldbe OFF ,but outofphasewhen ON. The polarityindicationis"ON" fornegative voltageinputs.
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication
10 IntegrationStatus(INTEN)
The INTEN isan outputsignaloftheconverter,itkeepson "high"duringthesignalintegrationphase.
11 De-IntegrationStatus(DEEN)
The DEEN isan outputsignaloftheconverter,itkeepson "high"duringthereferencede-integrationphase.
12 Hold
When theholdpinisconnectedtoV+ theconversionresultwillnotbe update.The conversionisstillfreerunningduring holdmode.
13 Lo w BatteryFlag(LB)
When thesupplyvoltage(V+ toV -)islessthen6.9Volt,The LCD segment ofLow BatteryFlagisturnedon. TestCircuit ES5116Q Clock Frequency 48KHz (3 readings/sec) LCD DISPLAY 100P 100K SET 100.0mV 24K1K 0.1u 0.01u 0.47u 0.22u 47K IN-
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication A pplicationCircuit 1. ThiscircuitusesanalogCOMMON voltageasreferencevoltage.Valuesherearefor200.0mV fullscale,3readings/sec. ES5116Q Clock Frequency 48KHz (3 readings/sec) LCD DISPLAY 100P 100K SET 100.0mV 24K1K 0.1u 0.01u 0.47u 0.22u 47K IN-
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CYR USTEK CO. ES5116 3 1/2D VM with hold and low batteryindication 2. The valuesofthiscircuitarefor2.000V fullscale,3readings/sec. ES5116Q Clock Frequency 48KHz (3 readings/sec) LCD DISPLAY 100P 100K 24K 0.1u 0.01u 0.047u 0.22u IN- SET 1V 25K 470K