EP9315-EB

EP9315 CIRRUS | Alldatasheet

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©Copyright 2005 Cirrus Logic (All Rights Reserved) MAR ‘05 DS638PP4 http://www.cirrus.com Enhanced Universal Platform System-on-Chip Processor EP9315 Data Sheet

FEATURES

16-kbyte Instruction Cache 16-kbyte Data Cache Linux®, Microsoft® Windows® CE-enabled MMU 100-MHz System Bus MaverickCrunch™ Math Engine Floating Point, Integer, and Signal Processing Instructions Optimized for digital music compression and decompression algorithms. Hardware interlocks allow in-line coding. MaverickKey™ IDs 32-bit Unique ID can be used for DRM-compliant 128-bit random ID. Integrated Peripheral Interfaces 32-bit SDRAM Interface (up to 4 Banks) 32-/16-bit SRAM / FLASH / ROM Serial EEPROM Interface EIDE (up to 2 devices) 1/10/100-Mbps Ethernet MAC Three UARTs Three-port USB 2.0 Full-speed Host (OHCI) (12 Mbits per second) LCD and Raster Interface with Graphics Accelerator IrDA Interface PCMCIA Interface Touchscreen Interface with ADC 8 x 8 Keypad Scanner One Serial Peripheral Interface (SPI™) Port 6-channel or 2-channel Serial Audio Interface (I2S) 2-channel, Low-cost Serial Audio Interface (AC'97)

2 High-resolution PWMs (16 bits each)

12 Direct Memory Access (DMA) Channels

Real-time Clock with Software Trim Dual PLL controls all clock domains. Watchdog Timer Two General-purpose 16-bit Timers One General-purpose 32-bit Timer One 40-bit Debug Timer Interrupt Controller Boot ROM Package 352-pin PBGA Unified SDRAM I/F Video/LCD Controller (3) USB Hosts EIDE I/F Ethernet MAC Bus Bridge Boot ROM MaverickKeyTM 12-channel DMA SRAM & Flash I/F PCMCIA MaverickCrunchTM ARM920T MMU D-Cache 16KB I-Cache 16KB Processor Bus Peripheral Bus Serial Audio Interface Interrupts & GPIO Clocks & Timers Keypad & Touch Screen I/F (3) UARTs IrDA Graphics Accelerator COMMUNICATIONS PORTS USER INTERFACE MEMORY AND STORAGE

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor The EP9315 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: Thin Client Computers for Business and Home Internet Radio Internet Access Devices Industrial Computers Specialized Terminals Point-of-sale Terminals Test and Measurement Equipment The ARM920T microprocessor core with separate 16-kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunch™ co- processor, enabling high-speed floating point calculations. MaverickKey™ unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. A high-performance 1/10/100-Mbps Ethernet media access controller (EMAC) is included along with external interfaces to SPI, I2S audio, Raster/LCD, IDE storage peripherals, keypad, and touchscreen. A three-port USB

2.0 Full Speed Host (OHCI) (12 Mbits per second) and

three UARTs are included as well. The EP9315 is a high-performance, low-power, RISC- based, single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1.8 V supply, while the I/O operates at 3.3 V with power usage between 100 mW and 750 mW (dependent on speed). OVERVIEW Table A. Change History Revision Date Changes PP1 January 2004 Initial Release. PP2 July 2004 Update AC data. Add ADC data. PP3 Febuary 2005 Update electrical characteristics based upon more complete characterization data. PP4 March 2005 Minor correction to block diagram on page 1. DD7 changed to pull down.

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor Table of Contents

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor List of Tables Table G.Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Processor Core - ARM920T The ARM920T is a Harvard architecture processor with separate 16-kbyte instruction and data caches with an 8- word line length but a unified memory. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory, and write stages. Key features include: ARM (32-bit) and Thumb (16-bit compressed) Instruction Sets 32-bit Advanced Micro-Controller Bus Architecture (AMBA) 16-kbyte Instruction Cache with Lockdown 16-kbyte Data Cache (programmable write-through or write-back) with Lockdown MMU for Linux®, Microsoft® Windows® CE and Other Operating Systems Translation Look Aside Buffers with 64 Data and 64 Instruction Entries Programmable Page Sizes of 1 Mbyte, 64 kbyte, 4 kbyte, and 1 kbyte Independent Lockdown of TLB Entries MaverickCrunch™ Math Engine The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiply-accumulate (MAC) instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include: IEEE-754 single and double precision floating point 32 / 64-bit integer Add / multiply / compare Integer MAC 32-bit input with 72-bit accumulate Integer Shifts Floating point to/from integer conversion Sixteen 64-bit register files Four 72-bit accumulators MaverickKey™ Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP9315 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9315 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances. General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) The EP9315 features a unified memory address model where all memory devices are accessed over a common address/data bus. A separate internal port is dedicated to the read-only Raster/LCD refresh engine, while the rest of the memory accesses are performed via the Processor bus. The SRAM memory controller supports 8, 16 and 32-bit devices and accommodates an internal boot ROM concurrently with 32-bit SDRAM memory. 1-4 banks of 32-bit 66 or 100 MHz SDRAM One internal port dedicated to the Raster/LCD Refresh Engine (Read Only) Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory NOR FLASH memory supported Table B. General Purpose Memory Interface Pin Assignments Pin Mnemonic Pin Description SDCLK SDRAM Clock SDCLKEN SDRAM Clock Enable SDCSn[3:0] SDRAM Chip Selects 3-0 RASn SDRAM RAS CASn SDRAM CAS SDWEn SDRAM Write Enable CSn[7:6] and CSn[3:0] Chip Selects 7, 6, 3, 2, 1, 0 AD[25:0] Address Bus 25-0 DA[31:0] Data Bus 31-0 DQMn[3:0] SDRAM Output Enables / Data Masks WRn SRAM Write Strobe RDn SRAM Read / OE Strobe WAITn SRAM Wait Input

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor IDE Interface The IDE Interface provides an industry-standard connection to two AT Advanced Packet Interface (ATAPI) compliant devices. The IDE port will attach to a master and a slave device. The internal DMA controller performs all data transfers using the Ultra DMA modes. The interface supports the following operating modes: PIO Mode 0 thru 4 Ultra DMA Modes 0 thru 3 Ethernet Media Access Controller (MAC) The MAC subsystem is compliant with the ISO/TEC 802.3 topology for a single shared medium with several stations. Multiple MII-compliant PHYs are supported. Features include: Supports 1/10/100 Mbps transfer rates for home / small-business / large-business applications Interfaces to an off-chip PHY through industry standard Media Independent Interface (MII) Serial Interfaces (SPI, I2S and AC ’97) The SPI port can be configured as a master or a slave, supporting the National Semiconductor®, Motorola® and Texas Instruments® signaling protocols. The AC'97 port supports multiple codecs for multichannel audio output with a single stereo input. Three I2S ports can be configured to support six channel 24-bit audio. These ports are multiplexed so that I2S port 0 will take over either the AC'97 pins or the SPI pins. The second and third I2S ports' serial input and serial output pins are multiplexed with EGPIO[4,5,6,13]. The clocks supplied in the first I2S port are also used for the second and third I2S ports. Normal Mode: One SPI Port and one AC’97 Port I2S on SSP Mode: One AC’97 Port and up to three I2S Ports I2S on AC’97 Mode: One SPI Port and up to three I2S Ports Raster / LCD Interface The Raster / LCD interface provides data and interface signals for a variety of display types. It features fully programmable video interface timing for non-interlaced flat panel or dual scan displays. Resolutions up to 1024 x 768 are supported from a unified SDRAM based frame buffer. A 16-bit PWM provides control for LCD panel contrast. LCD specific features include: Table C. IDE Interface Pin Assignments Pin Mnemonic Pin Description DD[15-0] IDE Data bus IDEDA[2-0] IDE Device address IDECSn[0,1] IDE Chip Select 0 and 1 DIORn IDE Read Strobe DIOWn IDE Write Strobe DMACKn IDE DMA acknowledge Table D. Ethernet Media Access Controller Pin Assignments Pin Mnemonic Pin Description MDC Management Data Clock MDIO Management Data I/O RXCLK Receive Clock MIIRXD[3:0] Receive Data RXDVAL Receive Data Valid RXERR Receive Data Error TXCLK Transmit Clock MIITXD[3:0] Transmit Data TXEN Transmit Enable TXERR Transmit Error CRS Carrier Sense CLD Collision Detect Table E. Audio Interfaces Pin Assignment Pin Name Normal Mode I2S on SSP Mode I2S on AC'97 Mode Pin

Description

SPI Frame Clock I2S Frame Clock SPI Frame Clock SSPRX1 SPI Serial Input I2S Serial Input SPI Serial Input SSPTX1 SPI Serial Output I2S Serial Output SPI Serial Output (No I2S Master Clock) ARSTn AC'97 Reset AC'97 Reset I2S Master Clock ABITCLK AC'97 Bit Clock AC'97 Bit Clock I2S Serial Clock ASYNC AC'97 Frame Clock AC'97 Frame Clock I2S Frame Clock ASDI AC'97 Serial Input AC'97 Serial Input I2S Serial Input ASDO AC'97 Serial Output AC'97 Serial Output I2S Serial Output

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Timing and interface signals for digital LCD and TFT displays Full programmability for either non-interlaced or dual- scan color and grayscale flat panel displays Dedicated data path to SDRAM controller for improved system performance Pixel depths of 4, 8, 16, or 24 bits per pixel or 256 levels of grayscale Hardware Cursor up to 64 x 64 pixels 256 x 18 Color Lookup Table Hardware Blinking 8-bit interface to low end panel Graphics Accelerator The EP9315 contains a hardware graphics acceleration engine that improves graphic performance by handling block copy, block fill and hardware line draw operations. The Graphics Accelerator is used in the system to off- load graphics operations from the processor. Pixel depths supported by the Graphics Accelerator are 4, 8, 16 or 24 bits per pixel. The 24 bits per pixel mode can be operated as packed (4 pixels every 3 words) or unpacked (1 pixel per word with the high byte unused.) The block copy operations of the Graphics Accelerator are similar to a DMA (Direct Memory Access) transfer that understands pixel organization, block width, transparency, and transformation from 1bpp to higher 4, 8, 16 or 24bpp. The line draw operations also allow for solid lines or dashed lines. The colors for line drawing can be either foreground color and background color or foreground color with the background being transparent. Touch Screen Interface with 12-bit Analog- to-digital Converter (ADC) The touch screen interface performs all sampling, averaging, ADC range checking, and control for a wide variety of analog resistive touch screens. This controller only interrupts the processor when a meaningful change occurs. The touch screen hardware may be disabled and the switch matrix and ADC controlled directly if desired. Features include: Support for 4-, 5-, 7-, or 8-wire analog resistive touch screens. Flexibility - unused lines may be used for temperature sensing or other functions. Touch screen interrupt function. 64-Key Keypad Interface The keypad circuitry scans an 8 x 8 array of 64 normally open, single-pole switches. Any one or two keys depressed will be de-bounced and decoded. An interrupt is generated whenever a stable set of depressed keys is detected. If the keypad is not utilized, the 16 column/row pins may be used as general purpose I/O. The Keypad interface: Provides scanning, debounce, and decoding for a 64- key switch array. Scans an 8-row by 8-column matrix. May decode 2 keys at once. Generates an interrupt when a new stable key is determined. Also generates a 3-key reset interrupt. Table F. LCD Interface Pin Assignments Pin Mnemonic Pin Description SPCLK Pixel Clock P[17:0] Pixel Data Bus [17:0] HSYNC / LP Horizontal Synchronization / Line Pulse VCSYNC / FP Vertical or Composite Synchronization / Frame Pulse BLANK Composite Blank BRIGHT Pulse Width Modulated Brightness Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments Pin Mnemonic Pin Description Xp, Xm Touch screen ADC X Axis Yp, Ym Touch screen ADC Y Axis SXp, SXm Touch screen ADC X Axis Voltage Feedback SYp, SYm Touch screen ADC Y Axis Voltage Feedback Table H. 64-Key Keypad Interface Pin Assignments Pin Mnemonic Pin COL[7:0] Key Matrix Column Inputs General Purpose I/O ROW[7:0] Key Matrix Row Inputs General Purpose I/O

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor Universal Asynchronous Receiver/Transmitters (UARTs) Three 16550-compatible UARTs are supplied. Two provide asynchronous HDLC (High-level Data Link Control) protocol support for full-duplex transmit and receive. The HDLC receiver handles framing, address matching, CRC checking, control-octet transparency, and optionally passes the CRC to the host at the end of the packet. The HDLC transmitter handles framing, CRC generation, and control-octet transparency. The host must assemble the frame in memory before transmission. The HDLC receiver and transmitter use the UART FIFOs to buffer the data streams. A third IrDA®- compatible UART is also supplied. UART1 supports modem bit rates up to 115.2 Kbps, supports HDLC and includes a 16-byte FIFO for receive and a 16-byte FIFO for transmit. Interrupts are generated on Rx, Tx, and modem status change. UART2 contains an IrDA encoder operating at either the slow (up to 115 Kbps), medium (0.576 or 1.152 Mbps), or fast (4 Mbps) IR data rates. It also has a 16- byte FIFO for receive and a 16-byte FIFO for transmit. UART3 supports HDLC and includes a 16-byte FIFO for receive and a 16-byte FIFO for transmit. Interrupts are generated on Rx and Tx. Triple Port USB Host The USB Open Host Controller Interface (Open HCI) provides full speed serial communications ports at a baud rate of 12 Mbits/sec. Up to 127 USB devices (printer, mouse, camera, keyboard, etc.) and USB hubs can be connected to the USB host in the USB “tiered- start” topology. This includes the following features: Compliance with the USB 2.0 specification Compliance with the Open HCI Rev 1.0 specification Supports both low speed (1.5 Mbps) and full speed (12 Mbps) USB device connections Root HUB integrated with 3 downstream USB ports Transceiver buffers integrated, over-current protection on ports Supports power management Operates as a master on the bus The Open HCI host controller initializes the master DMA transfer with the AHB bus: Fetches endpoint descriptors and transfer descriptors Accesses endpoint data from system memory Accesses the HC communication area Writes status and retire transfer descriptor Two-wire Interface The two-wire interface provides communication and control for synchronous-serial-driven devices. Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments Pin Mnemonic Pin Name - Description TXD0 UART1 Transmit RXD0 UART1 Receive CTSn UART1 Clear To Send / Transmit Enable DSRn / DCDn UART1 Data Set Ready / Data Carrier Detect DTRn UART1 Data Terminal Ready RTSn UART1 Ready To Send EGPIO[0] / RI UART1 Ring Indicator TXD1 / SIROUT UART2 Transmit / IrDA Output RXD1 / SIRIN UART2 Receive / IrDA Input TXD2 UART3 Transmit RXD2 UART3 Receive EGPIO[3] / TENn HDLC3 Transmit Enable Table J. Triple Port USB Host Pin Assignments Pin Mnemonic Pin Name - Description USBp[2:0] USB Positive signals USBm[2:0] USB Negative Signals Table K. Two-Wire Port with EEPROM Support Pin Assignments Pin Mnemonic Pin Name - Description Alternative Usage EECLK Two-Wire Interface Clock General Purpose I/O EEDATA Two-Wire Interface Data General Purpose I/O

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Real-Time Clock with Software Trim The software trim feature on the real time clock (RTC) provides software controlled digital compensation of the 32.768 kHz input clock. This compensation is accurate to ± 1.24 sec/month. Note: A real time clock must be connected to RTCXTALI or the EP9315 device will not boot. PLL and Clocking The processor and the peripheral clocks operate from a single 14.7456 MHz crystal. The real time clock operates from a 32.768 kHz external oscillator. Timers The Watchdog Timer insures proper operation by requiring periodic attention to prevent a reset-on-time- out. Two 16-bit timers operate as free running down-counters or as periodic timers for fixed interval interrupts and have a range of 0.03 ms to 4.27 seconds. One 32-bit timer, plus a 6-bit prescale counter, has a range of 0.03 µs to 73.3 hours. One 40-bit debug timer, plus 6-bit prescale counter, has a range of 1.0 µs to 12.7 days. Interrupt Controller The interrupt controller allows up to 64 interrupts to generate an Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) signal to the processor core. Thirty-two hardware priority assignments are provided for assisting IRQ vectoring, and two levels are provided for FIQ vectoring. This allows time critical interrupts to be processed in the shortest time possible. Internal interrupts may be programmed as active-high or active- low, level-sensitive inputs. GPIO may be programmed as active-high level-sensitive, active-low level-sensitive, rising-edge-triggered, falling-edge-triggered, or combined rising/falling-edge-triggered. Supports 64 interrupts from a variety of sources (such as UARTs, GPIO, and key matrix) Routes interrupt sources to either the ARM920T’s IRQ or FIQ (Fast IRQ) inputs Four dedicated off-chip interrupt lines INT[3:0] operate as active-high, level-sensitive interrupts Any of the 16 GPIO lines maybe configured to generate interrupts Software supported priority mask for all FIQs and IRQs Dual LED Drivers Two pins are assigned specifically to drive external LEDs. General Purpose Input/Output (GPIO) The 16 EGPIO pins may each be configured individually as an output, an input, or an interrupt input. Port F may be configured as GPIO. Each Port F pin may be configured individually as an output, input or an interrupt input. There are 23 pins that may be used as alternate inputs or outputs, but do not support interrupts. These pins are:

• Key Matrix ROW[7:0], COL[7:0]
• Ethernet MDIO
• Both LED Outputs
• Two-wire Clock and Data
• SLA [1:0] 6 pins may alternatively be used as inputs only:
• CTSn, DSRn / DCDn
• 4 Interrupt Lines 2 pins may alternatively be used as outputs only:
• RTSn
• ARSTn Table L. Real-Time Clock with Pin Assignments Pin Mnemonic Pin Name - Description RTCXTALI Real-Time Clock Oscillator Input RTCXTALO Real-Time Clock Oscillator Output Table M. PLL and Clocking Pin Assignments Pin Mnemonic Pin Name - Description XTALI Main Oscillator Input XTALO Main Oscillator Output VDD_PLL Main Oscillator Power GND_PLL Main Oscillator Ground Table N. External Interrupt Pin Assignment Pin Mnemonic Pin Name - Description INT[3:0] External Interrupt 3-0 Table O. Dual LED Pin Assignments Pin Mnemonic Pin Name -

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor Note: Port F defaults as PCMCIA pins. Port F must be configured by software to be used as GPIO. Reset and Power Management The chip may be reset through the PRSTn pin or through the open drain common reset pin, RSTOn. Clocks are managed on a peripheral-by-peripheral basis and may be turned off to conserve power. The processor clock is dynamically adjustable from 0 to 200 MHz (184 MHz for industrial conditions). Hardware Debug Interface The JTAG interface allows use of ARM’s Multi-ICE or other in-circuit emulators. Note: The JTAG interface does not support boundary scan. Internal Boot ROM The Internal 16-kbyte ROM allows booting from FLASH memory, SPI or UART. Consult the EP93xx User’s Manual for operational details 12-channel DMA Controller The DMA module contains 12 separate DMA channels. Ten of these may be used for peripheral-to-memory or memory-to-peripheral access. Two of these are dedicated to memory-to-memory transfers. Each DMA channel is connected to the 16-bit DMA request bus. The request bus is a collection of requests, Serial Audio, and UARTs. Each DMA channel can be used independently or dedicated to any request signal. For each DMA channel, source and destination addressing can be independently programmed to increment, decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses. PCMCIA Interface The EP9315 has a single PCMCIA port which can be used to access either 8 or 16-bit devices. Table P. General Purpose Input/Output Pin Assignment Pin Mnemonic Pin Name - Description EGPIO[15:0] Expanded General Purpose Input / Output Pins with Interrupts FGPIO[7:0] Expanded General Purpose Input / Output Pins with Interrupts Table Q. Reset and Power Management Pin Assignments Pin Mnemonic Pin Name - Description PRSTn Power On Reset RSTOn User Reset In/Out – Open Drain – Preserves Real Time Clock value Table R. Hardware Debug Interface Pin Mnemonic Pin Name - Description TCK JTAG Clock TDI JTAG Data In TDO JTAG Data Out TMS JTAG Test Mode Select TRSTn JTAG Port Reset Table S. PCMCIA Interface Pin Mnemonic Pin Name - Description VS1 Voltage sense VS2 Voltage sense MCD1 Card detect MCD2 Card detect MCBVD1 Voltage detection / status change MCBVD2 Voltage detection MCDIR Data transceiver direction control MCDAENn Data bus transceiver enable MCADENn Address bus transceiver enable MCREGn Memory card register MCEHn Memory card high byte select MCELn Memory card low byte select IORDn I/O card read IOWRn I/O card write MCRDn Memory card read MCWRn Memory card write READY Ready / interrupt WP Write protect MCWAITn Wait Input MCRESETn Card reset

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Electrical Specifications Absolute Maximum Ratings Note: 1. Includes all power generated due to AC and/or DC output loading. 2. The power supply pins are at recommended maximum values. 3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Recommended Operating Conditions (All grounds = 0 V, all voltages with respect to 0 V) Parameter Symbol Min Max Unit Power Supplies RVDD CVDD VDD_PLL VDD_ADC 3.96 2.16 2.16 3.96 V V V V Total Power Dissipation (Note 1) W Input Current per Pin, DC (Except supply pins) ±10 mA Output current per pin, DC ±50 mA Digital Input voltage (Note 2) -0.3 RVDD+0.3 V Storage temperature -40 +125 (All grounds = 0 V, all voltages with respect to 0 V) Parameter Symbol Min Typ Max Unit Power Supplies RVDD CVDD VDD_PLL VDD_ADC 3.0 1.65 1.65 3.0 3.3 1.80 1.80 3.3 3.6 1.94 1.94 3.6 V V V V Operating Ambient Temperature - Commercial TA +25 +70 Operating Ambient Temperature - Industrial TA -40 +25 +85 Processor Clock Speed - Commercial FCLK 200 MHz Processor Clock Speed - Industrial FCLK 184 MHz System Clock Speed - Commercial HCLK 100 MHz System Clock Speed - Industrial HCLK MHz

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor DC Characteristics Note: 4. For open drain pins, high level output voltage is dependent on the external load. 5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on page 60). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not driven and programmed as an input, it should be tied to power or ground through its own resistor. (TA = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V; All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted) Parameter Symbol Min Max Unit High level output voltage Iout = -4 mA (Note 4) Voh 0.85 × RVDD V Low level output voltage Iout = 4 mA Vol 0.15 × RVDD V High level input voltage (Note 5) Vih 0.65 × RVDD VDD + 0.3 V Low level input voltage (Note 5) Vil -0.3 0.35 × RVDD V High level leakage current Vin = 3.3 V (Note 5) Iih µA Low level leakage current Vin = 0 (Note 5) Iil -10 µA Parameter Min Typ Max Unit Power Supply Pins (Outputs Unloaded), 25° C Power Supply Current: CVDD / VDD_PLL Total RVDD 190 240 mA mA Low-Power Mode Supply Current CVDD / VDD_PLL Total RVDD 3.5 mA mA

Figure 1. Timing Diagram Drawing Key Unless specified otherwise, the following conditions are true for all timing measurements.

• TA = 0 to 70° C
• CVDD = VDD_PLL = 1.8V
• RVDD = 3.3 V
• All grounds = 0 V
• Logic 0 = 0 V, Logic 1 = 3.3 V
• Output loading = 50 pF
• Timing reference levels = 1.5 V
• The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between 33 MHz and 100 MHz (92 MHz for industrial conditions). Clock High to Low High/Low to High Bus Change Bus Valid Undefined/Invalid Valid Bus to Tristate Bus/Signal Omission

Figure 3. SDRAM Burst Read Cycle Timing Measurement

Figure 4. SDRAM Burst Write Cycle Timing Measurement

Figure 5. SDRAM Auto Refresh Cycle Timing Measurement

See “Timing Conditions” on page 14 for definition of HCLK. Figure 6. Static Memory Single Word Read Cycle Timing Measurement

Figure 7. Static Memory Single Word Write Cycle Timing Measurement

Figure 8. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement

Figure 9. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement

Figure 10. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement

Figure 11. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details. Figure 12. Static Memory Burst Read Cycle Timing Measurement

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details. Figure 13. Static Memory Burst Write Cycle Timing Measurement

Figure 14. Static Memory Single Read Wait Cycle Timing Measurement

Figure 15. Static Memory Single Write Wait Cycle Timing Measurement

Notes: 1. X and Y represent any two chip select numbers.

1. IDCY occurs on read-to-write and write-to-read.
2. IDCY is honored when going from a asynchronous device (CSx) to a synchronous device (/SDCSy).

Figure 16. Static Memory Turnaround Cycle Timing Measurement

1 - MCWAITn asserted will extend the MCRD / IORD strobe time. Figure 17. PCMCIA Read Cycle Timing Measurement

1 - MCWAITn asserted will extend the MCWR / IOWR strobe time. Figure 18. PCMCIA Write Cycle Timing Measurement

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor IDE Interface Register Transfers Note: 1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device. 3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable. 4. Timings based upon software control. See User’s Guide. 5. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t0 by utilizing the 16-bit PIO value. 6. All IDE timing is based upon HCLK = 100 MHz. Parameter Symbol Mode 0 (in ns) Mode 1 (in ns) Mode 2 (in ns) Mode 3 (in ns) Mode 4 (in ns) Cycle time (min) (Notes 1, 4, 5) 600 383 330 180 120 Address valid to DIORn / DIOWn setup (min) (Note 4) DIORn / DIOWn pulse width 8-bit (min) (Note 1, 4) 290 290 290 DIORn / DIOWn recovery time (min) (Note 1, 4) t2i DIOWn data setup (min) (Note 4) DIOWn data hold (min) DIORn data setup (min) DIORn data hold (min) DIORn data high impedance state (max) (Note 2, 4) t6z DIORn / DIOWn to address valid hold (min) (Note 4) Read Data Valid to IORDY (min) active (if IORDY initially low after tA) (Note 4) tRD IORDY Setup time (Note 3, 4) tA IORDY Pulse Width (max) (Note 4) tB 1250 1250 1250 1250 1250 IORDY assertion to release (max) tC DIOWn assert to data valid (max) tDDV

1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (7:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is

3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. and may be asserted for no more than tC before release: no wait generated. and DIORn is asserted, the device shall place read data on DD (7:0) for tRD before asserting IORDY. Figure 19. Register Transfer to/from Device

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor PIO Data Transfers Note: 1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device. 3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable. 4. Timings based upon software control. See User’s Guide. 5. All IDE timing is based upon HCLK = 100 MHz. Parameter Symbol Mode 0 (in ns) Mode 1 (in ns) Mode 2 (in ns) Mode 3 (in ns) Mode 4 (in ns) Cycle time (min) (Note 1, 4) 600 383 240 180 120 Address valid to DIORn / DIOWn setup (min) (Note 4) DIORn / DIOWn 16-bit (min) (Note 1, 4) 165 125 100 DIORn / DIOWn recovery time (min) (Note 1, 4) t2i DIOWn data setup (min) (Note 4) DIOWn data hold (min) DIORn data setup (min) DIORn data hold (min) DIORn data high impedance state (max) (Note 2, 4) t6z DIORn / DIOWn to address valid hold (min) (Note 4) Read Data Valid to IORDY (min) active (if IORDY initially low after tA) (Note 4) tRD IORDY Setup time (Note 3, 4) tA IORDY Pulse Width (max) (Note 4) tB 1250 1250 1250 1250 1250 IORDY assertion to release (max) tC DIOWn assert to data valid (max) tDDV

1. Device address consists of signals IDECS0n, IDECS1n and IDEDA (2:0)
2. Data consists of DD (15:0)
3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is

3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. and may be asserted for no more than tC before release: no wait generated. and DIORn is asserted, the device shall place read data on DD (15:0) for tRD before asserting IORDY. Figure 20. PIO Data Transfer to/from Device

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Ultra DMA Data Transfer Figure 21 through Figure 30 define the timings associated with all phases of Ultra DMA bursts. The following table contains the values for the timings for each of the Ultra DMA modes. Note: 1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies. 2. The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers. Timing for tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value. 3. tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the other to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum. 4. tZIORDY may be greater than tENV since the device has a pull up on IORDYn giving it a known state when released. 5. All IDE timing is based upon HCLK = 100 MHz. Timing reference levels = 1.5 V Parameter Symbol Mode 0 (in ns) Mode 1 (in ns) Mode 2 (in ns) Mode 3 (in ns) min max min max min max min max Cycle time allowing for asymmetry and clock variations (from DSTROBE edge to DSTROBE edge) tCYCRD 112 Two-cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of DSTROBE) t2CYCRD 230 154 115 Cycle time allowing for asymmetry and clock variations (from HSTROBE edge to HSTROBE edge) tCYCWR 230 170 130 100 Two-cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of HSTROBE) t2CYCWR 460 340 260 200 Data setup time at recipient (Read) tDS Data hold time at recipient (Read) tDH Data valid setup time at sender (Write) (Note 2) (from data valid until STROBE edge) tDVS Data valid hold time at sender (Write) (Note 2) (from STROBE edge until data may become invalid) tDVH First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) tFS 230 200 170 130 Limited interlock time (Note 3) tLI 150 150 150 100 Interlock time with minimum (Note 3) tMLI Unlimited interlock time (Note 3) tUI Maximum time allowed for output drivers to release (from asserted or negated) tAZ Minimum delay time required for output tZAH Drivers to assert or negate (from released) tZAD Envelope time (from DMACKn to STOP and HDMARDYn during data in burst initiation and from DMACKn to STOP during data out burst initiation) tENV Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDYn) tRFS Ready-to-pause time (that recipient shall wait to pause after negating DMARDYn) tRP 160 125 100 100 Maximum time before releasing IORDY tIORDYZ Minimum time before driving STROBE (Note 4) tZIORDY Setup and hold times for DMACKn (before assertion or negation) tACK Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) tSS

in effect until DMARQ and DMACKn are asserted. Figure 21. Initiating an Ultra DMA data-in Burst

longer in effect after DMARQ and DMACKn are negated. Figure 24. Device Terminating an Ultra DMA data-in Burst

longer in effect after DMARQ and DMACKn are negated. Figure 25. Host Terminating an Ultra DMA data-in Burst

in effect until DMARQ and DMACKn are asserted. Figure 26. Initiating an Ultra DMA data-out Burst

longer in effect after DMARQ and DMACKn are negated. Figure 29. Host Terminating an Ultra DMA data-out Burst

longer in effect after DMARQ and DMACKn are negated. Figure 30. Device Terminating an Ultra DMA data-out Burst

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor Ethernet MAC Interface STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium. PHY - Ethernet physical layer interface. Parameter Symbol Min Typ Max Unit

10 Mbit

100 Mbit

tTX_per 400 ns TXCLK high time tTX_high 140 200 260 ns TXCLK low time tTX_low 140 200 260 ns TXCLK to signal transition delay time tTXd ns TXCLK rise/fall time tTXrf ns RXCLK cycle time tRX_per 400 ns RXCLK high time tRX_high 140 200 260 ns RXCLK low time tRX_low 140 200 260 ns RXDVAL / RXERR setup time tRXs ns RXDVAL / RXERR hold time tRXh ns RXCLK rise/fall time tRXrf ns MDC cycle time tMDC_per 400 400 ns MDC high time tMDC_high 160 160 ns MDC low time tMDC_low 160 160 ns MDC rise/fall time tMDCrf ns MDIO setup time (STA sourced) tMDIOs ns MDIO hold time (STA sourced) tMDIOh ns MDC to MDIO signal transition delay time (PHY sourced) tMDIOd 300 300 ns

Figure 31. Ethernet MAC Timing Measurement

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor Audio Interface Note: The tspix_clk is programmable by the user. The following table contains the values for the timings of each of the SPI modes. Parameter Symbol Min Typ Max Unit SCLK cycle time tclk_per tspix_clk ns SCLK high time tclk_high (tspix_clk) / 2 ns SCLK low time tclk_low (tspix_clk) / 2 ns SCLK rise/fall time tclkrf ns Data from master valid delay time tDMd ns Data from master setup time tDMs ns Data from master hold time tDMh ns Data from slave setup time tDSs ns Data from slave hold time tDSh ns

Figure 34. SPI Format with SPH=1 Timing Measurement

ti2s_clk is programmable by the user. Figure 35. Inter-IC Sound (I2S) Timing Measurement

Figure 36. AC ‘97 Configuration Timing Measurement

Figure 37. LCD Timing Measurement

ADIV refers to bit 16 in the KeyTchClkDiv register. ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4. ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16. same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion. Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.

1. Read the TSXYResult register into a local variable to initiate a conversion.
2. If the value of bit 31 of the local variable is '0' then repeat step 1.
3. Delay long enough to meet the maximum sample rate as shown above.
4. Mask the local variable with 0xFFFF to remove extraneous data.
5. If signed mode is used, do a sign extend of the lower halfword.
6. Return the sampled value.

Figure 38. ADC Transfer Function

Figure 39. JTAG Timing Measurement

352 Pin BGA Package Outline

Figure 40. 352 Pin PBGA Pin Diagram

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Note: 1. Controlling Dimension: Millimeter. 2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C. 4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. 5. Reference Document: JEDEC MO-151, BAL-2

352 Pin BGA Pinout (Bottom View)

The following table shows the 352 pin BGA pinout. (For better understanding, compare the coordinates on the x and y axis on Figure 40, "352 PIN BGA PINOUT", on page 57 with Figure 40, "352 Pin PBGA Pin Diagram", on page 55.

• VDD_core is CVDD.
• VDD_ring is RVDD.
• All core and ring grounds are connected together and are labelled GND.
• Other special power requirements are clearly labelled (i.e. H18=ADC_VDD and H19=ADC_GND).
• NC means that the pin is not connected. Table R. 352 Pin Diagram Dimensions Symbol dimension in mm dimension in inches MIN NOM MAX MIN NOM MAX A 2.20 2.30 2.50 0.087 0.092 0.098 0.60 0.024 1.12 1.17 1.22 0.044 0.046 0.048 b 0.75 0.030 c 0.51 0.56 0.61 0.020 0.022 0.024 D 26.80 27.00 27.20 1.055 1.063 1.071 24.13 0.950 23.80 24.00 24.20 0.937 0.945 0.953 17.95 18.00 18.05 0.707 0.709 0.711 E 26.80 27.00 27.20 1.055 1.063 1.071 24.13 0.950 23.80 24.00 24.20 0.937 0.945 0.953 17.95 18.00 18.05 0.707 0.709 0.711 e 1.27 0.050 ddd 0.15 0.006 q 30° TYP 30° TYP

Figure 40. 352 PIN BGA PINOUT

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Pin List The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball. Ball Signal Ball Signal Ball Signal Ball Signal CSN[7] RVDD DA[16] T13 CVDD DA[28] E10 GND DA[15] T14 GND AD[18] E11 GND GND T15 INT[0] DD[8] E12 RVDD GND T16 USBM[1] DD[4] E13 CVDD GND T17 RXD[0] AD[17] E14 CVDD L10 GND T18 TXD[2] RDN E15 GND L11 GND T19 ROW[2] RXCLK E16 ASDI L12 GND T20 ROW[4] MIIRXD[0] E17 DIOWN L13 GND AD[0] A10 RXDVAL E18 EGPIO[0] L16 CVDD P[15] A11 MIITXD[2] E19 EGPIO[3] L17 COL[5] P[10] A12 TXERR E20 EGPIO[5] L18 COL[7] P[7] A13 CLD SDCSN[3] L19 RSTON P[6] A14 VS2 DA[22] L20 PRSTN P[4] A15 MCBVD1 DA[24] AD[7] P[0] A16 MCREGN AD[25] DA[14] AD[13] A17 EGPIO[12] RVDD AD[6] DA[3] A18 EGPIO[15] GND AD[5] U10 DA[0] A19 IOWRN CVDD CVDD U11 DSRN A20 MCRESETN F14 CVDD GND U12 BOOT[1] CSN[2] F15 GND GND U13 NC DA[31] F16 GND M10 GND U14 SSPRX1 DA[30] F17 EGPIO[2] M11 GND U15 INT[1] DA[27] F18 EGPIO[4] M12 GND U16 PWMOUT DD[7] F19 EGPIO[6] M13 GND U17 USBM[0] DD[3] F20 EGPIO[8] M16 GND U18 RXD[1] WRN SDCSN[0] M17 COL[4] U19 TXD[1] MDIO SDCSN[1] M18 COL[3] U20 ROW[1] MIIRXD[1] SDWEN M19 COL[6] P[16] B10 RXERR SDCLK M20 CSN[0] P[11] B11 MIITXD[1] RVDD DA[13] P[8] B12 CRS RVDD DA[12] DD[15] B13 VS1 G15 RVDD DA[11] DD[13] B14 MCD1 G16 RVDD AD[3] P[1] B15 MCBVD2 G17 EGPIO[7] CVDD AD[14] B16 MCEHN G18 EGPIO[9] CVDD AD[12] B17 EGPIO[13] G19 EGPIO[10] GND DA[2] B18 MCRDN G20 EGPIO[11] GND V10 IDECS0N B19 WAITN DQMN[3] N10 GND V11 IDEDA[2] B20 TRSTN CASN N11 GND V12 TDI CSN[1] RASN N12 GND V13 GND CSN[3] SDCSN[2] N13 GND V14 ASYNC

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor AD[20] CVDD N15 GND V15 SSPTX1 DA[29] GND N16 GND V16 INT[2] DD[10] GND N17 XTALO V17 RTSN DD[6] H10 GND N18 COL[0] V18 USBP[0] DD[2] H11 GND N19 COL[1] V19 CTSN MDC H12 GND N20 COL[2] V20 TXD[0] MIIRXD[3] H13 GND AD[4] P[12] C10 TXCLK H16 RVDD DA[10] P[9] C11 MIITXD[0] H17 RTCXTALO DA[9] DD[0] C12 READY H18 ADC_VDD BRIGHT P[5] C13 MCD2 H19 ADC_GND RVDD P[3] C14 MCDIR H20 XP RVDD DA[7] C15 MCELN DA[21] P15 RVDD DA[5] C16 IORDN DQMN[0] P16 RVDD AD[11] C17 MCWRN DQMN[1] P17 XTALI AD[9] C18 USBP[2] DQMN[2] P18 PLL_VDD W10 IDECS1N C19 IORDY GND P19 ROW[6] W11 IDEDA[1] C20 DMACKN GND P20 ROW[7] W12 TCK AD[24] GND AD[2] W13 TMS DA[25] J10 GND AD[1] W14 EECLK DD[11] J11 GND P[17] W15 SCLK1 SDCLKEN J12 GND P[14] W16 GRLED AD[19] J13 GND RVDD W17 INT[3] DD[9] J16 CVDD RVDD W18 SLA[1] DD[5] J17 RTCXTALI GND W19 SLA[0] AD[16] J18 XM CVDD W20 RXD[2] MIIRXD[2] J19 YP R13 CVDD HSYNC D10 MIITXD[3] J20 YM R14 GND DD[1] D11 TXEN AD[22] R15 RVDD DD[12] D12 MCWAITN DA[20] R16 RVDD P[2] D13 MCDAENN AD[21] R17 ROW[0] AD[15] D14 MCADENN DA[19] R18 ROW[3] DA[6] D15 EGPIO[14] RVDD R19 PLL_GND DA[4] D16 WP GND R20 ROW[5] AD[10] D17 USBM[2] GND DA[8] DA[1] D18 ARSTN K10 GND BLANK Y10 AD[8] D19 DIORN K11 GND P[13] Y11 IDEDA[0] D20 EGPIO[1] K12 GND SPCLK Y12 DTRN AD[23] K13 GND V_CSYNC Y13 TDO DA[23] K16 CVDD DD[14] Y14 BOOT[0] DA[26] K17 SYM GND Y15 EEDAT CSN[6] K18 SYP CVDD Y16 ASDO GND K19 SXM RVDD Y17 SFRM1 GND K20 SXP T10 GND Y18 RDLED CVDD DA[18] T11 GND Y19 USBP[1] CVDD DA[17] T12 RVDD Y20 ABITCLK Ball Signal Ball Signal Ball Signal Ball Signal

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor The following section focuses on the EP9315 pin signals from two viewpoints - the pin usage and pad characteristics, and the pin multiplexing usage. The first table (Table S) is a summary of all the EP9315 pin signals. The second table (Table T) illustrates the pin signal multiplexing and configuration options. Table S is a summary of the EP9315 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP).) Under the Pad Type column: A - Analog pad P - Power pad G - Ground pad I - Pin is an input only I/O - Pin is input/output 4mA - Pin is a 4 mA output driver 8mA - Pin is an 8 mA output driver 12mA - Pin is an 12 mA output driver See the text description for additional information about bi-directional pins. Under the Pull Type Column: PU - Resistor is a pull up to the RVDD supply PD - Resistor is a pull down to the RGND supply Table S. Pin Descriptions Pin Name Block Pad Type Pull Type I PD JTAG clock in TDI JTAG I PD JTAG data in TDO JTAG 4ma JTAG data out TMS JTAG I PD JTAG test mode select TRSTn JTAG I PD JTAG reset BOOT[1:0] System I PD Boot mode select in XTALI PLL A Main oscillator input XTALO PLL A Main oscillator output VDD_PLL PLL P Main oscillator power, 1.8V GND_PLL PLL G Main oscillator ground RTCXTALI RTC A RTC oscillator input RTCXTALO RTC A RTC oscillator output WRn EBUS 4ma SRAM Write strobe out RDn EBUS 4ma SRAM Read / OE strobe out WAITn EBUS I PU SRAM Wait in AD[25:0] EBUS 8ma Shared Address bus out DA[31:0] EBUS 8ma PU Shared Data bus in/out CSn[3:0] EBUS 4ma PU Chip select out CSn[7:6] EBUS 4ma PU Chip select out DQMn[3:0] EBUS 8ma Shared data mask out SDCLK SDRAM 8ma SDRAM clock out SDCLKEN SDRAM 8ma SDRAM clock enable out SDCSn[3:0] SDRAM 4ma SDRAM chip selects out RASn SDRAM 8ma SDRAM RAS out CASn SDRAM 8ma SDRAM CAS out SDWEn SDRAM 8ma SDRAM write enable out P[17:0] Raster 4ma PU Pixel data bus out SPCLK Raster 12ma PU Pixel clock in/out HSYNC Raster 8ma PU Horizontal synchronization / line pulse out V_CSYNC Raster 8ma PU Vertical or composite synchronization / frame pulse out BLANK Raster 8ma PU Composite blanking signal out BRIGHT Raster 4ma PWM brightness control out PWMOUT PWM 8ma Pulse width modulator output Xp, Xm ADC A Touchscreen ADC X axis Yp, Ym ADC A Touchscreen ADC Y axis sXp, sXm ADC A Touchscreen ADC X axis feedback sYp, sYm ADC A Touchscreen ADC Y axis feedback VDD_ADC ADC P Touchscreen ADC power, 3.3V GND_ADC ADC G Touchscreen ADC ground COL[7:0] Key 8ma PU Key matrix column inputs ROW[7:0] Key 8ma PU Key matrix row outputs USBp[2:0] USB A USB positive signals USBm[2:0] USB A USB negative signals TXD0 UART1 4ma Transmit out RXD0 UART1 I PU Receive in CTSn UART1 I PU Clear to send / transmit enable DSRn UART1 I PU Data set ready / Data Carrier Detect DTRn UART1 4ma Data Terminal Ready output RTSn UART1 4ma Ready to send TXD1 UART2 4ma Transmit / IrDA output RXD1 UART2 I PU Receive / IrDA input TXD2 UART3 4ma Transmit RXD2 UART3 I PU Receive MDC EMAC 4ma Management data clock Table S. Pin Descriptions (Continued) Pin Name Block Pad Type Pull Type

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor MDIO EMAC 4ma PU Management data input/output RXCLK EMAC I PD Receive clock in MIIRXD[3:0] EMAC I PD Receive data in RXDVAL EMAC I PD Receive data valid RXERR EMAC I PD Receive data error TXCLK EMAC I PU Transmit clock in MIITXD[3:0] EMAC I PD Transmit data out TXEN EMAC 4ma PD Transmit enable TXERR EMAC 4ma PD Transmit error CRS EMAC I PD Carrier sense CLD EMAC I PU Collision detect GRLED LED 12ma Green LED RDLED LED 12ma Red LED EECLK EEPROM 4ma PU EEPROM / Two-wire Interface clock EEDAT EEPROM 4ma PU EEPROM / Two-wire Interface data ABITCLK AC97 8ma PD AC97 bit clock ASYNC AC97 8ma PD AC97 frame sync ASDI AC97 I PD AC97 Primary input ASDO AC97 8ma PU AC97 output ARSTn AC97 8ma AC97 reset SCLK1 SPI1 8ma PD SPI bit clock SFRM1 SPI1 8ma PD SPI Frame Clock SSPRX1 SPI1 I PD SPI input SSPTX1 SPI1 8ma SPI output INT[3:0] INT I PD External interrupts PRSTn Syscon I PU Power on reset RSTOn Syscon 4ma User Reset in out - open drain SLA[1:0] EEPROM 4ma Flash programming voltage control VS1 PCMCIA I PU Voltage sense VS2 PCMCIA I PU Voltage sense MCD1 PCMCIA I PU Card detect MCD2 PCMCIA I PU Card detect MCBVD1 PCMCIA I PU Voltage detection / status change MCBVD2 PCMCIA I PU Voltage detection MCDIR PCMCIA 4ma Data transceiver direction control MCDAENn PCMCIA 4ma Data bus transceiver enable MCADENn PCMCIA 4ma Address bus transceiver enable MCREGn PCMCIA 4ma PU Memory card register MCEHn PCMCIA 4ma PU Memory card high byte select MCELn PCMCIA 4ma PU Memory card low byte select IORDn PCMCIA 4ma PU I/O card read IOWRn PCMCIA 4ma PU I/O card write MCRDn PCMCIA 4ma PU Memory card read MCWRn PCMCIA 4ma PU Memory card write READY PCMCIA I PU Ready / interrupt WP PCMCIA I PU Write protect MCWAITn PCMCIA I PU Wait Input MCRESETn PCMCIA 4ma Card reset Table S. Pin Descriptions (Continued) Pin Name Block Pad Type Pull Type EGPIO[15:0] GPIO I/O, 4 ma PU Enhanced GPIO DD[15:8] IDE 8ma PU IDE data bus DD7 IDE 8ma PD IDE data bus DD[6:0] IDE 8ma PU IDE data bus IDEDA[2:0] IDE 8ma IDE Device address output IDECS0n IDE 8ma IDE Chip Select 0 output IDECS1n IDE 8ma IDE Chip Select 1 output DIORn IDE 8ma IDE Read strobe output DIOWn IDE 8ma IDE Write strobe output DMACKn IDE 8ma IDE DMA acknowledge output IORDY IDE I PU IDE ready input CVDD Power P Digital power, 1.8V RVDD Power P Digital power, 3.3V CGND Ground G Digital ground RGND Ground G Digital ground Table S. Pin Descriptions (Continued) Pin Name Block Pad Type Pull Type

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor Table T illustrates the pin signal multiplexing and configuration options. Table T. Pin Multiplex Usage Information Physical Pin Name COL[7:0] GPIO GPIO Port D[7:0] ROW[7:0] GPIO GPIO Port C[7:0] EGPIO[0] Ring Indicator Input RI EGPIO[1] 1Hz clock monitor CLK1HZ EGPIO[2] IDE DMA request DMARQ EGPIO[3] Transmit Enable output / HDLC clocks TENn / HDLCCLK1 / HDLCCLK3 EGPIO[4] I2S Transmit Data 1 SDO1 EGPIO[5] I2S Receive Data 1 SDI1 EGPIO[6] I2S Transmit Data 2 SDO2 EGPIO[7] DMA Request 0 DREQ0 EGPIO[8] DMA Acknowledge 0 DACK0 EGPIO[9] DMA EOT 0 DEOT0 EGPIO[10] DMA Request 1 DREQ1 EGPIO[11] DMA Acknowledge 1 DACK1 EGPIO[12] DMA EOT 1 DEOT1 EGPIO[13] I2S Receive Data 2 SDI2 EGPIO[14] PWM 1 output PWMOUT1 EGPIO[15] IDE Device active / present DASP ABITCLK I2S Serial clock SCLK ASYNC I2S Frame Clock LRCK ASDO I2S Transmit Data 0 SDO0 ASDI I2S Receive Data 0 SDI0 ARSTn I2S Master clock MCLK SCLK1 I2S Serial clock SCLK SFRM1 I2S Frame Clock LRCK SSPTX1 I2S Transmit Data 0 SDO0 SSPRX1 I2S Receive Data 0 SDI0 IDEDA[2:0] GPIO GPIO Port E[7:5] IDECS0n GPIO GPIO Port E[4] IDECS1n GPIO GPIO Port E[3] DIORn GPIO GPIO Port E[2] GRLED LED GPIO Port E[1] RDLED LED GPIO Port E[0] DD[7:0] GPIO GPIO Port H[7:0] DD[15:12] GPIO GPIO Port G[7:4] SLA[1:0] GPIO GPIO Port G[3:2] EEDAT GPIO GPIO Port G[1] EECLK GPIO GPIO Port G[0] FGPIO[7] GPIO VS2 FGPIO[6] GPIO READY FGPIO[5] GPIO VS1 FGPIO[4] GPIO MCBVD2 FGPIO[3] GPIO MCBVD1 FGPIO[2] GPIO MCD2 FGPIO[1] GPIO MCD1 FGPIO[0] GPIO WP

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9315 Enhanced Universal Platform SOC Processor Acronyms and Abbreviations The following tables list abbreviations and acronyms used in this data sheet. Units of Measurement Term Definition ADC Analog-to-Digital Converter ALT Alternative AMBA Advanced Micro-controller Bus Architecture ATAPI ATA Packet Interface CODEC COder / DECoder CRC Cyclic Redundancy Check DAC Digital-to-Analog Converter DMA Direct-Memory Access EBUS External Memory Bus EEPROM Electronically Erasable Programmable Read Only Memory EMAC Ethernet Media Access Controller FIFO First In / First Out FIQ Fast Interrupt Request FLASH Flash memory GPIO General Purpose I/O HDLC High-level Data Link Control I/F Interface I2S Inter-IC Sound IC Integrated Circuit ICE In-Circuit Emulator IDE Integrated Drive Electronics IEEE Institute of Electronics and Electrical Engineers IrDA Infrared Data Association IRQ Standard Interrupt Request ISO International Standards Organization JTAG Joint Test Action Group LFSR Linear Feedback Shift Register MII Media Independent Interface MMU Memory Management Unit OHCI Open Host Controller Interface PHY Ethernet PHYsical layer interface PIO Programmed I/O RISC Reduced Instruction Set Computer SDMI Secure Digital Music Initiative SDRAM Synchronous Dynamic RAM SPI Serial Peripheral Interface SRAM Static Random Access Memory STA Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium TFT Thin Film Transistor TLB Translation Lookaside Buffer USB Universal Serial Bus Symbol Unit of Measure degree Celsius Hz Hertz = cycle per second Kbps Kilobits per second kbyte Kilobyte kHz KiloHertz = 1000 Hz Mbps Megabits per second MHz MegaHertz = 1,000 kHz µA microAmpere = 10-6 Ampere µs microsecond = 1,000 nanoseconds = 10-6 seconds mA milliAmpere = 10-3 Ampere ms millisecond = 1,000 microseconds = 10-3 seconds mW milliWatt = 10-3 Watts ns nanosecond = 10-9 seconds pF picoFarad = 10-12 Farads V Volt W Watt Term Definition

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS638PP4 EP9315 Enhanced Universal Platform SOC Processor

Ordering Information

The order numbers for the device are: EP9315-CB 0°C to +70°C 352-pin PBGA EP9315-CBZ 0°C to +70°C 352-pin PBGA Lead Free EP9315-IB -40°C to +85°C 352-pin PBGA EP9315-IBZ -40°C to +85°C 352-pin PBGA Lead Free EP9315 — CBZ Product Line: Embedded Processor Part Number Temperature Range: C = Commercial Version Package Type: B = 352-Ball, Plastic Ball Grid Array (27 mm x 27 mm) Note: Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative. I = Industrial Operating Version Z = Lead Free Lead Material: E = Extended Operating Version Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that infor- mation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIR- CRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRAN- TIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this doc- ument may be trademarks or service marks of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola and SPI are registered trademarks of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds.