EP9302-CQ

Cirrus Logic

High-speed ARM9 System-on-chip Processor with MaverickCrunch

Manufacturer: Cirrus Logic

Document: 42 Pages / 302Kb

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EP9302 CIRRUS | Alldatasheet

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Technical content

FEATURES

16-kbyte Instruction Cache 16-kbyte Data Cache Linux®, Microsoft® Windows® CE-enabled MMU 100-MHz System Bus MaverickCrunch™ Math Engine Floating point, Integer and Signal Processing Instructions Optimized for digital music compression and decompression algorithms. Hardware interlocks allow in-line coding. MaverickKey™ IDs 32-bit unique ID can be used for DRM-compliant, 128-bit random ID. Integrated Peripheral Interfaces 16-bit SDRAM Interface (up to 4 banks) 16-bit SRAM / FLASH / ROM Serial EEPROM Interface 1/10/100 Mbps Ethernet MAC Two UARTs Two-port USB 2.0 Full-speed Host (OHCI) (12 Mbits per second) IrDA Interface ADC Serial Peripheral Interface (SPI) Port 6-channel Serial Audio Interface (I2S) 2-channel, Low-cost Serial Audio Interface (AC'97) Internal Peripherals

12 Direct Memory Access (DMA) Channels

Real-time Clock with Software Trim Dual PLL controls all clock domains. Watchdog Timer Two General-purpose 16-bit Timers One General-purpose 32-bit Timer One 40-bit Debug Timer Interrupt Controller Boot ROM Package 208-pin LQFP Unified SDRAM I/F (2) USB Hosts Ethernet MAC Bus Bridge Boot ROM MaverickKeyTM

12 Channel DMA

SRAM & Flash I/F ARM920T MMU D-Cache 16KB I-Cache 16KB Processor Bus Peripheral Bus Serial Audio Interface Interrupts & GPIO Clocks & Timers (2) UARTs IrDA MaverickCrunchTM COMMUNICATIONS PORTS USER INTERFACE MEMORY AND STORAGE

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS653PP3 EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch The EP9302 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: Industrial controls Digital media servers Integrated home media gateways Digital audio jukeboxes Streaming audio players Set-top boxes Point-of-sale terminals Thin clients Biometric security systems GPS & fleet management systems Educational toys Industrial computers Industrial hand-held devices Voting machines Medical equipment The EP9302 is one of a series of ARM920T-based devices. Other members of the family have different peripheral sets, coprocessors and package configurations. The ARM920T microprocessor core with separate 16 kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunch™ co- processor enabling faster than real-time compression of audio CDs. The MaverickKey™ unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. A high-performance 1/10/100 Mbps Ethernet media access controller (EMAC) is included along with external interfaces to SPI, AC’97, and I2S audio. A two-port USB

2.0 Full-speed Host (OHCI) (12 Mbits per second), two

UARTs, and a analog voltage measurement analog-to- digital converter (ADC) are included as well. The EP9302 is a high-performance, low-power RISC- based, single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1.8 V supply, while the I/O operates at 3.3 V with power usage between 100 mW and 750 mW (dependent on speed). OVERVIEW Table A. Change History Revision Date Changes PP1 June 2004 Initial Release. PP2 July 2004 Update AC data. Add ADC data. PP3 March 2005 Update electrical specs with most-current characterization data.

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS653PP3 EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Processor Core - ARM920T The ARM920T is a Harvard architecture processor with separate 16-kbyte instruction and data caches with an 8- word line length but a unified memory. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory, and write stages. Key features include: ARM (32-bit) and Thumb (16-bit compressed) instruction sets 32-bit Advanced Micro-Controller Bus Architecture (AMBA) 16 kbyte Instruction Cache with lockdown 16 kbyte Data Cache (programmable write-through or write-back) with lockdown MMU for Linux®, Microsoft® Windows® CE and other operating systems Translation Look Aside Buffers with 64 Data and 64 Instruction Entries Programmable Page Sizes of 1 Mbyte, 64 kbyte, 4 kbyte, and 1 kbyte Independent lockdown of TLB Entries MaverickCrunch™ Math Engine The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiply-accumulate (MAC) instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include: IEEE-754 single and double precision floating point 32 / 64-bit integer Add / multiply / compare Integer MAC 32-bit input with 72-bit accumulate Integer Shifts Floating point to/from integer conversion Sixteen 64-bit register files Four 72-bit accumulators MaverickKey™ Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID are programmed into the EP9302 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9302 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances. General Purpose Memory Interface (SDRAM, SRAM, ROM, Flash) The EP9302 features a unified memory address model where all memory devices are accessed over a common address/data bus. Memory accesses are performed via the Processor bus. The SRAM memory controller supports 8 and 16-bit devices and accommodates an internal boot ROM concurrently with 16-bit SDRAM memory. 1 to 4 banks of 16-bit ,100-MHz SDRAM Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory NOR FLASH memory supported Table B. General Purpose Memory Interface Pin Assignments Pin Mnemonic Pin Description SDCLK SDRAM Clock SDCLKEN SDRAM Clock Enable SDCSn[3:0] SDRAM Chip Selects 3-0 RASn SDRAM RAS CASn SDRAM CAS SDWEn SDRAM Write Enable CSn[7:6] and CSn[3:0] Chip Selects 7, 6, 3, 2, 1, 0 AD[25:0] Address Bus 25-0 DA[15:0] Data Bus 15-0 DQMn[1:0] SDRAM Output Enables / Data Masks WRn SRAM Write Strobe RDn SRAM Read / OE Strobe WAITn SRAM Wait Input

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Ethernet Media Access Controller (MAC) The MAC subsystem is compliant with the ISO/TEC 802.3 topology for a single shared medium with several stations. Multiple MII-compliant PHYs are supported. Features include: Supports 1/10/100 Mbps transfer rates for home / small-business / large-business applications Interfaces to an off-chip PHY through industry- standard Media-independent Interface (MII) Serial Interfaces (SPI, I2S, and AC ’97) The Serial Peripheral Interface (SPI) port can be configured as a master or a slave, supporting the National Semiconductor®, Motorola®, and Texas Instruments® signaling protocols. The AC'97 port supports multiple codecs for multichannel audio output with a single stereo input. The I2S port supports stereo 24-bit audio. These ports are multiplexed so that the I2S port will take over either the AC'97 pins or the SPI pins. Normal Mode: One SPI Port and one AC’97 Port I2S on SSP Mode: One AC’97 Port and one I2S Port I2S on AC’97 Mode: One SPI Port and one I2S Port Note: I2S may not be output on AC’97 and SSP ports at the same time. 12-bit Analog-to-digital Converter (ADC) The ADC block consists of a 12-bit analog-to-digital converter with a analog input multiplexer. The multiplexer can select to measure battery voltage and other miscellaneous voltages on the external measurement pins. Features include: 5 external pins for ADC measurement Measurement pin input range: 0 to 3.3 V. ADC-conversion-complete interrupt signal Table C. Ethernet Media Access Controller Pin Assignments Pin Mnemonic Pin Description MDC Management Data Clock MDIO Management Data I / O RXCLK Receive Clock MIIRXD[3:0] Receive Data RXDVAL Receive Data Valid RXERR Receive Data Error TXCLK Transmit Clock MIITXD[3:0] Transmit Data TXEN Transmit Enable TXERR Transmit Error CRS Carrier Sense CLD Collision Detect Table D. Audio Interfaces Pin Assignment Pin Name Normal Mode I2S on SSP Mode I2S on AC'97 Mode Pin

Description

SPI Frame Clock I2S Frame Clock SPI Frame Clock SSPRX1 SPI Serial Input I2S Serial Input SPI Serial Input SSPTX1 SPI Serial Output I2S Serial Output SPI Serial Output (No I2S Master Clock) ARSTn AC'97 Reset AC'97 Reset I2S Master Clock ABITCLK AC'97 Bit Clock AC'97 Bit Clock I2S Serial Clock ASYNC AC'97 Frame Clock AC'97 Frame Clock I2S Frame Clock ASDI AC'97 Serial Input AC'97 Serial Input I2S Serial Input ASDO AC'97 Serial Output AC'97 Serial Output I2S Serial Output Table E. 12-bit Analog-to-Digital Converter Pin Assignments Pin Mnemonic Pin Description ADC[0] (Ym, pin 135) External Analog Measurement Input ADC[1] (sXp, pin 134) External Analog Measurement Input ADC[2] (sXm, pin 133) External Analog Measurement Input ADC[3] (sYp, pin 132) External Analog Measurement Input ADC[4] (sYm, pin 131) External Analog Measurement Input

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS653PP3 EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Universal Asynchronous Receiver/Transmitters (UARTs) Two 16550-compatible UARTs are supplied. One provides asynchronous HDLC (High-level Data Link Control) protocol support for full duplex transmit and receive. The HDLC receiver handles framing, address matching, CRC checking, control-octet transparency, and optionally passes the CRC to the host at the end of the packet. The HDLC transmitter handles framing, CRC generation, and control-octet transparency. The host must assemble the frame in memory before transmission. The HDLC receiver and transmitter use the UART FIFOs to buffer the data streams. The second UART provides IrDA® compatibility. UART1 supports modem bit rates up to 115.2 kbps, supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx, Tx and modem status change. UART2 contains an IrDA encoder operating at either the slow (up to 115 kbps), medium (0.576 or 1.152 Mbps), or fast (4 Mbps) IR data rates. It also has a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Dual-port USB Host The USB Open Host Controller Interface (Open HCI) provides full-speed serial communications ports at a baud rate of 12 Mbits/sec. Up to 127 USB devices (printer, mouse, camera, keyboard, etc.) and USB hubs can be connected to the USB host in the USB “tiered- star” topology. This includes the following feature: Compliance with the USB 2.0 specification Compliance with the Open HCI Rev 1.0 specification Supports both low-speed (1.5 Mbps) and full-speed (12 Mbps) USB device connections Root HUB integrated with 2 downstream USB ports Transceiver buffers integrated, over-current protection on ports Supports power management Operates as a master on the bus The Open HCI host controller initializes the master DMA transfer with the AHB bus: Fetches endpoint descriptors and transfer descriptors Accesses endpoint data from system memory Accesses the HC communication area Writes status and retire transfer descriptor Note: USBm[1] and USBp[1] are not bonded out. Two-wire Interface The two-wire interface provides communication and control for synchronous-serial-driven devices. Real-Time Clock with Software Trim The software trim feature on the real time clock (RTC) provides software controlled digital compensation of the 32.768 KHz input clock. This compensation is accurate to ± 1.24 sec/month. Note: A real time clock must be connected to RTCXTALI or the EP9302 device will not boot. Table F. Universal Asynchronous Receiver/Transmitters Pin Assignments Pin Mnemonic Pin Name - Description TXD0 UART1 Transmit RXD0 UART1 Receive CTSn UART1 Clear To Send / Transmit Enable DSRn / DCDn UART1 Data Set Ready / Data Carrier Detect DTRn UART1 Data Terminal Ready RTSn UART1 Ready To Send EGPIO[0] / RI UART1 Ring Indicator TXD1 / SIROUT UART2 Transmit / IrDA Output RXD1 / SIRIN UART2 Receive / IrDA Input Table G. Dual Port USB Host Pin Assignments Pin Mnemonic Pin Name - Description USBp[2,0] USB Positive signals USBm[2,0] USB Negative Signals Table H. Two-Wire Port with EEPROM Support Pin Assignments Pin Mnemonic Pin Name - Description Alternative Usage EECLK Two-wire Interface Clock General Purpose I/O EEDATA Two-Wire Interface Data General Purpose I/O Table I. Real-Time Clock with Pin Assignments Pin Mnemonic Pin Name - Description RTCXTALI Real-Time Clock Oscillator Input RTCXTALO Real-Time Clock Oscillator Output

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch PLL and Clocking The Processor and the Peripheral Clocks operate from a single 14.7456 MHz crystal. The Real Time Clock operates from a 32.768 KHz external oscillator. Timers The Watchdog Timer ensures proper operation by requiring periodic attention to prevent a reset-on-time- out. Two 16-bit timers operate as free running down-counters or as periodic timers for fixed interval interrupts and have a range of 0.03 ms to 4.27 seconds. One 32-bit timer, plus a 6-bit prescale counter, has a range of 0.03 µs to 73.3 hours. One 40-bit debug timer, plus 6-bit prescale counter, has a range of 1.0 µs to 12.7 days. Interrupt Controller The interrupt controller allows up to 54 interrupts to generate an Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) signal to the processor core. Thirty-two hardware priority assignments are provided for assisting IRQ vectoring, and two levels are provided for FIQ vectoring. This allows time critical interrupts to be processed in the shortest time possible. Internal interrupts may be programmed as active high or active low level sensitive inputs. GPIO pins programmed as interrupts may be programmed as active high level sensitive, active low level sensitive, rising edge triggered, falling edge triggered, or combined rising/falling edge triggered. Supports 54 interrupts from a variety of sources (such as UARTs, GPIO and ADC) Routes interrupt sources to either the ARM920T’s IRQ or FIQ (Fast IRQ) inputs Three dedicated off-chip interrupt lines operate as active high level sensitive interrupts Any of the 19 GPIO lines maybe configured to generate interrupts Software supported priority mask for all FIQs and IRQs Note: INT[2] is not bonded out. Dual LED Drivers Two pins are assigned specifically to drive external LEDs. General Purpose Input/Output (GPIO) The 16 EGPIO and the 3 FGPIO pins may each be configured individually as an output, an input, or an interrupt input. There are 10 pins that may alternatively be used as input, output, or open-drain pins, but do not support interrupts. These pins are:

Ethernet MDIO
Both LED Outputs
EEPROM Clock and Data
HGPIO[5:2]
CGPIO[0] 6 pins may alternatively be used as inputs only:
CTSn, DSRn / DCDn
3 Interrupt Lines 2 pins may alternatively be used as outputs only:
RTSn
ARSTn Table J. PLL and Clocking Pin Assignments Pin Mnemonic Pin Name - Description XTALI Main Oscillator Input XTALO Main Oscillator Output VDD_PLL Main Oscillator Power GND_PLL Main Oscillator Ground Table K. External Interrupt Controller Pin Assignment Pin Mnemonic Pin Name - Description INT[3] and INT[1:0] External Interrupts 2, 1, 0 Table L. Dual LED Pin Assignments Pin Mnemonic Pin Name -

Table M. General Purpose Input/Output Pin Assignment Pin Mnemonic Pin Name - Description EGPIO[15:0] Expanded General Purpose Input / Output Pins with Interrupts FGPIO[3:1] Expanded General Purpose Input / Output Pins with Interrupts

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS653PP3 EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Reset and Power Management The chip may be reset through the PRSTn pin or through the open drain common reset pin, RSTOn. Clocks are managed on a peripheral-by-peripheral basis and may be turned off to conserve power. The processor clock is dynamically adjustable from 0 to 200 MHz (184 MHz for industrial conditions). Hardware Debug Interface The JTAG interface allows use of ARM’s Multi-ICE or other in-circuit emulators. 12-Channel DMA Controller The DMA module contains 12 separate DMA channels. Ten of these may be used for peripheral-to-memory or memory-to-peripheral access. Two of these are dedicated to memory-to-memory transfers. Each DMA channel is connected to the 16-bit DMA request bus. The request bus is a collection of requests, Serial Audio and UARTs. Each DMA channel can be used independently or dedicated to any request signal. For each DMA channel, source and destination addressing can be independently programmed to increment, decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses. Internal Boot ROM The Internal 16-kbyte ROM allows booting from FLASH memory, SPI or UART. Consult the EP9301 User’s Guide for operational details. Table N. Reset and Power Management Pin Assignments Pin Mnemonic Pin Name - Description PRSTn Power On Reset RSTOn User Reset In/Out – Open Drain – Preserves Real Time Clock value Table O. Hardware Debug Interface Pin Mnemonic Pin Name - Description TCK JTAG Clock TDI JTAG Data In TDO JTAG Data Out TMS JTAG Test Mode Select TRSTn JTAG Port Reset

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Electrical Specifications Absolute Maximum Ratings Note: 1. Includes all power generated by AC and/or DC output loading. 2. The power supply pins are at maximum values listed in “Recommended Operating Conditions”, below. 3. At ambient temperatures above 70° C, total power dissipation must be limited to less than 2.5 Watts. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Recommended Operating Conditions (All grounds = 0 V, all voltages with respect to 0 V) Parameter Symbol Min Max Unit Power Supplies RVDD CVDD VDD_PLL VDD_ADC 3.96 2.16 2.16 3.96 V V V V Total Power Dissipation (Note 1) W Input Current per Pin, DC (Except supply pins) ±10 mA Output current per pin, DC ±50 mA Digital Input voltage (Note 2) -0.3 RVDD+0.3 V Storage temperature -40 +125 (All grounds = 0 V, all voltages with respect to 0 V) Parameter Symbol Min Typ Max Unit Power Supplies RVDD CVDD VDD_PLL VDD_ADC 3.0 1.65 1.65 3.0 3.3 1.80 1.80 3.3 3.6 1.94 1.94 3.6 V V V V Operating Ambient Temperature - Commercial TA +25 +70 Operating Ambient Temperature - Industrial TA -40 +25 +85 Processor Clock Speed - Commercial FCLK 200 MHz Processor Clock Speed - Industrial FCLK 184 MHz System Clock Speed - Commercial HCLK 100 MHz System Clock Speed - Industrial HCLK MHz

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS653PP3 EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch DC Characteristics Note: 4. For open drain pins, high level output voltage is dependent on the external load. 5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table Q on page 39). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not driven and programmed as an input, it should be tied to power or ground through its own resistor. (TA = 0 to 70° C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V; All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted) Parameter Symbol Min Max Unit High level output voltage Iout = -4 mA (Note 4) Voh 0.85 × RVDD V Low level output voltage Iout = 4 mA Vol 0.15 × RVDD V High level input voltage (Note 5) Vih 0.65 × RVDD VDD + 0.3 V Low level input voltage (Note 5) Vil −0.3 0.35 × RVDD V High level leakage current Vin = 3.3 V (Note 5) Iih µA Low level leakage current Vin = 0 (Note 5) Iil -10 µA Parameter Min Typ Max Unit Power Supply Pins (Outputs Unloaded) Power Supply Current: CVDD / VDD_PLL Total RVDD 180 230 mA mA Low-Power Mode Supply Current CVDD / VDD_PLL Total RVDD 1.0 3.5 mA mA

Figure 1. Timing Diagram Drawing Key Unless specified otherwise, the following conditions are true for all timing measurements.

TA = 0 to 70° C
CVDD = VDD_PLL = 1.8V
RVDD = 3.3 V
All grounds = 0 V
Logic 0 = 0 V, Logic 1 = 3.3 V
Output loading = 50 pF
Timing reference levels = 1.5 V
The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between 33 MHz and 100 MHz (92 MHz for industrial conditions). Clock High to Low High/Low to High Bus Change Bus Valid Undefined/Invalid Valid Bus to Tristate Bus/Signal Omission

Figure 3. SDRAM Burst Read Cycle Timing Measurement

Figure 4. SDRAM Burst Write Cycle Timing Measurement

Figure 5. SDRAM Auto Refresh Cycle Timing Measurement

Figure 6. Static Memory Multiple Word Read 8-bit Cycle Timing Measurement

Figure 7. Static Memory Multiple Word Write 8-bit Cycle Timing Measurement

Figure 8. Static Memory Multiple Word Read 16-bit Cycle Timing Measurement

Figure 9. Static Memory Multiple Word Write 16-bit Cycle Timing Measurement

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details. Figure 10. Static Memory Burst Read Cycle Timing Measurement

These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details. Figure 11. Static Memory Burst Write Cycle Timing Measurement

Figure 12. Static Memory Single Read Wait Cycle Timing Measurement

Figure 13. Static Memory Single Write Wait Cycle Timing Measurement

Notes: 1. X and Y represent any two chip select numbers.

IDCY occurs on read-to-write and write-to-read.
IDCY is honored when going from a asynchronous device (CSx) to a synchronous device (/SDCSy).

Figure 14. Static Memory Turnaround Cycle Timing Measurement

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Ethernet MAC Interface STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium. PHY - Ethernet physical layer interface. Parameter Symbol Min Typ Max Unit

10 Mbit

100 Mbit

tTX_per 400 ns TXCLK high time tTX_high 140 200 260 ns TXCLK low time tTX_low 140 200 260 ns TXCLK to signal transition delay time tTXd ns TXCLK rise/fall time tTXrf ns RXCLK cycle time tRX_per 400 ns RXCLK high time tRX_high 140 200 260 ns RXCLK low time tRX_low 140 200 260 ns RXDVAL / RXERR setup time tRXs ns RXDVAL / RXERR hold time tRXh ns RXCLK rise/fall time tRXrf ns MDC cycle time tMDC_per 400 400 ns MDC high time tMDC_high 160 160 ns MDC low time tMDC_low 160 160 ns MDC rise/fall time tMDCrf ns MDIO setup time (STA sourced) tMDIOs ns MDIO hold time (STA sourced) tMDIOh ns MDC to MDIO signal transition delay time (PHY sourced) tMDIOd 300 300 ns

Figure 15. Ethernet MAC Timing Measurement

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Audio Interface Note: The tspix_clk is programmable by the user. The following table contains the values for the timings of each of the SPI modes. Parameter Symbol Min Typ Max Unit SCLK cycle time tclk_per tspix_clk ns SCLK high time tclk_high (tspix_clk) / 2 ns SCLK low time tclk_low (tspix_clk) / 2 ns SCLK rise/fall time tclkrf ns Data from master valid delay time tDMd ns Data from master setup time tDMs ns Data from master hold time tDMh ns Data from slave setup time tDSs ns Data from slave hold time tDSh ns

Figure 18. SPI Format with SPH=1 Timing Measurement

ti2s_clk is programmable by the user. Figure 19. Inter-IC Sound (I2S) Timing Measurement

Figure 20. AC ‘97 Configuration Timing Measurement

ADIV refers to bit 16 in the KeyTchClkDiv register. ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4. ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16. same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion. Note that reading TSXYResult during a conversion will not affect the result of the ongoing process.

Read the TSXYResult register into a local variable to initiate a conversion.
If the value of bit 31 of the local variable is '0' then repeat step 1.
Delay long enough to meet the maximum sample rate as shown above.
Mask the local variable with 0xFFFF to remove extraneous data.
If signed mode is used, do a sign extend of the lower halfword.
Return the sampled value.

Figure 21. ADC Transfer Function

Figure 22. JTAG Timing Measurement

208 Pin LQFP Package Outline

2.19 208-Pin LQFP (28 × 28 × 1.40-mm Body) NOTES: Dimensions are in millimeters, and controlling dimension is millimeter. Package body dimensions do not include mold protrusion, which is 0.25 mm (0.010 in). Pin 1 identiﬁcation may be either ink dot or dimple. Package top dimensions can be smaller than bottom dimensions by 0.20 mm (0.008 in). The ‘lead width with plating’ dimension does not include a total allowable dambar protrusion of 0.08 mm (at maximum material condition). Ejector pin marks in molding are present on every package. Drawing above does not reﬂect exact package pin count. Pin 1 Indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) BSC 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0° MIN 7° MAX 0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 0.45 (0.018) 0.75 (0.030) 0.05 (0.002) 1.00 (0.039) BSC Pin 1 Pin 208 1.60 (0.063) 0.15 (0.006)

208 Pin LQFP Pinout

The following table shows the 208 pin LQFP pinout.

VDD_core is CVDD.
VDD_ring is RVDD.
NC means that the pin is not connected. Pin List The following Low-Profile Quad Flat Pack (LQFP) pin assignment table is sorted in order of pin. Table P. Pin List in Numerical Order by Pin Number Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name Pin Number Pin Name CSn[7] AD[5] AD[9] 106 USBp[0] 141 EGPIO[10] 176 TXEN CSn[6] DA[12] DA[1] 107 ABITCLK 142 EGPIO[9] 177 MIITXD[0] CSn[3] AD[4] AD[8] 108 CTSn 143 EGPIO[8] 178 MIITXD[1] CSn[2] DA[11] DA[0] 109 RXD[0] 144 EGPIO[7] 179 MIITXD[2] CSn[1] AD[3] DSRn 110 RXD[1] 145 EGPIO[6] 180 MIITXD[3] AD[25] vdd_ring DTRn 111 vdd_ring 146 EGPIO[5] 181 TXCLK vdd_ring gnd_ring TCK 112 gnd_ring 147 EGPIO[4] 182 RXERR gnd_ring DA[10] TDI 113 TXD[0] 148 EGPIO[3] 183 RXDVAL AD[24] AD[2] TDO 114 TXD[1] 149 gnd_ring 184 MIIRXD[0] SDCLK DA[9] TMS 115 CGPIO[0] 150 vdd_ring 185 MIIRXD[1] AD[23] AD[1] vdd_ring 116 gnd_core 151 EGPIO[2] 186 MIIRXD[2] vdd_core DA[8] gnd_ring 117 PLL_GND 152 EGPIO[1] 187 gnd_ring gnd_core AD[0] BOOT[1] 118 XTALI 153 EGPIO[0] 188 vdd_ring SDWEn vdd_ring BOOT[0] 119 XTALO 154 ARSTn 189 MIIRXD[3] SDCSn[3] gnd_ring gnd_ring 120 PLL_VDD 155 TRSTn 190 RXCLK SDCSn[2] NC NC 121 vdd_core 156 ASDI 191 MDIO SDCSn[1] NC EECLK 122 gnd_ring 157 USBm[2] 192 MDC SDCSn[0] vdd_ring EEDAT 123 vdd_ring 158 USBp[2] 193 RDn vdd_ring gnd_ring ASYNC 124 RSTOn 159 WAITn 194 WRn gnd_ring AD[15] vdd_core 125 PRSTn 160 EGPIO[15] 195 AD[16] RASn DA[7] gnd_core 126 CSn[0] 161 gnd_ring 196 AD[17] CASn vdd_core ASDO 127 gnd_core 162 vdd_ring 197 gnd_core DQMn[1] gnd_core SCLK1 128 vdd_core 163 EGPIO[14] 198 vdd_core DQMn[0] AD[14] SFRM1 129 gnd_ring 164 EGPIO[13] 199 HGPIO[2] AD[22] DA[6] SSPRX1 130 vdd_ring 165 EGPIO[12] 200 HGPIO[3] AD[21] AD[13] SSPTX1 131 ADC[4] 166 gnd_core 201 HGPIO[4] vdd_ring DA[5] GRLED 132 ADC[3] 167 vdd_core 202 HGPIO[5] gnd_ring AD[12] RDLED 133 ADC[2] 168 FGPIO[3] 203 gnd_ring DA[15] DA[4] vdd_ring 134 ADC[1] 169 FGPIO[2] 204 vdd_ring AD[7] AD[11] 100 gnd_ring 135 ADC[0] 170 FGPIO[1] 205 AD[18] DA[14] vdd_ring 101 INT[3] 136 ADC_VDD 171 gnd_ring 206 AD[19] AD[6] gnd_ring 102 INT[1] 137 RTCXTALI 172 vdd_ring 207 AD[20] DA[13] DA[3] 103 INT[0] 138 RTCXTALO 173 CLD 208 SDCLKEN vdd_core AD[10] 104 RTSn 139 ADC_GND 174 CRS gnd_core DA[2] 105 USBm[0] 140 EGPIO[11] 175 TXERR

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS653PP3 EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch The following section focuses on the EP9302 pin signals from two viewpoints - the pin usage and pad characteristics, and the pin multiplexing usage. The first table (Table Q) is a summary of all the EP9302 pin signals. The second table (Table R) illustrates the pin signal multiplexing and configuration options. Table Q is a summary of the EP9302 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP).) Under the Pad Type column: A - Analog pad P - Power pad G - Ground pad I - Pin is an input only I/O - Pin is input/output 4mA - Pin is a 4mA output driver 8mA - Pin is an 8mA output driver 12mA - Pin is an 12mA output driver See the text description for additional information about bi-directional pins. Under the Pull Type Column: PU - Resistor is a pull up to the RVDD supply PD - Resistor is a pull down to the RGND supply

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Table Q. Pin Descriptions Pin Name Block Pad Type Pull Type I PD JTAG clock in TDI JTAG I PD JTAG data in TDO JTAG 4ma JTAG data out TMS JTAG I PD JTAG test mode select TRSTn JTAG I PD JTAG reset BOOT[1:0] System I PD Boot mode select in XTALI PLL A Main oscillator input XTALO PLL A Main oscillator output VDD_PLL PLL P Main oscillator power, 1.8V GND_PLL PLL G Main oscillator ground RTCXTALI RTC A RTC oscillator input RTCXTALO RTC A RTC oscillator output WRn EBUS 4ma SRAM Write strobe out RDn EBUS 4ma SRAM Read / OE strobe out WAITn EBUS I PU SRAM Wait in AD[25:0] EBUS 8ma Shared Address bus out DA[15:0] EBUS 8ma PU Shared Data bus in/out CSn[3:0] EBUS 4ma PU Chip select out CSn[7:6] EBUS 4ma PU Chip select out DQMn[1:0] EBUS 8ma Shared data mask out SDCLK SDRAM 8ma SDRAM clock out SDCLKEN SDRAM 8ma SDRAM clock enable out SDCSn[3:0] SDRAM 4ma SDRAM chip selects out RASn SDRAM 8ma SDRAM RAS out CASn SDRAM 8ma SDRAM CAS out SDWEn SDRAM 8ma SDRAM write enable out ADC[4:0] ADC A External Analog Measurement Input VDD_ADC ADC P ADC power, 3.3V GND_ADC ADC G ADC ground USBp[2, 0] USB A USB positive signals USBm[2, 0] USB A USB negative signals TXD0 UART1 4ma Transmit out RXD0 UART1 I PU Receive in CTSn UART1 I PU Clear to send / transmit enable DSRn UART1 I PU Data set ready / Data Carrier Detect DTRn UART1 4ma Data Terminal Ready output RTSn UART1 4ma Ready to send TXD1 UART2 4ma Transmit / IrDA output RXD1 UART2 I PU Receive / IrDA input MDC EMAC 4ma Management data clock MDIO EMAC 4ma PU Management data input/output RXCLK EMAC I PD Receive clock in MIIRXD[3:0] EMAC I PD Receive data in RXDVAL EMAC I PD Receive data valid RXERR EMAC I PD Receive data error TXCLK EMAC I PU Transmit clock in MIITXD[3:0] EMAC I PD Transmit data out TXEN EMAC 4ma PD Transmit enable TXERR EMAC 4ma PD Transmit error CRS EMAC I PD Carrier sense CLD EMAC I PU Collision detect GRLED LED 12ma Green LED RDLED LED 12ma Red LED EECLK EEPROM 4ma PU EEPROM / Two-wire Interface clock EEDAT EEPROM 4ma PU EEPROM / Two-wire Interface data ABITCLK AC97 8ma PD AC97 bit clock ASYNC AC97 8ma PD AC97 frame sync ASDI AC97 I PD AC97 Primary input ASDO AC97 8ma PU AC97 output ARSTn AC97 8ma AC97 reset SCLK1 SPI1 8ma PD SPI bit clock SFRM1 SPI1 8ma PD SPI Frame Clock SSPRX1 SPI1 I PD SPI input SSPTX1 SPI1 8ma SPI output INT[3], INT[1:0] INT I PD External interrupts PRSTn Syscon I PU Power on reset RSTOn Syscon 4ma User Reset in out - open drain SLA[1:0] EEPROM 4ma Flash programming voltage control EGPIO[15:0] GPIO I/O, 4ma PU Enhanced GPIO FGPIO[3:1] GPIO I/O, 8ma PU GPIO on Port F HGPIO[5:2] GPIO I/O, 8ma PU GPIO on Port H CGPIO[0] GPIO I/O, 8ma PU GPIO on Port C CVDD Power P Digital power, 1.8V RVDD Power P Digital power, 3.3V CGND Ground G Digital ground RGND Ground G Digital ground Table Q. Pin Descriptions (Continued) Pin Name Block Pad Type Pull Type

©Copyright 2005 Cirrus Logic (All Rights Reserved) DS653PP3 EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Table R illustrates the pin signal multiplexing and configuration options. Table R. Pin Multiplex Usage Information Physical Pin Name EGPIO[0] Ring Indicator Input RI EGPIO[1] 1Hz clock monitor CLK1HZ EGPIO[3] HDLC Clock HDLCCLK1 EGPIO[4] I2S Transmit Data 1 SDO1 EGPIO[5] I2S Receive Data 1 SDI1 EGPIO[6] I2S Transmit Data 2 SDO2 EGPIO[7] DMA Request 0 DREQ0 EGPIO[8] DMA Acknowledge 0 DACK0 EGPIO[9] DMA EOT 0 DEOT0 EGPIO[10] DMA Request 1 DREQ1 EGPIO[11] DMA Acknowledge 1 DACK1 EGPIO[12] DMA EOT 1 DEOT1 EGPIO[13] I2S Receive Data 2 SDI2 EGPIO[14] PWM1 Output PWMOUT1 EGPIO[15] Device active / present DASP ABITCLK I2S Serial clock SCLK ASYNC I2S Frame Clock LRCK ASDO I2S Transmit Data 0 SDO0 ASDI I2S Receive Data 0 SDI0 ARSTn I2S Master clock MCLK SCLK1 I2S Serial clock SCLK SFRM1 I2S Frame Clock LRCK SSPTX1 I2S Transmit Data 0 SDO0 SSPRX1 I2S Receive Data 0 SDI0

©Copyright 2005 Cirrus Logic (All Rights Reserved) EP9302 High-speed ARM9 System-on-chip Processor with MaverickCrunch Acronyms and Abbreviations The following tables list abbreviations and acronyms used in this data sheet. Units of Measurement Term Definition ADC Analog-to-Digital Converter ALT Alternative AMBA Advanced Micro-controller Bus Architecture ATAPI ATA Packet Interface CODEC COder / DECoder CRC Cyclic Redundancy Check DAC Digital-to-Analog Converter DMA Direct-Memory Access EBUS External Memory Bus EEPROM Electronically Erasable Programmable Read Only Memory EMAC Ethernet Media Access Controller FIFO First In / First Out FIQ Fast Interrupt Request FLASH Flash memory GPIO General Purpose I/O HDLC High-level Data Link Control I/F Interface I2S Inter-IC Sound IC Integrated Circuit ICE In-Circuit Emulator IDE Integrated Drive Electronics IEEE Institute of Electronics and Electrical Engineers IrDA Infrared Data Association IRQ Standard Interrupt Request ISO International Standards Organization JTAG Joint Test Action Group LFSR Linear Feedback Shift Register MII Media-independent Interface MMU Memory Management Unit OHCI Open Host Controller Interface PHY Ethernet PHYsical layer interface PIO Programmed I/O RISC Reduced Instruction Set Computer SDMI Secure Digital Music Initiative SDRAM Synchronous Dynamic RAM SPI Serial Peripheral Interface SRAM Static Random Access Memory STA Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium TFT Thin Film Transistor TLB Translation Lookaside Buffer USB Universal Serial Bus Symbol Unit of Measure degree Celsius Hz Hertz = cycle per second kbps kilobits per second kbyte kilobyte kHz kiloHertz = 1000 Hz Mbps Megabits per second MHz MegaHertz = 1,000 KiloHertz µA microAmpere = 10-6 Ampere µs microsecond = 1,000 nanoseconds = 10-6 seconds mA milliAmpere = 10-3 Ampere ms millisecond = 1,000 microseconds = 10-3 seconds mW milliWatt = 10-3 Watts ns nanosecond = 10-9 seconds pF picoFarad = 10-12 Farads V Volt W Watt Term Definition

Ordering Information

The order numbers for the device are: EP9302-CQ 0°C to +70°C 208-pin LQFP EP9302-CQZ 0°C to +70°C 208-pin LQFP Lead Free EP9302-IQ -40°C to +85°C 208-pin LQFP EP9302-IQZ -40°C to +85°C 208-pin LQFP Lead Free EP9302 — CQZ Product Line: Embedded Processor Part Number Temperature Range: C = Commercial Package Type: Q = 208 pin, Low Profile Quad Flat Pack (28 mm x 28 mm) Note: Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative. Z = Lead Free Lead Material: I = Industrial Operating Version E = Extended Operating Version Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that infor- mation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIR- CRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRAN- TIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this doc- ument may be trademarks or service marks of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola and SPI are registered trademarks of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds.

Product Information

EP9302-CQ specifications and overview.

Summary

High-speed ARM9 System-on-chip Processor with MaverickCrunch

Description

High-speed ARM9 System-on-chip Processor with MaverickCrunch

Source title EP9302-CQ Datasheet(PDF) - Cirrus Logic

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