EP7312-IB-90

EP7312 CIRRUS | Alldatasheet

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Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) Nov ’03 DS508PP5 http://www.cirrus.com High-Performance, Low-Power System on Chip with SDRAM and Enhanced Digital Audio Interface EP7312 Data Sheet OVERVIEW BLOCK DIAGRAM

FEATURES

(cont.) (cont.) I ARM®720T Processor — ARM7TDMI CPU operating at speeds of 74 and 90 MHz — 8 KBytes of four-way set-associative cache — MMU with 64-entry TLB — Thumb code support enabled I Ultra low power — 90 mW at 74 MHz typical — 108 mW at 90 MHz typical — <.03 mW in the Standby State I Advanced audio decoder/decompression capability — Supports bit streams with adaptive bit rates — Allows for support of multiple audio decompression algorithms (MP3, WMA, AAC, Audible, etc.) LCD Controller Boot ROM M averickKeyTM ARM 7TDM I CPU Core M MU 8 KB Cache W rite Buffer Internal Data Bus E PB Bus M em ory Controller SDRAM I/F SRAM I/F On-chip S RAM 48 KB ICE-JTAG Clocks & Tim ers Keypad& Touch S creen I/F Interrupts, P W M & G P IO Bus Bridge (2) UARTs w/ IrDA Power M anagem ent S erial Interface Digital Audio Interface ARM720T SERIAL PORTS USER INTERFACE OVERVIEW The Cirrus Logic™EP7312 is designed for ultra-low- power portable and line-powered applications such as portable consumer entertainment devices, home and car audio juke box systems, and general purpose industrial control applications, or any device that features the added capability of digital audio compression decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 KBytes of four-way set-associative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft® Windows® CE and Linux®. MEMORY and STORAGE

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip FEATURES (cont) I 48 KBytes of on-chip SRAM I MaverickKey™IDs — 32-bit unique ID can be used for DRM compliance 128-bit random ID I Available in 74 and 90 MHz clock speeds I LCD controller — Interfaces directly to a single-scan panel monochrome STN LCD — Interfaces to a single-scan panel color STN LCD with minimal external glue logic I Full JTAG boundary scan and Embedded ICE support I Integrated Peripheral Interfaces — 32-bit SDRAM Interface up to 2 external banks — 8/32/16-bit SRAM/FLASH/ROM Interface — Digital Audio Interface providing glueless interface to low-power DACs, ADCs and CODECs — Two Synchronous Serial Interfaces (SSI1, SSI2) — CODEC Sound Interface — 8×8 Keypad Scanner — 27 General Purpose Input/Output pins — Dedicated LED flasher pin from the RTC I Internal Peripherals — Two 16550 compatible UARTs — IrDA Interface — Two PWM Interfaces — Real-time Clock — Two general purpose 16-bit timers — Interrupt Controller — Boot ROM I Package — 208-Pin LQFP — 256-Ball PBGA — 204-Ball TFBGA I The fully static EP7312 is optimized for low power dissipation and is fabricated on a 0.25 micron CMOS process OVERVIEW (cont.) The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V–3.3 V. The device has three basic power states: operating, idle and standby. MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, high quality ADCs, DACs, or CODECs such as the Cirrus Logic CS53L32A, CS43L42, and CS42L50 are easily added to an EP73xx design via the DAI. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Simply by adding desired memory and peripherals to the highly integrated EP7312 completes a low-power system solution. All necessary interface logic is integrated on- chip.

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip Table of Contents

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip EP7312

8 KB of 4-way set-associative cache. The EP7312 is designed for ultra-low-power operation.

• Operating — This state is the full performance state. All the clocks and peripheral logic are enabled.
• Idle — This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press.
• Standby — This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor. Table 1 shows the power management pin assignments. MaverickKey™ Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances. Memory Interfaces There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burst- mode capability, with six chip selects decoding six 256 MB sections of addressable space. For maximum flexibility, each bank can be specified to be 8-, 16-, or 32- bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industry- leading code density. shows the Static Memory Interface pin assignments. Note: Pins are multiplexed. See Table 19 on page 11 for more information.

Table 1. Power Management Pin Assignments Table 2. Static Memory Interface Pin Assignments

1. Pins A[27:13] map to DRA[0:14] respectively.

balance the load for large memory systems.

1. Pins are multiplexed. See Table 19 on page 11 for

to drive an infrared communication interface directly. Table 4 shows the UART pin assignments. audio DACs and the Crystal‚ CS53L32 low-power ADC. Table 3. SDRAM Interface Pin Assignments Table 4. Universal Asynchronous Receiver/Transmitters Pin Table 5. DAI Interface Pin Assignments

the DAI and CODEC interfaces through a multiplexer. Table 7 shows the SSI2 Interface pin assignments. Table 9 shows the LCD Interface pin assignments. Table 6. CODEC Interface Pin Assignments Table 7. SSI2 Interface Pin Assignments Table 8. Serial Interface Pin Assignments Table 9. LCD Interface Pin Assignments

Table 10 shows the Keypad Interface Pin Assignments. Table 11 shows the interrupt controller pin assignments. Table 12 shows the Real-Time Clock pin assignments.

3.6864 MHz crystal or external 13 MHz clock

74 MHz, and at 45 MHz when the processor is set to

Table 13 shows the PLL and clocking pin assignments. Table 10. Keypad Interface Pin Assignments Table 11. Interrupt Controller Pin Assignments Table 12. Real-Time Clock Pin Assignments Table 13. PLL and Clocking Pin Assignments

Table 15 shows the GPIO pin assignments. portable phone or an appointment reminder on a PDA. Table 17 shows the LED Flasher pin assignments. saved code to the on-board SRAM/FLASH. ball PBGA package, or a 204-ball TFBGA package. Table 14. DC-to-DC Converter Interface Pin Assignments Table 15. General Purpose Input/Output Pin Assignments Table 16. Hardware Debug Interface Pin Assignments Table 17. LED Flasher Pin Assignments

is controlled by the state of the SERSEL bit in SYSCON2. EP7312 User’s Manual for more information). Table 18. DAI/SSI2/CODEC Pin Multiplexing Table 19. Pin Multiplexing

necessary interface logic is integrated on-chip. Figure 1. A Fully-Configured EP7312-Based System A system can only use one of the following peripheral interfaces at any given time: SSI2,CODEC or DAI.

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics All characteristics are specified at VDDCORE = 2.5 V, VDDIO = 3.3 V and VSS = 0 V over an operating temperature of 0°C to +70°C for all frequencies of operation. The current consumption figures have test conditions specified per parameter.” DC Core, PLL, and RTC Supply Voltage 2.9 V DC I/O Supply Voltage (Pad Ring) 3.6 V DC Pad Input Current ±10 mA/pin; ±100 mA cumulative Storage Temperature, No Power –40°C to +125°C DC core, PLL, and RTC Supply Voltage 2.5 V ± 0.2 V DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.5 V DC Input / Output Voltage O–I/O supply voltage Operating Temperature Extended -20°C to +70°C; Commercial 0°C to +70°C; Industrial -40°C to +85°C Symbol Parameter Min Typ Max Unit Conditions VIH CMOS input high voltage 0.65 × VDDIO VDDIO + 0.3 V VDDIO = 2.5 V VIL CMOS input low voltage VSS − 0.3 0.25 × VDDIO V VDDIO = 2.5 V VT+ Schmitt trigger positive going threshold 2.1 V VT- Schmitt trigger negative going threshold 0.8 V Vhst Schmitt trigger hysteresis 0.1 0.4 V VIL to VIH VOH CMOS output high voltagea Output drive 1a Output drive 2a VDD – 0.2 2.5 2.5 V V V IOH = 0.1 mA IOH = 4 mA IOH = 12 mA VOL CMOS output low voltagea Output drive 1a Output drive 2a 0.3 0.5 0.5 V V V IOL = –0.1 mA IOL = –4 mA IOL = –12 mA IIN Input leakage current 1.0 µA VIN = VDD or GND IOZ Bidirectional 3-state leakage currentb c 100 µA VOUT = VDD or GND CIN Input capacitance 10.0 pF

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Note: 1) Total power consumption = IDDCORE x 2.5 V + IDDIO x 3.3 V 2) Pull-up current = 50 µA typical at VDD = 3.3 V. COUT Output capacitance 10.0 pF CI/O Transceiver capacitance 10.0 pF IDDSTANDBY @ 25 C Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V µA Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD ± 0.1 V, VIL = GND ± 0.1 V IDDSTANDBY @ 70 C Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V 570 111 µA Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD ± 0.1 V, VIL = GND ± 0.1 V IDDSTANDBY @ 85 C Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V 1693 163 µA Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = VDD ± 0.1 V, VIL = GND ± 0.1 V IDDidle at 74 MHz Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V mA Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = VDD ± 0.1 V, VIL = GND ± 0.1 V IDDIDLE at 90 MHz Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V mA Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = VDD ± 0.1 V, VIL = GND ± 0.1 V VDDSTANDBY Standby supply voltage 2.0 V Minimum standby voltage for state retention, internal SRAM cache, and RTC operation only Refer to the strength column in the pin assignment tables for all package types. Assumes buffer has no pull-up or pull-down resistors. The leakage value given assumes that the pin is configured as an input pin but is not currently being driven. Symbol Parameter Min Typ Max Unit Conditions

specified at VDDIO = 3.1 - 3.5 V and VSS = 0 V over an operating temperature of -40°C to +85°C. Pin loadings is 50 pF. The timing values are referenced to 1/2 VDD. Figure 2. Legend for Timing Diagrams

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes. Parameter Symbol Min Typ Max Unit SDCLK rising edge to SDCS assert delay time tCSa ns SDCLK rising edge to SDCS deassert delay time tCSd − 3 ns SDCLK rising edge to SDRAS assert delay time tRAa ns SDCLK rising edge to SDRAS deassert delay time tRAd − 3 ns SDCLK rising edge to SDRAS invalid delay time tRAnv ns SDCLK rising edge to SDCAS assert delay time tCAa − 2 ns SDCLK rising edge to SDCAS deassert delay time tCAd − 5 ns SDCLK rising edge to ADDR transition time tADv − 3 ns SDCLK rising edge to ADDR invalid delay time tADx − 2 ns SDCLK rising edge to SDMWE assert delay time tMWa − 2 ns SDCLK rising edge to SDMWE deassert delay time tMWd − 4 ns DATA transition to SDCLK rising edge time tDAs ns SDCLK rising edge to DATA transition hold time tDAh ns SDCLK rising edge to DATA transition delay time tDAd ns

1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Figure 3. SDRAM Load Mode Register Cycle Timing Measurement

1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal. Figure 4. SDRAM Burst Read Cycle Timing Measurement

1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Figure 5. SDRAM Burst Write Cycle Timing Measurement

1. Timings are shown with CAS latency = 2
2. The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.

Figure 6. SDRAM Refresh Cycle Timing Measurement

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip Static Memory Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory. The following table contains the values for the timings of each of the Static Memory modes. Parameter Symbol Min Typ Max Unit EXPCLK rising edge to nCS assert delay time tCSd ns EXPCLK falling edge to nCS deassert hold time tCSh ns EXPCLK rising edge to A assert delay time tAd ns EXPCLK falling edge to A deassert hold time tAh ns EXPCLK rising edge to nMWE assert delay time tMWd ns EXPCLK rising edge to nMWE deassert hold time tMWh ns EXPCLK falling edge to nMOE assert delay time tMOEd ns EXPCLK falling edge to nMOE deassert hold time tMOEh ns EXPCLK falling edge to HALFWORD deassert delay time tHWd ns EXPCLK falling edge to WORD assert delay time tWDd ns EXPCLK rising edge to data valid delay time tDv ns EXPCLK falling edge to data invalid delay time tDnv ns Data setup to EXPCLK falling edge time tDs ns EXPCLK falling edge to data hold time tDh ns EXPCLK rising edge to WRITE assert delay time tWRd ns EXPREADY setup to EXPCLK falling edge time tEXs ns EXPCLK falling edge to EXPREADY hold time tEXh ns

1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

1. Address, Halfword, Word, and Write hold state until next cycle.

Figure 7. Static Memory Single Read Cycle Timing Measurement

1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

1. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with

valid timing under zero wait state conditions.

1. Address, Data, Halfword, Word, and Write hold state until next cycle.

Figure 8. Static Memory Single Write Cycle Timing Measurement

cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.

1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

1. Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to

cycles. This improves performance so the SQAEN bit should always be set where possible.

1. Address, Halfword, Word, and Write hold state until next cycle.

Figure 9. Static Memory Burst Read Cycle Timing Measurement

1. Four cycles are shown in the above diagram (minimum wait states, 1-1-1-1). This is the maximum number of consecutive

cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.

1. The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at

where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.

1. Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with

valid timing under zero wait state conditions.

1. Address, Data, Halfword, Word, and Write hold state until next cycle.

Figure 10. Static Memory Burst Write Cycle Timing Measurement

Figure 11. SSI1 Interface Timing Measurement

Figure 12. SSI2 Interface Timing Measurement

Figure 13. LCD Controller Timing Measurement

Figure 14. JTAG Timing Measurement

1) Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 4) For pin locations, please see Figure 16. For pin descriptions see the EP7312 User’s Manual. Figure 15. 208-Pin LQFP Package Outline Drawing

1. N/C should not be grounded but left as no connects.

Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 208-Pin LQFP Numeric Pin Listing Table 20. 208-Pin LQFP Numeric Pin Listing

Description

nCS[5] Low O Chip select 5 VDDIO Pad Pwr Digital I/O power, 3.3 V VSSIO Pad Gnd I/O ground EXPCLK I Expansion clock input WORD Low O Word access select output WRITE/nSDRAS Low O Transfer direction / SDRAM RAS signal output RUN/CLKEN Low O Run output / clock enable output EXPRDY I Expansion port ready input TXD[2] High O UART 2 transmit data output RXD[2] I UART 2 receive data input TDI with p/u* I JTAG data input VSSIO Pad Gnd I/O ground PB[7] Input‡ I/O GPIO port B PB[6] Input‡ I/O GPIO port B PB[5] Input‡ I/O GPIO port B PB[4] Input‡ I/O GPIO port B PB[3] Input‡ I/O GPIO port B PB[2] Input‡ I/O GPIO port B PB[1] Input‡ I/O GPIO port B PB[0] Input‡ I/O GPIO port B VDDIO Pad Pwr Digital I/O power, 3.3 V TDO Input‡ O JTAG data out PA[7] Input‡ I/O GPIO port A PA[6] Input‡ I/O GPIO port A PA[5] Input‡ I/O GPIO port A PA[4] Input‡ I/O GPIO port A PA[3] Input‡ I/O GPIO port A PA[2] Input‡ I/O GPIO port A PA[1] Input‡ I/O GPIO port A PA[0] Input‡ I/O GPIO port A LEDDRV Low O IR LED drive TXD[1] High O UART 1 transmit data out VSSIO High Pad Gnd I/O ground PHDIN I Photodiode input CTS I UART 1 clear to send input RXD[1] I UART 1 receive data input DCD I UART 1 data carrier detect

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip DSR I UART 1 data set ready input nTEST[1] With p/u* I Test mode select input nTEST[0] With p/u* I Test mode select input EINT[3] I External interrupt nEINT[2] I External interrupt input nEINT[1] I External interrupt input nEXTFIQ I External fast interrupt input PE[2]/CLKSEL Input‡ I/O GPIO port E / clock input mode select PE[1]/BOOTSEL[1] Input‡ I/O GPIO port E / boot mode select PE[0]/BOOTSEL[0] Input‡ I/O GPIO port E / Boot mode select VSSRTC RTC Gnd Real time clock ground RTCOUT O Real time clock oscillator output RTCIN I Real time clock oscillator input VDDRTC RTC power Real time clock power, 2.5 V N/C PD[7]/SDQM[1] Low I/O GPIO port D / SDRAM byte lane mask PD[6]/SDQM[0] Low I/O GPIO port D / SDRAM byte lane mask PD[5] Low I/O GPIO port D PD[4] Low I/O GPIO port D VDDIO Pad Pwr Digital I/O power, 3.3 V TMS with p/u* I JTAG mode select PD[3] Low I/O GPIO port D PD[2] Low I/O GPIO port D PD[1] Low I/O GPIO port D PD[0]/LEDFLSH Low I/O GPIO port D / LED blinker output SSICLK Input‡ I/O DAI/CODEC/SSI2 serial clock VSSIO Pad Gnd I/O ground SSITXFR Low I/O DAI/CODEC/SSI2 serial clock SSITXDA Low O DAI/CODEC/SSI2 serial data output SSIRXDA I DAI/CODEC/SSI2 serial data input SSIRXFR Input‡ I/O DAI/CODEC/SSI2 frame sync ADCIN I SSI1 ADC serial input nADCCS High O SSI1 ADC chip select VSSCORE Core ground Core ground VDDCORE Core Pwr Core power, 2.5 V VSSIO Pad Gnd I/O ground VDDIO Pad Pwr Digital I/O power, 3.3 V DRIVE[1] High / Low I/O PWM drive output DRIVE[0] High / Low I/O PWM drive output ADCCLK Low O SSI1 ADC serial clock ADCOUT Low O SSI1 ADC serial data output Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip SMPCLK Low O SSI1 ADC sample clock FB[1] I PWM feedback input VSSIO Pad Gnd I/O ground FB[0] I PWM feedback input COL[7] High O Keyboard scanner column drive COL[6] High O Keyboard scanner column drive COL[5] High O Keyboard scanner column drive COL[4] High O Keyboard scanner column drive COL[3] High O Keyboard scanner column drive COL[2] High O Keyboard scanner column drive VDDIO Pad Pwr Digital I/O power, 3.3 V TCLK I JTAG clock COL[1] High O Keyboard scanner column drive COL[0] High O Keyboard scanner column drive BUZ Low O Buzzer drive output D[31] Low I/O Data I/O D[30] Low I/O Data I/O D[29] Low I/O Data I/O D[28] Low I/O Data I/O VSSIO Pad Gnd I/O ground A[27]/DRA[0] Low O System byte address / SDRAM address 100 D[27] Low I/O Data I/O 101 A[26]/DRA[1] Low O System byte address / SDRAM address 102 D[26] Low I/O Data I/O 103 A[25]/DRA[2] Low O System byte address / SDRAM address 104 D[25] Low I/O Data I/O 105 HALFWORD Low O Halfword access select output 106 A[24]/DRA[3] Low O System byte address / SDRAM address 107 VDDIO Pad Pwr Digital I/O power, 3.3 V 108 VSSIO Pad Gnd I/O ground 109 D[24] Low I/O Data I/O 110 A[23]/DRA[4] Low O System byte address / SDRAM address 111 D[23] Low I/O Data I/O 112 A[22]/DRA[5] Low O System byte address / SDRAM address 113 D[22] Low I/O Data I/O 114 A[21]/DRA[6] Low O System byte address / SDRAM address 115 D[21] Low I/O Data I/O 116 VSSIO Pad Gnd I/O ground 117 A[20]/DRA[7] Low O System byte address / SDRAM address

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip 118 D[20] Low I/O Data I/O 119 A[19]/DRA[8] Low O System byte address / SDRAM address 120 D[19] Low I/O Data I/O 121 A[18]/DRA[9] Low O System byte address / SDRAM address 122 D[18] Low I/O Data I/O 123 VDDIO Pad Pwr Digital I/O power, 3.3 V 124 VSSIO Pad Gnd I/O ground 125 nTRST I JTAG async reset input 126 A[17]/DRA[10] Low O System byte address / SDRAM address 127 D[17] Low I/O Data I/O 128 A[16]/DRA[11] Low O System byte address / SDRAM address 129 D[16] Low I/O Data I/O 130 A[15]/DRA[12] Low O System byte address / SDRAM address 131 D[15] Low I/O Data I/O 132 A[14]/DRA[13] Low O System byte address / SDRAM address 133 D[14] Low I/O Data I/O 134 A[13]/DRA[14] Low O System byte address / SDRAM address 135 D[13] Low I/O Data I/O 136 A[12] Low O System byte address 137 D[12] Low I/O Data I/O 138 A[11] Low O System byte address 139 VDDIO Pad Pwr Digital I/O power, 3.3 V 140 VSSIO Pad Gnd I/O ground 141 D[11] Low I/O Data I/O 142 A[10] Low O System byte address 143 D[10] Low I/O Data I/O 144 A[9] Low O System byte address 145 D[9] Low I/O Data I/O 146 A[8] Low O System byte address 147 D[8] Low I/O Data I/O 148 A[7] Low O System byte address 149 VSSIO Pad Gnd I/O ground 150 D[7] Low I/O Data I/O 151 nBATCHG I Battery changed sense input 152 nEXTPWR I External power supply sense input 153 BATOK I Battery OK input 154 nPOR Schmitt I Power-on reset input 155 nMEDCHG/nBROM I Media change interrupt input / internal ROM boot enable 156 nURESET Schmitt I User reset input 157 VDDOSC Oscillator Power Oscillator power in, 2.5 V 158 MOSCIN I Main oscillator input 159 MOSCOUT O Main oscillator output 160 VSSOSC Oscillator Ground Oscillator Ground

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 161 WAKEUP Schmitt I System wake up input 162 nPWRFL I Power fail sense input 163 A[6] Low O System byte address 164 D[6] Low I/O Data I/O 165 A[5] Low Out System byte address 166 D[5] Low I/O Data I/O 167 VDDIO Pad Pwr Digital I/O power, 3.3 V 168 VSSIO Pad Gnd I/O ground 169 A[4] Low O System byte address 170 D[4] Low I/O Data I/O 171 A[3] Low O System byte address 172 D[3] Low I/O Data I/O 173 A[2] Low O System byte address 174 VSSIO Pad Gnd I/O ground 175 D[2] Low I/O Data I/O 176 A[1] Low O System byte address 177 D[1] Low I/O Data I/O 178 A[0] Low O System byte address 179 D[0] Low I/O Data I/O 180 VSSCORE Core ground Core ground 181 VDDCORE Core Pwr Core power, 2.5 V 182 VSSIO Pad ground I/O ground 183 VDDIO Pad Power Digital I/O power, 3.3 V 184 CL[2] Low O LCD pixel clock out 185 CL[1] Low O LCD line clock 186 FRM Low O LCD frame synchronization pulse 187 M Low O LCD AC bias drive 188 DD[3] Low I/O LCD serial display data 189 DD[2] Low I/O LCD serial display data 190 VSSIO Pad Gnd I/O ground 191 DD[1] Low I/O LCD serial display data 192 DD[0] Low I/O LCD serial display data 193 nSDCS[1] High O SDRAM chip select 1 194 nSDCS[0] High O SDRAM chip select 0 195 SDQM[3] Low I/O SDRAM byte lane mask 196 SDQM[2] Low I/O SDRAM byte lane mask 197 VDDIO Pad Pwr Digital I/O power, 3.3 V 198 VSSIO Pad Gnd I/O ground 199 SDCKE Low I/O SDRAM clock enable output 200 SDCLK Low I/O SDRAM clock out 201 nMWE/nSDWE High O ROM, expansion write enable/ SDRAM write enable control signal 202 nMOE/nSDCAS High O ROM, expansion OP enable/SDRAM CAS control signal 203 VSSIO Pad Gnd I/O ground 204 nCS[0] High O Chip select 0 205 nCS[1] High O Chip select 1

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip *“With p/u” means with internal pull-up of 100 KOhms on the pin. † Strength 1 = 4 ma Strength 2 = 12 ma ‡Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. 206 nCS[2] High O Chip select 2 207 nCS[3] High O Chip select 3 208 nCS[4] High O Chip select 4

Figure 17. 204-Ball TFBGA Package

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Pinout (Top View) A VDDIO EXPCLK nCS[3] nCS[1] nMWE/ nSDWE SDQM[2 nSDCS[1] DD[2] FRM CL[1] GNDCORE D[1] A[2] D[4] A[5] nPWRFL MOSCOUT GNDIO GNDIO GNDIO A B WORD VDDIO nCS[5] nCS[2] nMOE/ nSDCAS SDCKE nSDCS[0] DD[1] M CL[2] D[0] A[1] D[3] A[4] D[6] WAKEUP MOSCIN GNDIO GNDIO nURESET B C RUN/ CLKEN EXPRDY VDDIO nCS[4] nCS[0] SDCLK SDQM[3] DD[0] DD[3] VDDCORE A[0] D[2] A[3] D[5] A[6] GNDOSC VDDOSC GNDIO BATOK nPOR C D PB[7] RXD[2] VDDIO GNDIO nBATCHG A[7] D E PB[4] TXD[2] WRITE/ nSDRAS nMEDCHG/n BROM nEXTPWR D[9] E F PB[3] PB[6] TDI D[7] A[8] D[10] F G PB[1] PB[2] PB[5] D[8] A[9] D[11] G H PA[7] TDO PB[0] A[10] D[12] A[12] H J PA[4] PA[5] PA[6] A[11] D[13] A[13]/ DRA[14] J K PA[1] PA[2] VDDIO D[14] A[14]/ DRA[13] D[15] K L TXD[1] LEDDRV PA[3] VDDIO D[16] A[16]/ DRA[11] L M RXD[1] CTS PA[0] A[15]/ DRA[12] A[17]/ DRA[10] nTRST M N DSR nTEST[1] PHDIN D[17] D[19] A[18]/ DRA[9] N P EINT[3] nEINT[2] DCD D[18] A[20]/ DRA[7] D[20] P R nEXTFIQ PE2/ CLKSEL nTEST[0] A[19]/ DRA[8] D[22] A[21]/ DRA6 R T PE[1]/ BOOT SEL[1] PE[0]/ BOOT SEL[0] nEINT[1] D[21] D[23] A[22]/ DRA5 T U GNDRTC RTCOUT RTCIN HALF WORD D[24] A[23]/ DRA4 U V VDDRTC GNDIO GNDIO PD[7]/ SDQM[1] PD[4] PD[2] SSICLK SSIRXD A nADCCS VDDIO ADCCLK COL[7] COL[4] TCLK BUZ D[29] A[26]/ DRA[1] VDDIO VDDIO A[24]/ DRA3 V W GNDIO GNDIO GNDIO PD[6]/ SDQM[0] TMS PD[1] SSITXFR SSIRXFR GNDCORE DRIVE[1] ADCOUT FB[0] COL[5] COL[2] COL[0] D[30] A[27]/ DRA[0] D[26] VDDIO D[25] W Y GNDIO GNDIO GNDIO PD[5] PD[3] PD[0]/ LED FLSH SSITXDA ADCIN VDDCORE DRIVE[0] SMPCLK FB[1] COL[6] COL[3] COL[1] D[31] D[28] D[27] A[25]/ DRA[2] VDDIO Y

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Ball Listing The list is ordered by ball location. Table 21. 204-Ball TFBGA Ball Listing Digital I/O power, 3.3 V EXPCLK I Expansion clock input nCS[3] High O Chip select 3 nCS[1] High O Chip select 1 nMWE/nSDWE High O ROM, expansion write enable/ SDRAM write enable control signal SDQM[2] Low O SDRAM byte lane mask nSDCS[1] High O SDRAM chip select 2 DD[2] Low O LCD serial display data FRM Low O LCD frame synchronization pulse A10 CL[1] Low O LCD line clock A11 VSSCORE Core ground Core ground A12 D[1] Low I/O Data I/O A13 A[2] Low O System byte address A14 D[4] Low I/O Data I/O A15 A[5] Low O System byte address A16 nPWRFL I Power fail sense input A17 MOSCOUT O Main oscillator out A18 VSSIO Pad ground I/O ground A19 VSSIO Pad ground I/O ground A20 VSSIO Pad ground I/O ground WORD Low O Word access select output VDDIO Pad power Digital I/O power, 3.3 V nCS[5] Low O Chip select 5 nCS[2] High O Chip select 2 nMOE/nSDCAS High O ROM, expansion OP enable/SDRAM CAS control signal SDCKE Low O SDRAM clock enable output nSDCS[0] High O SDRAM chip select 0 DD[1] Low O LCD serial display data M Low O LCD AC bias drive B10 CL[2] Low LCD pixel clock out B11 D[0] Low I/O Data I/O B12 A[1] Low O System byte address B13 D[3] Low I/O Data I/O

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip B14 A[4] Low O System byte address B15 D[6] Low I/O Data I/O B16 WAKEUP Schmitt I System wake up input B17 MOSCIN I Main oscillator input B18 VSSIO Pad ground I/O ground B19 VSSIO Pad ground I/O ground B20 nURESET Schmitt I User reset input RUN/CLKEN Low Run output / clock enable output EXPRDY I Expansion port ready input VDDIO Pad power Digital I/O power, 3.3 V nCS[4] High O Chip select 4 nCS[0] High O Chip select 0 SDCLK Low O SDRAM clock out SDQM[3] Low O SDRAM byte lane mask DD[0] Low O LCD serial display data DD[3] Low O LCD serial display data C10 VDDCORE Core power Digital core power, 2.5 V C11 A[0] Low O System byte address C12 D[2] Low I/O Data I/O C13 A[3] Low O System byte address C14 D[5] Low I/O Data I/O C15 A[6] Low O System byte address C16 VSSOSC Oscillator ground PLL ground C17 VDDOSC Oscillator power Oscillator power in, 2.5V C18 VSSIO Pad ground I/O ground C19 BATOK I Battery ok input Table 21. 204-Ball TFBGA Ball Listing (Continued)

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip C20 nPOR Schmitt I Power-on reset input PB[7] Input‡ I GPIO port B RXD[2] I UART 2 receive data input VDDIO Pad power Digital I/O power, 3.3V D18 VSSIO Pad ground I/O ground D19 nBATCHG I Battery changed sense input D20 A[7] Low O System byte address PB[4] Input‡ I GPIO port B TXD[2] High O UART 2 transmit data output WRITE/nSDRAS Low O Transfer direction / SDRAM RAS signal output E18 nMEDCHG/nBROM I Media change interrupt input / internal ROM boot enable E19 nEXTPWR I External power supply sense input E20 D[9] Low I/O Data I/O PB[3] Input‡ I/O GPIO port B PB[6] Input‡ I/O GPIO port B TDI with p/u* I JTAG data input F18 D[7] Low I/O Data I/O F19 A[8] Low O System byte address F20 D[10] Low I/O Data I/O PB[1] Input‡ I/O PB[2] Input‡ I/O GPIO port B PB[5] Input‡ I/O GPIO port B G18 D[8] Input‡ I/O Data I/O G19 A[9] Low O System byte address G20 D[11] Low I/O Data I/O PA[7] Input‡ I/O GPIO port A H[2] TDO Input‡ O JTAG data out H[3] PB[0] Input‡ I/O GPIO port B H[18] A[10] Low O System byte address H19 D[12] Low I/O Data I/O H20 A[12] Low O System byte address PA[4] Input‡ I/O GPIO port A

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip PA[5] Input‡ I/O GPIO port A PA[6] Input‡ I/O GPIO port A J18 A[11] Low O System byte address J19 D[13] Low I/O Data I/O J20 A[13]/DRA[14] Low O System byte address / SDRAM address PA[1] Input‡ I/O GPIO port A PA[2] Input‡ I/O GPIO port A VDDIO Pad power Digital I/O power, 3.3V K18 D[14] Low I/O Data I/O K19 A[14]/DRA[13] Low O System byte address / SDRAM address K20 D[15] Low I/O Data I/O TXD[1] High O UART 1 transmit data out LEDDRV Low O IR LED drive PA[3] Input‡ I/O GPIO port A L18 VDDIO Pad power Digital I/O power, 3.3V L19 D[16] Low I/O Data I/O L20 A[16]/DRA[11] Low O System byte address / SDRAM address RXD[1] I UART 1 receive data input CTS I UART 1 clear to send input PA[0] Input‡ I/O GPIO port A M18 A[15]/DRA[12] Low O System byte address / SDRAM address M19 A[17]/DRA[10] Low O System byte address / SDRAM address M20 nTRST I JTAG async reset input DSR I UART 1 data set ready input nTEST[1] With p/u* I Test mode select input PHDIN I Photodiode input N18 D[17] Low I/O Data I/O N19 D[19] Low I/O Data I/O N20 A[18]/DRA[9] Low O System byte address / SDRAM address EINT[3] I External interrupt nEINT[2] I External interrupt input DCD I UART 1 data carrier detect P18 D[18] Low I/O Data I/O P19 A[20]/DRA[7] Low O System byte address / SDRAM address

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip P20 D[20] Low I/O Data I/O nEXTFIQ I External fast interrupt input PE[2]/CLKSEL Input‡ I/O GPIO port E / clock input mode select nTEST[0] With p/u* I Test mode select input R18 A[19]/DRA[8] Low O System byte address / SDRAM address R19 D[22] Low I/O Data I/O R20 A[21]/DRA[6] Low O System byte address / SDRAM address PE[1]/BOOTSEL[1] Input‡ I/O GPIO port E / boot mode select PE[0]/BOOTSEL[0] Input‡ I/O GPIO port E / boot mode select nEINT[1] I External interrupt input T18 D[21] Low I/O Data I/O T19 D[23] Low I/O Data I/O T20 A[22]/DRA[5] Low O System byte address / SDRAM address VSSRTC RTC ground Real time clock ground RTCOUT O Real time clock oscillator output RTCIN I/O Real time clock oscillator input U18 HALFWORD Low O Halfword access select output U19 D[24] Low I/O Data I/O U20 A[23]/DRA[4] Low O System byte address / SDRAM address VDDRTC RTC power Real time clock power, 2.5V VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground PD[7]/SDQM[1] Low I/O GPIO port D / SDRAM byte lane mask PD[4] Low I/O GPIO port D PD[2] Low I/O GPIO port D SSICLK Input‡ I/O DAI/CODEC/SSI2 serial clock SSIRXDA I/O DAI/CODEC/SSI2 serial data input nADCCS High O SSI1 ADC chip select V10 VDDIO Pad power Digital I/O power, 3.3V V11 ADCCLK Low O SSI1 ADC serial clock V12 COL[7] High O Keyboard scanner column drive V13 COL[4] High O Keyboard scanner column drive V14 TCLK I JTAG clock V15 BUZ Low O Buzzer drive output V16 D[29] Low I/O Data I/O

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip V17 A[26]/DRA[1] Low O System byte address / SDRAM address V18 VDDIO Pad power Digital I/O power, 3.3 V V19 VDDIO Pad power Digital I/O power, 3.3 V V20 A[24]/DRA[3] Low O System byte address / SDRAM address VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground PD[6]/SDQM[0] Low I/O GPIO port D / SDRAM byte lane mask TMS with p/u* I JTAG mode select PD[1] Low I/O GPIO port D SSITXFR Low I/O DAI/CODEC/SSI2 frame sync SSIRXFR Input‡ I/O DAI/CODEC/SSI2 frame sync VSSCORE Core Ground Core Ground W10 DRIVE[1] High / Low I/O PWM drive output W11 ADCOUT Low O SSI1 ADC serial data output W12 FB[0] I PWM feedback input W13 COL[5] High O Keyboard scanner column drive W14 COL[2] High O Keyboard scanner column drive W15 COL[0] High O Keyboard scanner column drive W16 D[30] Low I/O Data I/O W17 A[27]/DRA[0] Low O System byte address / SDRAM address W18 D[26] Low I/O Data I/O W19 VDDIO Pad power Digital I/O power, 3.3V W20 D[25] Low I/O Data I/O VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground PD[5] Low I/O GPIO port D PD[3] Low I/O GPIO port D PD[0]/LEDFLSH Low I/O GPIO port D / LED blinker output SSITXDA Low O DAI/CODEC/SSI2 serial data output ADCIN I SSI1 ADC serial input VDDCORE Core power Digital core power, 2.5V Y10 DRIVE[0] Input‡ I/O PWM drive output

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip *“With p/u” means with internal pull-up of 100 KOhms on the pin. † Strength 1 = 4 ma Strength 2 = 12 ma ‡Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. 256-Ball PBGA Package Characteristics Figure 18. 256-Ball PBGA Package 1) For pin locations see Table 22. 3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information.

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip TOP VIEW 17.00 (0.669) 15.00 (0.590) SIDE VIEW BOTTOM VIEW A B C D E F G H J K L M N P R T 1.00 (0.040) Pin 1 Indicator Pin 1 Corner Pin 1 Corner 16 15 14 13 12 11 10 9 15.00 (0.590)

2 Layer

17.00 (0.669) 17.00 (0.669) 1.00 (0.040) 1.00 (0.040) 1.00 (0.040) 30° TYP REF REF 0.50

3 Places

0.85 (0.034) ±0.05 (.002) 0.40 (0.016) ±0.05 (.002) 0.36 (0.014) 17.00 (0.669) R D E ±0.20 (.008) ±0.20 (.008) ±0.20 (.008) ±0.20 (.008) ±0.09 (0.004) JEDEC #: MO-151 Ball Diameter: 0.50 mm ± 0.10 mm 17 ¥ 17 ¥ 1.61 mm body

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Pinout (Top View) A VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D[0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO A B nCS[5] VDDIO nCS[3] nMOE/ nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C D WRITE/ nSDRAS EXPRDY VSSIO VDDIO nCS[2] nMWE/ nSDWE nSDCS[0] CL[2] VSSRTC D[4] nPWRFL MOSCIN VDDIO VSSIO D[7] D[8] D E RXD[2] PB[7] TDI WORD VSSIO nCS[0] SDQM[2] FRM A[0] D[5] VSSOSC VSSIO nMEDCHG/ nBROM VDDIO D[9] D[10] E F PB[5] PB[3] VSSIO TXD[2] RUN/ CLKEN VSSIO SDCKE DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO F G PB[1] VDDIO TDO PB[4] PB[6] VSSCore VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] G H PA[7] PA[5] VSSIO PA[4] PA[6] PB[0] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13]/ DRA[14] VSSIO D[14] D[15] H J PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17]/ DRA[10] A[16]/ DRA[11] A[15]/ DRA[12] A[14]/ DRA[13] nTRST D[16] D[17] J K LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO K L RXD[1] DSR VDDIO nEINT[1] PE[2]/ CLKSEL VSSRTC PD[0]/ LEDFLSH VSSRTC COL[6] D[31] VSSRTC A[22]/ DRA[5] A[21]/ DRA[6] VSSIO A[18]/ DRA[9] A[19]/ DRA[8] L M nTEST[0] nEINT[2] VDDIO PE[0]/ BOOTSEL[0] TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23]/ DRA[4] VDDIO A[20]/ DRA[7] D[21] M N nEXTFIQ PE[1]/ BOOTSEL[1] VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] N P VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO VDDIO VSSIO VSSIO VDDIO VSSIO D[24] VDDIO P R RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27]/ DRA[0] A[25]/ DRA[2] VDDIO A[24]\\ DRA[3] R T VDDRTC PD[7]/ SDQM[1] PD[6]/ SDQM[0] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26]/ DRA[1] D[25] VSSIO T

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Ball Listing The list is ordered by ball location. Table 22. 256-Ball PBGA Ball Listing Digital I/O power, 3.3 V nCS[4] High O Chip select 4 nCS[1] High O Chip select 1 SDCLK Low O SDRAM clock out SDQM[3] Low O SDRAM byte lane mask DD[1] Low O LCD serial display data M Low O LCD AC bias drive VDDIO Pad power Digital I/O power, 3.3 V D[0] Low I/O Data I/O A10 D[2] Low I/O Data I/O A11 A[3] Low O System byte address A12 VDDIO Pad power Digital I/O power, 3.3V A13 A[6] Low O System byte address A14 MOSCOUT O Main oscillator out A15 VDDOSC Oscillator power Oscillator power in, 2.5 V A16 VSSIO Pad ground I/O ground nCS[5] Low O Chip select 5 VDDIO Pad power Digital I/O power, 3.3 V nCS[3] High O Chip select 3 nMOE/nSDCAS High O ROM, expansion OP enable/SDRAM CAS control signal VDDIO Pad power Digital I/O power, 3.3 V nSDCS[1] High O SDRAM chip select 1 DD[2] Low O LCD serial display data CL[1] Low O LCD line clock VDDCORE Core power Digital core power, 2.5V B10 D[1] Low I/O Data I/O B11 A[2] Low O System byte address B12 A[4] Low O System byte address B13 A[5] Low O System byte address B14 WAKEUP Schmitt I System wake up input B15 VDDIO Pad power Digital I/O power, 3.3 V B16 nURESET Schmitt I User reset input VDDIO Pad power Digital I/O power, 3.3V EXPCLK I Expansion clock input VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3 V VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3 V VSSIO Pad ground I/O ground C10 VSSIO Pad ground I/O ground C11 VSSIO Pad ground I/O ground C12 VDDIO Pad power Digital I/O power, 3.3 V C13 VSSIO Pad ground I/O ground

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip C14 VSSIO Pad ground I/O ground C15 nPOR Schmitt I Power-on reset input C16 nEXTPWR I External power supply sense input WRITE/nSDRAS Low O Transfer direction / SDRAM RAS signal output EXPRDY I Expansion port ready input VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3V nCS[2] High O Chip select 2 nMWE/nSDWE High O ROM, expansion write enable/ SDRAM write enable control signal nSDCS[0] High O SDRAM chip select 2 CL[2] Low O LCD pixel clock out VSSRTC Core ground Real time clock ground D10 D[4] Low I/O Data I/O D11 nPWRFL I Power fail sense input D12 MOSCIN I Main oscillator input D13 VDDIO Pad power Digital I/O power, 3.3V D14 VSSIO Pad ground I/O ground D15 D[7] Low I/O Data I/O D16 D[8] Low I/O Data I/O RXD[2] I UART 2 receive data input PB[7] Input‡ I GPIO port B TDI with p/u* I JTAG data input WORD Low O Word access select output VSSIO Pad ground I/O ground nCS[0] High O Chip select 0 SDQM[2] Low O SDRAM byte lane mask FRM Low O LCD frame synchronization pulse A[0] Low O System byte address E10 D[5] Low I/O Data I/O E11 VSSOSC Oscillator ground PLL ground E12 VSSIO Pad ground I/O ground E13 nMEDCHG/nBROM I Media change interrupt input / internal ROM boot enable E14 VDDIO Pad power Digital I/O power, 3.3V E15 D[9] Low I/O Data I/O E16 D[10] Low I/O Data I/O PB[5] Input‡ I GPIO port B PB[3] Input‡ I GPIO port B VSSIO Pad ground I/O ground TXD[2] High O UART 2 transmit data output RUN/CLKEN Low O Run output / clock enable output VSSIO Pad ground I/O ground SDCKE Low O SDRAM clock enable output DD[3] Low O LCD serial display data A[1] Low O System byte address F10 D[6] Low I/O Data I/O F11 VSSRTC RTC ground Real time clock ground F12 BATOK I Battery OK input Table 22. 256-Ball PBGA Ball Listing (Continued)

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip F13 nBATCHG I Battery changed sense input F14 VSSIO Pad ground I/O ground F15 D[11] Low I/O Data I/O F16 VDDIO Pad power Digital I/O power, 3.3V PB[1] Input‡ I GPIO port B VDDIO Pad power Digital I/O power, 3.3V TDO Input‡ O JTAG data out PB[4] Input‡ I GPIO port B PB[6] Input‡ I GPIO port B VSSCore Core ground Core ground VSSRTC RTC ground Real time clock ground DD[0] Low O LCD serial display data D[3] Low I/O Data I/O G10 VSSRTC RTC ground Real time clock ground G11 A[7] Low O System byte address G12 A[8] Low O System byte address G13 A[9] Low O System byte address G14 VSSIO Pad ground I/O ground G15 D[12] Low I/O Data I/O G16 D[13] Low I/O Data I/O PA[7] Input‡ I/O GPIO port A PA[5] Input‡ I/O GPIO port A VSSIO Pad ground I/O ground PA[4] Input‡ I/O GPIO port A PA[6] Input‡ I/O GPIO port A PB[0] Input‡ I/O GPIO port B PB[2] Input‡ I/O GPIO port B VSSRTC RTC ground Real time clock ground VSSRTC RTC ground Real time clock ground H10 A[10] Low O System byte address H11 A[11] Low O System byte address H12 A[12] Low O System byte address H13 A[13]/DRA[14] Low O System byte address / SDRAM address H14 VSSIO Pad ground I/O ground H15 D[14] Low I/O Data I/O H16 D[15] Low I/O Data I/O PA[3] Input‡ I/O GPIO port A PA[1] Input‡ I/O GPIO port A VSSIO Pad ground I/O ground PA[2] Input‡ I/O GPIO port A PA[0] Input‡ I/O GPIO port A TXD[1] High O UART 1 transmit data out

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip CTS I UART 1 clear to send input VSSRTC RTC ground Real time clock ground VSSRTC RTC ground Real time clock ground J10 A[17]/DRA[10] Low O System byte address / SDRAM address J11 A[16]/DRA[11] Low O System byte address / SDRAM address J12 A[15]/DRA[12] Low O System byte address / SDRAM address J13 A[14]/DRA[13] Low O System byte address / SDRAM address J14 nTRST I JTAG async reset input J15 D[16] Low I/O Data I/O J16 D[17] Low I/O Data I/O LEDDRV Low O IR LED drive PHDIN I Photodiode input VSSIO Pad ground I/O ground DCD I UART 1 data carrier detect nTEST[1] With p/u* I Test mode select input EINT[3] I External interrupt VSSRTC RTC ground Real time clock ground ADCIN I SSI1 ADC serial input COL[4] High O Keyboard scanner column drive K10 TCLK I JTAG clock K11 D[20] Low I/O Data I/O K12 D[19] Low I/O Data I/O K13 D[18] Low I/O Data I/O K14 VSSIO Pad ground I/O ground K15 VDDIO Pad power Digital I/O power, 3.3V K16 VDDIO Pad power Digital I/O power, 3.3V RXD[1] I UART 1 receive data input DSR I UART 1 data set ready input VDDIO Pad power Digital I/O power, 3.3V nEINT[1] I External interrupt input PE[2]/CLKSEL Input‡ I/O GPIO port E / clock input mode select VSSRTC RTC ground Real time clock ground PD[0]/LEDFLSH Low I/O GPIO port D / LED blinker output VSSRTC Core ground Real time clock ground COL[6] High O Keyboard scanner column drive L10 D[31] Low I/O Data I/O L11 VSSRTC RTC ground Real time clock ground L12 A[22]/DRA[5] Low O System byte address / SDRAM address L13 A[21]/DRA[6] Low O System byte address / SDRAM address L14 VSSIO Pad ground I/O ground L15 A[18]/DRA[9] Low O System byte address / SDRAM address L16 A[19]/DRA[8] Low O System byte address / SDRAM address nTEST[0] With p/u* I Test mode select input nEINT[2] I External interrupt input VDDIO Pad power Digital I/O power, 3.3V PE[0]/BOOTSEL[0] Input‡ I GPIO port E / Boot mode select TMS with p/u* I JTAG mode select

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip VDDIO Pad power Digital I/O power, 3.3V SSITXFR Low I/O DAI/CODEC/SSI2 frame sync DRIVE[1] High / Low I/O PWM drive output FB[0] I PWM feedback input M10 COL[0] High O Keyboard scanner column drive M11 D[27] Low I/O Data I/O M12 VSSIO Pad ground I/O ground M13 A[23]/DRA[4] Low O System byte address / SDRAM address M14 VDDIO Pad power Digital I/O power, 3.3V M15 A[20]/DRA[7] Low O System byte address / SDRAM address M16 D[21] Low I/O Data I/O nEXTFIQ I External fast interrupt input PE[1]/BOOTSEL[1] Input‡ I/O GPIO port E / boot mode select VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3V PD[5] Low I/O GPIO port D PD[2] Low I/O GPIO port D SSIRXDA I/O DAI/CODEC/SSI2 serial data input ADCCLK Low O SSI1 ADC serial clock SMPCLK Low O SSI1 ADC sample clock N10 COL[2] High O Keyboard scanner column drive N11 D[29] Low I/O Data I/O N12 D[26] Low I/O Data I/O N13 HALFWORD Low O Halfword access select output N14 VSSIO Pad ground I/O ground N15 D[22] Low I/O Data I/O N16 D[23] Low I/O Data I/O VSSRTC RTC ground Real time clock ground RTCOUT O Real time clock oscillator output VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3V VSSIO Pad ground I/O ground VSSIO Pad ground I/O ground VDDIO Pad power Digital I/O power, 3.3V VSSIO Pad ground I/O ground P10 VDDIO Pad power Digital I/O power, 3.3V P11 VSSIO Pad ground I/O ground P12 VSSIO Pad ground I/O ground P13 VDDIO Pad power Digital I/O power P14 VSSIO Pad ground I/O ground P15 D[24] Low I/O Data I/O P16 VDDIO Pad power Digital I/O power, 3.3V RTCIN I/O Real time clock oscillator input VDDIO Pad power Digital I/O power, 3.3V PD[4] Low I/O GPIO port D PD[1] Low I/O GPIO port D

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip *“With p/u” means with internal pull-up of 100 KOhms on the pin. † Strength 1 = 4 ma Strength 2 = 12 ma ‡Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. JTAG Boundary Scan Signal Ordering SSITXDA Low O DAI/CODEC/SSI2 serial data output nADCCS High O SSI1 ADC chip select VDDIO Pad power Digital I/O power, 3.3V ADCOUT Low O SSI1 ADC serial data output COL[7] High O Keyboard scanner column drive R10 COL[3] High O Keyboard scanner column drive R11 COL[1] High O Keyboard scanner column drive R12 D[30] Low I/O Data I/O R13 A[27]/DRA[0] Low O System byte address / SDRAM address R14 A[25]/DRA[2] Low O System byte address / SDRAM address R15 VDDIO Pad power Digital I/O power, 3.3V R16 A[24]/DRA[3] Low O System byte address / SDRAM address VDDRTC RTC power Real time clock power, 2.5V PD[7]/SDQM[1] Low I/O GPIO port D / SDRAM byte lane mask PD[6]/SDQM[0] Low I/O GPIO port D / SDRAM byte lane mask PD[3] Low I/O GPIO port D SSICLK Input‡ I/O DAI/CODEC/SSI2 serial clock SSIRXFR Input‡ I/O DAI/CODEC/SSI2 frame sync VDDCORE Core power Core power, 2.5V DRIVE[0] High / Low I/O PWM drive output FB[1] I PWM feedback input T10 COL[5] High O Keyboard scanner column drive T11 VDDIO Pad power Digital I/O power, 3.3V T12 BUZ Low O Buzzer drive output T13 D[28] Low I/O Data I/O T14 A[26]/DRA[1] Low O System byte address / SDRAM address T15 D[25] Low I/O Data I/O T16 VSSIO Pad ground I/O ground Table 23. JTAG Boundary Scan Signal Ordering

Table 23. JTAG Boundary Scan Signal Ordering (Continued)

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip 1) See EP7312 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable.

measurement, and conventions used in this data sheet. Table 24. Acronyms and Abbreviations Table 25. Unit of Measurement Table 24. Acronyms and Abbreviations (Continued)

an “h”, 0x or quotation marks are decimal. Table 26. Pin Description Conventions

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip

Ordering Information

The following EP7312 devices are available: — EP7312-CV — EP7312-IV — EP7312-CB — EP7312-CR — EP7312-CV-90 — EP7312-CB-90 — EP7312-CR-90 — EP7312-IB — EP7312-IR — EP7312-IV-90 — EP7312-IB-90 — EP7312-IR-90 Ordering Information Legend Note: Go to the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representative. EP7312 — CV —XX Product Line: Embedded Processor Part Number Temperature Range: Package Type: V = Low Profile Quad Flat Pack (208-pin LQFP) B = Plastic Ball Grid Array (17 mm x 17 mm) (256-ball PBGA) R = Reduced Ball Grid Array (13 mm x 13 mm) (204-pin TFBGA) C = Commercial E = Extended Operating Version I = Industrial Operating Version Processor Speed

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) EP7312 High-Performance, Low-Power System on Chip This page intentionally blank.

Copyright Cirrus Logic, Inc. 2003 (All Rights Reserved) DS508PP5 EP7312 High-Performance, Low-Power System on Chip Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that theinformation contained in thisdocument isaccurateand reliable. However, theinformationis subject tochange without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAINAPPLICATIONS USINGSEMICONDUCTORPRODUCTS MAYINVOLVE POTENTIALRISKS OFDEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARYAPPLICATIONS, PRODUCTSSURGICALLYIMPLANTEDINTOTHE BODY, LIFE SUPPORTPRODUCTS OROTHERCRITICALAPPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WAR- RANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, the Cirrus Logic logodesigns, MaverickKey are trademarks of Cirrus Logic, Inc. All other brand andproduct names in this document may betrademarks or service marks of their respective owners. Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation. LINUX is a registered trademark of Linus Torvalds.