EP7312_05 CIRRUS | Alldatasheet
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©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) AUG ‘05 DS508F1 http://www.cirrus.com High-performance, Low-power, System-on-chip with SDRAM & Enhanced Digital Audio Interface EP7312 Data Sheet OVERVIEW BLOCK DIAGRAM
FEATURES
(cont.) (cont.) ❑ ARM®720T Processor — ARM7TDMI CPU Operating at Speeds of 74 and
90 MHz
— 8 kBytes of Four-way Set-associative Cache — MMU with 64-entry TLB — Thumb ™ Code Support Enabled ❑ Ultra low power — 90 mW at 74 MHz Typical — 108 mW at 90 MHz Typical — <.03 mW in the Standby State ❑ Advanced Audio Decoder/decompression Capability — Supports bit streams with adaptive bit rates. — Allows for support of multiple audio decompression algorithms (MP3, WMA, AAC, Audible, etc.). LCD Controller Boot ROM MaverickKey TM ARM7TDMI CPU Core MMU 8 KB Cache Write Buffer Internal Data Bus EPB Bus Memory Controller SDRAM I/FSRAM I/F On-chip SRAM 48 KB ICE-JTAG Clocks & Timers Keypad& Touch Screen I/F Interrupts, PWM & GPIO Bus Bridge (2) UARTs w/ IrDA Power ManagementSerial Interface Digital Audio Interface ARM720T SERIAL PORTS USER INTERFACE OVERVIEW The Cirrus Logic ™ EP7312 is designed for ultra-low-power portable and line-powered ap plications such as portable consumer entertainment devices, home and car audio juke box systems, and general purpose industrial control applications, or any device that features the adde d capability of digital audio compression & decompression. The core-logic functionality of the device is built around an ARM720T processor with 8 kBytes of four-way set-asso ciative unified cache and a write buffer. Incorporated into the ARM720T is an enhanced memory management unit (MMU) which allows for support of sophisticated operating systems like Microsoft ® Windows ® CE and Linux®. MEMORY and STORAGE
2 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 EP7312 High-Performance, Low-Power System on Chip FEATURES (cont) ❑ 48 KBytes of On-chip SRAM ❑ MaverickKey™ IDs — 32-bit unique ID can be used for DRM-compliant 128- bit random ID. ❑ Available in 74 and 90 MHz clock speeds. ❑ LCD controller — Interfaces directly to a si ngle-scan panel monochrome STN LCD. — Interfaces to a single-scan panel color STN LCD with minimal external glue logic. ❑ Full JTAG Boundary Scan and Embedded ICE® Support ❑ Integrated Peripheral Interfaces — 32-bit SDRAM Interface, Up to 2 External Banks — 8/32/16-bit SRAM/FLASH/ROM Interface — Digital Audio Interface provides glueless interface to low-power DACs, ADCs, and CODECs. — Two Synchronous Serial Interfaces (SSI1, SSI2) — CODEC Sound Interface —8 ×8 Keypad Scanner — 27 General-purpose Input/Output Pins — Dedicated LED Flashe r Pin from the RTC ❑ Internal Peripherals — Two 16550-compatible UARTs — IrDA Interface — Two PWM Interfaces — Real-time Clock — Two General-purpose 16-bit Timers — Interrupt Controller — Boot ROM ❑ Package —2 0 8 - P i n L Q F P —2 5 6 - B a l l P B G A —2 0 4 - B a l l T F B G A ❑ The fully static EP7312 is optimized for low power dissipation and is fabricated using a 0.25 micron CMOS process. OVERVIEW (cont.) The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V , while its I/O has an operation range of 2.5 V–3.3 V . The device has three basic power states: operating, idle and standby. MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. The EP7312 integrates an interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, high quality ADCs, DACs, or CODECs such as the Cirrus Logic CS53L32A, CS43L42, and CS42L50 are easily added to an EP73xx design via the DAI. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Simply by adding desired memory and peripherals to the highly integrated EP7312 completes a low-power system solution. All necessary interface logic is integrated on-chip.
DS508F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 3 EP7312 High-Performance, Low-Power System on Chip Table of Contents
4 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 EP7312 High-Performance, Low-Power System on Chip EP7312
The following sections describe the EP7312 in more detail. controller that controls a wide range of on-chip peripherals.
- ARM (32-bit) and Thumb (16-bit compressed) instruction sets
- Enhanced MMU for Microsoft Windows CE and other operating systems
- 8 KB of 4-way set-associative cache.
- Translation Look Aside Buffers with 64 Translated Entries Power Management The EP7312 is designed for ultra-low-power operation. Its core operates at only 2.5 V , while its I/O has an operation range of 2.5 V–3.3 V . The device has three basic power states:
- Operating — This state is the full performance state. All the clocks and peripheral logic are enabled.
- Idle — This state is the same as the Operating State, except the CPU clock is halted while waiting for an event such as a key press.
- Standby — This state is equivalent to the computer being switched off (no display), and the main oscillator shut down. An event such as a key press can wake-up the processor. Table 1 shows the power management pin assignments. MaverickKey™ Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP7312 thr ough the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP7312 is powering, and then deliver the copyrighted information over a secure conn ection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today’s Internet appliances. Memory Interfaces There are two main external memory interfaces. The first one is the ROM/SRAM/FLASH-style interface that has programmable wait-state timings and includes burst-mode capability, with six chip sel ects decoding six 256 MB sections of addressable space. For maxi mum flexibility, each bank can be specified to be 8-, 16-, or 32-bits wide. This allows the use of 8-bit-wide boot ROM options to minimize overall system cost. The on-chip boot ROM can be used in product manufacturing to serially download system code into system FLASH memory. To further minimize system memory requirements and cost, the ARM Thumb instruction set is supported, providing for the use of high-speed 32-bit operations in 16-bit op-codes and yielding industry-leading code density. shows the St atic Memory Interface pin assignments. Note: Pins are multiplexed. See Table 19 on page 11 for more information.
Table 1. Power Management Pin Assignments Table 2. Static Memory Interface Pin Assignments
SDRAM Interface pin assignments. Note: 1. Pins A[27:13] map to DRA[0:14] respectively. balance the load for large memory systems.
- Pins are multiplexed. See Table 19 on page 11 for
Table 3. SDRAM Interface Pin Assignments Table 4. Universal Asynchronous Receiver/Transmitters Pin Table 5. DAI Interface Pin Assignments
shows the CODEC Interface Pin Assignments.
- Synchronous clock speeds of up to 512 kHz
- Separate 16 entry TX and RX half-word wide FIFOs
- Half empty/full interrupts for FIFOs
- Separate RX and TX frame s ync signals for asymmetric traffic Table 7 shows the SSI2 Interface pin assignments. Note: See Table 18 on page 11 for information on pin multiplexes. Synchronous Serial Interface The EP7312 Synchronous Serial Interface has these features:
- ADC (SSI) Interface: Ma ster mode only; SPI and Microwire1-compatible (128 kbps operation)
- Selectable serial clock polarity Table 8 shows the Synchronous Serial Interface pin assignments. LCD Controller A DMA address generator is provided that fetches video display data for the LCD controller from memory. The display frame buffer start address is pr ogrammable, allowing the LCD frame buffer to be in SDRAM, internal SRAM or external SRAM. The LCD controller has these features:
- Interfaces directly to a si ngle-scan panel monochrome STN LCD
- Interfaces to a single-scan panel color STN LCD with minimal external glue logic
- Panel width size is programmable from 32 to 1024 pixels in 16-pixel increments
- Video frame buffer size programmable up to 128 KB
- Bits per pixel of 1, 2, or 4 bits Table 9 shows the LCD Interface pin assignments. 64-Key Keypad Interface Matrix keyboards and keypads can be easily read by the EP7312. A dedicated 8-bit column driver output generates
Table 6. CODEC Interface Pin Assignments Table 7. SSI2 Interface Pin Assignments Table 8. Serial Interface Pin Assignments Table 9. LCD Interface Pin Assignments
- Column outputs can be individually set high with the remaining bits left at high-impedance
- Column outputs can be driven all-low, all-high, or all-high- impedance
- Keyboard interrupt driven by OR'ing together all Port A bits
- Keyboard interrupt can be used to wake up the system
- 8 ×8 keyboard matrix usable with no external logic, extra keys can be added with minimal glue logic Table 10 shows the Keypad Interface Pin Assignments. Interrupt Controller When unexpected events ar ise during the execution of a program (i.e., interrupt or memory fault) an exception is usually generated. When these exceptions occur at the same time, a fixed priority system determines the order in which they are handled. The EP7312 interrupt controller has two interrupt types: interrupt request (IRQ) and fast interrupt request (FIQ). The interrupt controller has the ability to control interrupts from 22 different FIQ and IRQ sources. The Interrupt controller has these features:
- Supports 22 interrupts from a variety of sources (such as UARTs, SSI1, and key matrix.)
- Routes interrupt sources to the ARM720T’s IRQ or FIQ (Fast IRQ) inputs
- Five dedicated off-chip inte rrupt lines operate as level sensitive interrupts Table 11 shows the interrupt controller pin assignments. Note: Pins are multiplexed. See Table 19 on page 11 for more information. Real-Time Clock The EP7312 contains a 32-bit Real Time Clock (RTC) that can be written to and read from in the same manner as the timer counters. It also contains a 32-bit output match register which can be programmed to generate an interrupt.
- Driven by an external 32.768 kHz crystal oscillator Table 12 shows the Real-Time Clock pin assignments. PLL and Clocking The EP7312 processor and peri pheral clocks have these features:
- Processor and peripheral clocks operate from a single
3.6864 MHz crystal or external 13 MHz clock
- Programmable clock speeds allo w the peripheral bus to run at 18 MHz when the processor is set to 18 MHz and at
36 MHz when the processor is set to 36, 49 or 74 MHz, and
at 45 MHz when the processor is set to 90 MHz. Table 13 shows the PLL and clocking pin assignments. Table 10. Keypad Interface Pin Assignments Table 11. Interrupt Controller Pin Assignments Table 12. Real-Time Clock Pin Assignments Table 13. PLL and Clocking Pin Assignments
- Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a positive or negative DC to DC converter Table 14 shows the DC-to-DC Converter Interface pin assignments.Timers
- Internal (RTC) timer
- Two internal 16-bit programmable hardware count-down timers General Purpose Input/Output (GPIO)
- Three 8-bit and one 3-bit GPIO ports
- Supports scanning keyboard matrix Table 15 shows the GPIO pin assignments. Note: Pins are multiplexed. See Table 19 on page 11 for more information. Hardware Debug Interface
- Full JTAG boundary scan and Embedded ICE ® support Table 16 shows the Hardware Debug Interface pin assignments. LED Flasher A dedicated LED flasher module can be used to generate a low frequency signal on Port D pin 0 for the purpose of blinking an LED without CPU intervention. The LED flasher feature is ideal as a visual annunciator in battery powered applications, such as a voice mail indicat or on a portable phone or an appointment reminder on a PDA. Table 17 shows the LED Flasher pin assignments.
- Software adjustable flash period and duty cycle
- Operates from 32 kHz RTC clock
- Will continue to flash in IDLE and STANDBY states
- 4 mA drive current Note: Pins are multiplexed. See Table 19 on page 11 for more information. Internal Boot ROM The internal 128-byte Boot ROM facilitates download of saved code to the on-board SRAM/FLASH. Packaging The EP7312 is available in a 208 -pin LQFP package, 256-ball PBGA package, or a 204-ball TFBGA package.
Table 14. DC-to-DC Converter Interface Pin Assignments Table 15. General Purpose Input/Output Pin Assignments Table 16. Hardware Debug Interface Pin Assignments Table 17. LED Flasher Pin Assignments
Manual for more information). Table 18. DAI/SSI2/CODEC Pin Multiplexing Table 19. Pin Multiplexing
interface logic is integrated on-chip. Figure 1. A Fully-Configured EP7312-Based System Note: A system can only use one of the following peripher al interfaces at any given time: SSI2,CODEC or DAI.
DS508F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 13 EP7312 High-Performance, Low-Power System on Chip ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Recommended Operating Conditions DC Characteristics All characteristics are specified at VDDCORE = 2.5 V , VDDIO = 3.3 V and VSS = 0 V over an operating temperature of 0°C to +70°C for all frequencies of operation. The current consumption figures have test conditions specified per parameter.” DC Core, PLL, and RTC Supply Voltage 2.9 V DC I/O Supply Voltage (Pad Ring) 3.6 V DC Pad Input Current ±10 mA/pin; ±100 mA cumulative Storage Temperature, No Power –40 °C to +125°C DC core, PLL, and RTC Supply Voltage 2.5 V ± 0.2 V DC I/O Supply Voltage (Pad Ring) 2.3 V - 3.5 V DC Input / Output Voltage O–I/O supply voltage Operating Temperature Extended -20°C to +70°C; Commercial 0°C to +70°C; Industrial -40°C to +85°C Symbol Parameter Min Typ Max Unit Conditions VIH CMOS input high voltage 0.65 × VDDIO - VDDIO + 0.3 V VDDIO = 2.5 V VIL CMOS input low voltage VSS − 0.3 - 0.25 × VDDIO V VDDIO = 2.5 V VT+ Schmitt trigger positive going threshold -- 2 . 1 V VT - Schmitt trigger negative going threshold 0.8 - - V Vhst Schmitt trigger hysteresis 0.1 - 0.4 V VIL to VIH VOH CMOS output high voltagea Output drive 1a Output drive 2a VDD – 0.2 2.5 2.5 V V V IOH = 0.1 mA IOH = 4 mA IOH = 12 mA VOL CMOS output low voltage a Output drive 1a Output drive 2a 0.3 0.5 0.5 V V V IOL = –0.1 mA IOL = –4 mA IOL = –12 mA IIN Input leakage current - - 1.0 µA VIN = VDD or GND IOZ Bidirectional 3-state leakage currentb c 25 - 100 µA VOUT = VDD or GND CIN Input capacitance 8 - 10.0 pF COUT Output capacitance 8 - 10.0 pF
14 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 EP7312 High-Performance, Low-Power System on Chip Note: 1) Total power consumption = IDD CORE x 2.5 V + IDDIO x 3.3 V 2) Pull-up current = 50 µA typical at VDD = 3.3 V. CI/O Transceiver capacitance 8 - 10.0 pF IDDSTANDBY @ 25 C Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V µA Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = V DD ± 0.1 V, VIL = GND ± 0.1 V IDDSTANDBY @ 70 C Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V 570 111 µA Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = V DD ± 0.1 V, VIL = GND ± 0.1 V IDDSTANDBY @ 85 C Standby current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V 1693 163 µA Only nPOR, nPWRFAIL, nURESET, PE0, PE1, and RTS are driven, while all other float, VIH = V DD ± 0.1 V, VIL = GND ± 0.1 V IDDidle at 74 MHz Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V mA Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = VDD ± 0.1 V, VIL = GND ± 0.1 V IDDIDLE at 90 MHz Idle current consumption1 Core, Osc, RTC @2.5 V I/O @ 3.3 V mA Both oscillators running, CPU static, Cache enabled, LCD disabled, VIH = VDD ± 0.1 V, VIL = GND ± 0.1 V VDDSTANDBY Standby supply voltage 2.0 - - V Minimum standby voltage for state retention, internal SRAM cache, and RTC operation only a. Refer to the strength column in the pi n assignment tables for all package types. b. Assumes buffer has no pull- up or pull-down resistors. c. The leakage value given assumes that the pin is conf igured as an input pin but is not currently being driven. Symbol Parameter Min Typ Max Unit Conditions
clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated. Figure 2. Legend for Timing Diagrams
16 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 EP7312 High-Performance, Low-Power System on Chip SDRAM Interface Figure 3 through Figure 6 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes. Parameter Symbol Min Typ Max Unit SDCLK falling edge to SDCS assert delay time tCSa 024 n s SDCLK falling edge to SDCS deassert delay time tCSd − 3 2 10 ns SDCLK falling edge to SDRAS assert delay time tRAa 137 n s SDCLK falling edge to SDRAS deassert delay time tRAd − 3 1 10 ns SDCLK falling edge to SDRAS invalid delay time tRAnv 247 n s SDCLK falling edge to SDCAS assert delay time tCAa − 22 5 n s SDCLK falling edge to SDCAS deassert delay time tCAd − 50 3 n s SDCLK falling edge to ADDR transition time tADv − 31 5 n s SDCLK falling edge to ADDR invalid delay time tADx − 22 5 n s SDCLK falling edge to SDMWE assert delay time tMWa − 31 5 n s SDCLK falling edge to SDMWE deassert delay time tMWd − 40 4 n s DATA transition to SDCLK falling edge time tDAs 2-- n s SDCLK falling edge to DATA transition hold time tDAh 1-- n s SDCLK falling edge to DATA transition delay time tDAd 0 - 15 ns
- The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Figure 3. SDRAM Load Mode Register Cycle Timing Measurement
- The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Designers should take care to ensure that delays between SDRAM control and data signals are approximately equal. Figure 4. SDRAM Burst Read Cycle Timing Measurement
- The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Figure 5. SDRAM Burst Write Cycle Timing Measurement
- The SDCLK signal may be phase shifted relative to the rest of the SDRAM control and data signals due to uneven loading.
Figure 6. SDRAM Refresh Cycle Timing Measurement
DS508F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 21 EP7312 High-Performance, Low-Power System on Chip Static Memory Figure 7 through Figure 10 define the timings associated with all phases of the Static Memory . The following table contains the values for the timings of each of the Static Memory modes. Parameter Symbol Min Typ Max Unit EXPCLK rising edge to nCS assert delay time tCSd 2 8 20 ns EXPCLK falling edge to nCS deassert hold time tCSh 2 7 20 ns EXPCLK rising edge to A assert delay time tAd 4 9 16 ns EXPCLK falling edge to A deassert hold time tAh 31 0 1 9 n s EXPCLK rising edge to nMWE assert delay time tMWd 3 6 10 ns EXPCLK rising edge to nMWE deassert hold time tMWh 3 6 10 ns EXPCLK falling edge to nMOE assert delay time tMOEd 3 7 10 ns EXPCLK falling edge to nMOE deassert hold time tMOEh 2 7 10 ns EXPCLK falling edge to HALFWORD deassert delay time tHWd 2 8 20 ns EXPCLK falling edge to WORD assert delay time tWDd 2 8 16 ns EXPCLK rising edge to data valid delay time tDv 81 3 2 1 n s EXPCLK falling edge to data invalid delay time tDnv 61 5 3 0 n s Data setup to EXPCLK falling edge time tDs --1 n s EXPCLK falling edge to data hold time tDh --3 n s EXPCLK rising edge to WRITE assert delay time tWRd 51 1 2 3 n s EXPREADY setup to EXPCLK falling edge time tEXs --0 n s EXPCLK falling edge to EXPREADY hold time tEXh --0 n s
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
- Address, Halfword, Word, and Write hold state until next cycle.
Figure 7. Static Memory Single Read Cycle Timing Measurement
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
- Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
- Address, Data, Halfword, Word, and Write hold state until next cycle.
Figure 8. Static Memory Single Write Cycle Timing Measurement
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
- The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
- Consecutive reads with sequential access enabled are identical except that the sequential access wait state field is used to
cycles. This improves performance so the SQAEN bit should always be set where possible.
- Address, Halfword, Word, and Write hold state until next cycle.
Figure 9. Static Memory Burst Read Cycle Timing Measurement
cycles that can be driven. The number of consecutive cycles can be programmed from 2 to 4, inclusively.
- The cycle time can be extended by integer multiples of the clock period (22 ns at 45 MHz, 27 ns at 36 MHz, 54 ns at
where EXPRDY is sampled again. EXPCLK need not be referenced when driving EXPRDY, but is shown for clarity.
- Zero wait states for sequential writes is not permitted for memory devices which use nMWE pin, as this cannot be driven with
valid timing under zero wait state conditions.
- Address, Data, Halfword, Word, and Write hold state until next cycle.
Figure 10. Static Memory Burst Write Cycle Timing Measurement
Figure 11. SSI1 Interface Timing Measurement
Figure 12. SSI2 Interface Timing Measurement
Figure 13. LCD Controller Timing Measurement
Figure 14. JTAG Timing Measurement
Note: 1) Dimensions are in millimeters (inches ), and controlling dimension is millimeter. 2) Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 4) For pin locations, please see Figure 16. For pin descriptions see the EP7312 User’s Manual. Figure 15. 208-Pin LQFP Package Outline Drawing
Note: 1. N/C should not be grounded but left as no connects. Figure 16. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram
Table 20. 208-Pin LQFP Numeric Pin Listing
3 VSSIO Pad Gnd I/O ground
4 EXPCLK 1 I Expansion clock input
5 WORD 1 Low O Word access select output
6 WRITE/nSDRAS 1 Low O Transfer direction / SDRAM
7 RUN/CLKEN 1 Low O Run output / clock enable
8 EXPRDY 1 I Expansion port ready input
9 TXD[2] 1 High O UART 2 transmit data output
10 RXD[2] I UART 2 receive data input
11 TDI with p/u* I JTAG data input
12 VSSIO Pad Gnd I/O ground
13 PB[7] 1 Input
14 PB[6] 1 Input‡ I/O GPIO port B
15 PB[5] 1 Input‡ I/O GPIO port B
16 PB[4] 1 Input‡ I/O GPIO port B
17 PB[3] 1 Input‡ I/O GPIO port B
18 PB[2] 1 Input‡ I/O GPIO port B
19 PB[1] 1 Input‡ I/O GPIO port B
20 PB[0] 1 Input‡ I/O GPIO port B
22 TDO 1 Input‡ O JTAG data out
23 PA[7] 1 Input‡ I/O GPIO port A
24 PA[6] 1 Input‡ I/O GPIO port A
25 PA[5] 1 Input‡ I/O GPIO port A
26 PA[4] 1 Input‡ I/O GPIO port A
27 PA[3] 1 Input‡ I/O GPIO port A
28 PA[2] 1 Input‡ I/O GPIO port A
29 PA[1] 1 Input‡ I/O GPIO port A
30 PA[0] 1 Input‡ I/O GPIO port A
31 LEDDRV 1 Low O IR LED drive
32 TXD[1] 1 High O UART 1 transmit data out
33 VSSIO 1 High Pad Gnd I/O ground
34 PHDIN I Photodiode input
35 CTS I UART 1 clear to send input
36 RXD[1] I UART 1 receive data input
37 DCD I UART 1 data carrier detect
38 DSR I UART 1 data set ready input
41 EINT[3] I External interrupt
45 PE[2]/CLKSEL 1 Input
46 PE[1]/BOOTSEL[1] 1 Input‡ I/O GPIO port E / boot mode
47 PE[0]/BOOTSEL[0] 1 Input‡ I/O GPIO port E / Boot mode
48 VSSRTC RTC Gnd Real time clock ground
49 RTCOUT O Real time clock oscillator
50 RTCIN I Real time clock oscillator
52 N/C
53 PD[7]/SDQM[1] 1 Low I/O GPIO port D / SDRAM byte
54 PD[6]/SDQM[0] 1 Low I/O GPIO port D / SDRAM byte
55 PD[5] 1 Low I/O GPIO port D
56 PD[4] 1 Low I/O GPIO port D
58 TMS with p/u* I JTAG mode select
59 PD[3] 1 Low I/O GPIO port D
60 PD[2] 1 Low I/O GPIO port D
61 PD[1] 1 Low I/O GPIO port D
62 PD[0]/LEDFLSH 1 Low I/O GPIO port D / LED blinker
63 SSICLK 1 Input
64 VSSIO Pad Gnd I/O ground
65 SSITXFR 1 Low I/O DAI/CODEC /SSI2 serial clock
66 SSITXDA 1 Low O DAI/CODEC/SSI2 serial data
67 SSIRXDA I DAI/CODEC/SSI2 serial data
68 SSIRXFR Input‡ I/O DAI/CODEC/SSI2 frame sync
69 ADCIN I SSI1 ADC serial input
71 VSSCORE Core ground Core ground
73 VSSIO Pad Gnd I/O ground
75 DRIVE[1] 2 High /
76 DRIVE[0] 2 High /
77 ADCCLK 1 Low O SSI1 ADC serial clock
78 ADCOUT 1 Low O SSI1 ADC serial data output
Table 20. 208-Pin LQFP Numeric Pin Listing (Continued)
79 SMPCLK 1 Low O SSI1 ADC sample clock
80 FB[1] I PWM feedback input
81 VSSIO Pad Gnd I/O ground
82 FB[0] I PWM feedback input
83 COL[7] 1 High O Keyboard scanner column
84 COL[6] 1 High O Keyboard scanner column
85 COL[5] 1 High O Keyboard scanner column
86 COL[4] 1 High O Keyboard scanner column
87 COL[3] 1 High O Keyboard scanner column
88 COL[2] 1 High O Keyboard scanner column
90 TCLK I JTAG clock
91 COL[1] 1 High O Keyboard scanner column
92 COL[0] 1 High O Keyboard scanner column
93 BUZ 1 Low O Buzzer drive output
94 D[31] 1 Low I/O Data I/O
95 D[30] 1 Low I/O Data I/O
96 D[29] 1 Low I/O Data I/O
97 D[28] 1 Low I/O Data I/O
98 VSSIO Pad Gnd I/O ground
99 A[27]/DRA[0] 2 Low O System byte address /
100 D[27] 1 Low I/O Data I/O
101 A[26]/DRA[1] 2 Low O System byte address /
102 D[26] 1 Low I/O Data I/O
103 A[25]/DRA[2] 2 Low O System byte address /
104 D[25] 1 Low I/O Data I/O
105 HALFWORD 1 Low O Halfword access select output
106 A[24]/DRA[3] 1 Low O System byte address /
108 VSSIO — Pad Gnd I/O ground
109 D[24] 1 Low I/O Data I/O
110 A[23]/DRA[4] 1 Low O System byte address /
111 D[23] 1 Low I/O Data I/O
112 A[22]/DRA[5] 1 Low O System byte address /
113 D[22] 1 Low I/O Data I/O
114 A[21]/DRA[6] 1 Low O System byte address /
115 D[21] 1 Low I/O Data I/O
116 VSSIO Pad Gnd I/O ground
117 A[20]/DRA[7] 1 Low O System byte address /
118 D[20] 1 Low I/O Data I/O
119 A[19]/DRA[8] 1 Low O System byte address /
120 D[19] 1 Low I/O Data I/O
121 A[18]/DRA[9] 1 Low O System byte address /
122 D[18] 1 Low I/O Data I/O
124 VSSIO Pad Gnd I/O ground
126 A[17]/DRA[10] 1 Low O System byte address /
127 D[17] 1 Low I/O Data I/O
128 A[16]/DRA[11] 1 Low O System byte address /
129 D[16] 1 Low I/O Data I/O
130 A[15]/DRA[12] 1 Low O System byte address /
131 D[15] 1 Low I/O Data I/O
132 A[14]/DRA[13] 1 Low O System byte address /
133 D[14] 1 Low I/O Data I/O
134 A[13]/DRA[14] 1 Low O System byte address /
135 D[13] 1 Low I/O Data I/O
136 A[12] 1 Low O System byte address
137 D[12] 1 Low I/O Data I/O
138 A[11] 1 Low O System byte address
140 VSSIO Pad Gnd I/O ground
141 D[11] 1 Low I/O Data I/O
142 A[10] 1 Low O System byte address
143 D[10] 1 Low I/O Data I/O
144 A[9] 1 Low O System byte address
145 D[9] 1 Low I/O Data I/O
146 A[8] 1 Low O System byte address
147 D[8] 1 Low I/O Data I/O
148 A[7] 1 Low O System byte address
149 VSSIO Pad Gnd I/O ground
150 D[7] 1 Low I/O Data I/O
153 BATOK I Battery OK input
158 MOSCIN I Main oscillator input
159 MOSCOUT O Main oscillator output
160 VSSOSC Oscillator Grou nd Oscillator Ground
161 WAKEUP Schmitt I System wake up input
163 A[6] 1 Low O System byte address
164 D[6] 1 Low I/O Data I/O
165 A[5] 1 Low Out System byte address
166 D[5] 1 Low I/O Data I/O
168 VSSIO Pad Gnd I/O ground
169 A[4] 1 Low O System byte address
170 D[4] 1 Low I/O Data I/O
171 A[3] 2 Low O System byte address
172 D[3] 1 Low I/O Data I/O
173 A[2] 2 Low O System byte address
174 VSSIO Pad Gnd I/O ground
175 D[2] 1 Low I/O Data I/O
176 A[1] 2 Low O System byte address
177 D[1] 1 Low I/O Data I/O
178 A[0] 2 Low O System byte address
179 D[0] 1 Low I/O Data I/O
180 VSSCORE Core ground Core ground
182 VSSIO Pad ground I/O ground
184 CL[2] 1 Low O LCD pixel clock out
185 CL[1] 1 Low O LCD line clock
186 FRM 1 Low O LCD frame synchronization
187 M 1 Low O LCD AC bias drive
188 DD[3] 1 Low I/O LCD serial display data
189 DD[2] 1 Low I/O LCD serial display data
190 VSSIO Pad Gnd I/O ground
191 DD[1] 1 Low I/O LCD serial display data
192 DD[0] 1 Low I/O LCD serial display data
195 SDQM[3] 2 Low I/O SDRAM byte lane mask
196 SDQM[2] 2 Low I/O SDRAM byte lane mask
198 VSSIO Pad Gnd I/O ground
199 SDCKE 2 Low I/O SDRAM clock enable output
200 SDCLK 2 Low I/O SDRAM clock out
203 VSSIO Pad Gnd I/O ground
*“With p/u” means with internal pull-up of 100 KOhms on the pin. ‡Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions.
Figure 17. 204-Ball TFBGA Package
DS508F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 39 EP7312 High-Performance, Low-Power System on Chip 204-Ball TFBGA Pinout (Top View) 12345 678 9 1 01 1 1 2 1 3 1 4 1 5 1 6 1 7 1 81 92 0 A VDDIO EXPCLK nCS[3] nCS[1] nMWE/ nSDWE SDQM[2 ] nSDCS[1] DD[2] FRM CL[1] GNDCORE D[1] A[2] D[4] A[5] nPWRFL MOSCOUT GNDIO GNDIO GNDIO A B WORD VDDIO nCS[5] nCS[2] nMOE/ nSDCAS SDCKE nSDCS[0] DD[1] M CL[2] D[0] A[1] D[3] A[4] D[6] WAKEUP MOSCIN GNDIO GNDIO nURESET B C RUN/ CLKEN EXPRDY VDDIO nCS[4] nCS [0] SDCLK SDQM[3] DD[0] DD[3] VDDCORE A[0] D[2 ] A[3] D[5] A[6] GNDOSC VDDOSC GNDIO BATOK nPOR C D PB[7] RXD[2] VDDIO GNDIO nBATCHG A[7] D E PB[4] TXD[2] WRITE/ nSDRAS nMEDCHG/n BROM nEXTPWR D[9] E F PB[3] PB[6] TDI D[7] A[8] D[10] F G PB[1] PB[2] PB[5] D[8] A[9] D[11] G H PA[7] TDO PB[0] A[10] D[12] A[12] H J PA[4] PA[5] PA[6] A[11] D[13] A[13]/ DRA[14] J K PA[1] PA[2] VDDIO D[14] A[14]/ DRA[13] D[15] K L TXD[1] LEDDRV PA[3] VDDIO D[16] A[16]/ DRA[11] L M RXD[1] CTS PA[0] A[15]/ DRA[12] A[17]/ DRA[10] nTRST M N DSR nTEST[1] PHDIN D[17] D[19] A[18]/ DRA[9] N P EINT[3] nEINT[2] DCD D[18] A[20]/ DRA[7] D[20] P R nEXTFIQ PE2/ CLKSEL nTEST[0] A[19]/ DRA[8] D[22] A[21]/ DRA6 R T PE[1]/ BOOT SEL[1] PE[0]/ BOOT SEL[0] nEINT[1] D[21] D[23] A[22]/ DRA5 T U GNDRTC RTCOUT RTCIN HALF WORD D[24] A[23]/ DRA4 U V VDDRTC GNDIO GNDIO PD[7]/ SDQM[1] PD[4] PD[2] SSICLK SSIRXD A nADCCS VDDIO ADCCLK COL[7] COL[4] TCLK BUZ D[29] A[26]/ DRA[1] VDDIO VDDIO A[24]/ DRA3 V W GNDIO GNDIO GNDIO PD[6]/ SDQM[0] TMS PD[1] SSITXFR SSIRXFR GNDCORE DRIVE[1] A DCOUT FB[0] COL[5] COL[2] COL[0] D[30] A[27]/ DRA[0] D[26] VDDIO D[25] W Y GNDIO GNDIO GNDIO PD[5] PD[3] PD[0]/ LED FLSH SSITXDA ADCIN VDDCORE DRIVE[0] SMPCLK FB[ 1] COL[6] COL[3] COL[1] D[31] D[28] D[27] A[25]/ DRA[2] VDDIO Y
The list is ordered by ball location. Table 21. 204-Ball TFBGA Ball Listing
Table 21. 204-Ball TFBGA Ball Listing (Continued)
*“With p/u” means with internal pull-up of 100 KOhms on the pin. ‡Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. Figure 18. 256-Ball PBGA Package Note: 1) For pin locations see Table 22. 3) Before beginning any new EP7312 design, contact Cirrus Logic for the latest package information.
DS508F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 47 EP7312 High-Performance, Low-Power System on Chip TOP VIEW 17.00 (0.669) 15.00 (0.590) SIDE VIEW BOTTOM VIEW A B C D E F G H J K L M N P R T 1.00 (0.040) Pin 1 Indicator Pin 1 Corner Pin 1 Corner 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 15.00 (0.590)
2 Layer
17.00 (0.669) 1.00 (0.040) 1.00 (0.040) 30° TYP REF REF 0.50
3 Places
0.85 (0.034) ±0.05 (.002) 0.40 (0.016) ±0.05 (.002) 0.36 (0.014) 17.00 (0.669) R D E ±0.20 (.008) ±0.20 (.008) ±0.20 (.008) ±0.20 (.008) ±0.09 (0.004) JEDEC #: MO-151 Ball Diameter: 0.50 mm ± 0.10 mm 17 ¥ 17 ¥ 1.61 mm body
48 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 EP7312 High-Performance, Low-Power System on Chip 256-Ball PBGA Pinout (Top View) 1 234 56789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 A VDDIO nCS[4] nCS[1] SDCLK SDQM[3] DD[1] M VDDIO D [0] D[2] A[3] VDDIO A[6] MOSCOUT VDDOSC VSSIO A B nCS[5] VDDIO nCS[3] nMOE/ nSDCAS VDDIO nSDCS[1] DD[2] CL[1] VDDCORE D[1] A[2] A[4] A[5] WAKEUP VDDIO nURESET B C VDDIO EXPCLK VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO VSSIO VDDIO VSSIO VSSIO nPOR nEXTPWR C D WRITE/ nSDRAS EXPRDY VSSIO VDDIO nCS[2] nMWE/ nSDWE nSDCS[0] CL[2] VSSRTC D[4] nPWRF L MOSCIN VDDIO VSSIO D[7] D[8] D E RXD[2] PB[7] TDI WORD VSSIO nCS[0] SDQM[2] FRM A[0] D[5] VSSOSC VSSIO nMEDCHG/ nBROM VDDIO D[9] D[10] E F PB[5] PB[3] VSSIO TXD[2] RUN/ CLKEN VSSIO SDCKE DD[3] A[1] D[6] VSSRTC BATOK nBATCHG VSSIO D[11] VDDIO F G PB[1] VDDIO TDO PB[4] PB[6] VSSCore VSSRTC DD[0] D[3] VSSRTC A[7] A[8] A[9] VSSIO D[12] D[13] G H PA[7] PA[5] VSSIO PA[4] PA[6] PB[0] PB[2] VSSRTC VSSRTC A[10] A[11] A[12] A[13]/ DRA[14] VSSIO D[14] D[15] H J PA[3] PA[1] VSSIO PA[2] PA[0] TXD[1] CTS VSSRTC VSSRTC A[17]/ DRA[10] A[16]/ DRA[11] A[15]/ DRA[12] A[14]/ DRA[13] nTRST D[16] D[17] J K LEDDRV PHDIN VSSIO DCD nTEST[1] EINT[3] VSSRTC ADCIN COL[4] TCLK D[20] D[19] D[18] VSSIO VDDIO VDDIO K L RXD[1] DSR VDDIO nEINT[1] PE[2]/ CLKSEL VSSRTC PD[0]/ LEDFLSH VSSRTC COL[6] D[31] VSSRTC A[22]/ DRA[5] A[21]/ DRA[6] VSSIO A[18]/ DRA[9] A[19]/ DRA[8] L M nTEST[0] nEINT[2] VDDIO PE[0]/ BOOTSEL[0] TMS VDDIO SSITXFR DRIVE[1] FB[0] COL[0] D[27] VSSIO A[23]/ DRA[4] VDDIO A[20]/ DRA[7] D[21] M N nEXTFIQ PE[1]/ BOOTSEL[1] VSSIO VDDIO PD[5] PD[2] SSIRXDA ADCCLK SMPCLK COL[2] D[29] D[26] HALFWORD VSSIO D[22] D[23] N P VSSRTC RTCOUT VSSIO VSSIO VDDIO VSSIO VSSIO VDDI O VSSIO VDDIO VSSIO VSSI O VDDIO VSSIO D[24] VDDIO P R RTCIN VDDIO PD[4] PD[1] SSITXDA nADCCS VDDIO ADCOUT COL[7] COL[3] COL[1] D[30] A[27]/ DRA[0] A[25]/ DRA[2] VDDIO A[24]\\ DRA[3] R T VDDRTC PD[7]/ SDQM[1] PD[6]/ SDQM[0] PD[3] SSICLK SSIRXFR VDDCORE DRIVE[0] FB[1] COL[5] VDDIO BUZ D[28] A[26]/ DRA[1] D[25] VSSIO T
The list is ordered by ball location. Table 22. 256-Ball PBGA Ball Listing
Table 22. 256-Ball PBGA Ball Listing (Continued)
*“With p/u” means with internal pull-up of 100 KOhms on the pin. ‡Input. Port A,B,D,E GPIOs default to input at nPOR and URESET conditions. Table 23. JTAG Boundary Scan Signal Ordering
4 A2 C2 EXPCLK I/O 3
6 E3 D1 WRITE/nSDRAS O 8
7 C1 F5 RUN/CLKEN O 10
8 C2 D2 EXPRDY I 13
10 D2 E1 RXD2 I 16
13 F3 E2 PB[7] I/O 17
14 D1 G5 PB[6] I/O 20
15 F2 F1 PB[5] I/O 23
16 E1 G4 PB[4] I/O 26
17 F1 F2 PB[3] I/O 29
18 G2 H7 PB[2] I/O 32
19 G1 G1 PB[1] I/O 35
20 H3 H6 PB[0] I/O 38
23 H1 H1 PA[7] I/O 41
24 J3 H5 PA[6] I/O 44
25 J2 H2 PA[5] I/O 47
26 J1 H4 PA[4] I/O 50
27 L3 J1 PA[3] I/O 53
28 K2 J4 PA[2] I/O 56
29 K1 J2 PA[1] I/O 59
30 M3 J5 PA[0] I/O 62
31 L2 K1 LEDDRV O 65
32 L1 J6 TXD1 O 67
34 N3 K2 PHDIN I 69
35 M2 J7 CTS I 70
36 M1 L1 RXD1 I 71
37 P3 K4 DCD I 72
38 N1 L2 DSR I 73
39 N2 K5 nTEST1 I 74
40 R3 M1 nTEST0 I 75
41 P1 K6 EINT3 I 76
42 P2 M2 nEINT2 I 77
43 T3 L4 nEINT1 I 78
44 R1 N1 nEXTFIQ I 79
45 R2 L5 PE[2]/CLKSEL I/O 80
46 T1 N2 PE[1]/
47 T2 M4 PE[0]/BOOTSEL0 I/O 86
53 V4 T2 PD[7]/SDQM[1] I/O 89
54 W4 T3 PD[6/SDQM[0]] I/O 92
55 Y4 N5 PD[5] I/O 95
Table 23. JTAG Boundary Scan Signal Ordering (Continued)
56 V5 R3 PD[4] I/O 98
59 Y5 T4 PD[3] I/O 101
60 V6 N6 PD[2] I/O 104
61 W6 R4 PD[1] I/O 107
62 Y6 L7 PD[0]/LEDFLSH O 110
68 W8 T6 SSIRXFR I/O 122
69 Y8 K8 ADCIN I 125
70 V9 R6 nADCCS O 126
75 W10 M8 DRIVE1 I/O 128
76 Y10 T8 DRIVE0 I/O 131
77 V11 N8 ADCCLK O 134
78 W11 R8 ADCOUT O 136
79 Y11 N9 SMPCLK O 138
80 Y12 T9 FB1 I 140
82 Y11 M9 FB0 I 141
83 Y12 R9 COL7 O 142
84 Y13 L9 COL6 O 144
85 W13 T10 COL5 O 146
86 V13 K9 COL4 O 148
87 Y14 R10 COL3 O 150
88 W14 N10 COL2 O 152
91 Y15 R11 COL1 O 154
92 W15 M10 COL0 O 156
93 V15 T12 BUZ O 158
94 Y16 L10 D[31] I/O 160
95 W16 R12 D[30] I/O 163
96 V16 N11 D[29] I/O 166
97 Y17 T13 D[28] I/O 169
99 Y16 R13 A[27]/DRA[0] Out 172
100 Y18 M11 D[27] I/O 174
101 V17 T14 A[26]/DRA[1] O 177
102 W18 N12 D[26] I/O 179
103 Y19 R14 A[25]/DRA[2] O 182
104 Y20 T15 D[25] I/O 184
105 U18 N13 HALFWORD O 187
106 V209 R16 A[24]/DRA[3] O 189
109 U19 P15 D[24] I/O 191
110 U20 M13 A[23]/DRA[4] O 194
111 T19 N16 D[23] I/O 196
112 T20 L12 A[22]/DRA[5] O 199
113 R19 N15 D[22] I/O 201
114 R20 L13 A[21]/DRA[6] O 204
115 T18 M16 D[21] I/O 206
117 P19 M15 A[20]/DRA[7] O 209
118 P20 K11 D[20] I/O 211
119 R18 L16 A[19]/DRA[8] O 214
120 N19 K12 D[19] I/O 216
121 N20 L15 A[18]/DRA[9] O 219
122 P18 K13 D[18] I/O 221
126 M19 J10 A[17]/DRA[10] O 224
127 N18 J16 D[17] I/O 226
128 L20 J11 A[16]/DRA[11] O 229
129 L19 J15 D[16] I/O 231
130 M18 J12 A[15]/DRA[12] O 234
131 K20 H16 D[15] I/O 236
132 K19 J13 A[14]/DRA[13] O 239
133 K18 H15 D[14] I/O 241
134 J20 H13 A[13]/DRA[14] O 244
135 J19 G16 D[13] I/O 246
136 H20 H12 A[12] O 249
137 H19 G15 D[12] I/O 251
138 J18 H11 A[11] O 254
141 G20 F15 D[11] I/O 256
142 H18 H10 A[10] O 259
143 F20 E16 D[10] I/O 261
144 G19 G13 A[9] O 264
145 E20 E15 D[9] I/O 266
146 F19 G12 A[8] O 269
147 G18 D16 D[8] I/O 271
148 D20 G11 A[7] O 274
150 F18 D15 D[7] I/O 276
151 D19 F13 nBATCHG I 279
152 E19 C16 nEXTPWR I 280
153 C19 F12 BATOK I 281
154 C20 C15 nPOR I 282
155 E18 E13 nMEDCHG/nBROM I 283
156 B20 B16 nURESET I 284
161 B16 B14 WAKEUP I 285
162 A16 D11 nPWRFL I 286
163 C15 A13 A[6] O 287
164 B15 F10 D[6] I/O 289
165 A15 B13 A[5] O 292
166 C14 E10 D[5] I/O 294
169 B14 B12 A[4] O 297
170 A14 D10 D[4] I/O 299
171 C13 A11 A[3] O 302
172 B13 G9 D[3] I/O 304
173 A13 B11 A[2] O 307
175 C12 A10 D[2] I/O 309
176 B12 F9 A[1] O 312
177 A12 B10 D[1] I/O 314
178 C11 E9 A[0] O 317
179 B11 A9 D[0] I/O 319
184 B10 D8 CL2 O 322
185 A10 B8 CL1 O 324
186 A9 E8 FRM O 326
187 B9 A7 M O 328
188 C9 F8 DD[3] O 330
189 A8 B7 DD[2] O 333
191 B8 A6 DD[1] O 336
192 C8 G8 DD[0] O 339
193 A7 B6 nSDCS[1] O 342
194 B7 D7 nSDCS[0] O 344
195 C7 A5 SDQM[3] I/O 346
196 A6 E7 SDQM[2] I/O 349
199 B6 F7 SDCKE I/O 352
200 C6 A4 SDCLK I/O 355
201 A5 D6 nMWE/nSDWE O 358
202 B5 B4 nMOE/nSDCAS O 360
204 C5 E6 nCS[0] O 362
205 A4 A3 nCS[1] O 364
206 B4 D5 nCS[2] O 366
207 A3 B3 nCS[3] O 368
208 C4 A2 nCS[4] O 370
DS508F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 59 EP7312 High-Performance, Low-Power System on Chip 1) See EP7312 Users’ Manual for pin naming / functionality. 2) For each pad, the JTAG connection ordering is input, output, then enable as applicable.
measurement, and conventions used in this data sheet. Table 24. Acronyms and Abbreviations Table 25. Unit of Measurement Table 24. Acronyms and Abbreviations (Continued)
Abbreviations used for signal directions are listed in Table 26. Table 26. Pin Description Conventions
62 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 EP7312 High-Performance, Low-Power System on Chip
Ordering Information
Environmental, Manufacturing, & Handling Information * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Temperature Package EP7312-CB 0 to +70 °C 256-pin PBGA, 17mm X 17mm EP7312-CB-90 (90 MHz) EP7312-IB -40 to +85 °C. EP7312-IB-90 (90 MHz) EP7312-CR 0 to +70 °C 204-pin TFBGA, 13mm X 13mm EP7312-CR-90 (90 MHz) EP7312-IR -40 to +85 °C. EP7312-IR-90 (90 MHz) EP7312-CV 0 to +70 °C 208-pin LQFP. EP7312-CV-90 (90 MHz) EP7312-IV -40 to +85 °C. EP7312-IV-90 (90 MHz) EP7312-CVZ (Lead Free) 0 to +70 °C Model Number Peak Reflow Temp MSL Rating* Max Floor Life EP7312-CB 225 °C
37 D a y s
EP7312-CB-90 (90 MHz) EP7312-IB EP7312-IB-90 (90 MHz) EP7312-CR EP7312-CR-90 (90 MHz) EP7312-IR EP7312-IR-90 (90 MHz) EP7312-CV EP7312-CV-90 (90 MHz) EP7312-IV EP7312-IV-90 (90 MHz) EP7312-CVZ (Lead Free) 260 °C
DS508F1 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) 63 EP7312 High-Performance, Low-Power System on Chip
Revision History
PP5 JAN 2004 Preliminary release. Updated SDRAM timing. F1 AUG 2005 Updated ordering information. Added MSL data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation. LINUX is a registered trademark of Linus Torvalds. Microsoft Windows and Microsoft are registered trademarks of Microsoft Corporation.
64 ©Copyright Cirrus Logic, Inc. 2005 (All Rights Reserved) DS508F1 EP7312 High-Performance, Low-Power System on Chip