EP7209

EP7209 CIRRUS | Alldatasheet

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FEATURES

(cont.) (cont.) Functional Block Diagram Copyright  Cirrus Logic, Inc. 1999 (All Rights Reserved)P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com EP7209 ■ Audio decoder system-on-chip — Allows for support of multiple audio decompression algorithms — Supports MPEG 1, 2, & 2.5 layer 3 audio decoding, including ISO compliant MPEG 1 & 2 layer 3 support for all standard sample rates and bit rates — Supports bit streams with adaptive bit rates — DAI (Digital Audio Interface) providing glueless interface to low power DACs, ADCs, and Codecs ■ Ultra low power consumption for MP3 playback — 87 mW (typical) for 44.1 kHz samples/sec, 128 kbits/second — 50 mW for 22.05 kHz samples/sec, 64 kbits/second — <1 mW in Standby State ■ ARM720T processor — ARM7TDMI CPU — 8 kbytes of four-way set-associative cache — MMU with 64-entry TLB (transition look-aside buffer) — Write Buffer — Windows  CE enabled — Thumb code support enabled The EP7209 is a complete integrated system on a chip for enabling personal digital audio solutions. It is designed specifically for implementing audio processing algorithms in power sensitive applica- tions. The core-logic functionality of the device is built around an ARM720T embedded processor. The EP7209 also includes a 32-bit Y2K-compliant Real-Time Clock (RTC) and comparator. 32.768-KHZ OSCILLATOR PLL INTERRUPT CONTROLLER POWER MANAGEMENT SSI1 (ADC) LCD CONTROLLER ARM7TDMI CPU CORE 8-KBYTE CACHE MMU TIMER COUNTERS (2) CODEC ARM720T INTERNAL DATA BUS PWM

3.6864 MHZ

32.768 KHZ

EINT[1:3], FIQ, MEDCHG BATOK, NEXTPWR PWRFL, BATCHG PORTS A, B, D (8-BIT) PORT E (3-BIT) KEYBD DRIVERS (0:7) BUZZER DRIVE ADCCLK, ADCIN, ADCOUT, SMPCLK, ADCCS SSICLK, SSITXFR, SSITXDA, SSIRXDA, SSIRSFR UART2 IrDA D[0:31] NPOR, RUN, RESET, WAKEUP EXPCLK, WORD, NCS[0:3], EXPRDY, WRITE A[0:27], DRA[0:12] LCD DRIVE LED AND PHOTODIODE ASYNC INTERFACE 2 GPIO INTERNAL ADDRESS BUS 13-MHZ INPUT ON-CHIP BOOT ROM ASYNC INTERFACE 1 ON-CHIP SRAM 38,400 BYTES CL-PS6700 INTFC. PB[0:1], NCS[4:5] EXPANSION CONTROL UART1SSI2 EPB BRIDGE EPB BUS RTCFLASHING LED DRIVE ICE-JTAG TEST AND DEVELOPMENT WRITE BUFFER DAI STATE CONTROL MEMORY CONTROLLER LCD DMA DC-TO-DC DEC ‘99 DS453PP2 Ultra-Low-Power Audio Decoder System-on-Chip EP7209

OVERVIEW (cont.) FEATURES (cont.)

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The EP7209 also includes a comprehensive set of integrated peripherals such as an LCD display con- troller, an audio DAC interface, and a FLASH memory interface. Using the EP7209, a portable audio decoder solution can be built with the addition of an LCD display, an audio DAC, a FLASH memory sub- system, and a small number of additional low cost components. The EP7209 uses its powerful 32-bit RISC process- ing engine to implement audio decompression algo- rithms in software. The nature of the on-board RISC processor and the availability of efficient C-compilers and other software development tools ensures that a wide range of audio decompression algorithms can easily be ported to and run on the EP7209. The EP7209 uses external memory for storing appli- cation code. The use of external memory to support software audio decompression algorithms ensures that the audio decompression system solution can be tailored to the requirements of the application. Soft- ware can be placed in a low cost mask ROM for price sensitive applications, or can be placed in external FLASH memory to enable upgradeable systems. The EP7209’s 8 kbyte on-board cache and programma- ble wait state generator ensure that a wide range of memory options can be utilized. The EP7209 runs a full ISO-compliant MPEG 1, 2, & 2.5 layer 3 audio decompression engine with less than 50% of its available processing capability. This leaves significant processing power available for product differentiation. MPEG 1, 2, & 2.5 Layer 3 Object Code Library Cirrus Logic provides an object code library for enabling MPEG 1, 2, & 2.5 layer 3 audio decompres- sion. This library supports the MPEG 1 sample rates of 48 k, 44.1 k and 32 k bits per second; the MPEG 2 sample rates of 24 k, 22.05 k and 16 k bits per sec- ond; and the MPEG 2.5 sample rates of 12 k, 11.025 k and 8 k bits per second. In addition to all standard fixed compressed data rates, the MPEG layer 3 object code library also supports decompres- sion of variable bit-rate data streams. ■ Dynamically programmable clock speeds of 18, 36, 49, and 74 MHz at 2.5 V ■ Performance matching 100 MHz Intel Pentium-based PC ■ OEM customization — Integrated ARM720T RISC processor — Up to 25 MHz of CPU processing power available (after digital audio decoding) for custom features such as soft- ware EQ or tone control, volume control, spectrum analyzer, random play order, etc. — Allows for control of digital voice recorder function ■ LCD controller — Interfaces directly to a single-scan panel monochrome LCD — Panel width is programmable from 32 to 1024 pixels in 16-pixel increments — Video frame buffer size programmable up to 128 kbytes — Bits per pixel of 1, 2, or 4 bits ■ Memory controller — Decodes up to 6 separate memory segments of up to

256 Mbytes each

— Each segment can be configured as 8, 16, or 32 bits wide and supports page-mode access — Programmable access time for conventional ROM/SRAM/FLASH memory — Supports Removable FLASH card interface — Enables connection to removable FLASH card for addi- tion of expansion FLASH memory modules ■ 38,400 bytes (0x9600) of on-chip SRAM for fast program execution and/or as a frame buffer ■ On-chip boot ROM for manufacturing support ■ Integrated DAI interface — Connects directly to a Crystal® audio DAC ■ 27-bits of general-purpose I/O — Three 8-bit and one 3-bit GPIO port — Supports scanning keyboard matrix ■ SIR (up to 115.2 kbps) infrared encoder/decoder — IrDA (Infrared Data Association) SIR protocol encoder/decoder ■ DC-to-DC converter interface (PWM) — Provides two 96 kHz clock outputs with programmable duty ratio (from 1-in-16 to 15-in-16) that can be used to drive a DC to DC converter ■ 208-pin LQFP or 256-ball PBGA packages ■ Full JTAG boundary scan and Embedded ICE support

OVERVIEW (cont.) DS453PP2 3 Power Management The EP7209 is designed for ultra-low-power opera- tion. Its core operates at only 2.5 V, while its I/O has an operation range of 2.5 V-3.3 V. Through careful design, Cirrus Logic has achieved extremely low power consumption with the EP7209. This is achieved by using a combination of dynamically adjustable core clock frequencies, low power states utilized during periods of inactivity, and fully static design principles. For example, when decompressing MPEG 1 layer 3 music data with sample rates of 44.1 kHz and 128 kbits/sec, the EP7209 consumes less than 87 mW. At sampling frequencies of 22.05 kHz and 64 kbits/sec, power consumption falls to 50 mW. Audio Data Memory Interfaces The EP7209 connects directly to both on-system FLASH memory and to removable FLASH memory- cards. The generality of the external interface on the EP7209 allows for the use of a wide variety of addi- tional memory types for compressed audio data stor- age. LCD Interface The EP7209 interfaces directly to a single-scan panel monochrome LCD display. For portable digital audio player applications that require LCDs, a 128 kbyte display buffer is provided. Data Download The EP7209 along with minimal glue logic can con- nect to a PC through the parallel port. This enables downloading of compressed music or data from a PC to an EP7209-based portable digital audio player. The EP7209 can also be connected to industry stan- dard USB slave devices through an external inter- face. The power of the EP7209 coupled with the

36 MHz external data bus ensures that the EP7209

can support rapid transfer of compressed audio data over a USB interface. The EP7209 also includes a built-in 115.2 kbps IrDA SIR protocol encoder/decoder that can be used to drive an infrared communication interface to down- load the data. Digital Audio Interface The EP7209 integrates an DAI interface to enable a direct connection to many low cost, low power, high quality audio converters. In particular, the DAI inter- face can be used to drive the Crystal CS43L41 / 42 / 43 low power audio DACs and the Crystal CS53L32 low power audio ADC. Some of these devices feature digital bass and treble boost, digital volume control and compressor-limiter functions. Packaging The EP7209 is available in a 208-pin LQFP package and a 256-ball PBGA package. System Design As shown in the system block diagram, simply adding FLASH memory, an LCD, an audio DAC, and some discrete components, a complete low power digital audio player system can be made. (See the following illustration). Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc.Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trade- marks and service marks can be found at http://www.cirrus.com.

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Figure 1. A Typical EP7209-Based Digital Audio Player Reference

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1.1 Acronyms and Abbreviations

ADC analog-to-digital converter. CPU central processing unit. EPB embedded peripheral bus. IrDA Infrared Data Association. JTAG Joint Test Action Group. Table 1. Acronyms and Abbreviations LQFP low profile quad flat pack. PBGA plastic ball grid array. PDA personal digital assistant. PIA peripheral interface adapter. SIR slow (9600 –115.2 kbps) infrared. SRAM static random access memory. SSI synchronous serial interface. TLB translation lookaside buffer. Table 1. Acronyms and Abbreviations(cont.)

(for example, ‘11’ designates a binary number). by a hyphen (for example, CODR[0–2]). ‘n/c’ indicates a pin that is a ‘no connect’.

1.4 Pin Description Conventions

Table 2. Unit of Measurement Table 3. Pin Description Conventions

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Figure 1. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

2.2 Pin Descriptions

stateable to enable the Hi-Z test modes to be supported.

2.2.1 External Signal Functions

bus cycle. This is used to insert wait states for an external bus cycle. cant bits of the address bus. behavior see the LDR instruction in the ARM7TDMI data sheet. Table 4. External Signal Functions

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processor to either boot from the internal Boot ROM, or from external memory. When low, the chip will boot from the internal Boot ROM.

1 I Power fail input; active low, deglitched input to force system into the Standby

pulse width of nPOR needs to be > 77 nsec). This pin is programmed to either output the RUN signal or the CLKEN signal. will be high when the system is active or idle, low while in the Standby State. State (For RUN, see Table 6). first detection has no effect (i.e., it is ignored). User reset input; active low deglitched input from user reset button. Table 4. External Signal Functions(cont.)

Port B I/O. All eight Port B bits can be used as GPIOs. from the boot code storage device (i.e., external 8-bit-wide FLASH bank). are always an output (See Table 6).

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2.2.2 SSI/Codec/DAI Pin Multiplexing

latched state of nURESET to select between the various device test models.

1. All deglitched inputs are via the 16.384 kHz clock. Each deglitched signal must be held active for at least two clock periods. Therefore, the

input signal must be active for at least ~125µs to be detected cleanly. NOTE: The RTC crystal must be populated for the device to function properly. the DAISEL bit in SYSCON3 (See SYSCON3 System Control Register 3). Table 5. SSI/Codec/DAI Pin Multiplexing

2.2.3 Output Bi-Directional Pins

RUN The RUN pin is looped back in to skew the address and data bus from each other. DD[3:0] DD[3:0] are looped back in on power up to enable the reading of the ID of some LCD modules. Table 6. Output Bi-Directional Pins

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1. FUNCTIONAL DESCRIPTION The EP7209 device is a single-chip embedded con- troller designed to be used in low cost and ultra- low-power digital audio players. Operating at

74 MHz, the EP7209 delivers approximately

66 Dhrystone 2.1 MIPS of sustained performance (74 MIPS peak). This is approximately the same as a 100 MHz Pentium-based PC. The EP7209 contains the following functional blocks:  ARM720T processor which consists of the fol- lowing functional sub-blocks: - ARM7TDMI CPU core (which supports the logic for the Thumb instruction set, core debug, enhanced multiplier, JTAG, and the Embedded ICE) running at a dynamically programmable clock speed of 18 MHz, 36 MHz, 49 MHz, or 74 MHz. - Memory Management Unit (MMU) com- patible with the ARM710 core (providing address translation and a 64 entry transla- tion lookaside buffer) with added support for Windows CE. - 8 kbytes of unified instruction and data cache with a four-way set associative cache controller. - Write buffer  38,400 bytes (0x9600) of on-chip SRAM that can be shared between the LCD controller and general application use.  Memory interfaces for up to 6 independent

256 Mbyte expansion segments with program-

ming wait states.  27 bits of general purpose I/O - multiplexed to provide additional functionality where neces- sary.  Digital Audio Interface (DAI) for connection to CD-quality DACs and codecs.  Interrupt controller  Advanced system state control and power man- agement.  Two full-duplex 16550A compatible UARTs with 16-byte transmit and receive FIFOs.  IrDA SIR protocol controller capable of speeds up to 115.2 kbps.  Programmable 1-, 2-, or 4-bit-per-pixel LCD controller with 16-level gray scaler.  Programmable frame buffer start address, al- lowing a system to be built using only internal SRAM for memory.  On-chip boot ROM programmed with serial load boot sequence.  Two 16-bit general purpose timer counters.  A 32-bit Real Time Clock (RTC) and compar- ator.  Dedicated LED flasher pin driven from the RTC with programmable duty ratio (multi- plexed with a GPIO pin).  Two synchronous serial interfaces for Micro- wire or SPI peripherals such as ADCs, one sup- porting both the master and slave mode and the other supporting only the master mode.  Full JTAG boundary scan and Embedded ICE support.  Two programmable pulse-width modulation interfaces.  An interface to one or two Cirrus Logic CL- PS6700 PC Card controller devices to support two PC Card slots.

 A low power 32.768 kHz oscillator. 256-ball PBGA or a 208-pin LQFP package. external 28-bit address bus and control signals.

3.1 CPU Core

Figure 2. EP7209 Block Diagram

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3.2 State Control

Real Time Clock and its associated logic powered.

3.2.1 Standby State

13 MHz mode, if the CLKENSL bit is set low, then

quired, be used to disable an external oscillator. ware will leave some interrupt sources enabled. Figure 3. State Diagram

transitioning back to the Operating State. State is to the Operating State. a low level on nPWRFL or BATOK. allow the clock to the CPU time to settle.

3.2.1.1 UART in Standby State

Table 7. Peripheral Status in Different Power Management States

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1) Permanently connect the RX pin to one of the active low external interrupt pins. 2) Ensure that on entry to the Standby State, the chosen interrupt source is not masked, and the UART is enabled. 3) Send a preamble that consists of one start bit, 8 bits of zero, and one stop bit. This will cause the EP7209 to wake and execute the enabled interrupt vector. The UART will automatically be re-enabled when the processor re-enters the Operating State, and the preamble will be received. Since the UART was not awake at the start of the pream- ble, the timing of the sample point will be off- center during the preamble byte. However, the next byte transmitted will be correctly aligned. Thus, the actual first real byte to be received by the UART will get captured correctly.

3.2.2 Idle State

If in the Operating State, the Idle State can be en- tered by writing to a special internal memory lo- cation (HALT) in the EP7209. If an interrupt occurs, the EP7209 will return immediately back to the Operating State and execute the next in- struction. The WAKEUP signal can not be used to exit the Idle State. It is only used to exit the Standby State. In the Idle State, the device functions just like it does when in the Operating State. However, the CPU clock is halted while it waits for an event such as a key press to generate an interrupt. The PLL (in 18.432–73.728 MHz mode) or the exter- nal 13 MHz clock source always remains active in the Idle State.

3.2.3 Keyboard Interrupt

For the case of the keyboard interrupt, the fol- lowing options are available and are selectable according to bits 1 and 3 of the SYSCON2 regis- ter (refer to the SYSCON2 Register Description for details).  If the KBWEN bit (SYSCON2 bit 3) is set low, then a keypress will cause a transition from a power saving state only if the key- board interrupt is non-masked (i.e., the inter- rupt mask register 2 (INTMR2 bit 0) is high).  When KBWEN is high, a keypress will cause the device to wake up regardless of the state of the interrupt mask register. This is called the “Keyboard Direct Wakeup’ mode. In this mode, the interrupt request may not get ser- viced. If the interrupt is masked (i.e., the in- terrupt mask register 2 (INTMR2 bit 0) is low), the processor simply starts re-execut- ing code from where it left off before it en- tered the power saving state. If the interrupt is non-masked, then the processor will ser- vice the interrupt.  When the KBD6 bit (SYSCON2 bit 1) is low, all 8 of Port A inputs are OR’ed together to produce the internal wakeup signal and key- board interrupt request. This is the default re- set state.  When the KBD6 bit (SYSCON2 bit 1) is high, only the lowest 6 bits of Port A are OR ’ed together to produce the internal wake- up signal and keyboard interrupt request. The two most significant bits of Port A are avail- able as GPIO when this bit is set high. In the case where KBWEN is low and the INTMR2 bit 0 is low, it will only be possible to wakeup the device by using the external WAKE- UP pin or another enabled interrupt source. The keyboard interrupt capability allows an OS to use either a polled or interrupt-driven keyboard rou- tine, or a combination of both.

NOTE: The keyboard interrupt is NOT deglitched.

3.3 Resets

There are three asynchronous resets to the EP7209: nPOR, nPWRFL and nURESET. If any of these are active, a system reset is generated internally. This will reset all internal registers in the EP7209 except the RTC data and match registers. These registers are only cleared by nPOR allowing the system time to be preserved through a user reset or power fail condition. Any reset will also reset the CPU and cause it to start execution at the reset vector when the EP7209 returns to the Operating State. Internal to the EP7209, three different signals are used to reset storage elements. These are nPOR, nSYSRES and nSTBY. nPOR is an external signal. nSTBY is equivalent to the external RUN signal. nPOR (Power On Reset, active low) is the highest priority reset signal. When active (low), it will reset all storage elements in the EP7209. nPOR active forces nSYSRES and nSTBY active. nPOR will only be active after the EP7209 is first powered up and not during any other resets. nPOR active will clear all flags in the status register except for the cold reset flag (CLDFLG) bit, which is set. nSYSRES (System Reset, active low) is generated internally to the EP7209 if nPOR, nPWRFL or nURESET are active. It is the second highest prior- ity reset signal, used to asynchronously reset most internal registers in the EP7209. nSYSRES active forces nSTBY and RUN low. nSYSRES is used to reset the EP7209 and force it into the Standby State with no co-operation from software. The CPU is also reset. The nSTBY and RUN signals are high when the EP7209 is in the Operating or Idle States and low when in the Standby State. The main system clock is valid when nSTBY is high. The nSTBY signal will disable any peripheral block that is clocked from the master clock source (i.e., everything ex- cept for the RTC). In general, a system reset will clear all registers and nSTBY will disable all pe- ripherals that require a main clock. The following peripherals are always disabled by a low level on nSTBY: two UARTs and IrDA SIR encoder, timer counters, telephony codec, and the two SSI inter- faces. In addition, when in the Standby State, the LCD controller and PWM drive are also disabled. When operating from an external 13 MHz oscilla- tor which has become disabled in the Standby State by using the CLKEN signal (i.e., with CLKENSL = 0), the oscillator must be stable within 0.125 sec from the rising edge of the CLKEN signal.

3.4 Clocks

There are two clocking modes for the EP7209. Ei- ther an external clock input can be used or the on- chip PLL. The clock source is selected by a strap- ping option on Port E, pin 2 (PE[2]). If PE[2] is high at the rising edge of nPOR (i.e., upon power- up), the external clock mode is selected. If PE[2] is low, then the on-chip PLL mode is selected. After power-up, PE[2] can be used as a GPIO. The EP7209 device contains several separate sec- tions of logic, each clocked according to its own clock frequency requirements. When the EP7209 is in external clock mode, the actual frequencies at the peripherals will be different than when in PLL mode. See each peripheral device section for more details. The section below describes the clocking for both the ARM720T and address/data bus.

3.4.1 On-Chip PLL

The ARM720T clock can be programmed to 18.432 MHz, 36.864 MHz, 49.152 MHz or

73.728 MHz with the PLL running at twice the

highest possible CPU clock frequency (147.456 MHz). The PLL uses an external 3.6864 MHz crystal. By chip default, the on-chip PLL is used and configured such that the ARM720T and address/data buses run at 18.432 MHz.

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When the clock frequency is selected to be

36 MHz, both the ARM720T and the address/data

buses are clocked at 36 MHz. When the clock fre- quency is selected higher than 36 MHz, only the ARM720T gets clocked at this higher speed. The address/data will be fixed at 36 MHz. The clock frequency used is selected by programming the CLKCTL[1:0] bits in the SYSCON3 register. The clock frequency selection does not effect the EPB. Therefore, all the peripheral clocks are fixed, re- gardless of the clock speed selected for the ARM720T. NOTE: After modifying the CLKCTL[1:0] bits, the next instruction should always be a ‘NOP ’.

3.4.1.1 Characteristics of the PLL Interface

When connecting a crystal to the on-chip PLL in- terface pins (i.e. MOSCIN and MOSCOUT), the crystal and circuit should conform to the following requirements:  The 3.6864 MHz frequency should be created by the crystals fundamental tone (i.e., it should be a fundamental mode crystal).  A start-up resistor is not necessary, since one is provided internally.  Start-up loading capacitors may be placed on each side of the external crystal and ground. Their value should be in the range of 10 pF. However, their values should be selected based upon the crystal specifications. The total sum of the capacitance of the traces between the EP7209 ’s clock pins, the capacitors, and the crystal leads should be subtracted from the crystal’s specifications when determining the values for the loading capacitors.  The crystal should have a maximum 100 ppm frequency drift over the chip’s operating tem- perature range. Alternatively, a digital clock source can be used to drive the MOSCIN pin of the EP7209. With this approach, the voltage levels of the clock source should match that of the Vdd supply for the EP7209 ’s pads (i.e. the supply voltage level used to drive all of the non-Vdd core pins on the EP7209). The output clock pin (i.e., MOSCOUT) should be left floating.

3.4.2 External Clock Input (13 MHz)

An external 13 MHz crystal oscillator can be used to drive all of the EP7209. When selected the ARM720T and the address/data buses both get clocked at 13 MHz. The fixed clock sources to the various peripherals will have different frequencies than in the PLL mode. In this configuration, the PLL will not be used at all. NOTE: When operating at 13 MHz, the CLKCTL[1:0] bits should not be changed from their default value of ‘00’.

Figure 4. CLKEN Timing Entering the Standby State

13 MHz

Figure 5. CLKEN Timing Entering the Standby State

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3.4.3 Dynamic Clock Switching When in the

3.5 Interrupt Controller

determines the order in which they are handled. input and five sources are mapped to the FIQ input. Table 9. All interrupts are level sensitive; that is, they must conform to the following sequence. ternal) asserts the appropriate interrupt. INTSR1 Interrupt Status Register 1). jump to the appropriate address. reading the UART RX register). of Interrupt’ Locations for more details. and allocation of interrupts in the EP7209. Table 8. Exception Priority Handling

Table 9. Interrupt Allocation in the First Interrupt Register Table 10. Interrupt Allocation in the Second Interrupt Register Table 11. Interrupt Allocation in the Third Interrupt Register

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3.5.1 Interrupt Latencies in Different

3.5.1.1 Operating State

The ARM720T processor checks for a low level on its FIQ and IRQ inputs at the end of each instruc- tion. The interrupt latency is therefore directly re- lated to the amount of time it takes to complete execution of the current instruction when the inter- rupt condition is detected. First, there is a one to two clock cycle synchronization penalty. For the case where the EP7209 is operating at 13 MHz with a 16-bit external memory system, and instruc- tion sequence stored in one wait state FLASH memory, the worst case interrupt latency is 251 clock cycles. This includes a delay for cache line fills for instruction prefetches, and a data abort occurring at the end of the LDM instruction, and the LDM being non-quad word aligned. In addi- tion, the worst-case interrupt latency assumes that LCD DMA cycles to support a panel size of 320 x 240 at 4 bits-per-pixel, 60 Hz refresh rate, is in progress. This would give a worst-case interrupt latency of about 19.3µs for the ARM720T processor operat- ing at 13 MHz in this system. For those interrupt inputs which have de-glitching, this figure is in- creased by the maximum time required to pass through the deglitcher, which is approximately 125 µs (2 cycle of the 16.384 kHz clock derived from the RTC oscillator). This would create an absolute worst case latency of approximately 141µs. If the ARM720T is run at 36 MHz or greater and/or 32 bit wide external memory, the 19.3µs value will be reduced. All the serial data transfer peripherals included in the EP7209 (except for the master-only SSI1) have local buffering to ensure a reasonable interrupt la- tency response requirement for the OS of 1 ms or less. This assumes that the maximum data rates de- scribed in this specification are complied with. If the OS cannot meet this requirement, there will be a risk of data over/underflow occurring. Idle State When leaving the Idle State as a result of an inter- rupt, the CPU clock is restarted after approximately two clock cycles. However, there is still potentially up to 20µsec latency as described in the first sec- tion above, unless the code is written to include at least two single cycle instructions immediately af- ter the write to the IDLE register (in which case the latency drops to a few microseconds). This is im- portant, as the Idle State can only be left because of a pending interrupt, which has to be synchronized by the processor before it can be serviced.

3.5.1.2 Standby State

In the Standby State, the latency will depend on whether the system clock is shut down and if the FASTWAKE bit in the SYSCON3 register is set. If the system is configured to run from the internal PLL clock, then the PLL will always be shut down when in the Standby State. In this case, if the FASTWAKE bit is cleared, then there will be a la- tency of between 0.125 sec to 0.25 sec. If the FASTWAKE bit is set, then there will be a latency of between 250µsec to 500µsec. If the system is running from the external clock (at 13 MHz), with the CLKENSL bit in SYSCON2 set to 0, then the latency will also be between 0.125 sec and 0.25 sec to allow an external oscillator to stabilize. In the case of a 13 MHz system where the clock is not dis- abled during the Standby State (CLKENSL = 1), then the latency will be the same as described in the Idle State section above. Whenever the EP7209 is in the Standby State, the external address and data buses are driven low. The RUN signal is used internally to force these buses to be driven low. This is done to prevent peripher- als that are power-down from draining current. Al- so, the internal peripheral’s signals get set to their Reset State.

3.6 EP7209 Boot ROM

ments to describe the stages of execution. ry device connected to CS[0] (normal boot mode). actually start the boot sequence. read back from address range 0x70000000. Including PLL/osc. settling time, approx. Table 12. External Interrupt Source Latencies Table 13. Chip Select Address Ranges After Boot From

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3.7 Memory and I/O Expansion Interface

nPOR to select the boot option. Table 14. Boot Options

3.8 CL-PS6700 PC Card Controller

nCS5 (once enabled by bits 5 and 6 of SYSCON2). onto the lower 16 bits of the main data bus. connected to the EP7209’s WRITE output pin. Table 15. CL-PS6700 Memory Map

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de-asserted, these port bits are available for GPIO. signal indicates if data is available.

00 Attribute

01 I/O

10 Common memory

11 CL-PS6700 registers

Table 16. Space Field Decoding

then allow the DMA address generator to gain con- trol of the bus, to allow LCD refreshes to continue. When the CL-PS6700 is ready with the data, it as- serts the PRDY signal. The EP7209 then arbitrates for the bus and, once the request is granted, the sus- pended read cycle is resumed. The EP7209 re- sumes the cycle by asserting the appropriate chip select, and data is transferred on the next two clocks if a word read (one clock if a byte read). There is no support within the EP7209 for detecting time-outs. The CL-PS6700 device must be pro- grammed to force the cycle to be completed (with invalid data for a read) and then generate an inter- rupt if a read or write access has timed out (i.e., RD_FAIL or WR_FAIL interrupt). The system software can then determine which access was not successfully completed by reading the status regis- ters within the CL-PS6700. The CL-PS6700 has support for DMA data trans- fers. However, DMA is supported only by software emulation because the DMA address generator built into the EP7209 is dedicated to the LCD con- troller interface. If DMA is enabled within the CL- PS6700, it will assert its PDREQ signal to make a DMA request. This can be connected to one of the EP7209 ’s external interrupts and be used to inter- rupt the CPU so that the software can service the DMA request under program control. Each of the CL-PS6700 devices can generate an in- terrupt PIRQ. The PIRQ output is open drain on the CL-PS6700 devices, so if there are two CL-PS6700 devices they may be wire OR’ed to the same inter- rupt which can be connected to one of the EP7209 ’s active low external interrupt sources. On the receipt of an interrupt, the CPU can read the in- terrupt status registers on the CL-PS6700 devices to determine the cause of the interrupt. All transactions are synchronized to the EXPCLK output from the EP7209 in 18.432 MHz mode or the external 13 MHz clock. The EXPCLK should be permanently enabled, by setting the EXCKEN bit in the SYSCON1 register, when the CL-PS6700 is used. The reason for this is that the PC Card in- terface and CL-PS6700 internal write buffers need to be clocked after the EP7209 has completed its bus cycles. A GPIO signal from the EP7209 can be connected to the PSLEEP pin of the CL-PS6700 devices to al- low them to be put into a power saving state before the EP7209 enters the Standby State. It is essential that the software monitor the appropriate status registers within the CL-PS6700s to ensure that there are no pending posted bus transactions before the Standby State is entered. Failure to do this will result in incomplete PC Card accesses.

3.9 Endianness

The EP7209 uses a Little Endian configuration for internal registers. However, it is possible to con- nect the device to a Big Endian external memory system. The Big-endian/Little-endian bit in the ARM720T control register sets whether the EP7209 treats words in memory as being stored in Big Endian or Little Endian format. Memory is viewed as a linear collection of bytes numbered up- wards from zero. Bytes 0 to 3 hold the first stored word, bytes 4 to 7 the second, and so on. In the Lit- tle Endian scheme, the lowest numbered byte in a word is considered to be the least significant byte of the word and the highest numbered byte is the most significant. Byte 0 of the memory system should be connected to data lines 7 through 0 (D[7:0]) in this scheme. In the Big Endian scheme the most significant byte of a word is stored at the lowest numbered byte, and the least significant byte is stored at the highest numbered byte. There- fore, Byte 0 of the memory system should be con- nected to data lines 31 through 24 (D[31:24]). Load and store are the only instructions affected by the Endianness. Tables 17 and 18 demonstrate the behavior of the EP7209 in Big and Little Endian mode, including the effect of performing non-aligned word access-

34 DS453PP2

es. The register definition section of this specifica- tion defines the behavior of the internal EP7209 registers in the Big Endian mode in more detail. For further information, refer to ARM Application Note 61, Big and Little Endian Byte Addressing.

3.10 Internal UARTs (Two) and SIR

The EP7209 contains two built-in UARTs that of- fers similar functionality to National Semiconduc- tor’s 16C550A device. Both UARTs can support bit rates of up to 115.2 kbits/s and include two 16- byte FIFOs: one for receive and one for transmit. One of the UARTs (UART1) supports the three modem control input signals CTS, DSR and DCD. The additional RI input, and RTS and DTR output modem control lines are not explicitly supported but can be implemented using GPIO ports in the EP7209. UART2 has only the RX and TX pins. UART operation and line speeds are controlled by the UBLCR1 (UART bit rate and line control). Three interrupts can be generated by UART1: RX, TX, and modem status interrupts. Only two can be generated by UART2: RX and TX. The RX inter- rupt is asserted when the RX FIFO becomes half full or if the FIFO is non-empty for longer than three character length times with no more charac- ters being received. The TX interrupt is asserted if the TX FIFO buffer reaches half empty. The mo- dem status interrupt for UART1 is generated if any of the modem status bits change state. Framing and parity errors are detected as each byte is received and pushed onto the RX FIFO. An overrun error generates an RX interrupt immediately. All error bits can be read from the 11-bit wide data register. The FIFOs can also be programmed to be one byte depth only (i.e., like a conventional 16450 UART with double buffering). The EP7209 also contains an IrDA (Infrared Data Association) SIR protocol encoder as a post-pro- cessing stage on the output of UART1. This encod- er can be optionally switched in to the TX and RX signals of UART1, so that these can be used to drive an infrared interface directly. If the SIR pro- tocol encoder is enabled, the UART TXD1 line is held in the passive state and transitions of the RXD1 line will have no effect. The IrDA output pin is LEDDRV, and the input from the photodiode is PHDIN. Modem status lines will cause an interrupt (which can be masked) irrespective of whether the SIR interface is being used. Both the UARTs operate in a similar manner to the industry standard 16C550A. When CTS is deas- serted on the UART, the UART does not stop shift- ing the data. It relies on software to take appropriate action in response to the interrupt gen- erated. Baud rates supported for both the UARTs are de- pendent on frequency of operation. When operat- ing from the internal PLL, the interface supports various baud rates from 115.2 kbps downwards. The master clock frequency is chosen so that most of the required data rates are obtainable exactly. When operating with a 13.0 MHz external clock source, the baud rates generated will have a slight error, which is less than or equal to 0.75%. The rates obtainable from the 13 MHz clock include 9.6 k, 19.2 k, 38 k, 58 k and 115.2 kbps. See UBRLCR1-2 UART1-2 Bit Rate and Line Control Registers for full details of the available bit rates in the 13 MHz mode.

3.11 Serial Interfaces

In addition to the two UARTs, the EP7209 offers the following serial interfaces shown in Table 19. The inputs/outputs of three of the serial interfaces (DAI, codec, and SSI2) are multiplexed onto a sin- gle set of external interface pins. If the DAISEL bit of SYSCON3 is low, then either SSI2 or the codec interface will be selected to connect to the external pins. When bit 0 of SYSCON2 (SERSEL) is high, then the codec is connected to the external pins, when low the master/slave SSI2 is connected to

operation to avoid external drive clashes). three multiplexed interfaces. unique internal pin names for clarity. Table 19. Serial Interface Options

63 SSICLK SSICLK = serial bit

65 SSITXFR SSKTXFR = TX

66 SSITXDA SSITXDA = TX data;

67 SSIRXDA SSIRXDA = RX data;

68 SSIRXFR SSIRXFR = RX

Table 20. Serial-Pin Assignments

36 DS453PP2

3.11.1 Codec Sound Interface

for the receive data, another for the transmit data). enable bits in the SYSCON1 register. 1 msec after one of the FIFOs is enabled. rupt occurs, the receive FIFO will be half full. transmit FIFO (See Figure 6). Figure 6. Codec Interrupt Timing

cycle, this data is loaded into a shift/load register. read from the CODR register.

3.11.2 Digital Audio Interface

audio connection to DAI compatible audio devices. ported by a number of manufacturers.

9.216 MHz or set via an externally supplied MCLK

Figure 7. DAI Interface

38 DS453PP2

3.11.2.1 DAI Operation

1 to these register bits (in the DAISR register). clock (SCLK), and the serial frame clock (LRCK).

3.11.2.2 DAI Frame Format

right side of an audio sample.

3.11.2.3 DAI Signals

sending playback data to a DAC. the positive going edge of SCLK.

128 SCLKs

Figure 8. EP7209 Rev C - Digital Audio Interface Timing – MSB/Left Justified format

3.11.3 ADC Interface — Master Mode Only

vices can be connected directly to the EP7209. ing nADCCS as a common RFS/TFS line. and the SSIBUSY bit is cleared. terfaces, such as for a touch-screen ADC interface.

3.11.4 Master/Slave SSI2 (Synchronous

ter/slave capability is provided by the EP7209.

13.0 MHz Operation ADCCLK

Table 21. ADC Interface Operation Frequencies

40 DS453PP2

than 1 msec, which is acceptable. rupts are called SS2RX and SS2TX, respectively. Register SS2DR is used to access the FIFOs. master mode, is shown in Figure 9. SYSCON1 register (i.e., the ADCKSEL bits). Figure 9. SSI2 Port Directions in Slave and Master Mode

(W/B) Data in Memory (as seen by the EP7209) Byte Lanes to Memory/Ports/Registers R0 Contents Big Endian Memory Little Endian Memory 7:0 15:8 23:16 31:24 7:0 15:8 23: 16 31: 24 Big Endian Little Endian Word + 0 (W) 11223344 44 33 22 11 44 33 22 11 11223344 11223344 Word + 1 (W) 11223344 44 33 22 11 44 33 22 11 44112233 44112233 Word + 2 (W) 11223344 44 33 22 11 44 33 22 11 33441122 33441122 Word + 3 (W) 11223344 44 33 22 11 44 33 22 11 22334411 22334411 Word + 0 (H) 11223344 44 33 22 11 44 33 22 11 00001122 00003344 Word + 1 (H) 11223344 44 33 22 11 44 33 22 11 22000011 44000033 Word + 2 (H) 11223344 44 33 22 11 44 33 22 11 00003344 00001122 Word + 3 (H) 11223344 44 33 22 11 44 33 22 11 44000033 22000011 Word + 0 (B) 11223344 dc dc dc 11 44 dc dc dc 00000011 00000044 Word + 1 (B) 11223344 dc dc 22 dc dc 33 dc dc 00000022 00000033 Word + 2 (B) 11223344 dc 33 dc dc dc dc 22 dc 00000033 00000022 Word + 3 (B) 11223344 44 dc dc dc dc dc dc 11 00000044 00000011 NOTE: dc = don’t care Table 17. Effect of Endianness on Read Operations

Contents

Byte Lanes to Memory/Ports/Registers Big Endian Memory Little Endian Memory 7:0 15:8 23:16 31:24 7:0 15:8 23:16 31:24 Word + 0 (W) 11223344 44 33 22 11 44 33 22 11 Word + 1 (W) 11223344 44 33 22 11 44 33 22 11 Word + 2 (W) 11223344 44 33 22 11 44 33 22 11 Word + 3 (W) 11223344 44 33 22 11 44 33 22 11 Word + 0 (H) 11223344 44 33 44 33 44 33 44 33 Word + 1 (H) 11223344 44 33 44 33 44 33 44 33 Word + 2 (H) 11223344 44 33 44 33 44 33 44 33 Word + 3 (H) 11223344 44 33 44 33 44 33 44 33 Word + 0 (B) 11223344 44 44 44 44 44 44 44 44 Word + 1 (B) 11223344 44 44 44 44 44 44 44 44 Word + 2 (B) 11223344 44 44 44 44 44 44 44 44 Word + 3 (B) 11223344 44 44 44 44 44 44 44 44 NOTE: Bold indicates active byte lane. Table 18. Effect of Endianness on Write Operations

42 DS453PP2

in the AC Characteristics section of this document.

3.11.4.1 Read Back of Residual Data

the next half-word to be clocked into the FIFO. valid and upper 16 bits are ignored).

3.11.4.2 Support for Asymmetric Traffic

data throughput than the TX path, or vice versa. Figure 10. Residual Byte Reading

mum possible clock frequency, assuming that the interrupt response of the target OS is sufficiently quick.

3.11.4.3 Continuous Data Transfer

Data bytes may be sent/received in a contiguous manner without interleaving clocks between bytes. The frame sync control line(s) are eight clocks apart and aligned with the clock representing bit D0 of the preceding byte (i.e., one bit in advance of the MSB).

3.11.4.4 Discontinuous Clock

In order to save power during the idle times, the clock line is put into a static low state. The master is responsible for putting the link into the Idle State. The Idle State will begin one clock, or more, after the last byte transferred and will resume at least one clock prior to the first frame sync assertion. To dis- able the clock, the TX section is turned off. In Master mode, the EP7209 does not support the discontinuous clock.

3.11.4.5 Error Conditions

RX FIFO overflows are detected and conveyed via a status bit in the SYSFLG2 register. This register should be accessed at periodic intervals by the ap- plication software. The status register should be read each time the RX FIFO interrupts are generat- ed. At this time the error condition (i.e., overrun flag) will indicate that an error has occurred but cannot convey which byte contains the error. Writ- ing to the SRXEOF register location clears the overrun flag. TX FIFO underflow condition is de- tected and conveyed via a bit in the SYSFLG2 reg- ister, which is accessed by the application software. A TX underflow error is cleared by writing data to be transmitted to the TX FIFO.

3.11.4.6 Clock Polarity

Clock polarity is fixed. TX data is presented on the bus on the rising edge of the clock. Data is latched into the receiving device on the falling edge of the clock. The TX pin is held in a tristate condition when not transmitting.

3.12 LCD Controller with Support for On-

The LCD controller provides all the necessary con- trol signals to interface directly to a single panel multiplexed LCD. The panel size is programmable and can be any width (line length) from 32 to 1024 pixels in 16 pixel increments. The total video frame buffer size is programmable up to 128 kbytes. This equates to a theoretical maximum pan- el size of 1024 x 256 pixels in 4-bits-per-pixel mode. The video frame buffer can be located in any portion of memory controlled by the chip selects. Its start address will be fixed at address 0x0000000 within each chip select. The start address of the LCD video frame buffer is defined in the FBAD- DR[3:0] register. These bits become the most sig- nificant nibble of the external address bus. The default start address is 0xC000 0000 (FBADDR = 0xC). A system built using the on-chip SRAM (OCSR), will then serve as the LCD video frame buffer and miscellaneous data store. The LCD vid- eo frame buffer start address should be set to 0x6 in this option. Programming of the register FBADDR is only permitted when the LCD is disabled (this is to avoid possible cycle corruption when changing the register contents while a LCD DMA cycle is in progress). There is no hardware protection to pre- vent this. It is necessary for the software to disable the LCD controller before reprogramming the FBADDR register. Full address decoding is pro- vided for the OCSR, up to the maximum video frame buffer size programmable into the LCDCON register. Beyond this, the address is wrapped around. The frame buffer start address must not be programmed to 0x4 or 0x5 if either CL-PS6700 in-

44 DS453PP2

terface is in use (PCMEN1 or PCMEN2 bits in the SYSCON2 register are enabled). FBADDR should never be programmed to 0x7 or 0x8, as these are the locations for the on-chip Boot ROM and inter- nal registers. The screen is mapped to the video frame buffer as one contiguous block where each horizontal line of pixels is mapped to a set of consecutive bytes or words in the video RAM. The video frame buffer can be accessed word wide as pixel 0 is mapped to the LSB in the buffer such that the pixels are ar- ranged in a Little Endian manner. The pixel bit rate, and hence the LCD refresh rate, can be programmed from 18.432 MHz to 576 kHz when operating in 18.432–73.728 MHz mode, or

13 MHz to 203 kHz when operating from a

13 MHz clock. The LCD controller is programmed by writing to the LCD control register (LCDCON). The LCDCON register should not be repro- grammed while the LCD controller is enabled. The LCD controller also contains two 32-bit palette registers, which allow any 4-, 2-, or 1-bit pixel val- ue to be mapped to any of the 15 gray scale values available. The required DMA bandwidth to support a ½ VGA panel displaying 4-bits-per-pixel data at an 80 Hz refresh rate is approximately 6.2 Mbytes/sec. Assuming the frame buffer is stored in a 32-bit wide the maximum theoretical bandwidth available is 86 Mbytes/sec at 36.864 MHz, or 29.7 Mbytes/sec at 13 MHz. The LCD controller uses a nine stage 32-bit wide FIFO to buffer display data. The LCD controller re- quests new data when there are five words remain- ing in the FIFO. This means that for a ½ VGA display at 4-bits-per-pixel and 80 Hz refresh rate, the maximum allowable DMA latency is approxi- mately 3.25µsec ((5 words x 8 bits/byte)/(640 x 240 x 4bpp x 80 Hz)) = 3.25µsec). The worst-case latency is the total number of cycles from when the DMA request appears to when the first DMA data word actually becomes available at the FIFO. DMA has the highest priority, so it will always hap- pen next in the system. The maximum number of cycles required is 36 from the point at which the DMA request occurs to the point at which the STM is complete, then another 6 cycles before the data actually arrives at the FIFO from the first DMA read. This creates a total of 42 cycles. Assuming the frame buffer is located in 32-bit wide, the worst case latency is almost exactly 3.2µs, with 13 MHz page mode cycles. With each cycle consuming ~77 ns (i.e., 1/1 MHz), the value of 3.2µs comes from 42 cycles x 77 ns/cycle = ~3.23µsec. If 16-bit wide, then the worst case latency will double. In this case, the maximum permissible display size will be halved, to approx. 320 x 240 pixels, assum- ing the same pixel depth and refresh rate has to be maintained. If the frame buffer is to be stored in static memory, then further calculations must be performed. If 18 MHz mode is selected, and 32-bit wide, then the worst case latency will be 2.26µsec (i.e., 42 cycles x 54 nsec/cycle). If 36 MHz mode is selected, and 32-bit wide, then the worst case laten- cy drops down to 1.49µs. This calculation is a little more complex for 36 MHz mode of operation. The total number of cycles = (12 x 4) + 7 = 55. Thus, 55 x 27 ns = ~1.49 µsec. Figure 11 shows the organization of the video map for all combinations of bits per pixel. The refresh rate is not affected by the number of bits per pixel; however the LCD controller fetches twice the data per refresh for 4-bits-per-pixel com- pared to 2-bits-per-pixel. The main reason for re- ducing the number of bits per pixel is to reduce the power consumption of the memory where the video frame buffer is mapped.

3.13 Timer Counters

EP7209. These are referred to as TC1 and TC2. the value written to the data register immediately.

4 Bits per pixel

2 Bits per pixel

1 Bit per pixel

Figure 11. Video Buffer Mapping

46 DS453PP2

(thus generating a 500 kHz frequency when using the 13 MHz source). This divider is enabled by set- ting the OSTB (Operating System Timing Bit) in the SYSCON2 register (bit 12). When this bit is set high to select the 500 kHz mode, the 500 kHz fre- quency is routed to the timers instead of the 541 kHz clock. This does not affect the frequencies derived for any of the other internal peripherals. The timer counters can operate in two modes: free running or pre-scale.

3.13.1 Free Running Mode

In the free running mode, the counter will wrap around to 0xFFFF when it under flows and it will continue to count down. Any value written to TC1 or TC2 will be decremented on the second edge of the selected clock.

3.13.2 Prescale Mode

In the prescale mode, the value written to TC1 or TC2 is automatically re-loaded when the counter under flows. Any value written to TC1 or TC2 will be decremented on the second edge of the selected clock. This mode can be used to produce a pro- grammable frequency to drive the buzzer (i.e., with TC1) or generate a periodic interrupt.

3.14 Real Time Clock

The EP7209 contains a 32-bit Real Time Clock (RTC). This can be written to and read from in the same way as the timer counters, but it is 32 bits wide. The RTC is always clocked at 1 Hz, generat- ed from the 32.768 kHz oscillator. It also contains a 32-bit output match register, this can be pro- grammed to generate an interrupt when the time in the RTC matches a specific time written to this reg- ister. The RTC can only be reset by an nPOR cold reset. Because the RTC data register is updated from the 1 Hz clock derived from the 32 kHz source, which is asynchronous to the main memory system clock, the data register should always be read twice to ensure a valid and stable reading. This also applies when reading back the RTCDIV field of the SYSCON1 register, which reflects the status of the six LSBs of the RTC counter.

3.14.1 Characteristics of the Real Time

When connecting a crystal to the RTC interface pins (i.e., RTCIN and RTCOUT), the crystal and circuit should conform to the following require- ments:  The 32.768 kHz frequency should be created by the crystals fundamental tone (i.e., it should be a fundamental mode crystal)  A start-up resistor is not necessary, since one is provided internally.  Start-up loading capacitors may be placed on each side of the external crystal and ground. Their value should be in the range of 10 pF. However, their values should be selected based upon the crystal specifications. The total sum of the capacitance of the traces between the EP7209 ’s clock pins, the capacitors, and the crystal leads should be subtracted from the crystal’s specifications when determining the values for the loading capacitors.  The crystal should have a maximum 5 ppm fre- quency drift over the chip’s operating tempera- ture range.  The voltage for the crystal must be 2.5 V + 0.2 V. Alternatively, a digital clock source can be used to drive the RTCIN pin of the EP7209. With this ap- proach, the voltage levels of the clock source should match that of the Vdd supply for the EP7209 ’s pads (i.e., the supply voltage level used to drive all of the non-Vdd core pins on the EP7209) (i.e., RTCOUT). The output clock pin should be left floating.

3.15 Dedicated LED Flasher

provide up to 4 mA of drive current.

3.16 Two PWM Interfaces

time) can be programmed from 1 in 16 to 15 in 16. drive ratio fields are zeroed.

3.17 Boundary Scan

lowed by the 4-bit scan-chain identification code. Table 22. Instructions Supported in JTAG Mode

48 DS453PP2

3.18 In-Circuit Emulation

3.18.1 Introduction

3.18.2 Functionality

supported by substitution of the actual code.

3.19 Maximum EP7209-Based System

Table 23. Device ID Register

Figure 12. A Maximum EP7209 Based System

50 DS453PP2

abort exception for access to this area. Table 24. EP7209 Memory Map in External Boot Mode

1. REGISTER DESCRIPTIONS

5.1 Internal Registers

Table 25 shows the Internal Registers of the EP7209 that are compatible with the CL-PS7111 when the CPU is configured to a Little Endian Memory System. Table 26 shows the differences that occur when the CPU is configured to a Big En- dian Memory System for byte-wide access to Ports A, B, and D. All the internal registers are inherently Little Endian (i.e., the least significant byte is at- tached to bits 7 to 0 of the data bus). Hence, the sys- tem Endianness affects the addresses required for byte accesses to the internal registers, resulting in a reversal of the byte address required to read/write a particular byte within a register. Note that the inter- nal registers have been split into two groups – the “old” and the “new ”. The old ones are the same as that used in CL-PS7111 and are there for compati- bility. The new registers are for accessing the addi- tional functionality of the DAI interface and the LED flasher. There is no effect on the register addresses for word accesses. Bits A[0:1] of the internal address bus are only decoded for Ports A, B, and D (to allow read/write to individual ports). For all other regis- ters, bits A[0:1] are not decoded, so that byte reads will return the whole register contents onto the EP7209 ’s internal bus, from where the appropriate byte (according to the Endianness) will be read by the CPU. To avoid the additional complexity, it is preferable to perform all internal register accesses as word operations, except for ports A to D which are explicitly designed to operate with byte access- es, as well as with word accesses. An 8 k segment of memory in the range 0x8000.0000 to 0x8000.3FFF is reserved for inter- nal use in the EP7209. Accesses in this range will not cause any external bus activity unless debug mode is enabled. Writes to bits that are not explic- itly defined in the internal area are legal and will have no effect. Reads from bits not explicitly de- fined in the internal area are legal but will read un- defined values. All the internal addresses should only be accessed as 32-bit words and are always on a word boundary, except for the PIO port registers, which can be accessed as bytes. Address bits in the range A[0:5] are not decoded (except for Ports A –D), this means each internal register is valid for 64 bytes (i.e., the SYSFLG1 register appears at lo- cations 0x8000.0140 to 0x8000.017C). There are some gaps in the register map for backward com- patibility reasons, but registers located next to a gap are still only decoded for 64 bytes. The GPIO port registers are byte-wide and can be accessed as a word but not as a half-word. These registers additionally decode A[0:1]. All addresses are in hexadecimal notation. NOTE: All byte-wide registers should be accessed as words (except Port A to Port D registers, which are designed to work in both word and byte modes). All registers bit alignment starts from the LSB of the register (i.e., they are all right shift justified). The registers which interact with the 32 kHz clock or which could change during read- back (i.e., RTC data registers, SYSFLG1 register (lower 6-bits only), the TC1D and TC2D data registers, port registers, and interrupt status registers), should be read twice and compared to ensure that a stable value has been read back. All internal registers in the EP7209 are reset (cleared to zero) by a system reset (i.e., nPOR, nRESET, or nPWRFL signals becoming active), and the Real Time Clock data register (RTCDR) and match register (RTCMR), which are only reset by nPOR becoming active. This ensures that the system time preserved through a user reset or pow- er fail condition. In the following register descrip- tions, Little Endian is assumed.

52 DS453PP2

Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode)

Table 25. EP7209 Internal Registers Compatible with CL-PS7111 (Little Endian Mode)(cont.)

54 DS453PP2

Table 26. EP7209 Internal Registers (Big Endian Mode)

5.1.1 PADR Port A Data Register

A, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.2 PBDR Port B Data Register

B, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.3 PDDR Port D Data Register

D, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.4 PADDR Port A Data Direction Register

clearing a bit sets the pin to input. All bits are cleared by a system reset.

5.1.5 PBDDR Port B Data Direction Register

clearing a bit sets the pin to input. All bits are cleared by a system reset.

5.1.6 PDDDR Port D Data Direction Register

ADDRESS: 0x8000.0043 Bits cleared in this 8-bit read/write register will select the corresponding pin in Port D to become an output, setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output by default.

5.1.7 PEDR Port E Data Register

ADDRESS: 0x8000.0080 Values written to this 3-bit read/write register will be output on Port E pins if the corresponding data direction bits are set high (port output). Values read from this register reflect the external state of Port E, not necessarily the value written to it. All bits are cleared by a system reset.

5.1.8 PEDDR Port E Data Direction Register

ADDRESS: 0x8000.00C0 Bits set in this 3-bit read/write register will select the corresponding pin in Port E to become an output, clearing bit sets the pin to input. All bits are cleared by a system reset so that Port E is input by default.

56 DS453PP2

5.2 SYSTEM Control Registers

5.2.1 SYSCON1 The System Control Register 1

system reset. The bits in the system control register SYSCON1 are defined in Table 27. ing it sets the clock source to 2 kHz. ing it sets the clock source to 2 kHz. 8 UART1EN : Internal UART enable bit. Setting this bit enables the internal UART. Table 27. SYSCON1

0 All driven high

1 All driven low

8 Column 0 only driven high all others high impedance

9 Column 1 only driven high all others high impedance

10 Column 2 only driven high all others high impedance

11 Column 3 only driven high all others high impedance

12 Column 4 only driven high all others high impedance

13 Column 5 only driven high all others high impedance

14 Column 6 only driven high all others high impedance

15 Column 7 only driven high all others high impedance

12 LCDEN : LCD enable bit. Setting this bit enables the LCD controller. transmission to an external codec device. reception from an external codec device. mode. The frequencies obtained in 13.0 MHz mode can be found in Table 21. Table 27. SYSCON1 (cont.)

58 DS453PP2

wait state generation enabled only. 19 WAKEDIS : Setting this bit disables waking up from the Standby State, via the wakeup input. but will probably reduce transmission distances.

5.2.2 SYSCON2 System Control Register 2

SYSCON2 register is reset to all 0s on power up. pins. See the table below for the selection options. bit, and thus the external pins are connected to the DAI interface.

1 KBD6 : The state of this bit determines how many of the Port A inputs are OR’ed together to cre-

keyboard. It is assumed that the keyboard row lines are connected into Port A.

3 KBWEN : When the KBWEN bit is high, the EP7209 will awaken from a power saving state into

power) in master mode, if the receive side is low. CL-PS6700 interface protocol. CL-PS6700 interface protocol. Table 28. SYSCON2

0 Master/slave SSI2

1 Codec

60 DS453PP2

interface will be in a power saving state. 8 UART2EN : Internal UART2 enable bit. Setting this bit enables the internal UART2. tion. This bit also controls the directionality of the interface pins. 12 OSTB : This bit (operating system timing bit) is for use only with the 13 MHz clock source mode. this frequency is not clocked when this bit is set low. 13 CLKENSL : CLKEN select. When low, the CLKEN signal will be output on the RUN/CLKEN pin. When high, the RUN signal will be output on RUN/CLKEN.

14 BUZFREQ : The BUZFREQ bit is used to select which hardware source will be used as the

the BZTOG bits (SYSCON2) for more details. Table 28. SYSCON2 (cont.)

5.2.3 SYSCON3 System Control Register 3

EP7209. The bits of this third system control register are defined in Table 29.

0 ADCCON : Determines whether the ADC Configuration Extension field SYNCIO(31:16) is to be

value in the ADC Configuration Byte (SYNCIO(6:0)) selects the length of the data (8-bit to 16-bit). 1:2 CLKCTL(1:0): Determines the frequency of operation of the processor and Wait State scaling. The table below lists the available options. NOTE: To determine the number of wait states programmed refer to Table 36 and Table 37.

4 ADCCKNSEN : When set, configuration data is transmitted on ADCOUT at the rising edge of the

5:7 VERSN[0:2]: Additional read-only version bits — will read ‘000’.

8 FASTWAKE : When set, the device will wake from the Standby State within one to two cycles of a

to two cycles of the 8 Hz clock. 9 DAIEN : This bit enables the Digital Audio Interface when set (i.e., when DAIEN is high). Table 29. SYSCON3

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5.2.4 SYSFLG1 — The System Status Flags Register

mation. The bits in the system status flags register SYSFLG1 are defined in Table 30.

1 DCDET : This bit will be set if a non-battery operated power supply is powering the system (it is

the inverted state of the nEXTPWR input pin). 2 WUDR : Wake up direct read. This bit reflects the non-latched state of the wakeup signal.

3 WUON : This bit will be set if the system has been brought out of the Standby State by a rising

8 CTS : This bit reflects the current status of the clear to send (CTS) modem control input to

9 DSR : This bit reflects the current status of the data set ready (DSR) modem control input to

10 DCD : This bit reflects the current status of the data carrier detect (DCD) modem control input to

guaranteed to remain set until the complete byte has been sent, including all stop bits. nBATCHG input, it is cleared by writing to the STFCLR location. nURESET input low. It is cleared by writing to the STFCLR location. pin, it is cleared by writing to the STFCLR location. Table 30. SYSFLG

it is cleared by writing to the STFCLR location. to 1 Hz for the RTC. The MSB is the 32 Hz output, the LSB is the 1 Hz output. 24 CRXFE : Codec RX FIFO empty bit. This will be set if the 16-byte codec RX FIFO is empty. 25 CTXFF : Codec TX FIFO full bit. This will be set if the 16-byte codec TX FIFO is full. or out of the synchronous serial interface, when clear data is valid to read. 27:28 BOOTBIT0 –1: These bits indicate the default (power-on reset) bus width of the ROM interface. of these bits reflect the state of Port E[0:1] during power on reset, as shown in the table below. 29 ID: Will always read ‘1’ for the EP7209 device. Table 30. SYSFLG (cont.)

11 R e s e r v e d

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5.2.5 SYSFLG2 System Status Register 2

PS7111. The bits of the second system status register are defined in Table 31.

1. Empty the FIFO (remove data from FIFO) and then write to SRXEOF location.
2. Disable the RX (affects of disabling the RX will not take place until a full SSI2 clock

1 RESVAL : Master/slave SSI2 RX FIFO residual byte present, cleared by popping the residual

byte into the SSI2 RX FIFO or by a new RX frame sync pulse.

2 RESFRM : Master/slave SSI2 RX FIFO residual byte present, cleared only by a new RX frame

will get cleared when data is removed from the FIFO or the EP7209 is reset. mit when TX FIFO is empty. This will be cleared when FIFO gets loaded with data. chip is operating from an external 13 MHz clock. guaranteed to remain set until the complete byte has been sent, including all stop bits. Table 31. SYSFLG2

5.3 Interrupt Registers

5.3.1 INTSR1 Interrupt Status Register 1

is active. The interrupt assignment is given in Table 32. and is mapped to the FIQ input on the ARM720T processor. NOTE: BLINT is disabled during the Standby State. NOTE: WEINT is disabled during the Standby State. Watch dog timer tick rate is 64 Hz (in 13 MHz and 73.728–18.432 MHz modes). Watchdog timer is turned off during the Standby State.

4 CSINT: Codec sound interrupt, generated when the data FIFO has reached half full or empty

(depending on the interface direction). It is cleared by writing to the COEOI location. is cleared by returning nEINT1 to the passive (high) state. is cleared by returning nEINT2 to the passive (high) state. is cleared by returning EINT3 to the passive (low) state. Table 32. INTSR1

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writing to the TC1EOI location. writing to the TC2EOI location. NOTE: TINT is disabled/turned off during the Standby State. data in the UART1 TX data holding register and be cleared by writing to the UART1 data register. and is cleared by filling the FIFO to at least half full. three character time out period. It is cleared by reading all the data from the RX FIFO. ing the ADC data from the SYNCIO register. Table 32. INTSR1(cont.)

5.3.2 INTMR1 Interrupt Mask Register 1

ADDRESS: 0x8000.0280 This interrupt mask register is a 32-bit read/write register, which is used to selectively enable any of the first 16 interrupt sources within the EP7209. The four shaded interrupts all generate a fast interrupt request to the ARM720T processor (FIQ), this will cause a jump to processor virtual address 0000.0001C. All other interrupts will generate a standard interrupt request (IRQ), this will cause a jump to processor virtual address 0000.00018. Setting the appropriate bit in this register enables the corresponding interrupt. All bits are cleared by a system reset. Please refer to INTSR1 Interrupt Sta- tus Register 1 for individual bit details.

5.3.3 INTSR2 Interrupt Status Register 2

ADDRESS: 0x8000.1240 This register is an extension of INTSR1, containing status bits for backward compatibility with CL- PS7111. The interrupt status register also reflects the current state of the new interrupt sources within the EP7209. Each bit is set if the appropriate interrupt is active. The interrupt assignment is given in Table 33. 15 14 13 12 11 10 9 8 SSEOTI UMSINT URXINT UTXINT TINT RTCMI TC2OI TC1OI 7 6543210 EINT3 EINT2 EINT1 CSINT MCINT WEINT BLINT EXTFIQ 15:14 13 12 11:3 2 1 0 Reserved URXINT2 UTXINT2 Reserved SS2TX SS2RX KBDINT Bit Description 0 KBDINT : Keyboard interrupt. This interrupt is generated whenever a key is pressed, from the log- ical OR of the first 6 or all 8 of the Port A inputs (depending on the state of the KBD6 bit in the SYSCON2 register. The interrupt request is latched, and can be de-asserted by writing to the KBDEOI location. NOTE: KBDINT is not deglitched. 1 SS2RX : Synchronous serial interface 2 receive FIFO half or greater full interrupt. This is gener- ated when RX FIFO contains 8 or more half-words. This interrupt is cleared only when the RX FIFO is emptied or one SSI2 clock after RX is disabled. 2 SS2TX : Synchronous serial interface 2 transmit FIFO less than half empty interrupt. This is gen- erated when TX FIFO contains fewer than 8 byte pairs. This interrupt gets cleared by loading the FIFO with more data or disabling the TX. One synchronization clock required when disabling the TX side before it takes effect. 12 UTXINT2 : UART2 transmit FIFO half empty interrupt. The function of this interrupt source depends on whether the UART2 FIFO is enabled. If the FIFO is disabled (FIFOEN bit is clear in the UART2 bit rate and line control register), this interrupt will be active when there is no data in the UART2 TX data holding register and be cleared by writing to the UART2 data register. If the FIFO is enabled this interrupt will be active when the UART2 TX FIFO is half or more empty, and is cleared by filling the FIFO to at least half full.

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5.3.4 INTMR2 Interrupt Mask Register 2

with the CL-PS7111. Please refer to INTSR2 for individual bit details.

5.3.5 INTSR3 Interrupt Status Register 3

Table 34. 5.3.6 INTMR3 Interrupt Mask Register 3 tures of the EP7209. Please refer to INTSR3 for individual bit details. there is valid RX data in the UART2 RX data holding register and be cleared by reading this data. out period. It is cleared by reading all the data from the RX FIFO. Table 34. INTSR3 Table 33. INSTR2(cont.)

5.4 Memory Configuration Registers

5.4.1 MEMCFG1 Memory Configuration Register 1

ADDRESS: 0x8000.0180 Expansion and ROM space is selected by one of eight chip selects. One of the chip selects (nCS[6]) is used internally for the on-chip SRAM, and the configuration is hardwired for 32-bit wide, minimum wait state operation. nCS[7] is used for the on-chip Boot ROM and the configuration field is hardwired for 8-bit wide, minimum wait state operation. Data written to the configuration fields for either nCS[6] or nCS7 will be ignored. Two of the chip selects (nCS[4:5]) can be used to access two CL-PS6700 PC CARD controller devices, and when either of these interfaces is enabled, the configuration field for the appropriate chip select in the MEMCFG2 register is ignored. When the PC CARD1 or 2 control bit in the SYSCON2 register is disabled, then nCS[4] and nCS[5] are active as normal and can be programmed using the relevant fields of MEMCFG2, as for the other four chip selects. All of the six external chip selects are active for 256 Mbytes and the timing and bus transfer width can be pro- grammed individually. This is accomplished by programming the six byte-wide fields contained in two 32-bit registers, MEMCFG1 and MEMCFG2. All bits in these registers are cleared by a system reset (except for the nCS[6] and nCS[7] configurations). The Memory Configuration Register 1 is a 32-bit read/write register which sets the configuration of the four expansion and ROM selects nCS[0:3]. Each select is configured with a 1-byte field starting with expansion select 0.

5.4.2 MEMCFG2 Memory Configuration Register 2

ADDRESS: 0x8000.01C0 The Memory Configuration Register 2 is a 32-bit read/write register which sets the configuration of the two expansion and ROM selects nCS[4:5]. Each select is configured with a 1-byte field starting with expansion select 4. Each of the six non-reserved byte fields for chip select configuration in the memory configuration reg- isters are identical and define the number of wait states, the bus width, enable EXPCLK output during accesses and enable sequential mode access. This byte field is defined below. This arrangement ap- plies to nCS[0:3], and nCS[4:5] when the PC CARD enable bits in the SYSCON2 register are not set. The state of these bits is ignored for the Boot ROM and local SRAM fields in the MEMCFG2 register. Table 35 defines the bus width field. Note that the effect of this field is dependent on the two BOOTBIT bits that can be read in the SYSFLG1 register. All bits in the memory configuration register are cleared by a system reset and the state of the BOOTBIT bits are determined by Port E bits 0 and 1 on the EP7209 during power-on reset. The state of PE[1] and PE[0] determine whether the EP7209 is going to boot from either 32-bit wide, 16-bit wide or 8-bit wide ROMs. Table 36 shows the values for the wait states for random and sequential wait states at 13 and 18 MHz bus rates. At 36 MHz bus rate, the encoding becomes more complex. Table 37 preserves compati- bility with the previous devices, while allowing the previously unused bit combinations to specify more variations of random and sequential wait states. 31:24 23:16 15:8 7:0 nCS[3] configuration nCS[2] configuration nCS[1] configuration nCS[0] configuration 31:24 23:16 15:8 7:0 (Boot ROM) (Local SRAM) nCS[5] configuration nCS[4] configuration 76 5 : 2 1 : 0 CLKENB SQAEN Wait States Field Bus width

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Table 35. Values of the Bus Width Field Table 36. Values of the Wait State Field at 13 MHz and 18 MHz Table 37. Values of the Wait State Field at 36 MHz

See the AC Electrical Specification section for more detail on bus timing. a configuration field in MEMCFG2. It is automatically set up for 32-bit wide, no wait state accesses. For the Boot ROM, it is automatically set up for 8-bit, no wait state accesses. Chip selects nCS[4] and nCS[5] are used to select two CL-PS6700 PC CARD controller devices. MEMCFG2 register have no meaning when these interfaces are enabled.

5.5 Timer/Counter Registers

5.5.1 TC1D Timer Counter 1 Data Register

value written will be decremented on the next rising edge of the clock.

5.5.2 TC2D Timer Counter 2 Data Register

value written will be decremented on the next rising edge of the clock.

5.5.3 RTCDR Real Time Clock Data Register

ister is reset only by nPOR.

5.5.4 RTCMR Real Time Clock Match Register

match it will assert the RTCMI interrupt source. This register is reset only by nPOR. that the chip select is de-asserted periodically between accesses for easier debug. set to zero when operating in 13 MHz mode. Table 38. MEMCFG

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5.6 LEDFLSH Register

LED will be off when disabled. Table 39. LED Flash Rates Table 40. LED Duty Ratio

5.7 PMPCON Pump Control Register

the PWM is disabled. The same applies to FB[1]. They are read upon power-up. master clock, or 101.6 kHz when operating from the 13 MHz source. determine which of the above fields to use. Table 41. PMPCON Table 42. Sense of PWM control lines

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5.8 CODR — The CODEC Interface Data Register

8 kBytes/s, giving an interrupt rate of 1 kHz.

5.9 UART Registers

5.9.1 UARTDR1 –2 UART1 –2 Data Registers

Data written to these registers is pushed onto the 16-byte data TX holding FIFO if the FIFO is enabled. If not it is stored in a one byte holding register. This write will initiate transmission from the UART. pushed onto the RX FIFO. The RX FIFO is 10-bits wide by 16 deep. NOTE: These registers should be accessed as words. bit is cleared by reading the UARTDR register. Table 43. UARTDR1-2 UART1-2

5.9.2 UBRLCR1 –2 UART1 –2 Bit Rate and Line Control Registers

sets the bit rate and mode of operation for the internal UARTs. 12 BREAK : Setting this bit will drive the TX output active (high) to generate a break. clearing it sets odd parity. This bit has no effect if the PRTEN bit is clear. data byte, clearing it will transmit one stop bit after each data byte. Table 44. UBRLCR1-2 UART1-2

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17:18 WRDLEN : This two bit field selects the word length according to the table below. Table 44. UBRLCR1-2 UART1-2 (cont.)

5.10 LCD Registers

5.10.1 LCDCON — The LCD Control Register

more information on video buffer mapping. The LCDCON register should only be reprogrammed when the LCD controller is disabled. The minimum value allowed is 3 for this bit field. The minimum value that can be programmed into this register is a 1 (i.e., 0 is not a legal value). Rounding 2.428 down to the nearest whole number equals 2. Which gives an actual refresh frequency of 12.288E6/(640x240) = 80 Hz. Table 45. LCDCON

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5.10.2 PALLSW Least Significant Word — LCD Palette Register

5.10.3 PALMSW Most Significant Word — LCD Palette Register

scale values are shown in Table 46. Note that colors 8–15 are the inverse of colors 7–0 respectively.

1. The steps in the gray scale are non-linear, but have been chosen to give a close approximation

close to 50% gray (See PALLSW description). mally 13, but must not be exactly divisible by the number of lines in the display. is cleared each bit in the video map directly corresponds to a pixel in the display. setting it sets it to 4 bits per pixel (16 gray scales). This bit has no effect if GSEN is cleared. Table 45. LCDCON (cont.)

5.10.4 FBADDR LCD Frame Buffer Start Address

when the LCD is disabled (i.e., setting the LCDEN bit within SYSCON2 low).

5.11 SSI Register

5.11.1 SYNCIO Synchronous Serial ADC Interface Data Register

Table 46. Gray Scale Value to Color Mapping

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able number of bits are sent from SYNCIO[16:31] as determined by the ADC Configuration Length. edge, if ADCCKNSEN in SYSCON3 is set) and the result is shifted in to the SYNCIO read register. SYNCIO register is the last sixteen bits shifted out of the ADC. Configuration Extension section of the SYNCIO register.

5.12 STFCLR Clear all ‘Start Up Reason’ flags location

(i.e., a new battery was installed). Any value may be written to this location. ADC Configuration Extension field for sending to the ADC. In extended mode, AD7811/12, this is 23 = (10 for configuration byte + 3 null + 10 bits result).

13 SMCKEN : Setting this bit will enable a free running sample clock at twice the programmed ADC

clock frequency to be output on the SMPLCK pin. Table 47. SYNCIO

5.13 ‘End Of Interrupt’ Locations These locations are written to after the appropriate interrupt has been serviced. The write is per- formed to clear the interrupt status bit, so that other interrupts can be serviced. Any value may be writ- ten to these locations.

5.13.1 BLEOI Battery Low End of Interrupt

ADDRESS: 0x8000.0600 A write to this location will clear the interrupt generated by a low battery (falling edge of BATOK with nEXTPWR high).

5.13.2 MCEOI Media Changed End of Interrupt

ADDRESS: 0x8000.0640 A write to this location will clear the interrupt generated by a falling edge of the nMEDCHG input pin.

5.13.3 TEOI Tick End of Interrupt Location

ADDRESS: 0x8000.0680 A write to this location will clear the current pending tick interrupt and tick watch dog interrupt.

5.13.4 TC1EOI TC1 End of Interrupt Location

ADDRESS: 0x8000.06C0 A write to this location will clear the under flow interrupt generated by TC1.

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5.13.5 TC2EOI TC2 End of Interrupt Location

ADDRESS: 0x8000.0700 A write to this location will clear the under flow interrupt generated by TC2.

5.13.6 RTCEOI RTC Match End of Interrupt

ADDRESS: 0x8000.0740 A write to this location will clear the RTC match interrupt

5.13.7 UMSEOI UART1 Modem Status Changed End of Interrupt

ADDRESS: 0x8000.0780 A write to this location will clear the modem status changed interrupt.

5.13.8 COEOI Codec End of Interrupt Location

ADDRESS: 0x8000.07C0 A write to this location clears the sound interrupt (CSINT).

5.13.9 KBDEOI Keyboard End of Interrupt Location

ADDRESS: 0x8000.1700 A write to this location clears the KBDINT keyboard interrupt.

5.13.10 SRXEOF End of Interrupt Location

ADDRESS: 0x8000.1600 A write to this location clears the SSI2 RX FIFO overflow status bit.

5.14 State Control Registers

5.14.1 STDBY Enter the Standby State Location

ADDRESS: 0x8000.0840 A write to this location will put the system into the Standby State by halting the main oscillator. A write to this location while there is an active interrupt will have no effect. NOTES: 1) Before entering the Standby State, the LCD Controller should be disabled. The LCD controller should be enabled on exit from the Standby State. 2) If the EP7209 is attempting to get into the Standby State when there is a pending interrupt request, it will not enter into the low power mode. The instruction will get executed, but the processor will ignore the command.

5.14.2 HALT Enter the Idle State Location

ADDRESS: 0x8000.0800 A write to this location will put the system into the Idle State by halting the clock to the processor until an interrupt is generated. A write to this location while there is an active interrupt will have no effect.

5.15 SS2 Registers

5.15.1 SS2DR Synchronous Serial Interface 2 Data Register

ADDRESS: 0x8000.1500 This is the 16-bit wide data register for the full-duplex master/slave SSI2 synchronous serial interface. Writing data to this register will initiate a transfer. Writes need to be word writes and the bottom 16 bits are transferred to the TX FIFO. Reads will be 32 bits as well; the low 16 bits contain RX data and the upper 16-bits should be ignored. Although the interface is byte-oriented, data is written in two bytes at a time to allow higher bandwidth transfer. It is up to the software to assemble the bytes for the data stream in an appropriate manner. All reads/writes to this register must be word reads/writes.

5.15.2 SS2POP Synchronous Serial Interface 2 Pop Residual Byte

ADDRESS: 0x8000.16C0 This is a write-only location which will cause the contents of the RX shift register to be popped into the RX FIFO, thus enabling a residual byte to be read. The data value written to this register is ig- nored. This location should be used in conjunction with the RESVAL and RESFRM bits in the SYSFLG2 register.

5.16 DAI Register Definitions

There are five registers within the DAI Interface, one control register, three data registers, and one status register. The control register is used to mask or unmask interrupt requests to service the DAI’s FIFOs, and to select whether an on-chip or off-chip clock is used to drive the bit rate, and to en- able/disable operation. The first pair of data register addresses the top of the right channel transmit FIFO and the bottom of the right channel receive FIFO. A read accesses the receive FIFOs, and a write the transmit FIFOs. Note that these are four physically separate FIFOs to allow full-duplex trans- mission. The status register contains bits which signal FIFO overrun and underrun errors and transmit and receive FIFO service requests. Each of these status conditions signal an interrupt request to the interrupt controller. The status register also flags when the transmit FIFOs are not full when the re- ceive FIFOs are not empty.

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5.16.1 DAI Control Register

7 Reserved

15 Reserved

the SSI2/codec/DAI pin mulitiplexing logic to assign I/O pins 60-64 to another block. the above mentioned DAI ports are connected to I/O pins 60–64. 17 ECS: External Clock Select selects external MCLK when = 1.

18 Reserved

sent to interrupt controller). sent to interrupt controller). sent to interrupt controller). sent to interrupt controller). Table 48. DAI Control Register

5.16.1.1 DAI Enable (DAIEN)

The DAI enable (DAIEN) bit is used to enable and disable all DAI operation. to zero to ensure the DAI timing is disabled following a reset of the device. fore re-enabling the DAI interface.

5.16.1.2 DAI Interrupt Generation

DAI interface. This interrupt is the wired OR of all eight interrupts (after masking where appropriate). ing the DAI interrupt in the interrupt controller register.

5.16.1.3 Left Channel Transmit FIFO Interrupt Mask (LCTM)

clear LCTS; it only blocks the generation of the interrupt request.

5.16.1.4 Left Channel Receive FIFO Interrupt Mask (LARM)

clear LCRS, it only blocks the generation of the interrupt request. SDOUT, SCLK, and LRCK pins is given to the PPC unit. Table 48. DAI Control Register(cont.)

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5.16.1.5 Right Channel Transmit FIFO Interrupt Mask (RCTM)

The right channel transmit FIFO interrupt mask (RCTM) bit is used to mask or enable the right channel transmit FIFO service request interrupt. When RCTM = 0, the interrupt is masked and the state of the right channel transmit FIFO service request (RCTS) bit within the DAI status register is ignored by the interrupt controller. When RCTM = 1, the interrupt is enabled and whenever RCTS is set (one) an in- terrupt request is made to the interrupt controller. Note that programming RCTM = 0 does not affect the current state of RCTS or the right channel transmit FIFO logic’s ability to set and clear RCTS; it only blocks the generation of the interrupt request.

5.16.1.6 Right Channel Receive FIFO Interrupt Mask (RCRM)

The right channel receive FIFO interrupt mask (RCRM) bit is used to mask or enable the right channel receive FIFO service request interrupt. When RCRM = 0, the interrupt is masked and the state of the right channel receive FIFO service request (RCRS) bit within the DAI status register is ignored by the interrupt controller. When RCRM = 1, the interrupt is enabled and whenever RCRS is set (one) an interrupt request is made to the interrupt controller. Note that programming RCRM = 0 does not affect the current state of RCRS or the right channel receive FIFO logic’s ability to set and clear RCRS; it only blocks the generation of the interrupt request.

5.16.1.7 Loop Back Mode (LBM)

The loop back mode (LBM) bit is used to enable and disable the ability of the DAI’s transmit and re- ceive logic to communicate. When LBM = 0, the DAI operates normally. The transmit and receive data paths are independent and communicate via their respective pins. When LBM = 1, the output of the serial shifter (MSB) is directly connected to the input of the serial shifter (LSB) internally and control of the SDOUT, SDIN, SCLK, and LRCK pins are given to the peripheral pin control (PPC) unit. Table 48 shows the bit locations corresponding to the ten different control bit fields within the DAI con- trol register. Note that the DAIEN bit is the only control bit which is reset to a known state to ensure the DAI is disabled following a reset of the device. The reset state of all other control bits is unknown and must be initialized before enabling the DAI. Writes to reserved bits are ignored and reads return zeros.

5.16.2 DAI Data Registers

5.16.2.1 DAI Data Register 0

all remaining values within the FIFO automatically transfer down one location. rially shifted out onto the SDOUT pin. bits are ignored and reads return zeros. Table 49. DAI Data Register 0

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5.16.2.2 DAI Data Register 1

maining values within the FIFO automatically transfer down one location. then serially shifted out onto the SDOUT pin.

5.16.2.3 DAI Data Register 2

(FIFO) is set in the DAI status register before writing another value to this register. Table 50. DAI Data Register 1

5.16.3 DAI Status Register

ADDRESS: 0x8000.2100 The DAI Status Register (DAISR) contains bits which signal FIFO overrun and underrun errors and FIFO service requests. Each of these conditions signal an interrupt request to the interrupt controller. The status register also flags when transmit FIFOs are not full, when the receive FIFOs are not empty, when a FIFO operation is complete, and when the right channel or left channel portion of the codec is enabled (no interrupt generated). Bits which cause an interrupt signal the interrupt request as long as the bit is set. Once the bit is cleared, the interrupt is cleared. Read/write bits are called status bits, read-only bits are called flags. Status bits are referred to as “sticky” (once set by hardware, they must be cleared by software). Writ- ing a one to a sticky status bit clears it, writing a zero has no effect. Read-only flags are set and cleared by hardware, and writes have no effect. Additionally some bits which cause interrupts have corresponding mask bits in the control register and are indicated in the section headings below. Note that the user has the ability to mask all DAI interrupts by clearing the DAI bit within the interrupt con- troller mask register INTMR3.

5.16.3.1 Right Channel Transmit FIFO Service Request Flag (RCTS)

The right channel transmit FIFO service request flag (RCTS) is a read-only bit which is set when the right channel transmit FIFO is nearly empty and requires service to prevent an underrun. RCTS is set any time the right channel transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it has five or more entries of valid data. When the RCTS bit is set, an interrupt request is made unless the right channel transmit FIFO interrupt request mask (RCTM) bit is cleared. After the CPU fills the FIFO such that four or more locations are filled within the right channel transmit FIFO, the RCTS flag (and the service request and/or interrupt) is automatically cleared.

5.16.3.2 Right Channel Receive FIFO Service Request Flag (RCRS)

The right channel receive FIFO service request flag (RCRS) is a read-only bit which is set when the right channel receive FIFO is nearly filled and requires service to prevent an overrun. RCRS is set any time the right channel receive FIFO has six or more entries of valid data (half full or more), and cleared when it has five or fewer (less than half full) entries of data. When the RCRS bit is set, an interrupt request is made unless the right channel receive FIFO interrupt request mask (RCRM) bit is cleared. After six or more entries are removed from the receive FIFO, the LCRS flag (and the service request and/or interrupt) is automatically cleared.

5.16.3.3 Left Channel Transmit FIFO Service Request Flag (LCTS)

The left channel transmit FIFO service request flag (LCTS) is a read-only bit which is set when the left channel transmit FIFO is nearly empty and requires service to prevent an underrun. LCTS is set any time the left channel transmit FIFO has four or fewer entries of valid data (half full or less), and is cleared when it has five or more entries of valid data. When the LCTS bit is set, an interrupt request is made unless the left channel transmit FIFO interrupt request mask (LCTM) bit is cleared. After the CPU fills the FIFO such that four or more locations are filled within the left channel transmit FIFO, the LCTS flag (and the service request and/or interrupt) is automatically cleared.

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5.16.3.4 Left Channel Receive FIFO Service Request Flag (LCRS)

The left channel receive FIFO service request flag (LCRS) is a read-only bit which is set when the left channel receive FIFO is nearly filled and requires service to prevent an overrun. LCRS is set any time the left channel receive FIFO has six or more entries of valid data (half full or more), and cleared when it has five or fewer (less than half full) entries of data. When the LCRS bit is set, an interrupt request is made unless the left channel receive FIFO interrupt request mask (LCRM) bit is cleared. After six or more entries are removed from the receive FIFO, the LCRS flag (and the service request and/or interrupt) is automatically cleared.

5.16.3.5 Right Channel Transmit FIFO Underrun Status (RCTU)

The right channel transmit FIFO underrun status bit (RCTU) is set when the right channel transmit logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the right channel transmit logic continuously transmits the last valid right channel value which was transmitted before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the right channel transmit logic uses the new value within the FIFO for transmis- sion. When the RCTU bit is set, an interrupt request is made.

5.16.3.6 Right Channel Receive FIFO Overrun Status (RCRO)

The right channel receive FIFO overrun status bit (RCRO) is set when the right channel receive logic attempts to place data into the right channel receive FIFO after it has been completely filled. Each time a new piece of data is received, the set signal to the RCRO status bit is asserted, and the newly received data is discarded. This process is repeated for each new sample received until at least one empty FIFO entry exists. When the RCRO bit is set, an interrupt request is made.

5.16.3.7 Left Channel Transmit FIFO Underrun Status (LCTU)

The left channel transmit FIFO underrun status bit (LCTU) is set when the left channel transmit logic attempts to fetch data from the FIFO after it has been completely emptied. When an underrun occurs, the left channel transmit logic continuously transmits the last valid left channel value which was trans- mitted before the underrun occurred. Once data is placed in the FIFO and it is transferred down to the bottom, the left channel transmit logic uses the new value within the FIFO for transmission. When the LCTU bit is set, an interrupt request is made.

5.16.3.8 Left Channel Receive FIFO Overrun Status (LCRO)

The left channel receive FIFO overrun status bit (LCRO) is set when the left channel receive logic places data into the left channel receive FIFO after it has been completely filled. Each time a new piece of data is received, the set signal to the LCRO status bit is asserted, and the newly received sample is discarded. This process is repeated for each new piece of data received until at least one empty FIFO entry exists. When the LCRO bit is set, an interrupt request is made.

5.16.3.9 Right Channel Transmit FIFO Not Full Flag (RCNF)

The right channel transmit FIFO not full flag (RCNF) is a read-only bit which is set whenever the right channel transmit FIFO contains one or more entries which do not contain valid data and is cleared when the FIFO is completely full. This bit can be polled when using programmed I/O to fill the right channel transmit FIFO. This bit does not request an interrupt.

5.16.3.10 Right Channel Receive FIFO Not Empty Flag (RCNE)

The right channel receive FIFO not empty flag (RCNELCNF) is a read-only bit which is set when ever the right channel receive FIFO contains one or more entries of valid data and is cleared when it no longer contains any valid data. This bit can be polled when using programmed I/O to remove remain- ing data from the receive FIFO. This bit does not request an interrupt.

5.16.3.11 Left Channel Transmit FIFO Not Full Flag (LCNF)

transmit FIFO. This bit does not request an interrupt.

5.16.3.12 Left Channel Receive FIFO Not Empty Flag (LCNE)

from the receive FIFO. This bit does not request an interrupt.

5.16.3.13 FIFO Operation Completed Flag (FIFO)

FIFO is automatically cleared when DAIDR2 is read or written. This bit does not request an interrupt. Table 51. DAI Control, Data and Status Register Locations

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13 Reserved

14 Reserved

Table 51. DAI Control, Data and Status Register Locations(cont.)

1. ELECTRICAL SPECIFICATIONS

6.1 Absolute Maximum Ratings

6.2 Recommended Operating Conditions

6.3 DC Characteristics

Table 52. absolute Maximum Ratings Table 53. Recommended Operating Conditions Table 54. DC Characteristics

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Pull-up current = 50 µA typical at VDD = 3.3 volts. Table 54. DC Characteristics(cont.)

6.4 AC Characteristics

The values for 36 MHz include 1 wait state, the 18 MHz values have 0 wait states. Table 55. AC Timing Characteristics

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Table 56. Timing Characteristics

Figure 13. Consecutive Memory Read Cycles with Minimum Wait States EXPRDY, but is shown for clarity. mance so the SQAEN bit should always be set where possible.

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Figure 14. Sequential Page Mode Read Cycles with Minimum Wait States EXPRDY, but is shown for clarity. mance so the SQAEN bit should always be set where possible.

Figure 15. Consecutive Memory Write Cycles with Minimum Wait States driving EXPRDY, but is shown for clarity. mance so the SQAEN bit should always be set where possible. as this cannot be driven with valid timing under zero wait state conditions.

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Figure 16. LCD Controller Timings 1) The figure shows the end of a line. 2) If FRM is high during the CL[1] pulse, this marks the first line in the display. Figure 17. SSI Interface for AD7811/2

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6.5 I/O Buffer Characteristics

trolled output stages to reduce system noise. Table 57. I/O Buffer Output Characteristics

6.6 JTAG Bandary Scan Signal Ordering

2 VDDIO Pad Pwr

3 VSSIO Pad Gnd

4 EXPCLK I/O 1

5 WORD Out 1 Low

7 RUN/CLKEN I/O 1 Low

9 TXD[2] Out 1 High

10 RXD[2] In

11 TDI In with p/u*

12 VSSIO Pad Gnd

13 PB[7] I/O 1 Input

14 PB[6] I/O 1 Input

15 PB[5] I/O 1 Input

16 PB[4] I/O 1 Input

17 PB[3] I/O 1 Input

18 PB[2] I/O 1 Input

Table 58. 208-Pin LQFP Numeric Pin Listing

19 PB[1]/

20 PB[0]/

21 VDDIO Pad Pwr

22 TDO Out 1 Tristate

23 PA[7] I/O 1 Input

24 PA[6] I/O 1 Input

25 PA[5] I/O 1 Input

26 PA[4] I/O 1 Input

27 PA[3] I/O 1 Input

28 PA[2] I/O 1 Input

29 PA[1] I/O 1 Input

30 PA[0] I/O 1 Input

31 LEDDRV Out 1 Low

32 TXD[1] Out 1 High

33 VSSIO Pad Gnd 1 High

34 PHDIN In

35 CTS In

36 RXD[1] In

Table 58. 208-Pin LQFP Numeric Pin Listing(cont.)

37 DCD In

38 DSR In

41 EINT[3] In

45 PE[2]/

46 PE[1]/

47 PE[0]/

48 VSSRTC RTC Gnd

49 RTCOUT Out

50 RTCIN In

51 VSSRTC RTC

52 N/C

53 PD[7] I/O 1 Low

54 PD[6] I/O 1 Low

55 PD[5] I/O 1 Low

56 PD[4] I/O 1 Low

57 VDDIO Pad Pwr

58 TMS In with p/u*

59 PD[3] I/O 1 Low

60 PD[2] I/O 1 Low

61 PD[1] I/O 1 Low

62 PD[0]/

63 SSICLK I/O 1 Input

64 VSSIO Pad Gnd

65 SSITXFR I/O 1 Low

66 SSITXDA Out 1 Low

67 SSIRXDA In

68 SSIRXFR I/O Input

69 ADCIN In

71 VSSCORE Core

72 VDDCORE Core Pwr

73 VSSIO Pad Gnd

74 VDDIO Pad Pwr

75 DRIVE[1] I/O 1 High/

76 DRIVE[0] I/O 1 High/

77 ADCCLK Out 1 Low

78 ADCOUT Out 1 Low

79 SMPCLK Out 1 Low

80 FB[1] In

81 VSSIO Pad Gnd

82 FB[0] In

83 COL[7] Out 1 High

84 COL[6] Out 1 High

85 COL[5] Out 1 High

86 COL[4] Out 1 High

87 COL[3] Out 1 High

88 COL[2] Out 1 High

89 VDDIO Pad Pwr

90 TCLK In

91 COL[1] Out 1 High

92 COL[0] Out 1 High

93 BUZ Out 1 Low

94 D[31] I/O 1 Low

95 D[30] I/O 1 Low

96 D[29] I/O 1 Low

97 D[28] I/O 1 Low

98 VSSIO Pad Gnd

99 A[27] Out 2 Low

100 D[27] I/O 1 Low

101 A[26] Out 2 Low

102 D[26] I/O 1 Low

103 A[25] Out 2 Low

104 D[25] I/O 1 Low

105 HALFWORD Out 1 Low

106 A[24] Out 1 Low

107 VDDIO Pad Pwr —

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108 VSSIO Pad Gnd —

109 D[24] I/O 1 Low

110 A[23] Out 1 Low

111 D[23] I/O 1 Low

112 A[22] Out 1 Low

113 D[22] I/O 1 Low

114 A[21] Out 1 Low

115 D[21] I/O 1 Low

116 VSSIO Pad Gnd

117 A[20] Out 1 Low

118 D[20] I/O 1 Low

119 A[19] Out 1 Low

120 D[19] I/O 1 Low

121 A[18] Out 1 Low

122 D[18] I/O 1 Low

123 VDDIO Pad Pwr

124 VSSIO Pad Gnd

126 A[17] Out 1 Low

127 D[17] I/O 1 Low

128 A[16] Out 1 Low

129 D[16] I/O 1 Low

130 A[15]] Out 1 Low

131 D[15] I/O 1 Low

132 A[14] Out 1 Low

133 D[14] I/O 1 Low

134 A[13] Out 1 Low

135 D[13] I/O 1 Low

136 A[12] Out 1 Low

137 D[12] I/O 1 Low

138 A[11] Out 1 Low

139 VDDIO Pad Pwr

140 VSSIO Pad Gnd

141 D[11] I/O 1 Low

142 A[10] Out 1 Low

143 D[10] I/O 1 Low

144 A[9] Out 1 Low

145 D[9] I/O 1 Low

146 A[8] Out 1 Low

147 D[8] I/O 1 Low

148 A[7] Out 1 Low

149 VSSIO Pad Gnd

150 D[7] I/O 1 Low

153 BATOK In

157 VDDOSC Osc Pwr

158 MOSCIN Osc

159 MOSCOUT Osc

160 VSSOSC Osc Gnd

161 WAKEUP In Schmitt

163 A[6] Out 1 Low

164 D[6] I/O 1 Low

165 A[5] Out 1 Low

166 D[5] I/O 1 Low

167 VDDIO Pad Pwr

168 VSSIO Pad Gnd

169 A[4] Out 1 Low

170 D[4] I/O 1 Low

171 A[3] Out 2 Low

172 D[3] I/O 1 Low

173 A[2] Out 2 Low

174 VSSIO Pad Gnd

175 D[2] I/O 1 Low

176 A[1] Out 1 Low

177 D[1] I/O 1 Low

178 A[0] Out 1 Low

179 D[0] I/O 1 Low

180 VSS CORE Core Gnd

181 VDD CORE Core Pwr

182 VSSIO Pad Gnd

183 VDDIO Pad Pwr

184 CL[2] Out 1 Low

185 CL[1] Out 1 Low

186 FRM Out 1 Low

187 M Out 1 Low

188 DD[3] I/O 1 Low

189 DD[2] I/O 1 Low

190 VSSIO Pad Gnd

191 DD[1] I/O 1 Low

192 DD[0] I/O 1 Low

193 N/C

194 N/C

195 N/C

196 N/C

197 VDDIO Pad Pwr

198 VSSIO Pad Gnd

199 N/C

200 N/C

203 VSSIO Pad Gnd

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their state is latched on the rising edge of NPOR. the test signals unique to that mode.

7.1 Oscillator and PLL Bypass Mode

7.2 Oscillator and PLL Test Mode

576 kHz and the Real Time Clock divide chain.

110 X 11

101 X 11

Table 59. EP7209 Hardware Test Modes

7.3 Debug/ICE Test Mode

saves approximately 3% on power.

7.4 Hi-Z (System) Test Mode

7.5 Software Selectable Test

out of the device on port pins. Table 60. Oscillator and PLL Test Mode Signals Table 61. Software Selectable Test Functionality

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Figure 20. 208-Pin LQFP (Low Profile Quad Flat Pack) Pin Diagram

Table 62. 208-Pin LQFP Numeric Pin Listing Table 62. 208-Pin LQFP Numeric Pin Listing(cont.)

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75 DRIVE[1] I/O 2 High/

76 DRIVE[0] I/O 2 High/

176 A[1] Out 2 Low

178 A[0] Out 2 Low

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8.3 256-Pin PBGA Pin Diagram A B C D E F G H J K L M N P R T 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 256-Ball PBGA (Bottom View) NOTE: For package specifications, please see 256-Ball PBGA Dimensions page 118

Table 63. 256-Ball PBGA Ball Listing Table 63. 256-Ball PBGA Ball Listing(cont.)

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116 DS453PP2

8.4.1 PBGA Ground Connections

not used on the PBGA package. Table 64. PBGA Balls to Connect to Ground (VSS)

1. PACKAGE SPECIFICATIONS 9.1 208-Pin LQFP Package Outline Drawing Pin 1 Indicator 29.60 (1.165) 30.40 (1.197) 0.17 (0.007) 0.27 (0.011) 27.80 (1.094) 28.20 (1.110) 0.50 (0.0197) BSC 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 1.35 (0.053) 1.45 (0.057) 0° MIN 7° MAX 0.09 (0.004) 0.20 (0.008) 1.40 (0.055) 0.45 (0.018) 0.75 (0.030) 0.05 (0.002) 1.00 (0.039) BSC Pin 1 Pin 208 EP7209 208-Pin LQFP NOTES: 1) Dimensions are in millimeters (inches), and controlling dimension is millimeter. 2) Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 4) For pin description, please see 208-Pin LQFP Pin Diagram page 12

118 DS453PP2

9.2 EP7209 256-Ball PBGA (17 × 17 × 1.53-mm Body) Dimensions TOP VIEW 17.00 (0.669) 15.00 (0.590) SIDE VIEW BOTTOM VIEW 1.00 (0.040) Pin 1 Indicator Pin 1 Corner Pin 1 Corner 16 15 14 13 12 11 109 8 7 6 5 4 3 21 +0.70 (.027) -0.00 15.00 (0.590) +0.70 (.027) -0.00

4 Layer

2 Layer

17.00 (0.669) 1.00 (0.040) 1.00 (0.040) 30° TYP REF REF 0.50

3 Places

0.80 (0.032) ±0.05 (.002) 0.40 (0.016) ±0.10 (.004) 0.56 (0.022) ±0.06 (0.002) 0.36 (0.022) +0.04 (0.001) –0.06 (0.002) 17.00 (0.669) R NOTE: For pin description, please see 256-Ball PBGA Pin Diagram page 112 A B C D E F G H J K L M N P R T

1. ORDERING INFORMATION The order number for the device is: EP7209 — CV — A Product Line: Embedded Processor Part Number Temperature Range: C = Commercial Package Type: V = Low Profile Quad Flat Pack B = Plastic Ball Grid Array (17 mm x 17 mm) Revision † NOTE: † Contact Cirrus Logic for up-to-date information on revisions. Go to the Cirrus Logic Internet site at http://cirrus.com/corporate/contacts to find contact information for your local sales representa- tive.

120 DS453PP2

1. APPENDIX A: BOOT CODE ;(C) Copyright 1995-1996, Cirrus Logic, Inc. All Rights Reserved. TTL CL-EP7209 Sample program ; version 1.0 (initial version) ;ks ; boot from uart1 AREA |C$$code|,CODE,READONLY ENTRY ; System constants HwBaseAddress EQU 0x80000000 HwControl EQU 0x00000100 HwControl2 EQU 0x00001100 HwControlUartEnable EQU 0x00000100 HwStatus EQU 0x00000140 HwStatus2 EQU 0x000001140 HwStatusUartRxFifoEmpty EQU 0x00400000 HwUartData EQU 0x00000480 HwUartData2 EQU 0x00001480 HwUartDataFrameErr EQU 0x0100 HwUartDataParityErr EQU 0x0200 HwUartDataOverrunErr EQU 0x0400 HwUartControl EQU 0x000004C0 HwUartControl2 EQU 0x000014C0 HwUartControlRate EQU 0x00000FFF HwUartControlRate115200 EQU 0x001 HwUartControlRate76800 EQU 0x002 HwUartControlRate57600 EQU 0x003 HwUartControlRate38400 EQU 0x005

HwUartControlRate19200 EQU 0x00B HwUartControlRate14400 EQU 0x00F HwUartControlRate9600 EQU 0x017 HwUartControlRate4800 EQU 0x02F HwUartControlRate2400 EQU 0x05F HwUartControlRate1200 EQU 0x0BF HwUartControlRate600 EQU 0x17F HwUartControlRate300 EQU 0x2FF HwUartControlRate150 EQU 0x5FF HwUartControlRate110 EQU 0x82E HwUartControlRate115200_13 EQU 0x000 HwUartControlRate57600_13 EQU 0x001 HwUartControlRate38400_13 EQU 0x002 HwUartControlRate19200_13 EQU 0x005 HwUartControlRate14400_13 EQU 0x007 HwUartControlRate9600_13 EQU 0x00b HwUartControlRate4800_13 EQU 0x017 HwUartControlRate2400_13 EQU 0x02F HwUartControlRate1200_13 EQU 0x060 HwUartControlRate600_13 EQU 0x0c0 HwUartControlRate300_13 EQU 0x182 HwUartControlRate150_13 EQU 0x305 HwUartControlRate110_13 EQU 0x41E HwUartControlBreak EQU 0x00001000 HwUartControlParityEnable EQU 0x00002000 HwUartControlPartiyEvenOrOdd EQU 0x00004000 HwUartControlTwoStopBits EQU 0x00008000 HwUartControlFifoEnable EQU 0x00010000 HwUartControlDataLength EQU 0x00060000 HwUartControlDataLength5 EQU 0x00000000 HwUartControlDataLength6 EQU 0x00020000 HwUartControlDataLength7 EQU 0x00040000 HwUartControlDataLength8 EQU 0x00060000 ; 9600baud, 8bits/ch no parity, 1 stop bit UartValue EQU HwUartControlRate9600+HwUartControlDataLength8 UartValue_13 EQU HwUartControlRate9600_13+HwUartControlDataLength8 BufferAddress EQU 0x10000000 ;start address sram snooze buffer codeexeaddr EQU 0x10000000 ; count EQU 0x00000800 ;2k bytes

122 DS453PP2

startflag EQU ’<’ endflag EQU ’>’ CLKMOD EQU 0x40 ;clock mode 1 = 13 MHz ; ARM Processor constants ArmIrqDisable EQU 0x00000080 ArmFiqDisable EQU 0x00000040 ; 26bit mode is not supported ArmUserMode EQU 0x10 ArmFIQMode EQU 0x11 ArmIRQMode EQU 0x12 ArmSVCMode EQU 0x13 ArmAbortMode EQU 0x17 ArmUndefMode EQU 0x1B ArmMaskMode EQU 0x1F ArmMmuCP CP 0xF ArmMmuId CN 0x00 ArmMmuControl CN 0x01 ArmMmuControlMmuEnable EQU 0x00000001 ArmMmuControlAlignFaultEnable EQU 0x00000002 ArmMmuControlCacheEnable EQU 0x00000004 ArmMmuControlWriteBufferEnable EQU 0x00000008 ArmMmuControl32BitCodeEnable EQU 0x00000010 ArmMmuControl32BitDataEnable EQU 0x00000020 ArmMmuControlMandatory EQU 0x00000040 ArmMmuControlBigEndianEnable EQU 0x00000080 ArmMmuControlSystemEnable EQU 0x00000100 ArmMmuControlRomEnable EQU 0x00000200 ArmMmuPageTableBase CN 0x02 ArmMmuDomainAccess CN 0x03 ArmMmuFlushTlb CN 0x05

;InitialMmuConfig EQU ArmMmuControl32BitCodeEnable +ArmMmuControl32BitDataEnable +ArmMmuControlMandatory +ArmMmuControlBigEndianEnable InitialMmuConfig EQU ArmMmuControl32BitCodeEnable +ArmMmuControl32BitDataEnable +ArmMmuControlMandatory ;leave as little endian 11/6/96 ks ====== ; REAL CODE START ; set little endian, 32bit code, 32bit data by writing to CP15’s control register LDR r0, =InitialMmuConfig MCR ArmMmuCP, 0, r0, ArmMmuControl, c0 ; set the cpu to SVC32 mode MRS r0, CPSR ;read psr BIC r0, r0, #ArmMaskMode ;remove the mode bits ORR r0, r0, #ArmSVCMode ;set to supervisor 32 bit mode MSR CPSR, r0 ; Now set the CPU into the new mode ; initialize HW control UARTEnable LDR r12,=HwBaseAddress MOV r0,#HwControlUartEnable ;Enable UART STR r0,[r12,#HwControl] LDR r1,=HwStatus2 ADD r1,r1,r12 LDR r2,[r1] ;read system flag2 TST r2,#CLKMOD LDREQ r0,=UartValue ;load 18 mhz value if bit not set LDRNE r0,=UartValue_13 ;load 13 mhz value if bit set

124 DS453PP2

STR r0,[r12,#HwUartControl] ;initialise Uart ; Send ready signal LDR r0,=startflag STRB r0,[r12,#HwUartData] ; send ready ; receive the data LDR r3,=count LDR r2,=BufferAddress ; wait for byte available LDR r1,[r12,#HwStatus] ; spin, if Rx FIFO is empty TST r1,#HwStatusUartRxFifoEmpty BNE %b01 ; read the data ,store it and accumulate checksum LDRB r0,[r12,#HwUartData] ; read data STRB r0,[r2],#1 ; save it in memory SUBS r3,r3,#1 ; decrement count BNE %b01 ; do more if count has not expired ; all received, send end flag LDR r0,=endflag STRB r0,[r12,#HwUartData] ; send reply LDR r15,=codeexeaddr ;jump to execution address LTORG END

1. INDEX Symbols / BOOTSEL0 15 / BOOTSEL1 15 / CLKSEL 15 / LEDFLSH 15 /PRDY1 15 Numerics pin information PB 15 PD 15 PE 15 DRIVE 15 FB 15 NTEST 16 A 13 NCS 13 pin information DD 15 NCS 13 D 13 COL 15 PA 15 PD 15 PB 15 PE 15 NEINT 14 RXD 15 TXD 15 PE 15 /PRDY2 PB 15 pin information NCS 13 B boundary scan47 C clocks23 external clock input (13 MHz)24 on-chip PLL23 CPU core 19 D dedicated LED flasher47 E endianness 33 F functional block diagram19 functional description18 I idle state28 iInternal UARTs34 in-circuit emulation48 interrupt Ccontroller23 L LCD controller43 M memory and I/O expansion interface30 CL-EP7211 boot ROM 29 O operating state28 P PADDR Port A Data Direction Register54 PADR Port A Data Register54 PBDR Port B Data Register54 PBGA ground connections116 PDDDR Port D Data Direction Register55 PDDR Port D Data Register54 PEDDR Port E Data Direction Register55 pin descriptions, external signal functions13 pin diagram12, 108 pin information ADCCLK 15 ADCIN 15 ADCOUT 15 BATOK 14 BUZ 15 CL1 15 CL2 15 CTS 15 DCD 15 DSR 15 EINT3 14 EXPCLK 13 EXPRDY 13 FRM 15 LEDDRV 15 M 15 MOSCIN 16 MOSCOUT 16 NADCCS 15 NBATCHG 14

126 DS453PP2

R realtime clock46 resets23 S serial interface ADC iInterface39 clock polarity43 continuous data transfer43 discontinuous clock43 error conditions43 MCP interface37 MCP operation38 readback of residual data42 support for asymmetric traffic42 serial interfaces34 codec sound interface36 SIR encoder34 standby state28 state control20 SYSFLG, The System Status Flags Register62 T timer counters45 free running mode46 prescale mode46 U UART 19

• Notes