ECT25S80 E-CMOS | Alldatasheet
Document overview
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Technical content
Features
- Serial Peripheral Interface(SPI) - Standard SPI: SCLK, /CS, SI, SO, /WP, /HOLD - Dual SPI: SCLK, /CS, IO0, IO1, /WP, /HOLD - Quad SPI: SCLK, /CS, IO0, IO1, IO2, IO3
- Read - Normal Read (Serial): 50MHz clock rate - Fast Read (Serial): 108MHz clock rate - Dual/Quad (Multi-I/O) Read: 108MHz clock rate
- Program - Serial-input Page Program up to 256bytes - Program Suspend and Resume
- Erase - Block erase (64/32 KB) - Sector erase (4 KB) - Chip erase - Erase Suspend and Resume
- Program/Erase Speed - Page Program time: 0.7ms typical - Sector Erase time: 60ms typical - Block Erase time: 0.2/0.4s typical - Chip Erase time: 7s typical
- Flexible Architecture - Sector of 4K-byte - Block of 32/64K-byte
- Low Power Consumption - 20mA maximum active current - 5uA maximum power down current
- Software/Hardware Write Protection - 3x256-Byte Security Registers with OTP Lock
Figure 3. Pin Configuration DIP8L See Section “DC Electrical Characteristics”).These signals are described next. Table 1. Signal Names all input signals are ignored and all output signals are high impedance. Active Power mode. After Power Up, a falling edge on /CS is required prior to the start of any instruction. Write Protect in single bit or Dual data Instructions. IO2 in Quad mode. in the host system if not used for Quad Instructions. left unconnected in the host system if not used for Quad Instructions.
ECT25S80 8M BIT SPI NOR FLASH Serial Clock (SCLK) This input signal provides the synchronization reference for the SPI interface. Instructions, addresses, or data Input are latched on the rising edge of the SCLK signal. Data output changes after the falling edge of SCLK. Serial Input (SI)/IO0 This input signal is used to transfer data serially into the device. It receives instructions, addresses, and data to be programmed. Values are latched on the rising edge of serial SCK clock signal. SI becomes IO0 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). Serial Data Output (SO)/IO1 This output signal is used to transfer data serially out of the device. Data is shifted out on the falling edge of the serial SCK clock signal. SO becomes IO1 an input and output during Dual and Quad Instructions for receiving instructions, addresses, and data to be programmed (values latched on rising edge of serial SCK clock signal) as well as shifting out data (on the falling edge of SCK). Write Protect (/WP)/IO2 When /WP is driven Low (VIL), while the Status Register Protect bits (SRP1andSRP0) o f the status Registers (SR2[0] and SR1[7]) are set to 0 and 1 respectively, it is not possible to write to the status Registers. This prevents any alteration of the Status Registers. As a consequence, all the data bytes in the memory area that are protecte d by the Block Protect, TB, SEC, and CMP bits in the status registers, are also hardware protected against data modification while /WP remains Low. The /WP function is not available when the Quad mode is enabled (QE) in Status Register 2 (SR2[1]=1). The /WP function is replaced by IO2 for input and output during Quad mode for receiving addresses, and data to be programmed (values are latched on rising edge of the SCK signal) as well as shifting out data (on the falling edge of SCK). /WP has an internal pull-up resistance; when unconnected; /WP is at VIH and may be left unconnected in the host system if not used for Quad mode. HOLD (/HOLD)/IO3 The /HOLD signal goes low to stop any serial communications with the device, but doesn’t stop the operation of wire staus register, programming, or erasing in progress. The operation of HOLD,need /CS keep low, and starts on falling edge of the /HOLD signal, with SCLK signal being low(if SCLK is not being low, HOLD operation will not start until SCLK being low). The HOLD condition ends on rising edge of /HOLD signal with SCLK being low (If SCLK is not being low, HOLD operation will not end until SCLK being low). The Hold condition starts on the falling edge of the Hold (/HOLD) signal, provided that this coincides with SCK being at the logic low state. If the falling edge does not coincide with the SCK signal being at the logic low state, the Hold condition starts whenever the SCK signal reaches the logic low state.Taking the /HOLD signal to the logic low state does not terminate any Write, Program or Erase operation that is currently in progress. VCC Power Supply
VCC is the supply voltage. is the single voltage used for all device functions including read, program, and erase. VSS is the reference for the VCC supply voltage. Table 2. Block/Sector Addresses of ECT25S80
ECT25S80 8M BIT SPI NOR FLASH 1.Block = Uniform Block, and the size is 64K bytes. 2.Half block = Half Uniform Block, and the size is 32k bytes. 3.Sector = Uniform Sector, and the size is 4K bytes. SPI Operation Standard SPI Instructions The ECT25S80 features a serial peripheral interface on 4 signals bus: Serial Clock (SCLK), Chip Select (/CS), Serial Data Input (SI) and Serial Data Output (SO). Both SPI bus mode 0 and 3 are supported. Input data is latched on the rising edge of SCLK and data shifts out on the falling edge of SCLK. Dual SPI Instructions The ECT25S80 supports Dual SPI operation when using the “Dual Output Fast Read” and “Dual I/O Fast Read” (3BH and BBH) instructions. These instructions allow data to be transferred to or from the device at two times the rate of the standard SPI. When using the Dual SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1. Quad SPI Instructions The ECT25S80 supports Quad SPI operation when using the “Quad Output Fast Read”, “Quad I/O Fast Read” (6BH, EBH) instructions. These instructions allow data to be transferred t -o or from the device at four times the rate of the standard SPI. When using the Quad SPI instruction the SI and SO pins become bidirectional I/O pins: IO0 and IO1, and /WP and /HOLD pins become IO2 and IO3. Quad SPI instructions require the non-volatile Quad Enable bit (QE) in Status Register-2 to be set. Operation Features Supply Voltage Operating Supply Voltage Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see operating ranges). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a Write instruction, until the completion of the internal write cycle (tW). Power-up Conditions When the power supply is turned on, VCC rises continuously from VSS to VCC. Dur ing this time, the Chip Select (/CS) line is not allowed to float but should follow the VCC voltage, it is therefore recommended to connect the /CS line to VCC via a suitable pull-up resistor. In addition, the Chip Select (/CS) input offers a built-in safety feature, as the /CS input is edge sensitive as well as level sensitive: after power-up, the device does not become selected until a falling edge has first been detected on Chip Select (/CS). This ensures that Chip Select (/CS) must have been High, prior to going Low to start the first operation.
voltage defined in operating ranges). When VCC has passed the POR threshold, the device is reset. device then goes in to the Standby Power mode, and the device consumption drops to ICC1. with Chip Select(/CS) Low. Normally, the device is kept selected, for the whole duration of the Hold condition. this mechanism can be used if it is required to reset any processes that had been in progress. already being Low (as shown in Figure 4). with Serial Clock (SCLK) being Low. Figure 4. Hold condition activation
Erase/Program Suspend status. Table 3. Status Register-2 (SR2) Table 4. Status Register-1 (SR1)
7 SUS Suspend
6 CMP Complement
5 LB3 Security
0 OTP Lock Bits 3:1 for Security Registers 3:1
4 LB2 0
3 LB1 0
2 Reserved Reserved 0
1 QE Quad
0 SRP1
7 SRP0
6 SEC Sector/Block
5 TB Top/Bottom
4 BP2 Block Protect
2 BP0 0
1 WEL Write Enable
0 WIP
ECT25S80 8M BIT SPI NOR FLASH The Status and Control Bits WIP bit The Write in Progress (WIP) bit indicates whether the memory is busy in program/erase/write status register progress. When WIP bit sets to 1, means the device is busy in program/erase/write status register progress, when WI P bit sets 0, means the device is not in program/erase/write status register progress. WEL bit The Write Enable Latch bit indicates the status of the internal Write Enable Latch. When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and no Write Status Register, Program or Erase instruction is accepted. SEC, TB, BP2, BP1, BP0 bits The Block Protect (SEC, TB, BP2, BP1, BP0) bits are non-volatile. They define the size of the area to be software protected against Program and Erase instructions. These bits are written with the Write Status Register instruction. When the Block Protect (SEC, TB, BP2, BP1, BP0) bits are set to 1,the relevant memory area(as defined in Table 6 and Table 7).becomes protected against Page Program, Sector Erase and Block Erase instructions. The Block Protect (SEC, TB, BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. SRP1, SRP0 bits The Status Register Protect (SRP1 and SRP0) bits are non-volatile Read/Write bits in the status register. The SRP bits control the method of write protection: software protection, hardware protection, power supply lock- down or one time programmable protection. QE bit The Quad Enable (QE) bit is a non-volatile Read/Write bit in the Status Register that allows Quad operation. When the QE bit is set to 0 (Default) the /WP pin and /HOLD pin are enable. When the QE pin is set to 1, the Quad IO2 and IO3 pins are enabled. (The QE bit should never be set to 1 during standard SPI or Dual SPI operation if the /WP or /HOLD pins directly to the power supply or ground). LB3/LB2/LB1 bit The LB bit is a non-volatile One Time Program (OTP) bit in Status Register that provide the write protect control and status to the Security Registers. The default state of LB is 0, the security registers are unlocked. LB can be set to 1 individually using the Write Register instruction. LB is One Time Programmable, once it’s set to 1, the 256byte Security Registers will become read-only permanently, LB3/2/1 for Security Registers 3:1. CMP bit The CMP bit is a non-volatile Read/Write bit in the Status Register2 (bit6). It is used in conjunction the SEC- BP0 bits to provide more flexibility for the array protection. Please see the Status registers Memory Protection table for details. The default setting is CMP=0. SUS bit The SUS bit is a read only bit in the status register2 (bit7) that is set to 1 after executing an Erase/Program Suspend (75H) instruction. The SUS bit is cleared to 0 by Erase/Program Resume (7AH) instruction as well as a power-down, power-up cycle.
Table 5. Status Register protect table
- When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.
- The One time Programfeature is available upon special order.
- Software Protection: The Block Protect (SEC, TB, BP2, BP1, BP0) bits define the section of
thememory array that can be read but not change.
- Hardware Protection: /WP going low to protected the BP0~SEC bits and SRP0~1 bits.
- Deep Power-Down: In Deep Power-Down Mode,all instructions are ignored except the Release from
deep Power-Down Mode instruction.
- Write Enable: The Write Enable Latch(WEL) bit must be set prior to every Page Program, Sector
written to after a Write Enable instruction, WEL=1.
Table 6. Status Register Memory Protection (CMP=0)
0 X 1 0 1 0 to15 000000H-0FFFFFH 1MB ALL
Table 8. ECT25S80 ID Definition table
ECT25S80 8M BIT SPI NOR FLASH All instructions, addresses and data are shifted in and out of the device, beginning with the most significant bit on the first rising edge of SCLK after /CS is driven low. Then, the one byte instruction code must be shifted in to the device, most significant bit first on SI, each bit being latched on the rising edges of SCLK. See Table 9, every instruction sequence starts with a one-byte instruction code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. /CS must be driven high after the last bit of the instruction sequence has been shifted in. For the instruction of Read, Fast Read, Read Status Register or Release from Deep Power Down, and Read Device ID, the shifted-in instruction sequence is followed by a data out sequence. /CS can be driven high after any bit of the data-out sequence is being shifted out. For the instruction of Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Write Enable, Write Disable or Deep Power-Down instruction, /CS must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. That is /CS must driven high when the number of clock pulses after /CS being driven low is an exact multiple of eight. For Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be reset.
Table 9. Instruction Set Table
ECT25S80 8M BIT SPI NOR FLASH Notes: 1. Dual Output data IO0 = (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1) 2. Dual Input Address IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0, M6, M4, M2, M0 IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1, M7, M5, M3 3. Quad Output Data IO0 = (D4, D0,…..) IO1 = (D5, D1,…..) IO2 = (D6, D2,…..) IO3 = (D7, D3,…..) 4. Quad Input Address IO0 = A20, A16, A12, A8, A4, A0, M4, M0 IO1 = A21, A17, A13, A9, A5, A1, M5, M1 IO2 = A22, A18, A14, A10, A6, A2, M6, M2 IO3 = A23, A19, A15, A11, A7, A3, M7, M3 5. Fast Read Quad I/O Data IO0 = (x, x, x, x, D4, D0,…) IO1 = (x, x, x, x, D5, D1,…) IO2 = (x, x, x, x, D6, D2,…) IO3 = (x, x, x, x, D7, D3,…) 6. Security Registers Address: Security Register0: A23-A16=00h, A15-A8=00h, A7-A0= Byte Address; Security Register1: A23-A16=00h, A15-A8=01h, A7-A0= Byte Address; Security Register2: A23-A16=00h, A15-A8=02h, A7-A0= Byte Address; Security Register3: A23-A16=00h, A15-A8=03h, A7-A0= Byte Address; Security Register 0 can be used to store the Flash Discoverable Parameters,
address after each byte of data is shifted out. Figure 13. Quad Output Fast Read Sequence Diagram higher address after each byte of data is shifted out.
Continuous Read Mode and return to normal SPI operation. To reset “Continuous Read Mode” during Quad I/O operation, only eight clocks are needed. Figure 18. Continuous Read Mode Reset Sequence Diagram
ECT25S80 8M BIT SPI NOR FLASH Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around” The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing a “Set Burst with Wrap”(77h)instruction prior to EBh. The “Set Burst with Wrap”(77h) instruction can either enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is enabled, the data being accessed can be limited to either an 8,16,32 or 64-byte section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary automatically until /CS is pulled high to terminate the instruction. The Burst with Wrap feature allows applications that use cache to quickly fetch a critical Address and then fill the cache afterwards within a fixed length (8/16/32/64-byte) of data Without issuing multiple read instructions. The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is Used to enable or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section within a page. Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low and then shifting the instruction code “77h” followed by 24 dummy bits and 8 “Wrap Bits”, W7-0. Wrap bit W7 and the lower nibble W3-0 are not used. Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and“Word Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64- byte section within any page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap instruction should be issued to set W4=1. The default value of W4 upon power on is 1. W6 W5 W4 = 0 W4 =1 (DEFAULT) Wrap Around Wrap Length Wrap Around Wrap Length 0 0 Yes 8-byte No N/A 0 1 Yes 16-byte No N/A 1 0 Yes 32-byte No N/A 1 1 Yes 64-byte No N/A
The JEDEC ID instruction should not be issued while the device is in Deep Power -Down Mode. time during data output. When /CS is driven high, the device is put in the Standby Mode. Figure 21. JEDEC ID Sequence Diagram
shifting the instruction code “B9h” as shown in Figure 22. Figure 22. Deep Power-Down Sequence Diagram remain high during the tRES1 time duration. completed by driving /CS high.
Figure 24. Read Security Registers instruction Sequence Diagram security and other important information separately from the main memory array. permanently locked; the Erase Security Registers instruction will be ignored.
been latched in; otherwise the Page Program instruction is not executed. Protect (SEC, TB, BP2, BP1, BP0) is not executed. Figure 27. Page Program Sequence Diagram
byte on SI. Any address inside the sector is a valid address for the Sector Erase instruction. /CS must be driven low for the entire duration of the sequence. Figure 28. Sector Erase Sequence Diagram Erase instruction. /CS must be driven low for the entire duration of the sequence. Protect (SEC, TB, BP2, BP1, BP0) bits (see Table 6&7) is not executed.
The Chip Erase instruction sets all memory within the device to the erased state of all 1s (FFh). sequence is shown in Figure 31. SEC, TB, BP2, BP1, and BP0) bits(see Table 6&7). Figure 31. Chip Erase Sequence Diagram instruction sequence is shown in Figure 32.
ECT25S80 8M BIT SPI NOR FLASH
Electrical Characteristics
Notes: 1.JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms) Operating Ranges Data Retention and Endurance Latch Up Characteristics PARAMETERS SYMBOL CONDITIONS RANGE UNIT Supply Voltage VCC –0.5 to 4 V Voltage Applied to Any Pin VIO Relative to Ground –0.5 to 4 V Transient Voltage on any Pin VIOT <20nS Transient Relative to Ground –2.0V to VCC+2.0V V Storage Temperature TSTG –65 to +150 °C Electrostatic Discharge Voltag e VESD Human Body Model(1) –2000 to +2000 V PARAMETER SYMBOL CONDITIONS SPEC UNIT MIN MAX Supply Voltage VCC FR = 108MHz, fR = 50MHz 2.7 3.6 V Temperature Operating TA Commercial Industrial –40 +70 +85 Parameter Test Condition Min Units Minimum Pattern Data Retention Time 150°C 10 Years 125°C 20 Years Erase/Program Endurance -40 to 85°C 100K Cycles Parameter Min Max Input Voltage Respect To VSS On I/O Pins -1.0V VCC+1.0V VCC Current -100mA 100mA
Figure 34. Power-up Timing and Voltage Levels
ECT25S80 8M BIT SPI NOR FLASH Note: (1) ICC3 is measured with ATE loadi ng Symbo l Parameter Test Condition Min. Typ Max. Unit. ILI Input Leakage Curr ent ±2 µA ILO Output Leakage Current ±2 µA ICC1 Standby Current /CS=VCC, VIN=VCC or VSS 13 25 µA ICC2 Deep Power-Down Current /CS=VCC, VIN=VCC or VSS 2 5 µA ICC3 Current: Read Single/Dual/Quad 1MHz SCLK=0.1VC 0.9VCC(1) 3/4/5 3.5/5/6 mA Current: Read Single/Dual/Quad 33MHz Current: Read Single/Dual/Quad 50MHz Current: Read Single/Dual/Quad 108MHz 10/33/60 12/35/65 mA ICC4 Operating Current(Page Program) /CS=VCC 15 mA ICC5 Operating Current(WRSR) /CS=VCC 5 mA ICC6 Operating Current(Sector Era se) /CS=VCC 20 mA ICC7 Operating Current(Block Eras /CS=VCC 20 mA ICC8 Operating Current (Chip Erase) /CS=VCC 20 mA VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.8VCC VCC+0.4 V VOL Output Low Voltage IOL =100µA 0.4 V VOH Output High Voltag e IOH =-100µA VCC-0.2 V
Figure 35. AC Measurement I/O Waveform Symbol Parameter Min. Typ. Max. Unit.
ECT25S80 8M BIT SPI NOR FLASH Note: 1. Tested with clock frequency lower than 50 MHz. 2. tW can be up to 45 ms at -40℃ during the characterization of the current design. It will be improved in the future design. Symbol Parameter Min. Typ. Max. Unit. tSHSL /CS High Time（read/write） 20 ns tSHQZ Output Disable Time 6 ns tCLQX Output Hold Time 0 ns tDVCH Data In Setup Time 2 ns tCHDX Data In Hold Time 2 ns tHLCH /Hold Low Setup Time (relative to Clock) 5 ns tHHCH /Hold High Setup Time (relative to Clock) 5 ns tCHHL /Hold High Hold Time (relative to Clock) 5 ns tCHHH /Hold Low Hold Time (relative to Clock) 5 ns tHLQZ /Hold Low To High-Z Output 6 ns tHHQX /Hold Low To Low-Z Output 6 ns tCLQV Clock Low To Output Valid 7 ns tWHSL Write Protect Setup Time Before /CS Low 20 ns tSHWL Write Protect Hold Time After /CS High 100 ns tDP /CS High To Deep Power-Down Mode 0.1 µs tRES1 /CS High To Standby Mode Without Electr onic Signature Read 3 µs tRES2 /CS High To Standby Mode With Ele ctronic Signature Read 1.5 µs tSUS /CS High To Next Instruction After Suspend 2 us tW Write Status Register Cycle Time 10 15(2) ms tPP Page Programming Time 0.7 2.4 ms tSE Sector Erase Time 60 300 ms tBE Block Erase Time(32K Bytes/64K Bytes) 0.2/0.4 1/1.2 s tCE Chip Erase Time 7 18 s
ECT25S80 8M BIT SPI NOR FLASH Ordering Information & Marking Information ECT25S XX X XX X X Device Function 80＝8M bit R：Tape & Reel C：Commercial(0°C to +70°C) I:Industrial(-40°C to +85°C) M1：SOP-8(150mil) M2：SOP-8(208mil) P1：PDIP S：3V L：1.8V
ECT25S80 8M BIT SPI NOR FLASH
Package Information
SOP -8L(150mil)
ECT25S80 8M BIT SPI NOR FLASH SOP -8L(208mil)
ECT25S80 8M BIT SPI NOR FLASH