EC24C02A

EC24C02A E-CMOS | Alldatasheet

Document overview

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Technical content

Features

The EC24C02A/04A/08A/16A provides 2048/4096 /8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) org- anized as 256/512/1024/2048 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The EC24C02A/04A/08A/16A is available in space saving PDIP-8,SOP-8, TSSOP-8,MSOP8, DFN-8 and SOT23-5 packages and is accessed via a two- wire serial interface.  Wide Voltage Operation - VCC = 1.7V to 5.5V  Operating Ambient Temperature: -40°C to +85°C  Internally Organized: - EC24C02A, 256 X 8 (2K bits) - EC24C04A, 512 X 8 (4K bits) - EC24C08A, 1024 X 8 (8K bits) - EC24C16A, 2048 X 8 (16K bits)  Two-wire Serial Interface  Schmitt Trigger, Filtered Inputs for Noise Suppression  Bidirectional Data Transfer Protocol  1 MHz (5V), 400 kHz (1.7V, 2.5V, 2.7V) Compatibility  Write Protect Pin for Hardware Data Protection  8-byte Page (2K), 16-byte Page (4K, 8K,16K) Write Modes  Partial Page Writes Allowed  Self-timed Write Cycle (5 ms max)  High-reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years  PDIP-8,SOP-8, TSSOP-8,MSOP-8,DFN-8 and SOT23-5 packages Pin Configuration SOP-8 TSSOP-8 DFN-8 SOT23-5 (EC24C02A/04A/08A/16A) (EC24C02A/04A/08A/16A) (EC24C02A/04A/08A/16A) (EC24C02A/04A/08A) Top-View Top-View Bottom view Top-View PDIP-8 MSOP -8 (EC24C02A/04A/08A/16A) (EC24C02A/04A/08A/16A) Top-View Top-View Pin Name Functions A0 - A2 Address Inputs SDA Serial Data SCL Serial Clock Input WP Write Protect GND Ground VCC Power Supply

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Block Diagram

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Pin Descriptions DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard-wired for the EC24C02A. Eight 2K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). The EC24C04A uses the A2 and A1 inputs for hard -wired addressing and a total of f our 4K devices may be addressed on a single bus system. The A0 (P0) pin is a no connection or can be connected to ground. The EC24C08A only uses the A2 input for hard -wired addressing and a total of two 8K devices may be addressed on a single bus system. T he A0 (P0) and A1 (P1) pins are no connections or can be connected to ground. The EC24C16A does not use the device address pins, which limits the number of devices on a single bus to one. The A0 (P0), A1 (P1), and A2 (P2) pins are no connections or can be connected to ground. SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open -drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The EC24C02A/04A/08A/16A has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/wr ite operations when connected to ground (GND). When the Write Protect pin is connected to V CC, the write protection feature is enabled and operates as shown in the following. Write Protect WP Pin Status Part of the Array Protected EC24C02A EC24C04A EC24C08A EC24C16A At VCC Full (2K) Array Full (4K) Array Full (8K) Array Full (16K) Array At GND Normal Read / Write Operations

Ordering Information

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Available package types Part Number SOP-8 TSSOP-8 DFN-8 SOT23-5 MSOP-8 PDIP-8 EC24C02A V V V V V V EC24C04A V V V V V V EC24C08A V V V V V V EC24C16A V V V -- V V Marking Information Package type Part Number Marking Marking Information PDIP-8 EC24CXXANP1GX 24CXXA LLLLL YYWWT XX is the memory of production. LLLLL is the last five numbers of wafer lot number YYWW is Date Code. T is tracking Code ,T=X SOP-8 EC24CXXANM1GX TSSOP-8 EC24CXXANE1GX MSOP-8 EC24CXXANR1GX SOT23-5 EC24CXXANB2GX 24CXXA LLLLL XX is the memory of production. LLLLL is the last five numbers of wafer lot number DFN-8 EC24CXXANF2GX CXXA LLLL XX is the memory of production. LLLL is the last four numbers of wafer lot number Memory Organization EC24C02A, 2K SERIAL EEPROM: Internally organized with 32 pages of 8 bytes each, the 2K requires an 8-bit data word address for random word addressing. EC24C04A, 4K SERIAL EEPROM: Internally organized with 32 pages of 16 bytes each, the 4K requires a 9-bit data word address for random word addressing. EC24C08A, 8K SERIAL EEPROM: Internally organized with 64 pages of 16 bytes each, the 8K requires a 10-bit data word address for random word addressing. EC24C16, 16K SERIAL EEPROM: Internally organized with 128 pages of 16 bytes each, the 16K requires an 11-bit data word address for random word addressing. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL lo w time periods (see to Figure 1 ). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (see to Figure 2). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (see to Figure 2). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8 -bit words. The EEPROM sends a "0" to acknowledge that it has received each word. This happens during the ninth clock cycle (see to Figure 3).

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Figure 3: Output Acknowledge Device Addressing The 2K, 4K, 8K and 16K EEPROM devices all require an 8 -bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 2K EEPROM. These 3 bits must compare to their corresponding hard-wired input pins. The 4K EEPROM uses the A2 and A1 device address bits with the third bit being a mem ory page address bit. The two device address bits must compare to their corresponding hard -wired input pins. The A0 (P0) pin is no connection. The 8K EEPROM only uses the A2 device address bit with the next 2 bits being for memory page addressing. The A2 b it must compare to its corresponding hard -wired input pin. The A1 (P1) and A0 (P0) pins are no connections. The 16K does not use any device address bits but instead the 3 bits are used for memory page addressing. These page addressing bits on the 4K, 8K an d 16K devices should be considered the most significant bits of the data word address which follows. The A0 (P0), A1 (P1) and A2 (P2) pins are no connections. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. DATA SECURITY: The EC24C02A/04A/08A/16A has a hardware data protection scheme that allows the user to write protect the entire memory when the WP pin is at VCC. Write Operations BYTE WRITE: A write operation requires an 8 -bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8 -bit data word. Following receipt of the 8 -bit data word, the EEPROM will output a "0" and th e addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Figure 6: Page Write Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address a ccessed during the last read or write operation, increased by one. But for EC24C16A, only lower 8 bits of the internal data word address counter maintains the last address accessed, the higher 3 bits (P2, P1, P0) will follow the device address input at each current address read. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. T he microcontroller does not respond with an input "0" but does generate a following stop condition (see to Figure 7). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and da ta word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM a cknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a "0" but does generate a following stop condition (see to Figure 8). SEQUENTIAL READ: Sequential reads are initiated by either a current add ress read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data w ords. When the memory address limit is reached, the data word address will "roll over" and the sequential read will continue. Th e sequential read operation is terminated when the microcont roller does not respond with a "0" but does generate a following stop condition (see to Figure 9).

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM

Electrical Characteristics

Absolute Maximum Stress Ratings Comments Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exp osure to the absolute maximum rating conditions for extended periods may affect device reliability. Applicable over recommended operating range from: TA = -40°C to +85°C, VCC = +1.7V to +5.5V (unless otherwise noted) Parameter Symbol Min. Typ. Max. Unit Condition Supply Voltage VCC 1.7 5.5 V Supply Current VCC = 5.0V ICC1 0.4 1.0 mA READ at 400 kHz Supply Current VCC = 5.0V ICC2 2.0 3.0 mA WRITE at 400 kHz Standby Current ISB 3.0 μA VIN = VCC or GND Input Leakage Current ILI 3.0 μA VIN = VCC or GND Output Leakage Current ILO 0.05 3.0 μA VOUT = VCC or GND Input Low Level VIL1 -0.3 VCC x 0.3 V VCC = 1.8V to 5.5V Input High Level VIH1 VCC x 0.7 VCC + 0.3 V VCC = 1.8V to 5.5V Input Low Level VIL2 -0.3 VCC x 0.2 V VCC = 1.7V Input High Level VIH2 VCC x 0.7 VCC + 0.3 V VCC = 1.7V Output Low Level VCC =5.0V VOL3 0.4 V IOL = 3.0 mA Output Low Level VCC =3.0V VOL2 0.4 V IOL = 2.1 mA Output Low Level VCC =1.7V VOL1 0.2 V IOL = 0.15 mA Pin Capacitance Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.7V Parameter Symbol Min. Typ. Max. Unit Condition Input/Output Capacitance (SDA) CI/O - - 8 pF VI/O = 0V Input Capacitance (A0, A1, A2, SCL) CIN - - 6 pF VIN = 0V

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Applicable over recommended operating range from T A = -40°C to +85°C, VCC = +1.7V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Clock Frequency, SCL fSCL - - 400 - - 1000 kHz Clock Pulse Width Low tLOW 1.2 - - 0.6 - - μs Clock Pulse Width High tHIGH 0.6 - - 0.4 - - μs Noise Suppression Time tI - - 50 - - 40 ns Clock Low to Data Out Valid tAA 0.05 - 0.9 0.05 - 0.55 μs Time the bus must be free before a new transmission can start tBUF 1.2 - - 0.5 - - μs 1Start Hold Time tHD.STA 0.6 - - 0.25 - - μs Start Setup Time tSU.STA 0.6 - - 0.25 - - μs Data In Hold Time tHD.DAT 0 - - 0 - - μs Data In Setup Time tSU.DAT 100 - - 100 - - ns Inputs Rise Time(1) tR - - 0.3 - - 0.3 μs Inputs Fall Time(1) tF - - 300 - - 100 ns Stop Setup Time tSU.STO 0.6 - - 0.25 - - μs Data Out Hold Time tDH 50 - - 50 - - ns Write Cycle Time tWR - 1.5 5 - 1.5 5 ms 5.0V, 25°C, Byte Mode Endurance 1M - - - - - Write Cycles Note 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: RL (connects to VCC): 1.3kΩ (2.5V, 5V), 10kΩ (1.7V) Input pulse voltages: 0.3 x VCC to 0.7 x VCC Input rise and fall time: ≦50 ns Input and output timing reference voltages: 0.5 x VCC The value of RL should be concerned according to the actual loading on the user's system.

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Mechanical Dimensions OUTLINE DRAWING PDIP - 8 Available package types : EC24C02A/04A/08A/16A Top View Side View Section B - B End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A 3.60 4.00 A1 0.51 - A2 3.10 3.50 A3 1.50 1.70 b 0.44 0.53 b1 0.43 0.48 B 1.52 BSC c 0.25 0.31 c1 0.24 0.26 D 9.05 9.45 E1 6.15 6.55 e 2.54 BSC eA 7.62 BSC eB 7.62 9.50 eC 0 0.94 L 3.00 -

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Mechanical Dimensions OUTLINE DRAWING SOP- 8 Available package types：EC24C02A/04A/08A/16A Top View End View Side View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A 1.35 1.75 A1 0.10 0.25 B 0.31 0.51 C 0.17 0.25 D 4.70 5.10 E1 3.80 4.00 E 5.79 6.20 e 1.27 BSC L 0.40 1.27 θ 0° 8°

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Mechanical Dimensions OUTLINE DRAWING TSSOP-8 Available package types：EC24C02A/04A/08A/16A Top View End View Side View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX D 2.80 3.20 E 6.20 6.60 E1 4.20 4.60 A - 1.20 A2 0.80 1.15 b 0.19 0.30 e 0.65 BSC L 0.45 0.75 L1 1.00 BSC θ 0° 8°

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Mechanical Dimensions OUTLINE DRAWING DFN-8 Available package types：EC24C02A/04A/08A/16A Top View End View Side View Bottom View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A 0.70 0.80 A1 - 0.05 b 0.18 0.30 c 0.18 0.25 D 1.90 2.10 D2 1.50 REF e 0.50 BSC Nd 1.50 BSC E 2.90 3.10 E2 1.60 BSC L 0.30 0.50 h 0.20 0.30

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Mechanical Dimensions OUTLINE DRAWING MSOP-8 Available package types : EC24C02A/04A/08A/16A Top View Side View Section B -B End View COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A - 1.10 A1 0.05 0.15 A2 0.75 0.95 A3 0.30 0.40 b 0.29 0.38 b1 0.28 0.33 c 0.15 0.20 c1 0.14 0.16 D 2.90 3.10 E 4.70 5.10 E1 2.90 3.10 e 0.65 BSC L 0.40 0.70 L1 0.95 BSC θ 0° 8°

2K/4K/8K/16K-bit 2-WIRE SERIAL CMOS EEPROM Mechanical Dimensions OUTLINE DRAWING SOT23-5 Available package types：EC24C02A/04A/08A Top View End View Side View Section B-B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN MAX A 1.05 1.30 A1 0 0.10 A2 1.00 1.20 A3 0.55 0.75 b 0.30 0.50 b1 0.33 0.38 c 0.10 0.21 c1 0.14 0.16 D 2.72 3.12 E 2.60 3.00 E1 1.40 1.80 e 0.95 BSC L 0.30 0.60 θ 0° 8°