EC8320 E-CMOS | Alldatasheet
Document overview
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Technical content
Features
- Adjustable Output Low to 0.8V
- Input Voltage as Low as 1.6V and VPP Voltage 5V
- 240mV Dropout @ 2A
- Over Current and Over Temperature Protection
- Enable Pin
- Low Reverse Leakage (Output to Input )
- Power SOP-8(EP) Packages with Thermal Pad
- ±2% Output Voltage
- VO Power OK Signal
- 1.2V, 1.5V, 1.8V, 2.5V Options and Adjustable
- Externally Using Resistors
- VO Pull Low Resistance when Disable
Applications
- Motherboards
- Peripheral Cards
- Network Cards
- Set Top Boxes
- Notebook Computers Pin Assignments
2A Low Dropout Regulator with Enable EC8320 Pin Description
Ordering Information
1 PGOOD Assert high once VO reaches 92% of its rating voltage. Open-drain output. 2 EN Enable Input. (Active High) 3 VIN Input voltage. Large bulk capacitance should be placed closely to this pin. A 10µF ceramic capacitor is recommended at this pin. 4 VDD Input voltage for controlling circuit. 5 NC Not connected. 6 VOUT The power output of the device. A pull low resistance exists when deactivate device by VEN.
7 ADJ This pin, EC8320A/B when grounded, sets the output voltage by the internal
feedback resistors.If external feedback resistors are used, the output voltage will be VO = 0.8(R1+R2)/R2 Volts. 8 GND Reference ground. Part Number Package Marking Marking Information EC8320AXXMHR SOP-8 (Exposed PAD) 8320A XXLLL YYWWT 1.XX: Output Voltage(Ex- 12:1.2V;AJ:ADJ) 2. LLL: Last three number of Lot No 3. YYWW: Date Code 4. T: Internal Tracking Code EC8320BXXMHR 8320B XXLLL YYWWT
Figure 1. Package Types of EC8320
2A Low Dropout Regulator with Enable EC8320 Absolute Maximum Ratings Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operationof the device at these or any other conditions above those indicated in the operation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Parameter Rating Unit VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 6 V VIN Supply Voltage (VIN to GND) -0.3 ~ 6 V VOUT to GND Voltage -0.3 ~ VIN+0.3 V PGOOD to GND Voltage -0.3 ~ 7 V EN, ADJ to GND Voltage -0.3 ~ VCNTL+0.3 V Power Dissipation Internally Limited Maximum Junction Temperature 150 ℃ Storage Temperature Range -65°C ≤TJ ≤ +150 ℃ Lead Temperature (soldering, 10sec) 260 ℃ Thermal Resistance Junction to Ambient 50 ℃/W Thermal Resistance Junction to Case 20 ℃/W Operating Temperature Range -40 to +125 ℃ Storage Temperature -65 to +150 ℃ ESD Rating (Human Body Model) 2000 V Symbol Parameter Range Unit VDD VCNTL Supply Voltage 3.0 ~ 5.5 V VIN VIN Supply Voltage 1.2 ~ 5.5 V VOUT VOUT Output Voltage (when VCNTL-VOUT>1.7V) 0.8 ~ VIN – VDROP V IOUT VOUT Output Current 0~2 A R2 ADJ to GND 1K ~ 24K Ω COUT VOUT Output Capacitance IOUT = 2A at 25% nominal VOUT 8~770 uF IOUT = 1A at 25% nominal VOUT 8~1400 IOUT = 0.5A at 25% nominal VOUT 8~1700 ESRCOUT ESR of VOUT Output Capacitor 0 ~ 200 mΩ TA Ambient Temperature -40 ~ 85 ºC TJ Junction Temperature -40 ~ 125 ºC
2A Low Dropout Regulator with Enable EC8320
Electrical Characteristics
Note:Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.8V, VOUT=1.2V, and TA= -40 ~ 85℃, unless otherwise specified.Typical values are at TJ=25℃. Symbol Parameter Test Conditions Min. Typ. Max. Unit POR Threshold 2.4 2.7 3 V POR Hysteresis 0.15 0.2 V VTH_ADJ Adjustable Pin Threshold IOUT=1mA 0.2 0.4 V VADJ Reference Voltage IOUT=1mA 0.784 0.8 0.816 V ΔVOUT Fixed Output Voltage Range -2 0 +2 % ΔVLINE_IN Line Regulation(VIN) VIN=VOUT+0.5V TO 5V IOUT=1mA 0.2 0.6 % ΔVLOAD Load Regulation VIN=VOUT+1V IOUT=1mA TO 2A 0.1 1 % VDROP Dropout Voltage IOUT= 2A 150 250 mV IQ Quiescent Current VDD=5.5V 0.6 1.2 mA ILIM Current Limit 2.8 3.2 A Short Circuit Current VOUT<0.2V 0.5 1.8 A In-rush Current COUT=10uF,Enable Start-up 0.6 A VOUT Pull-Low Resistance VEN=0V 150 Ω Chip Enable IEN EN Input Bias Current VEN=0V 12 uA ISHDN VDD Shutdown Current EC8320A 10 20 uA EC8320B 1 VENL EN Threshold Logic-Low Voltage - - 0.2 V Logic-High Voltage 1.2 Power Good PGOOD Rising Threshold 90 93 % PGOOD Hysteresis 3 10 - % PGOOD Sink Capability IPGOOD=10mA 0.2 0.4 V PGOOD Delay 0.5 1.5 5 mS Thermal Protection TSD Thermal Shutdown Temperature - 160 - ℃ ΔTSD Thermal Shutdown Hysteresis - 30 - ℃ Thermal Shutdown Temperature Fold-back VOUT<0.4V - 110 - ℃
2A Low Dropout Regulator with Enable EC8320 Typical Operating Characteristics Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current Current-Limit vs. Junction Temperature Short Current-Limit vs. Junction Temperature
2A Low Dropout Regulator with Enable EC8320 Typical Operating Characteristics(Cont.) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current Reference Voltage vs. Junction Temperature
2A Low Dropout Regulator with Enable EC8320 Typical Operating Characteristics(Cont.) VCNTL Power Supply Rejection Ratio(PSRR) VIN Power Supply Rejection Ratio(PSRR)
2A Low Dropout Regulator with Enable EC8320 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25℃ unless otherwise specified Power On Power Off COUT=10uF, CIN=10uF, RL=0.6Ω/TIME: 5ms/Div COUT=10uF, CIN=10uF, RL=0.6Ω / TIME: 10ms/Div CH1: VCNTL, 5V/Div, DC/CH2: VIN, 1V/Div, DC CH1: VCNTL, 5V/Div, DC/CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC/CH4: VPOK, 5V/Div, DC CH3: VOUT, 1V/Div, DC/CH4: VPOK, 5V/Div, DC Load Transient Response Over Current Protection IOUT=10mA to 2A to 10mA (rise / fall time = 1us) COUT=10uF, CIN=10uF COUT=10mF, CIN=10mF, IOUT=1A to 3.4A CH1: VOUT, 50mV/Div, AC/CH4: IOUT, 1A/Div, DC/ TIME: 20us/Div CH1: VOUT, 1V/Div, DC/ CH4: IOUT, 1A/Div, DC/ TIME: 0.2ms/Div
2A Low Dropout Regulator with Enable EC8320 Operating Waveforms(Cont.) Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25℃ unless otherwise specified Shutdown Enable COUT=10mF, CIN=10mF, RL=0.6W/ TIME: 5us/Div COUT=10mF, CIN=10mF, RL=0.6W/ TIME: 0.5ms/Div CH1: VEN, 5V/Div, DC/CH2: VOUT, 1V/Div, DC CH1: VEN, 5V/Div, DC/CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC/CH4: IOUT, 2A/Div, DC CH3: VPOK, 5V/Div, DC/CH4: IOUT, 2A/Div, DC
2A Low Dropout Regulator with Enable EC8320 Typical Application Circuit Figure3:Fixed Voltage Regulator Application Circuit of EC8320A/B Figure4:Adjustable Voltage Regulator Application Circuit of EC8320A/B
2A Low Dropout Regulator with Enable EC8320 Function Description PowerOn Reset A Power-On-Reset (POR) circuit monitors both of supply voltages on VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process after both of the supply voltages exceed their rising POR voltage thresholds during powering on. The POR function also pulls low the POK voltage regardless of the output status when one of the supply voltages falls below its falling POR voltage threshold. Internal Soft Start An internal soft-start function controls rise rate of the Output voltage to limit the current surge during start-up. The typical soft-start interval is about 0.6ms. Output Voltage Regulation An error amplifier working with a temperature compensated 0.8V reference and an output NMOS regulates output to the preset voltage. The error amplifier is designed with high bandwidth and DC gain provides very fast transient response and less load regulation. It compares the reference with the feedback voltage and amplifies the difference to drive the output NMOS which provides load current from VIN to VOUT. Current Limit Protection The EC8320 monitors the current flowing through the output NMOS and limits the maximum current to prevent load and EC8320 from damages during current overload conditions. Short Current Limit Protection The short current-limit function reduces the current-limit level down to 0.8A (typical) when the voltage on ADJ pin falls below 0.2V (typical) during current overload or shortcircuit conditions. The short current-limit function is disabled for successful start-up during soft-start. Thermal Shutdown A thermal shutdown circuit limits the junction temperature of EC8320. When the junction temperature exceeds +170 ℃, a thermal sensor turns off the output NMOS, allowing the device to cool down. The regulator regulates the output again through initiation of a new soft-start process after the junction temperature cools by 50℃, resulting in a pulsed output during continuous thermal overload conditions. The thermal shutdown is designed with a 50 ℃ hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. For normal operation, the device power dissipation should be externally limited so that junction temperatures will not exceed +125 ℃. Enable Control The EC8320A/B has a dedicated enable pin (EN). EC8320A:A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (5uA typical) to enable normal operation. It’s not necessary to use an external transistor to Save Cost.
2A Low Dropout Regulator with Enable EC8320 Function Description(Cont.) EC8320B: A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (5uA typical) to turn off operation. PowerOK and Delay The EC8320 indicates the status of the output voltage by monitoring the feedback voltage (VADJ) on ADJ pin. As the VADJ rises and reaches the rising Power-OK voltage threshold(VTHPOK), an internal delay function starts to work. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is ok. As the VADJ falls and reaches the falling Power-OK voltage threshold, the IC turns on the NMOS of the POK ( after a debounce time of 10ms typical ).
2A Low Dropout Regulator with Enable EC8320
Application Information
The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. Output Capacitor The EC8320 requires a proper output capacitor to maintain stability and improve transient response. The output capacitor selection is dependent upon ESR (equivalent series resistance) and capacitance of the output capacitorover the operating temperature. u Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) can all be used as output capacitors. During load transients, the output capacitors which is depending on the stepping amplitude and slew rate of load current, are used to reduce the slew rate of the current seen by the EC8320 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors must be placed at the load and ground pins as close as possible and the impedance of the layout must be minimized. Input Capacitor The EC8320 requires proper input capacitors to supply current surge during stepping load transients to prevent the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors can all be used as an input capacitor of VIN. For most applications, the recommended input capacitance of VIN is 10uF at least. However, if the drop of the input voltage is not cared, the input capacitance can be less than 10uF. More capacitance reduces the variations of the supply voltage on VIN pin. Setting The Output Voltage The output voltage is programmed by the resistor divider connected to ADJ pin. The preset output voltage is calculated by the following equation : where R1 is the risistor connected from VOUT to ADJ with Kelvin sensing connection and R2 is the risistor connected from ADJ to GND. A bypass capacitor(C1) may be connected with R1 in parallel to improve load transient response and stability. o
2A Low Dropout Regulator with Enable EC8320 Layout Consideration(See Figure A) 1. Please solder the Exposed Pad on the system ground pad on the top-layer of PCBs. The ground pad must have wide size to conduct heat into the ambient air through the system ground plane and PCB as a heat sink. 2. Please place the input capacitors for VIN and VCNTL pins near the pins as close as possible for decoupling high-frequency ripples. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible for decoupling high-frequency ripples. 4. To place EC8320 and output capacitors near the load reduces parasitic resistance and inductance for excellent load transient response. 5. The negative pins of the input and output capacitors and the GND pin must be connected to the ground plane of the load. 6. Large current paths, shown by bold lines on the figure A, must have wide tracks. 7. Place the R1, R2, and C1 (option) near the EC8320 as clos as to avoid noise coupling. 8. Connect the ground of the R2 to the GND pin by using a dedicated track. 9. Connect the one pin of the R1 to the load for Kelvin sensing. 10. Connect one pin of the C1 (option) to the VOUT pin Figure A. Thermal Consideration Refer to the figure B, the SOP-8(EP) is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications The exposed pad must be soldered to the top-layer ground plane. It is recommended to connect the top-layer ground pad to the internal ground plan by using vias. The copper of the ground plane on the top-layer conducts heat into the PCB and ambient air. Please enlarge the area of the top-layer pad and the ground plane to reduce the case-to-ambient resistance (θCA). Figure B.
2A Low Dropout Regulator with Enable EC8320
Package Information
SOP-8(Exposed PAD) Package Outline Dimensions