DS1220AB-200-IND

DS1220Y ARTSCHIP | Alldatasheet

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Technical content

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FEATURES

.10 years minimum data retention in the absence of external power .Data is automatically protected during power loss .Directly replaces 2k x 8 volatile static RAM of EEPROM .Unlimited write cycles .Low-power CMOS .JEDEC standard 24-pin DIP package .Read and write access times as fast as 100ns .Full ±10% operating range .Optional industrial temperature range of -40 ¥ to +85 ¥, designated IND PIN ASSIGNMENT 24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A10 -Address Inputs DQ0-DQ7 -Data In/Data Out - C h i p E n a b l e -Write Enable - O u t p u t E n a b l e V c c - P o w e r ( + 5 V ) GND -Ground

DESCRIPTION

The DS1220Y 16K Nonvolatile SRAM is a 16, 384-bit, fully static, nonvolatile RAM organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors Vcc for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and wr ite protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 2K x 8 SRAMs dire ctly conforming to the popular bytewide 24-pin DIP standard. The DS1220Y also matches the pinout of t he 2716 EPROM or the 2816 EEPROM, allowing direst substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. READ MODE The DS1220Y executes a read cycle whenever (Write Enable) is inactive (high) and (Chip Enable) and (Output Enable) are active (low). The unique address specified by the 11 address inputs (A0-A10) defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within t ACC (Access Time) after the last address input signal is stable, providing the and access times are also satisfied. If and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either t CO f o r or t OE for rather than address access. WRITE MODE The DS1220Y executes a write cycle whenever the and signals are active (low) after address inputs are stable. The later-occurring falling earlier rising edge of or . All address inputs must be kept valid throughout the write cycle. must return to the high state for a minimum recovery time (t WR) before another cycle c an be initiated. The control signal should be kept inactive (high) during write cycles to avoid bus cont ention. However, if the out put drivers are enabled ( and active) then will disable the outputs in tODW from its falling edge.

www.artschip.com 2 DATA RETENTION MODE The DS1220Y provides full-functional capability for Vcc greater than 4.5 volts and write protects at 4.25 nominal. Data is maintained in the absence of Vcc without any additional support circuitry. T he DS1220Y constantly monitors Vcc. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As Vcc falls below approximately 3.0 volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power -up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects exte rnal Vcc to RAM and disconnects the lith ium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts. ABSOLUTE MAXIMUM RATINGS* Voltage on Any Pin Relative to Ground -0.3V to +7.0V O p e r a t i n g T e m p e r a t u r e 0¥ to 70 ¥; -40¥ to +85 ¥ for IND parts Storage Temperature -40 ¥ to +70 ¥; -40¥ to +85 ¥ for IND parts S o l d e r i n g T e m p e r a t u r e 2 6 0¥ for 10 seconds * This is a stress rating only and function al operation of the device at these or any other condit ions above those indicated in the operation sections of this specif ication is not implied. Exposure to absolute ma ximum rating conditions for extended periods of time may affect reliability. RECOMMENDED DC OPERATING CONDITIONS ( T A : S e e N o t e 1 0 ) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Power Supply Voltage Vcc 4.5 5.0 5.5 V Input Logic 1 V IH 2.2 Vcc V Input Logic 0 V IL 0.0 +0.8 V DC ELECTRICAL CHARACTERISTICS ( T A:See Note 10; Vcc=5V ±10%) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Leakage Current I IL -1.0 +10 µA I/O Leakage Current ≥VIH ≤ Vcc IIO -10 +1.0 µA Output Current @ 2.4 V I OH -1.0 mA Output Current @ 0.4V I OL 2.0 mA Standby Current =2.2V ICCSI 3.0 7.0 mA Standby Current =Vcc-0.5V ICCS2 2.0 4.0 mA Operating Current tCYC =200ns (Commercial) Icco1 75 mA Operating Current tCYC=200ns (Industrial) Icco1 85 mA Write Protection Voltage V TP 4.25 V CAPACITANCE ( T A=25¥) PARAMETER SYMBOL MIN TYP MAX UNITS NOTES Input Capacitance C IN 5 10 pF Input/Output Capacitance C I/O 5 12 pF

www.artschip.com 3 AC ELECTRICAL CHARACTERISTICS ( T A: See Note 10; Vcc =5.0V ±10%) DS1220Y-100 DS1220Y-120 DS1220Y-150 DS1220Y-200 PARAMETER SYM MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTE Read Cycle Time t RC 100 120 150 200 ns Access Time t ACC 100 120 150 200 ns to Output Valid tOE 50 60 70 100 ns to Output Valid tCO 100 120 150 200 ns or to Output Active tCOE 5 5 5 5 ns 5 Output High Z From Deslection tOD 35 35 35 35 ns 5 Output Hold from Address Change tOH 5 5 5 5 ns Write Cycle Time t WC 100 120 150 200 ns Write Pulse Width t WP 75 90 100 150 ns 3 Address SetupTime t AW 0 0 0 0 ns Write Recovery Time t WR1 tWR2 ns ns Output High Z from tODW 35 35 35 35 ns 5 Output Active from tOEW 5 5 5 5 ns 4 Data Setup Time t DS 40 50 60 80 ns 4 Data Hold Time t DH1 tDH2 ns ns READ CYCLE SEE NOTE1

www.artschip.com 4 WRITE CYCLE 1 SEE NOTES 2,3,4,6,7,8 AND 12 WRITE CYCLE 2 SEE NOTE 2,3,4,6,7,8 AND 13

www.artschip.com 5 POWER-DOWN/POWER-UP CONDITION SEE NOTE 11 POWER-DOWN/POWER-UP TIMING PARAMETER SYMBOL MIN MAX UNITS NOTES at V IH before Power-Down tPD 0 µs 11 VCC Slew from VTP to 0V t F 100 µs Vcc Slew from 0V to VTP t R 0 µs at V IH after Power -Up tREC 2 ms (TA=25¥) PARAMETER SYMBOL MIN MAX UNITS NOTES Expected Data Retention Time t DR 10 years 9 WARNING: Under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. NOTES: is high for a read cycle. = V IH or VIL. If = V IH during a write cycle, the output buffers remain in a high impedance state. 3.tWP is specified as the logical AND of and . tWP is measured from the latter of or going low to the earlier of or going high. 4.tDS are measured from the earlier of or going high. 5.These parameters are sampled with a 5 pF load and are not 100% tested. 6.If the low transition occurs simultaneously with or later than the low transition in write cycle 1, the output buffers remain in a high impedance state during this period. 7.If the high transition occurs prior to or simultaneously with the high transition, the output buffers remain in a high impedance state during this period. 8.If is low or the low transition occurs prior to or simultaneously with the low transition, the output buffers remain in a high impedance state during this period. 9.Each DS1220Y is marked with a 4-digit date code AABB. AA des ignates the year of manufactu re. BB designates the week of manufacture. The expected tDR is defined as starting at the date of manufacture.

www.artschip.com 6 10.All AC and DC electrical characteristics are valid over the full operating temperature range. For commercial products, this range is 0 ¥ to 70 ¥. For industrial products (IND), this range is -40¥ to +85 ¥. 11. In a power-down condition the voltage on any pin may not exceed the voltage of Vcc. 12.tWR1, tDH1 are measured from going high. 13.tWR2,tDH2 are measured from going high. 14.DS1220Y modules are recognized by Underwriters Laboratory (U.L ®) under file E99151 (R). DC TEST CONDITIONS Outputs open. All voltages are referenced to ground. AC TEST CONDITIONS Output Load: 100pF +1TTL Gate Input Pulse Levels: 0-3.0V Timing Measurement Reference Levels Input: 1.5V Output 1.5V Input Pulse Rise and Fall Times: 5ns

ORDERING INFORMATION

www.artschip.com 7 DS1220Y NONVOLATILE SRAM,24-PIN 720-MIL EXTENDED MODULE