DM7800 NSC | Alldatasheet

Document overview

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Technical content

.... Q Level Translators/Buffers DM7800/DM8800 dual voltage translator general description The DM7800/DM8800 are dual voltage translators designed for interfacing between conventional TTL or DTL voltage levels and those levels associated with high impedance junction or MOS FET-type devices_ The design allows the user a wide latitude in his selection of power supply voltages, thus pro­ viding custom control of the output swing. The translator is especially useful in analog switching; and since low power dissipation occurs in the "off" state, minimum system power is required.

features

  • 31 volt (max) output swing
  • 1 mW power dissipation in nor~al state
  • Standard 5V power supply
  • Temperature range: DM7800 DM8800 _55°C to +125°C O°C to +70°C
  • Compatible with all MOS devices schematic and connection diagrams typical applications 4-Channel Analog Switch on OR TTL INPUT LEVElS rlOi ___ 4.l...,1 MM&51 I I ANALOG INPUT t·I I FO..r---.cCO I I ANALOG INPUT 2 I ANAlOGINPUTl ANALOG INPUT 4 ANALOG OUTPUT I ... Analog sllJIlals wlthm the range of +8V to -BV Metal Can Package OUTPUT X TOI'VIEW Order Number DM7800H or DM8800H See Package 12 Bipolar to MOS I nteriacing rJ---0 on~MOSS"IFT OR REGISTER TTL OMJlOO I INPUT~~ lEVElS~ L1---r ':'" -IOV

Vee Supply Voltage 7.aV V 2 Supply Voltage -3aV V 3 Supply Voltage +3aV V 3,V2 Voltage Differential 4aV Input Voltage 5.5V Storage Temperature Range _65°C to +15aoC Operating Temperature Range DM78aa _55°C to +125°C DM88aa aOc to 7aoC Lead Temperature (Soldering, 1a sec) 3aaOc electrical characteristics (Note 1) PARAMETER CONDITIONS MIN TYP MAX UNITS (Note 4) Logical "1" Input Voltage DM78aa Vee ~ 4.5V 2.a DM88aa Vee ~ 4.75V V Logical "a" Input Voltage DM78aa Vee ~ 4.5V a.8 V DM88aa Vee - 4.75V Logical" 1" I nput Current DM78aa Vee ~ 5.5V Y'N ~ 2.4V 5 p.A DM88aa Vee~ 5.25V Logical "1" Input Current DM78aa Vee ~ 5.5V Y,N ~ 5.5V 1 mA DM88aa Vee - 5.25V Output Leakage Current (Note 2) DM78aa Vee ~ 5.5V Y'N ~ a.8V (Note 5) 1a p.A DM88aa Vee - 5.25V Output Collector Resistor TA ~ 25°C 11.5 16.a 2a.a kn Logical "a" Output Voltage DM78aa Vee = 4.5V Y'N = 2.aV (Note 5) V 2 + 2.a V DM88aa Vee ~ 4.75V Power Supply Current DM78aa Vee = 5.5V Logical "a" (Note 3) Y,N ~ 4.5V a.85 1.6 mA (Each Gate) DM88aa Vee = 5.25V Power Supply Current DM78aa Vee ~ 5.5V Logical" 1" (Note 3) Y'N ~ av a.22 a.41 mA (Each Gate) DM88aa Vee ~ 5.25V Transition Time to Logical "a" Output TA ~ 25°C C ~ 15 pF (Note 6) 25 70 125 ns Transition Time to Logical "1" Output TA ~ 25°C C ~ 15 pF (Note 7) 25 62 125 ns Note 1: Minimax limits apply across the guaranteed temperature range of -55°C to +12So,C for the DM7800 and oOe to +70°C for the DM8800 unless otherwise specified. Note 2: Current measured IS ~rawn from V3 supply. Note 3: Current measured IS drawn from Vee supply. Note 4: All typical values are measured at T A = 2Soe with Vee = S.OV, V2 = -22V, V3 = +8V. Note 5: SpeCification applies for all allowable values of V2 and V3. Note 6: Measured from 1.5V on Input to 50% level on output. Note 7: Measured from 1.SV on Input to logic "0" voltage, plus lV. 2·11 c s: o o

Q o o CO .... Q 2-12 theory of operation The two input diodes perform the AND function on TTL or DTL input voltage levels. When at least one input voltage is a 10gicar"0", current from Vee (nominally 5.0V) passes through R 1 and out the input(s) which is at the low voltage. Other than small leakage currents, this current drawn from Vee through the 20 kn resistor is the on Iy source of power dissipation in the logical "1" output state. When both inputs are at logical" 1" levels, current passes through R 1 and diverts to transistor 0 1 , turn· ing it on and thus pulling current through R 2. Cur­ rent is then supplied to the PNP transistor, O 2 , The voltage losses caused by current through 0 1, D 3, and O 2 necessitate that node P reach a voltage suf­ ficient to overcome these losses before current be­ gins to flow. To achieve this voltage at node P, the inputs must be raised to a voltage level which is one diode potential lower than node P. Since these levels are exactly the same as those experienced with con­ ventional TTL and DTL, the interfacing with these types of circuits is achieved. Transistor O 2 provides "constant current switch­ ing" to the output due to the common base con­ nection of O 2, When at least one input is at the logical "0" level, no current is delivered to O 2; so that its collector supplies essentially zero current to the output stage. But when both inputs are raised to a logical "1" level current is supplied to O 2 , selecting power supply voltage The graph shows the boundary conditions which must be used for proper operation of the unit. The range of operation for power supply V 2 is shown on the X axis_ It must be between -25V and -8V. The allowable range for power supply V 3 is gov­ erned by supply V 2. With a value chosen for V 2, V 3 may be selected as any value along a vertical line passing through .the V 2 value and terminated by the boundaries of the operating region. A voltage difference between power supplies of at least 5V should be maintained for adequate signal swing. switching time waveforms INPUT OUTPUT---t-'"\\ Since this current is relatively constant, the collec­ tor of O 2 acts as a constant current source for the output stage. Logic inversion is performed since logIcal "1" input voltages cause current to be sup­ plied to O 2 and to 0 3, And when 0 3 turns on the output voltage drops to the logical "0" level. The reason for the PNP current source, O 2 , is so that the output stage can be driven from a high impedance. This allows voltage V 2 to be adjusted in accordance with the application. Negative volt­ ages to -25V can be applied to V 2' Since the out­ put will neither source nor sink large amounts of current, the output voltage range is almost exclu­ sively dependent upon the values selected for V 2 and V 3 . Maximum leakage current through the output tran­ sistor 0 3 is specified at 10 J1A under worst-case voltage between V 2 and V 3. This will result in a logical "1" output voltage which is 0.2V below V 3. Likewise the clamping action of diodes D 4, D s, and D 6, prevents the logical "0" output voltage from falling lower than 2V above V 2, thus establishing the output voltage swing at typically 2 volts less than the voltage separation between V 2 and V 3' 1_ 10V ----+--~-,-'--~