DAC1006 NSC | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 22
Technical content
Features
Y Uses easy to adjust END POINT specs, NOT BEST STRAIGHT LINE FIT Y Low power consumption Y Direct interface to all popular microprocessors Y Integrated thin film on CMOS structure Y Double-buffered, single-buffered or flow through digital data inputs Y Loads two 8-bit bytes or a single 10-bit word Y Logic inputs which meet TTL voltage level specs (1.4V logic threshold) Y Works with g10V referenceÐfull 4-quadrant multiplica- tion Y Operates STAND ALONE (without mP) if desired Y Available in 0.3 × standard 20-pin package Y Differential non-linearity selection available as special order Key Specifications Y Output Current Settling Time 500 ns Y Resolution 10 bits Y Linearity 10, 9, and 8 bits (guaranteed over temp.) Y Gain Tempco b0.0003% of FS/ §C Y Low Power Dissipation 20 mW (including ladder) Y Single Power Supply 5 to 15 V DC Typical Application DAC1006/1007/1008 * NOTE: FOR DETAILS OF BUS CONNECTION SEE SECTION 6.0 TL/H/5688–1 C1995 National Semiconductor Corporation RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes1&2 ) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage (V CC)1 7 V DC Voltage at Any Digital Input V CC to GND Voltage at V REF Input g25V Storage Temperature Range b65§Ct o a150§C Package Dissipation at T Ae25§C (Note 3) 500 mW DC Voltage Applied to I OUT1 or I OUT2 (Note 4) b100 mV to V CC ESD Susceptibility (Note 11) 800V Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260 Dual-In-Line Package (ceramic) 300 §C Operating Ratings (Note 1) Temperature Range T MIN s TA s TMAX Part numbers with ‘‘LCN’’ and ‘‘LCWN’’ suffix 0 §Ct o7 0 §C Voltage at Any Digital Input V CC to GND
Electrical Characteristics
Tested at V CC e 4.75 V DC and 15.75 V DC,T Ae25§C, V REFe10.000 V DC unless otherwise noted See VCCe12VDCg5% VCCe5VDCg5%Parameter Conditions Note to 15V DCg5% Units Resolution 10 10 bits Linearity Error Endpoint adjust only 4,7 TMINkTAkTMAX 6 b10VsVREFsa10V 5 DAC1006 0.05 0.05 % of FSR DAC1007 0.1 0.1 % of FSR DAC1008 0.2 0.2 % of FSR Differential Endpoint adjust only 4,7 Nonlinearity T MINkTAkTMAX 6 b10VsVREFsa10V 5 DAC1006 0.1 0.1 % of FSR DAC1007 0.2 0.2 % of FSR DAC1008 0.4 0.4 % of FSR Monotonicity T MINkTAkTMAX 4,6 b10VsVREFsa10V 5 DAC1006 10 10 bits DAC1007 9 9 bits DAC1008 8 8 bits Gain Error Using internal R fb Gain Error Tempco T MINkTAkTMAX 6 Using internal R fb 9 b0.0003 b0.001 b0.0006 b0.002 % of FS/ §C Power Supply All digital inputs Rejection latched high VCCe14.5V to 15.5V 0.003 0.008 % FSR/V 11.5V to 12.5V 0.004 0.010 % FSR/V 4.75V to 5.25V 0.033 0.10 % FSR/V Reference Input Resistance 10 15 20 10 15 20 k X Output Feedthrough V REF e 20Vp-p,f e100 kHz Error All data inputs 90 90 mV p-p latched low Output I OUT1 All data inputs 60 60 pF Capacitance I OUT2 latched low 250 250 pF IOUT1 All data inputs 250 250 pF IOUT2 latched high 60 60 pF Supply Current Drain T MINsTAsTMAX 6 0.5 3.5 0.5 3.5 mA
Tested at V CC e 4.75 V DC and 15.75 V DC,T Ae25§C, V REFe10.000 V DC unless otherwise noted (Continued) See VCCe12VDCg5% VCCe5VDCg5%Parameter Conditions Note to 15V DCg5% Units Output Leakage T MINsTAsTMAX 6 Current I OUT1 All data inputs latched low 10 200 200 nA IOUT2 All data inputs latched high 200 200 nA Digital Input T MINsTAsTMAX 6 Voltages Low level LCN and LCWM suffix 0.8, 0.8 0.7, 0.8 V DC High level (all parts) 2.0 2.0 V DC Digital Input T MINsTAsTMAX 6 Currents Digital inputs k0.8V b40 b150 b40 b150 mADC Digital inputs l2.0V 1.0 a10 1.0 a10 mADC Current Settling t S VILe0V, V IHe5V 500 500 ns Time Write and XFER tW VILe0V, V IHe5V, Pulse Width T Ae25§C 8 150 60 320 200 ns TMINsTAsTMAX 9 320 100 500 250 ns Data Set Up Time t DS VILe0V, V IHe5V, TAe25§C 9 150 80 320 170 ns TMINsTAsTMAX 320 120 500 250 ns Data Hold Time t DH VILeOV, V IHe5V TAe25§C 9 200 100 320 220 ns TMINsTAsTMAX 250 120 500 320 ns Control Set Up t CS VILe0V, V ILe5V, Time T Ae25§C 9 150 60 320 180 ns TMINsTAsTMAX 320 100 500 260 ns Control Hold Time t CH VILe0V, V IHe5V, TAe25§C 9 10 0 10 0 ns TMINsTAsTMAX 10 0 10 0 ns Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device beyond its specified operating conditions. Note 2: All voltages are measured with respect to GND, unless otherwise specified. Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify the power dissipation) removes concern for heat sinking. Note 4: For current switching applications, both I OUT1 and I OUT2 must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier. The linearity error is degraded by approximately V OSdVREF. For example, if V REFe1 0 Vt h e na1m V offset, V OS,o nI OUT1 or I OUT2 will introduce an additional 0.01% linearity error. Note 5: Guaranteed at V REFeg10 V DC and V REFeg1V DC. Note 6: TMINe0§C and T MAXe70§C for ‘‘LCN’’ and ‘‘LCWM’’ suffix parts. Note 7: The unit ‘‘FSR’’ stands for ‘‘Full Scale Range.’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on a particular V REF value and to indicate the true performance of the part. The ‘‘Linearity Error’’ specification of the DAC1006 is ‘‘0.05% of FSR (MAX).’’ This guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within 0.05% cVREF of a straight line which passes through zero and full scale. Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t W) of 320 ns. A typical part will operate with t W of only 100 ns. The entire write pulse must occur within the valid data interval for the specified t W,t DS,t DH, and t S to apply. Note 9: Guaranteed by design but not tested. Note 10: A 200 nA leakage current with R fbe20K and V REFe10V corresponds to a zero error of (200 c10b9c20c103)c100d10 which is 0.04% of FS. Note 11: Human body model, 100 pF discharged through a 1.5 k X resistor.
TL/H/5688–2 Typical Performance Characteristics Errors vs. Supply Voltage Errors vs. Temperature Write Width, t W Control Setup Time, t CS Data Setup Time, t DS Data Hold Time, t DH Digital Threshold vs. Supply Voltage Digital Input Threshold vs. Temperature TL/H/5688–3
Block and Connection Diagrams DAC1006/1007/1008 (20-Pin Parts) USE DAC1006/1007/1008 FOR LEFT JUSTIFIED DATA TL/H/5688–5 DAC1006/1007/1008 (20-Pin Parts) Dual-In-Line Package TL/H/5688–28 Top View See Ordering Information DAC1006/1007/1008ÐSimple Hookup for a ‘‘Quick Look’’ *A TOTAL OF 10 INPUT SWITCHES & 1K RESISTORS TL/H/5688–7 Notes: 1. For V REFeb10.240 V DC the output voltage steps are approximately 10 mV each. 2. SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data can be loaded into the input latch via the 10 SW2 switches. When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes.
1.0 DEFINITION OF PACKAGE PINOUTS
1.1 Control Signals (All control signals are level actuated.) CS: Chip Select Ð active low, it will enable WR . WR: Write Ð The active low WR is used to load the digital data bits (DI) into the input latch. The data in the input latch is latched when WR is high. The 10-bit input latch is split into two latches; one holds 8 bits and the other holds 2 bits. The Byte1/Byte2 control pin is used to select both input latches when Byte1/Byte2 e1 or to overwrite the 2-bit input latch when in the low state. Byte1/Byte2: Byte Sequence Control Ð When this control is high, all ten locations of the input latch are enabled. When low, only two locations of the input latch are enabled and these two locations are overwritten on the second byte write. On the DAC1006, 1007, and 1008, the Byte1/Byte2 must be low to transfer the 10-bit data in the input latch to the DAC register. XFER : Transfer Control Signal, active low Ð This signal, in combination with others, is used to transfer the 10-bit data which is available in the input latch to the DAC register Ð see timing diagrams.
1.2 Other Pin Functions
i (ie0 to 9): Digital Inputs Ð DI 0 is the least significant bit (LSB) and DI g is the most significant bit (MSB). IOUT1: DAC Current Outpu t1ÐI OUT1 is a maximum for a digital input code of all 1s and is zero for a digital input code of all 0s. I OUT2: DAC Current Outpu t2ÐI OUT2 is a constant minus IOUT1,o r IOUT1aIOUT2e1023 V REF 1024 R where R j 15 k X. RFB: Feedback Resistor Ð This is provided on the IC chip for use as the shunt feedback resistor when an external op amp is used to provide an output voltage for the DAC. This on-chip resistor should always be used (not an external re- sistor) because it matches the resistors used in the on-chip R-2R ladder and tracks these resistors over temperature. V REF: Reference Voltage Input Ð This is the connection for the external precision voltage source which drives the R-2R ladder. V REF can range from b10 to a10 volts. This is also the analog voltage input for a 4-quadrant multiplying DAC application. V CC: Digital Supply Voltage Ð This is the power supply pin for the part. V CC can be from a5t o a15 V DC. Operation is optimum for a15V. The input threshold voltages are nearly independent of V CC. (See Typical Performance Characteris- tics and Description in Section 3.0, T 2L compatible logic inputs.) GND: Ground Ð the ground pin for the part.
1.3 Definition of Terms
Resolution: Resolution is directly related to the number of switches or bits within the DAC. For example, the DAC1006 has 2 10 or 1024 steps and therefore has 10-bit resolution. Linearity Error: Linearity error is the maximum deviation from a straight line passing through the endpoints of the DAC transfer characteristic. It is measured after adjusting for zero and full-scale. Linearity error is a parameter intrinsic to the device and cannot be externally adjusted. National’s linearity test (a) and the ‘‘best straight line’’ test (b) used by other suppliers are illustrated below. The ‘‘best straight line’’ requires a special zero and FS adjustment for each part, which is almost impossible for user to determine. The ‘‘end point test’’ uses a standard zero and FS adjust- ment procedure and is a much more stringent test for DAC linearity. Power Supply Sensitivity: Power supply sensitivity is a measure of the effect of power supply changes on the DAC full-scale output (which is the worst case). a. End Point Test After Zero and FS Adj. b. Best Straight Line TL/H/5688–8
to full-scale or full-scale to zero output change. error between an ideal DAC and the actual device output.
2.0 DOUBLE BUFFERING
3.0 TTL COMPATIBLE LOGIC INPUTS
4.0 APPLICATION HINTS
signals is next in importance. ductive foam or anti-static rails.
4.1 Power Supply Sequencing & Decoupling
or LF356 is used Ð these diodes are not required. used for the op amp are adequate for the DAC. FIGURE 1. Basic Logic Threshold Loop
4.2 Op Amp Bias Current & Input Leads
strongly recommended for these DACs. prevent inadvertent noise pickup.
5.0 ANALOG APPLICATIONS
and in the voltage switching mode. complete applications circuits.
5.1 Operation in Current Switching Mode
REF) can therefore range from b10V to a10V.
5.1.1 Providing a Unipolar Output Voltage with the
applied input current to be diverted to the feedback resistor. direction of current flow through the feedback resistor. FIGURE 2. Current Mode Switching FIGURE 3. Converting I OUT to V OUT
5.1.2 Providing a Bipolar Output Voltage with the
resistor common to existing bipolar multiplying DAC circuits. verting the state of the MSB in either software or hardware. decimal equivalent of the 2’s complement processor data. used separately as the resistors labeled 2R. FIGURE 4. Providing a Unipolar Output Voltage FIGURE 5. Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode
5.2 Analog Operation in the Voltage Switching Mode
gain stage as shown in Figure 9 . FIGURE 8. Voltage Mode Switching FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)
FIGURE 10. Providing a Bipolar Output Voltage with a Single Op Amp FIGURE 11. Increasing the Output Voltage Swing
5.3 Op Amp V OS Adjust (Zero Adjust) for Current
of the op amp and make the zeroing easier to sense.
5.4 Full-Scale Adjust
5.4.1 Current Switching with Unipolar Output Voltage
This completes the DAC calibration.
5.4.2 Current Switching with Bipolar Output Voltage
The circuit of Figure 12 shows the 3 adjustments needed. be opposite that of the applied reference. this time will be the same as that of the reference voltage.
5.4.3 Voltage Switching with a Unipolar Output Voltage
5.4.4 Voltage Switching with a Bipolar Output Voltage
recheck the full-scale values. FIGURE 12. Full Scale Adjust Ð Current Switching with Bipolar Output Voltage FIGURE 13. Full Scale Adjust Ð Voltage Switching with a Unipolar Output Voltage
FIGURE 14. Voltage Switching with a Bipolar Output Voltage
6.0 DIGITAL CONTROL DESCRIPTION
format can be either left justified or right justified. neous transfer, or updating, of more than one DAC. the analog output without the use of any data latches. of 6.1 through 6.4 need be considered.
6.1 Interfacing to an 8-Bit Data Bus
- Is the data to be left justified (considered as fractional
- Which byte will be transferred first, the most significant
Section Figure No. Section Figure No. Section Figure No.
word is located within the 16-bit data source (CPU) register.
6.1.1 For Left Justified Data
6.2 Controlling Data Transfer for an 8-Bit Data Bus
nal strobe. The details of these options are now shown. FIGURE 15. Fitting a 10-Bit Data Word into 16 Available Bit Locations FIGURE 16. Input Connections and Controls for DAC1006/1007/1008 Left Justified Data
6.2.1 Automatic Transfer
This makes use of a double byte (double precision) write. The first byte (8 bits) is strobed into the input latch and the second byte causes a simultaneous strobe of the two re- maining bits into the input latch and also the transfer of the complete 10-bit word from the input latch to the DAC regis- ter. This is shown in the following timing diagram; the point in time where the analog output is updated is also indicated on this diagram. DAC1006/1007/1008 (20-Pin Parts) TL/H/5688–18 *SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL
6.2.2 Transfer Using mP Write Stroke
The input latch is loaded with the first two write strobes. The XFER signal is provided by external logic, as shown below, to cause the transfer to be accomplished on a third write strobe. This is shown in the following diagram: DAC1006/1007/1008 (20-Pin Parts) TL/H/5688–19
6.2.3 Transfer Using an External Strobe
This is similar to the previous operation except the XFER signal is not provided by the mP. The timing diagram for this is: DAC1006/1007/1008 (20-Pin Parts) TL/H/5688–20
6.3 Interfacing to a 16-Bit Data Bus
The interface to a 16-bit data bus is easily handled by con- necting to 10 of the available bus lines. This allows a wiring selected right justified or left justified data format. This is shown in the connection diagram of Figure 17 , where the use of DB6 to DB15 gives left justified data operation. Note that any part number can be used and the Byte1/Byte2 con- trol should be wired Hi.
FIGURE 17. Input Connections and Logic for DAC1006/1007/1008 with 16-Bit Data Bus
6.3.1 Single Buffered
6.3.2 Double Buffered
6.4 Stand Alone Operation
6.4.1 Single Buffered
6.4.2 Double Buffered
*For a connection diagram of this operating mode use Figure 16 for the Logic and Figure 17 for the Data Input connections.
7.0 MICROPROCESSOR INTERFACE
7.1 DAC1001/1/2 to INS8080A Interface
DAC1006 to an INS8080A based microprocessor system. NOTE: DOUBLE BYTE STORES CAN BE USED. TRANSFERS THE RESULT TO THE DAC REGISTER. BE AN ODD ADDRESS FOR PROPER TRANSFER. FIGURE 18. Interfacing the DAC1000 to the INS8080A CPU Group
write strobes of the PUSH instruction. generate the byte number and transfer strobes.
7.2 DAC1006 to MC6820/1 PIA Interface
7.3 Noise Considerations
transferred between the latches of the device. nating noise spikes when changing digital codes. FIGURE 19. DAC1000 to MC6820/1 PIA Interface
FIGURE 20. Isolating Data Bus from DAC Circuitry to Eliminate Digital Noise Coupling FIGURE 21. Digitally Controlled Amplifier/Attenuator
7.4 Digitally Controlled Amplifier/Attenuator
gVMAX, depending on the sign of V IN.
TL/H/5688–27 FIGURE 22. Digital to Synchro Converter
Ordering Information
For Left Justified Data Ð 20-pin package. Accuracy Temperature Range 0§ to a70§C 0.05% (10-bit) DAC1006LCN DAC1006LCWM 0.10% (9-bit) DAC1007LCN 0.20% (8-bit) DAC1008LCN Package Outline N20A M20B
Physical Dimensions inches (millimeters) Order Number DAC1006LCWM
DAC1006/DAC1007/DAC1008 mP Compatible, Double-Buffered D to A Converters Physical Dimensions inches (millimeters) (Continued) Order Number DAC1006LCN, DAC1007LCN or DAC1008LCN LIFE SUPPORT POLICY NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or 2. A critical component is any component of a life systems which, (a) are intended for surgical implant support device or system whose failure to perform can into the body, or (b) support or sustain life, and whose be reasonably expected to cause the failure of the life failure to perform, when properly used in accordance support device or system, or to affect its safety or with instructions for use provided in the labeling, can effectiveness. be reasonably expected to result in a significant injury to the user. National Semiconductor National Semiconductor National Semiconductor National Semiconductor Corporation Europe Hong Kong Ltd. Japan Ltd.
1111 West Bardin Road Fax: (
a49) 0-180-530 85 86 13th Floor, Straight Block, Tel: 81-043-299-2309 Arlington, TX 76017 Email: cnjwge @ tevm2.nsc.com Ocean Centre, 5 Canton Rd. Fax: 81-043-299-2408 Tel: 1(800) 272-9959 Deutsch Tel: ( a49) 0-180-530 85 85 Tsimshatsui, Kowloon Fax: 1(800) 737-7018 English Tel: ( a49) 0-180-532 78 32 Hong Kong Fran3ais Tel: ( a49) 0-180-532 93 58 Tel: (852) 2737-1600 Italiano Tel: ( a49) 0-180-534 16 80 Fax: (852) 2736-9960 National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.