CS98200 CIRRUS | Alldatasheet
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Copyright 2002 Cirrus Logic (All Rights Reserved) OCT ’02 DS581PP2 http://www.cirrus.com New Highly-Integrated Processor for Tomorrow’s DVD Players and DVD Receivers (cont.) CS98200 Data Sheet Preliminary Product InformationThis document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
FEATURES
I DVD-Video, VCD, VCD 2.0, SVCD, CD, and other popular standards I DVD-Audio including CPPM and Verance ™ watermark protection I MPEG-1, MPEG-2, and leading edge MPEG-4 audio and video decoding I Kodak Picture CD I Flexible ATAPI or AV bus DVD loader support with no additional logic I Dual 32-bit RISC processors, supported by RTOS, C/C++ compilers, and source level debuggers I 32-bit DSP capable of running AC-3, MPEG, DTS, MP3, WMA, and AAC audio decode algorithms I High quality integrated video encoder with six 10-bit video D/A converters I Component (RGB or YUV) or composite & S-Video output I Interlaced (PAL/NTSC) or progressive (480p) output, with Macrovision™ copy protection I CCIR656 video I/O for video capture, PVR and DVR type applications, picture-in-picture support I IEC60958/937 (S/PDIF) & simultaneous PCM output I 5.1 downmix, karaoke echo mix, pitch shift, and many other effects I PAL / NTSC transcoding I Dual 16550 compatible UARTs I ATAPI/ IDE interface for hard disk, audio server, and Personal Video Recorder (PVR) applications I 240-pin MQFP package ORDERING INFORMATION: CS98200-CM See ordering information legend on page 60. OVERVIEW CS98200 is a highly-integrated processor that provides all of the audio and video processing functions needed for the next generation of feature-rich DVD players, DVD receivers and Internet DVD applications. Tomorrow's features available today in a single chip solution are DVD-Audio, MP3, WMA ®, MPEG-2/4: AAC, Kodak Picture CD ™ , Dolby Digital ™ , Dolby ProLogic II ™ , and DTS Digital Surround ™ decoding. It supports most popular CD formats, DVD navigation, disk control, video decoding and up to eight channels of audio output. An extension of Cirrus' CS98000 DVD product line, the CS98200 integrates six 10-bit video digital-to-analog converters (DACs) and TV encoding with progressive scan functionality . Progressive scan video provides high resolution and eliminates the "flickering" effect present in traditional video playback. Other features enabled by this integrated chip include karaoke functionality and video special effects. Its extended feature set makes it ideal for your next innovative DVD application … today. Need to get your product to market quickly? Cirrus' Total Entertainment platform solutions include DVD front-end controllers, MPEG encoders, audio DSPs, and digital power amplifiers … everything you need to launch your product before the competition. CS98200 is a Cirrus Total Entertainment Total-E ™ IC solution specifically designed for consumer entertainment electronics.
2 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor OVERVIEW (cont.) Here is a summary of the CS98200 features. System Characteristics Dual 32-bit (180 MHz) RISC processors 32-bit DSP processor ~ 180 MIPS 2 4 0 - p i n M Q F P p a c k a g e All I/O pins are 3 V with 5 V tolerance Advanced 0.18 µ CMOS technology Low power modes and clock shutoff Memory Controller Up to 120 MHz SDRAM from 4 MB to 32 MB FLASH databus isolated from SDRAM bus to allow faster SDRAM access 32-bit data bus for DRAM, 8-bit data bus for ROM data flow engine Two DMA controllers — local memory based and direct memory-to-memory DMA to/from main RAM into local SRAM MPEG Video Decoder DVD, VCD, VCD 2.0 and SVCD MPEG-1, MPEG-2, and MPEG-4 simple profile Anti-tearing logic controls picture decode and presentation Advanced error concealment hardware Audio Interface 8 channels PCM output at 24-bits/192 kHz output rate 2 channels I2S input at 24-bits/96 kHz IEC 60958/61937 capabilities External Interface Serial master/slave ports for controlling DVD device ATAPI/IDE interface can also control hard disk drives for PVR features Programmable bidirectional I/O pins All pins not used for other functions can be reassigned as general purpose I/O pins Hardware assisted support for infrared remote devices, such as remote control, infrared keyboard, mouse, printer, and more Programmable parallel host master interface supports formats including ATAPI, ISA, and more I/O channel interface supports all DVD loader protocols Video Processor OSD module with multiple regions and transparencies Full screen graphics module, with 16 bit true-color graphics plane High quality video scaling using multi-tap programmable vertical and horizontal filters Video Encoder Six 10-bit video DAC's, drives 37.5 Ω load directly Progressive (480p) or interlaced PAL (B, D, G, H, I, N, M, 60) and NTSC mode output Component (RBG or YUV) or composite + S-Video output M a c r o v i s i o n™ 7.1 support (interlaced) and Macrovision™ 1.03 support (progressive) Wide-screen signaling support (interlaced and progressive) and CGMS Closed captioning support
DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 3 CS98200 Next Generation DVD Processor RISC 0 RISC 1 DSP Audio InterfaceInstruction Cache Data Cache CPU Pipe MAC Instruction Cache Data Cache MACCPU Pipe CPU/MAC Instruction Cache X,Y Data Memory PCM Out PCM In SPDIF OutDVD Loader I/O MPEG Decoder VLC Parser Motion Comp IDCTRAM DVD Custom Loader Parallel/Serial Data Serial Control ATAPI/Generic Parallel Bus Interface Host Bus I/O Dataflow Engine System Controls NTSC/PAL Encoder Video Processor Subpicture SRAM + CPU IF System Sync Simple I/O DRAM Controller Video Capture Graphics DMA (Rd + Wr) FLASH Memory.Control STC Schedule DMA(2)t SRAM Buffer Decryption Misc. Register Banks Interrupt PLL PLL Timers Digital Encoding
3 DACs
32 KByte
Picture in Picture Overlay Line Buffer / Flicker Filter Main GraphicsDecoder FIFO SDRAM Control Video Mixing Dual UART PWM Semi-DAC 2-W ire Serial (I2C) 3/4 Wire Serial (SPI) Programm able I/O Infrared Input PLL MPEG4 Video Decoder Accelerator CPU Interface ALU + logic BLOCK DIAGRAM
4 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Table of Contents Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus” ) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” wi thout warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that info rmation being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this info r mation as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the infor- mation contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promoti onal purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or techn o logies described in this material and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER - STOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names i n this document may be trademarks or service marks of their respective owners. Purchase of I 2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those com- ponents in a standard I2C system Microsoft® and Windows Media Technology™ are registered trademarks or trademarks of Microsoft, Inc. in the United States and/or other countries. . HDCD ®, High Definition Compatible Digital® and Pacific Microsonics™ Inc. are either registered trademarks or trademarks of Pacific Microsonics Inc. in the United States and/or other countries. HDCD technology provided under license from Pacific Microsonics Inc. This products design (and/or software) is covered by one or more of the following: 5,479,168; 5,638,074; 5,640,161; 5,808,574; 5,838,274; 5,854,600; 5,864,311; 5,872,531 with other patents pending. Dolby Digital, AC-3, Dolby Pro Logic, Dolby Pro Logic II, Dolby Surround, Surround EX, Virtual Dolby Digital and the “AAC” logo are trademarks and the “Dolby Digital” logo, “Dolby Digital with Pro Logic II” logo, “Dolby” and the double-”D” symbol are registered trademarks of Dolby Laboratories Licensing Corporation. DTS, DTS Digital Surround, DTS-ES Extended Surround, DTS Neo:6, and DTS Virtual 5.1 are trademarks and the “DTS”, “DTS-ES”, “DTS Virtual 5.1” logos are registered trademarks of the Digital Theater Systems Corporation. The “MPEG Logo” is a registered trademark of Philips Electronics N. V. Home THX Cinema and THX are registered trademarks of Lucasfilm Ltd. Surround EX is a jointly developed technology of THX and Dolby Labs, Inc. AAC (Advanced Audio Coding) is an “MPEG-2-standard-based” digital audio compression algorithm (offering up 5.1 discrete decoded channels for this implementation) collaboratively developed by AT&T, the Fraunhofer Institute, Dolby Laborato- ries, and the Sony Corporation. In regards to the MP3 capable functionality of the CS98XXX Family DSP (via downloading of mp3_49 3xxx_vv.ld and mp3e_493xxx_vv.ld application codes) the following statements are applicable: “Supply of this product conveys a license for personal, private and non-commercial use. MPEG Layer III audio decoding technology licensed from Fraunhofer IIS and THOMSON Multimedia.”
DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 5 CS98200 Next Generation DVD Processor 8.12 I
Table 25. I
8 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor 1. CHARACTERISTICS AND SPECIFICATIONS
1.1 AC AND DC PARAMETRIC SPECIFICATIONS
(AGND, DGND=0 V, all voltages with respect to 0 V)
1.1.1 ABSOLUTE MAXIMUM RATING
CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent dam- age to the device. Cirrus Logic recommends that CS98200 devices operate at the settings described in the next table.
1.1.2 RECOMMENDED OPERATING CONDITIONS
1.1.3 ELECTRICAL CHARACTERISTICS
Symbol Description Min Max Unit VDD IO Power Supply Voltage on analog core and I/O ring -0,5 4.6 Volts VDD CORE Power Supply Voltage on core logic and PLL -0.5 2.5 Volts VI Digital Input Applied Voltage (power applied) -0.5 5.5 Volts II Digital Input Forced Current -10 10 mA IO Digital Output Forced Current -50 50 mA TSOL Lead Soldering Temperature - 260 oC TVSOL Vapor Phase Soldering Temperature - 235 oC TSTOR Storage Temperature (no power applied) -40 125 oC TAMB Ambient Temperature (power applied) 0 70 oC Ptotal Total Power consumption - 2.2 W Parameter Symbol Min Typ Max Units Supply Voltage, Analog and IO V IO & VAA 3.0 3.3 3.6 Volts Supply Voltage, Core Logic and PLL V PLL &VDD 1.62 1.8 1.98 Volts Ambient Temperature (power applied) T AMB 02 5 7 0 oC Parameter Symbol Conditions Min Typ Max Units Supply Current, IO I DD Normal Operating 65 mA Supply Current, Core Logic and PLL IDD Normal Operating 210 mA Input Voltage, High V IH 2.0 - Volts Input Voltage, Low V IL -- 0 . 8 V o l t s Input Current I IN VIN = VDD or VSS -1 - 1 µA Input Pull up/down resistor R I -7 5-K Ω Output Voltage, High V OH @ buffer rating 2.2 - - Volts Output Voltage, Low V OL @ buffer rating - - 0.4 Volts High-Z-state Leakage I OZ VOUT = VSS or VDD -1 - 1 µA Video DACs1 R SET = 174Ω DAC Resolution 10 bits DAC to DAC matching2 MAT 2 % Output Voltage Range V out R LOAD = 37.5Ω 3 1.28 Volts
DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 9 CS98200 Next Generation DVD Processor Differential Gain DG 1 % Differential Phase DP 0.5 % Signal to Noise SNR 74 dB Chrominance AM Noise AM 80 dB Chrominance PM Noise PM 75 dB 1.Video parameters guaranteed only with 1% tolerance resistors or better for Rset and RLoad. 2.Only applies to each set of three DACs. 3.RLoad is a double terminated load, which includes a 75 Ω resistor at the video DAC and a 75 Ω resistor at the video monitor.
2.1 Timing Diagram Conventions
meaning should be attached unless specifically stated. Figure 1. Legend for Timing Diagrams
2.2 DC CHARACTERISTICS
2.2.1 ATAPI Interface
transaction and a write ATAPI transaction. Table 1. ATAPI Interface Characteristics Figure 2. ATAPI Interface Timing Diagram
2.2.2 DVD Loader Interface
Figure 3. DVD Loader Host Interface
Figure 6. DVD Loader CD Interface Formats
2.2.3 DVD Serial Interface Timing
Figure 7. DVD Serial Interface Timing
2.2.4 SDRAM Interface
the refresh cycle performed by CS98200. Table 2. SDRAM Interface Characteristics Figure 8. SDRAM Refresh Transaction Figure 9. SDRAM Burst Write Transaction
2.2.5 ROM/NVRAM Interface
Table 3. RAM/NVROM Characteristics Figure 12. ROM/NVRAM Reading Timing
Figure 13. ROM/NVRAM Write Timing
2.2.6 Digital Video Output Interface
Figure 14 illustrates the signal timing for the digital video interface pins. 2.It is recommanded that the output data should be taken at the opposite edge of the CLK27_O. Table 4. CS98200 Digital Video Interface Characteristics Figure 14. CS98200 Digital Video Interface Timing Diagram
2.2.7 Video Input Interface
Table 5. Video Input Interface Symbols and Characterization Data Figure 15. Video Input Timing
2.2.8 Audio Input Interface Timing
Table 6. Audio Input Interface Symbols and Characterization Data Figure 16. Audio Input Timings
2.2.9 Audio Output Interface Timing
Figure 17 and Figure 16 illustrate the signal timing for the digital audio pins. Table 7. Digital Audio Out Characteristics Figure 17. Digital Audio Out Timing Diagram
2.2.10 Miscellaneous Timings
1.XTLCLK must meet the requirement of external the video encoder for correct chroma (27 MHz ± 1 KHz). Table 8. Miscellaneous Timing Characteristics Figure 18. Miscellaneous Timings
The Figure 19 shows a typical example of a complete DVD Receiver solution using the CS98200.
6 Video DACs
8 Channels
Figure 19. CS98200 Typical Application
4.1 Block Diagram
The CS98200 block diagram is shown in Figure 20.
4.2 CS98200 Device Details
4.2.1 RISC-32 Processors
4.2.2 Powerful 24/32-Bit DSP
4.2.3 System Controls
4.2.4 Memory Controller
Figure 20. CS98200 Block Diagram
DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 27 CS98200 Next Generation DVD Processor High speed, can handle up to 120 MHz DRAM speeds Supports 8-bit parallel ROM or FLASH, up to 8 MB Single bank of SDRAM only. Single bank of ROM/FLASH only Separate data bus for ROM, reduces loading for improved speed, Also handles 5 V easier.
4.2.5 Data Flow Engine
2432 bytes of internal memory DMA to/from main RAM into local SRAM Supports endian conversion and byte, short, long data formats on DMA Supports block transfers for graphics bit blits
4.2.6 MPEG Video Decoder
Supports VCD, VCD 2.0, DVD video stan- dards Supports trick features, including smooth 2x play and reverse play Special anti-tearing logic controls picture de- code and presentation Advanced error concealment hardware New acceleration modules for MPEG-4 Sim- ple Profiles support
4.2.7 System Synchronization
System time clock (STC) for audio/video synchronization Flexible interrupt structure for controlling decode and presentation times Hardware scheduling of subpicture and highlight events
4.2.8 Audio Interface
Supports 8 channels PCM output at up to 24 bits and 192 kHz output rate. Supports 2 channels I2S input at up to 24 bits and 96 kHz input rate. Simultaneous IEC-958 (SPDIF) output with programmable channel status and user data. SPDIF, PCM input, and PCM output can all have different XCLK dividers. Supports simultaneous 192 Khz front and 96 Khz surround, for DVD audio
4.2.9 Video Input
NTSC/PAL video decoder input interface Video input image can be displayed in small window, or as main picture
4.2.10 External Interface
Serial I2C® master and slave port 29 independent fully programmable bi-di- rectional I/O pins 8 edge or level detection interrupt pins Hardware assisted support for infrared re- mote devices, such as remote control, infra- red keyboard Dual UART
4.2.11 Video Processor
Supports 24-bit 4:2:0 and 4:2:2 video modes and 16-bit true color graphics modes. Picture-in-picture module includes horizon- tal and vertical downscaling with program- mable output sizes, positions, and borders Overlay mixer with RGB to YUV conversion and output formatting Supports 4:2:0, 4:2:2, YUV655, RGB565 and RGB555 frame buffer inputs Outputs 4:2:2 video in CCIR-601 or CCIR- 656 format High quality scaling using a vertical and a horizontal 16 taps polyphase programmable filter and supports any size image up to 768x576 3 taps adaptative anti-flicker filtering Master or Slave video sync configuration Multiple video plains overlay (main video / video input / picture_in_picture / pic- ture/on-screen / display) Gamma correction
4.2.12 Sub-Picture Processor
Run-length decode DVD sub-pictures Hardware vertical scaling supports NTSC- PAL format conversion 16-level alpha blending
4.2.13 Graphics Engine
16 bit true color Progressive and interlaced mode support
28 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor Supports gamma correction Color-key type transparency support Global blending support Frame buffer wrap around support for scrolling 3 tap horizontal and vertical filtering
4.2.14 On Screen Display Module
Supports 2-bit and 4-bit pixel modes 3 separate regions support 16 transparency overlay levels support
4.2.15 DVD Loader Interface
4-pin serial interface to low-cost DVD load- ers Loader control via separate 2-wire serial master control port IO channel interface supports standard 8 bit DVD loader protocols
4.2.16 CPU Interface and SRAM Controller
Internal SRAM of 32 KByte, and controller, synchronous with the CPUs at 180 Mhz Fast interfaces to RISCs and DSP Asynchronous interfaces to the main system clock Special DMA engine, with multiple software clients, and command FIFO Special interface to MPEG-4 video module
4.2.17 Host Bus Interface
Programmable parallel host master interface supports formats including ATAPI, ISA, and more Internal DMA module, for I/O type reads and writes on the host bus Extra chip selects, for more external devices
4.2.18 Video Encoder
Six 10-bit video DACs, drive 37.5 W load di- rectly without external buffering Supports PAL (B, D, G, H, I, N, M, 60) and NTSC Component (RBG or YUV) or composite + S- Video output Progressive or interlaced mode output Macrovision 7.1 support (interlaced) and Macrovision 1.03 support (progressive) Wide-screen signalling support (interlaced and progressive) and CGMS support Closed captioning support
4.2.19 System Functions
240-pin MQFP package All I/O pins are 3 V with 5V tolerance Advanced 0.18 micron CMOS technology Internal processors run at 180 MHz Supports Low Power modes and clock shut- off
DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 29 CS98200 Next Generation DVD Processor 5. FUNCTIONAL DESCRIPTION
5.1 RISC Processor
The CS98200 includes two powerful, third-gen- eration proprietary 32-bit RISC processors, RISC0 and RISC1, with optimizing C compiler support and source level debugger. The RISC processors fully support many Real Time Oper- ation Systems (RTOS). The DVD application user interface resides on RISC1 and is customer programmable. The real time control of low lev- el DVD functions is performed by RISC0. RISC1 gains access to system resources controlled by RISC0 via calls through an Applications Pro- gramming Interface, See the CS98200 Software API. All RISC0 firmware, API and sample appli- cation code are supplied with the CS98200. The RISC processors also have a MAC engine, which performs multiply/accumulate in 2 cy- cles in a pipelined fashion with C support, effec- tively achieving single cycle throughout. The RISC0 processor coordinates on-chip multi- threaded tasks, as well as system activities such as remote control and front panel control. The DVD application end-user interface resides on RISC1, and any modifications to that interface occur through the CS98200 API.
5.2 DSP Processor
The CS98200 contains a proprietary digital sig- nal processor (DSP), which is optimized for au- dio applications. The DSP performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. The multiply-accumulator has single-cycle through- put, with two cycle latency. The DSP is opti- mized for bit packing and unpacking operations. The interface to main memory is de- signed for handling flexible block sizes and skip counts.
5.3 Memory Control
The DRAM Interface performs the SDRAM con- trol and arbitration functions for all the other modules in the CS98200. The DRAM interface services and arbitrates a number of clients and stores their code and/or data within the local memory. This arbitration and scheduling guar- antees the allocation of sufficient bandwidth to the various clients. The DRAM Interface sup- ports up to 32 Mbytes. For a typical DVD player application, CS98200 requires 8 Mbytes memo- ry space. Sharing the same interface, CS98200 also sup- ports FLASH ROM, OTP, or mask ROM inter- face. Code is stored in ROM. After the system is booted, the code is shadowed inside SDRAM for execution. The FLASH ROM interface is pro- vided so that the code can be upgraded in the field once the communications channel is estab- lished. Utility software will be provided to de- bug and upgrade code for the system manufacturer.
5.4 Dataflow Control (DMA)
The DMA controller moves data between the external memory and internal memory. The ex- ternal memory address can be specified using a register, or in FIFO mode, using start and end address registers. Separate start/end address registers are used for DMA read and write oper- ations. The DMA interface also has a block transfer function, which allows for the transfer of one block of data from one external memory location to another external memory location. In effect, this feature combines a DMA read and write into one operation. In addition, the DMA write operation allows for byte, short, word, and other types of masking.
5.5 System Control Functions
The system control functions are used to coordi- nate the activities of the multiple processors, and to provide the supporting system opera- tions. Eight 32-bit communication registers are available for inter-processor communication, and 32 semaphore registers are used for re- source locking. Timers are available for general- purpose functions, as well as more specialized
30 Copyright 2002 Cirrus Logic (All Rights Reserved) DS581PP2 CS98200 Next Generation DVD Processor functions such as watchdog timers and perfor- mance monitoring. The large number of general purpose I/Os of- fers flexibility in system configurations. An I 2C master allows for control of other I 2C devices, such as a video encoder. An I 2C slave port shares the same pins, and can be used for debug functions. Interrupts can be generated on specif- ic or generic events. Infrared inputs can be fil- tered to make them free of glitches or stored unfiltered into memory. Control of all the inter- nal clocks is also possible. There are two sepa- rate PLLs that are clocked by the 27 MHz clock input. One PLL generates the main clock and DRAM interface clock, and the second gener- ates the Audio 256X/384X clock.
5.6 DVD/ATAPI Interface
The CS98200 has a programmable interface port which can be configured to connect to industry standard CD/DVD loaders without external glue logic. The CD/DVD interface fully sup- ports many popular CD/DVD loaders. The in- terface consists of DVD control and data ports and an optional CD control/data port. The CS98200 hardware manages the DVD inter- face and moving data to an arbitrary size input FIFO in DRAM. The same interface pins can be optionally configured as a generic 16-bit host master port. In this mode, the CS98200 can con- trol up to four devices (using 4 chip select out- puts), each of which may use different protocol and timing. The interface can be set up in ATA- PI mode, to connect directly to any ATAPI DVD loader (using two chip selects). Si- multaneously, the other two chip selects can be configured to connect to other devices, such as a super I/O chip or hard disk. A third option is to configure the interface for micro-less DVD loader operation, which may also be configured to connect without external glue logic.
5.7 Serial DVD Interface
The CS98200 has a 4-pin serial port which inter- faces to the data port of popular low-cost DVD loaders. This type of loader provides for low system cost by eliminating the track buffer, in- terface FIFO, and flow control logic. The CS98200 contains a large internal SRAM to han- dle high burst data rates, without requiring re- verse flow control. The CS98200 performs error detection, sector number tracking, and interrupt generation.
5.8 MPEG Video Decoding
Compressed MPEG data is read from the DVD disk into an input FIFO in DRAM. The data flow (DMA) controller moves Video packets from the input FIFO into the MPEG decoder’s input FIFO (also in DRAM). The DMA controller can also perform advanced functions such as start code search, relieving the RISC processors. The Sys- tem Synchronization function is used to control the timing of MPEG picture decoding. The MPEG Video decoder processes I, B, and P frames, and writes to video frame buffers in DRAM for output to the display. Special anti- tearing logic ensures that currently displayed frame buffers are not overwritten.
5.9 Audio Processing
Compressed Audio data is read from the DVD disk into an input FIFO in DRAM. The data is decompressed, then written to a PCM output FIFO, also in DRAM. Presentation time stamps (PTS) are extracted from the stream to update the STC, in order to maintain audio/video syn- chronization. The DMA and decompression stages of audio processing can be done with a combination of the DMA unit, DSP, and RISC processors. The DSP is optimized for audio processing, so most common formats can be handled by the DSP alone, including AC-3, DTS, MPEG2 audio, and MP3. The DSP has enough reserve bandwidth
DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 31 CS98200 Next Generation DVD Processor to handle the Karaoke echo-mix and pitch shift, and AC-3 down-mix functions. The audio output data is written into a DRAM FIFO in 16-, 18-, 20- or 24-bit PCM format. A flexible audio output stage can simultaneously output 8 channels of PCM data to audio DACs up to 192 KHz sample rate, plus an IEC-958 en- coded output at up to 48 KHz. The audio inter- face also includes a flexible audio input interface, which can input a wide range of pro- tocols from an audio ADC or an IEC-958 receiv- er at up to 96 KHz.
5.10 Video Encoder with Progressive Video
ed as close as possible to the video connectors. shows the video DAC connections. PAL) and 1.03 for the progressive scan (480p). Management System), and Closed Caption. Figure 21. Video DAC Connections
DS581PP2 Copyright 2002 Cirrus Logic (All Rights Reserved) 33 CS98200 Next Generation DVD Processor
5.11 Video Input/Output Interface
In addition to the six 10-bit video DACs, the CS98200 provides a separate Digital Video In- terface that will give you flexible and powerful means of outputting digital video data to exter- nal devices in CCIR601/3 and CCIR656 formats. The interface directly supports NTSC/PAL vid- eo encoding, in both master and slave synchro- nization configurations. The internal frame buffer format could be 4:2:0, 4:2:2, YUV655, RGB565 and RGB555. The CS98200 also features an NTSC/PAL video decoder input interface. The interface accepts CCIR601, CIF, and QCIF formats, out of many TV decoders on the market. The video processor also allows overlay of multiple video planes (main video / video input / picture_in_picture / on-screen display). The Video Input Scaler (VIS) module inputs 8- bit digital video data from a camera or PAL/NTSC decoder and simply dump all the data to DRAM. The scaled image, with a border, can be overlaid anywhere on the screen into a ½ or ¼-screen sized window by the Picture in Pic- ture (PIP) module. An alternate method of using the Video Input function is to input a full sized picture and present it on the screen full size (bypass mode). In this mode, the PIP module can place full mo- tion DVD images in the small window. An inter- nal glitch-free mux can switch the video processor clock source from the internal clock to the Video Input clock, allowing the PIP mode to switch back and forth on the fly, with no drop- out.
5.12 Universal Asynchronous
fers over the UART interface. have been enabled for added functionality. otherwise, you must use the system clock. Figure 22. UART Data Transfer
6.1 Processor Memory Map
identifies whether each segment is mapped or cacheable. Table 9. Memory Map-RISC0 Processor Table 10. Host Debug Port Address Map Table 11. DSP Address Map
Figure 24 shows the pin names associated with each type of CS98200 interface.
7.3 Pin Configuration Summary
AUDO_D_0 and AUDO_LR values are set through pull up or pull down resistors on the pins. Table 12. Pin Configuration Summary Figure 24. 240-Pin MQFP Pinout Summary
7.4 Explanation of Pin Types
Table 13 lists the conventions used to identify the pin type and direction. function is chosen when the chip is reset. Table 13. Pin Type Legen d
2 RST_N ISU Reset I
3 TEST I Manufacturing Test I
4 IR_IN ISU IR in I
5 CDC_CLK B4S GPIO_MIS[18] B
6 CDC_SYNC B4S GPIO_MIS[19] B
7 CDC_SDO B4S GPIO_MIS[20] B
8 CDC_SDI B4S GPIO_MIS[21] B
10 M_DQM_3 B8 DRAM Byte_Enable[3] O
Table 14. 240-Pin MQFP Pin Assignments
11 M_D_31 B8 DRAM Data[31] B
12 M_D_30 B8 DRAM Data[30] B
13 M_D_29 B8 DRAM Data[29] B
14 IO_GND Gnd IO Ground
15 M_D_28 B8 DRAM Data[28] B NVRAM Address[23] O
16 M_D_27 B8 DRAM Data[27] B NVRAM Address[22] O
17 M_D_26 B8 DRAM Data[26] B NVRAM Address[21] O
18 M_D_25 B8 DRAM Data[25] B NVRAM Address[20] O
20 M_D_24 B8 DRAM Data[24] B NVRAM Address[19] O
21 M_D_23 B8 DRAM Data[23] B NVRAM Address[18] O
23 M_D_22 B8 DRAM Data[22] B NVRAM Address[17] O
24 DIG_GND Gnd Digital Ground
25 IO_GND Gnd IO Ground
26 M_D_21 B8 DRAM Data[21] B NVRAM Address[16] O
27 M_D_20 B8 DRAM Data[20] B NVRAM Address[15] O
28 M_D_19 B8 DRAM Data[19] B NVRAM Address[14] O
29 M_D_18 B8 DRAM Data[18] B NVRAM Address[13] O
30 M_D_17 B8 DRAM Data[17] B NVRAM Address[12] O
32 M_D_16 B8 DRAM Data[16] B NVRAM Address[11] O
33 M_DQM_2 B8 DRAM Byte_Enable[2] O
34 IO_GND Gnd IO Ground
35 M_DQM_1 B8 DRAM Byte_Enable[1] O
36 M_D_15 B8 DRAM Data[15] B
37 M_D_14 B8 DRAM Data[14] B
38 M_D_13 B8 DRAM Data[13] B
39 M_D_12 B8 DRAM Data[12] B
40 M_D_11 B8 DRAM Data[11] B
Table 14. 240-Pin MQFP Pin Assignments (Continued)
42 M_D_10 B8 DRAM Data[10] B
43 IO_GND Gnd IO Ground
44 DIG_GND Gnd Digital Ground
45 M_D_9 B8 DRAM Data[9] B
47 M_D_8 B8 DRAM Data[8] B
48 M_D_7 B8 DRAM Data[7] B
49 M_D_6 B8 DRAM Data[6] B
50 M_D_5 B8 DRAM Data[5] B
51 M_D_4 B8 DRAM Data[4] B
52 IO_GND Gnd IO Ground
53 M_D_3 B8 DRAM Data[3] B
55 M_D_2 B8 DRAM Data[2] B
56 M_D_1 B8 DRAM Data[1] B
61 M_D_0 B8 DRAM Data[0] B
62 M_DQM_0 B8 DRAM Byte_En[0] O
63 IO_GND Gnd IO Ground
64 M_CKO O8 DRAM Clock O Drc_Clock Eternal Input I
66 M_CKE B8 DRAM Clock Enable O
67 M_AP B8 DRAM Auto Precharge O NVRAM_OE_N O
68 M_BS1_N B8 DRAM BankSel[1] O
69 M_BS0_N B8 DRAM BankSel[0] O
70 M_RAS_N B8 DRAM Row Strobe O
72 IO_GND Gnd IO Ground
73 M_WE_N B8 DRAM Write Enable O NVRAM_WE_N O
74 NV_CE_N O4 ROM Chip Enable O
76 M_A_10 B8 DRAM Address[10] O NVRAM Address[10] O
77 M_A_9 B8 DRAM Address[9] O NVRAM Address[9] O
78 M_A_8 B8 DRAM Address[8] O NVRAM Address[8] O
79 M_A_7 B8 DRAM Address[7] O NVRAM Address[7] O
80 M_A_6 B8 DRAM Address[6] O NVRAM Address[6] O
82 M_A_5 B8 DRAM Address[5] O NVRAM Address[5] O
83 DIG_GND Gnd Digital Ground
84 IO_GND Gnd IO Ground
85 M_A_4 B8 DRAM Address[4] O NVRAM Address[4] O
87 M_A_3 B8 DRAM Address[3] O NVRAM Address[3] O
88 M_A_2 B8 DRAM Address[2] O NVRAM Address[2] O
89 M_A_1 B8 DRAM Address[1] O NVRAM Address[1] O
90 M_A_0 B8 DRAM Address[0] O NVRAM Address[0] O
91 NV_D_0 B8 NVRAM Data[0] B
92 NV_D_1 B8 NVRAM Data[1] B
93 NV_D_2 B8 NVRAM Data[2] B
94 NV_D_3 B8 NVRAM Data[3] B
95 NV_D_4 B8 NVRAM Data[4] B
96 NV_D_5 B8 NVRAM Data[5] B
97 IO_GND Gnd IO Ground
98 DIG_GND Gnd Digital Ground
99 NV_D_6 B8 NVRAM Data[6]
101 NV_D_7 B8 NVRAM Data[7]
107 SCL1 B4SU I2C Debug Slave B
108 SDA1 B4SU I2C Debug Slave B
109 SCL2 B4SU I2C Master/Simple Slave B GPIO_MIS[0] B
110 SDA2 B4SU I2C Master/Simple Slave B GPIO_MIS[1] B
111 TXD_1 B4 UART1 Tx Data O GPIO_MIS[6] B
112 RXD_1 B4 UART1 Rx Data I GPIO_MIS[7] B
113 TXD_2 B4 UART2 Tx Data O GPIO_MIS[8] B
114 RXD_2 B4 UART2 Rx Data I GPIO_MIS[9] B
115 PWM_O B4 PWM Output O GPIO_MIS[10] B
117 DVDL_DI B4 Primary DVD Control Data In I
118 DVDL_DO B4 Primary DVD Control Data Out O
119 DVDL_CK B4S Primary DVD Control Clock O
121 PLL_GND Gnd PLL Ground
122 IO_GND Gnd IO Ground
123 H_D_0 B4 Host Master Data[0] B
124 H_D_1 B4 Host Master Data[1] B
125 H_D_2 B4 Host Master Data[2] B
126 H_D_3 B4 Host Master Data[3] B
127 H_D_4 B4 Host Master Data[4] B
128 VIN_VS B4 Primary Video_In Vsync I
129 VIN_HS B4 Primary Video_In Hsync I
132 IO_GND Gnd IO Ground
133 H_D_5 B4 Host Master Data[5] B
134 H_D_6 B4 Host Master Data[6] B
135 H_D_7 B4 Host Master Data[7] B
140 H_D_12 B4 Host Master Data[12] B
141 H_D_13 B4S Host Master Data[13] B
142 H_D_14 B4 Host Master Data[14] B
143 H_D_15 B4 Host Master Data[15] B
144 CD_BCLK B4S Primary CD Bit Clock I
145 CD_LRCK B4 Primary CD L/R Clock I
146 CD_DATA B4 Primary CD Data I
147 CD_C2P0 B4 Primary CD C2P0 I
148 DAC_AGND Gnd Analog Ground
150 DAC_DGND Gnd Digital Ground
151 C_OUT Anlg C_OUT
153 DAC_AGND Gnd Analog Ground
154 Y_OUT Anlg Y_OUT
156 DAC_AGND Gnd Analog Ground
157 CV_OUT Anlg CV_OUT
159 DAC_AGND Gnd Analog Ground
160 COMP1 Anlg Compensation
161 ISET1 Anlg Current Set
162 VREF1 Anlg Voltage Ref
163 DAC_AGND Gnd Analog Ground
165 DAC_AGND Gnd Analog Ground
171 DIG_GND Gnd Digital Ground
174 DVD_D_0 B4 Primary DVD Data[0] I
175 DVD_D_1 B4 Primary DVD Data[1] I
177 H_ALE B4 Host Master Address Latch O GPIO_HST[20] B
178 DVD_D_2 B4 Primary DVD Data[2] I
179 DVD_D_3 B4 Primary DVD Data[3] I
181 PLL_GND Gnd PLL Ground
182 DVD_D_4 B4 Primary DVD Data[4] I
183 DVD_D_5 B4 Primary DVD Data[5] I
184 DVD_D_6 B4 Primary DVD Data[6] I
185 DVD_D_7 B4 Primary DVD Data[7] I
186 H_CS_0 B4 Host Master Chip_Select[0] O
187 H_CS_1 B4 Host Master Chip_Select[1] O (1) Secondary DVD Error
189 H_CS_2 B4 Host Master Chip_Select[2] O GPIO_HST[23] B
190 IO_GND Gnd IO Ground
191 H_CS_3 B4 Host Master Chip_Select[3] O GPIO_HST[24] B
192 H_RD B4 Host Master Read O
193 H_WR B4 Host Master Write O
194 H_RDY B4S Host Master Ready I
195 SPI_CLK B4S SPI Clock B GPIO_MIS[2] B
196 SPI_DO B4 SPI Data Out/InOut B GPIO_MIS[3] B
197 SPI_DI B4 SPI Data In I GPIO_MIS[4] B
198 SPI_RDY B4 SPI Ready / Chip Select B GPIO_MIS[5] O
199 AUDI_D B4 PCM Input Data I GPIO_MIS[15] B
200 AUDI_LR B4 PCM LR Clock I GPIO_MIS[16] B
201 AUDI_BCK B4S PCM Input Clock I
202 DAC_AGND Gnd Analog Ground
204 DAC_DGND Gnd Digital Ground
205 UB_OUT Anlg UB_OUT_1
207 DAC_AGND Gnd Analog Ground
208 YG_OUT Anlg YG_OUT_1
210 DAC_AGND Gnd Analog Ground
211 VR_OUT Anlg VR_OUT_1
213 DAC_AGND Gnd Analog Ground
214 COMP2 Anlg Compensation
215 ISET2 Anlg Current Set
216 VREF2 Anlg Voltage Ref
217 DAC_AGND Gnd Analog Ground
219 DAC_AGND Gnd Analog Ground
225 DIG_GND Gnd Digital Ground
226 AUD_XCLK B4S PCM MCLK Output O PCM MCLK External Input I
231 XTLCLK_I OSC 27 MHz Clock In I
232 XTLCLK_O OSC 27 MHz Clock Out O
233 IO_GND Gnd IO Ground
235 SPDIF_O B4 SPDIF O Process_Monitor_Out O
240 PLL_GND Gnd PLL Ground
8.1 SDRAM Interface Pins
15 on how to interface with any particular configuration of SDRAM.
8.2 ROM/NVRAM Interface Pins
M_D[31:0] B Memory Data Bus. CS98200 uses all 32 bits.
64 M_CKO O Memory Clock
66 M_CKE O Memory Clock Enable
69 M_BS0_N O Bank Selection. Always connect to RAM BS or BS0 pin. 68 M_BS1_N O Bank Selection. Always connect to RAM BS or BS0 pin. 67 M_AP O Memory Auto Pre-charge. Always connect to RAM AP pin.
70 M_RAS_N O Memory Row Address Strobe
71 M_CAS_N O Memory Column Address Strobe
73 M_WE_N O Memory Write Enable
Table 15. SDRAM Interface Pins NV_D[7:0] B Memory Data Bus.
67 M_AP O Output Enable
Table 16. ROM/NVRAM Interfa c e
8.3 Video Output Interface Pins
Table 17. This interface uses the same pins of the Video Input Interface, so you are not able to use Video Input (primary) and Video Output (Secondary) at the same time. .
8.4 Video Input Interface Pins
74 NV_CE_N O ROM/NVRAM Chip Enable. 131s VOUT_CLK O 27 Mhz Clock Output. master, input when the video encoder is master. ter, input when the video encoder is master. VOUT_D[7:0] O Video Data Output[7:0] in Cb, Y, Cr, Y format. Table 17. Video Output Interface 131 VIN_CLK I Video Input Clock. 128 VIN_VS I Video Input Vertical Sync. 129 VIN_HS I Video Input Horizontal Sync. VIN_D [7:0] I Video Data Input[7:0] in Cb, Y , Cr, Y format. Table 18. Video Input Interface Table 16. ROM/NVRAM Interface (Continued)
8.5 Audio PCM Interface Pins
the size of the samples are programmable for both input and output direction. output, is generated from CS98200 internal PLL. 224 AUDO_BCK O Audio Bit Clock output to serial DAC. 222 AUDO_LR O Audio Out Left/Right Clock to serial DAC. 234 AUDO_D_0 O Audio Serial Data Out[0]. 227 AUDO_D_1 O Audio Serial Data Out[1]. 228 AUDO_D_2 O Audio Serial Data Out[2]. 229 AUDO_D_3 O Audio Serial Data Out[3].
235 SPDIF_O O S/PDIF Output
clock, in which case this pin is not required. erated LR clock, in which case this pin is not required. 199 AUDI_D I Audio Input Data from Serial ADC. Table 19. PCM Audio Interfa c e
8.6 Host Master/ATAPI Interface
192 H_RD O Host Read Request. 193 H_WR O Host Write Request. H_A[3:0] O Host Address[3:0]. or pull-down if host is not used. Table 20. Host Master/ATAPI Interface
8.7 DVD Loader Interface
CD Data. (See Table 21.) This interface shares CS98200 pins with the Host Master/ATAPI interface. modes are mutually exclusive.
8.8 DVD Serial Data Interface
pins are then free to be used for a second DVD loader, a general purpose ATAPI, or as GPIOs.
168 DVDL_RDY I Primary DVD Control Ready
236 DVD_STB I Primary DVD Data Strobe
237 DVD_ENA I Primary DVD Data Enable
238 DVD_SOS I Primary DVD Start Sector
239 DVD_ERR I Primary DVD Error
116 DVD_RDY O Primary DVD Data Request
117 DVDL_DI I Primary DVD Control Data In
118 DVDL_DO O Primary DVD Control Data Out
119 DVDL_CK O Primary DVD Control Clock
144 CD_BCLK I Primary CD Bit Clock
145 CD_LRCK I Primary CD L/R Clock
146 CD_DATA I Primary CD Data
147 CD_C2PO I Primary CD C2P0
Table 21. DVD I/O Channel Interface
8.9 SPI Interface
der control of an external processor, for example, in a combination unit.
8.10 General Purpose Input/Output (GPIO)
describes the General Purpose I/O Interface. Additional pins may also be re-defined as GPIOs.
195 SPI_CLK B SPI Clock
196 SPI_DO B SPI Data In/Out
197 SPI_DI I SPI Data In
198 SPI_RDY B SPI Ready / Chip Select
Table 22. SPI Interface Table 23. General Purpose I/O Interface
8.11 UART Interface Pins
16-byte FIFOs for receiving and transmitting data.
8.12 I2C Interface
The I2C pins are used for both master and slave mode.
8.13 Miscellaneous Interface Pins
These pins are used for used for basic functions such as clock and reset input. See Table 26.
111 TXD_1 O UART1 Tx Data
112 RXD_1 I UART1 Rx Data
113 TXD_2 O UART2 Tx Data
114 RXD_2 I UART2 Rx Data
Table 24. UART Interface Pins
107 SCL1 B I2C Debug Slave
108 SDA1 B I2C Debug Slave
109 SCL2 B I2C Master/Simple Slave
110 SDA2 B I2C Master/Simple Slave
Table 25. I2C Interface Pins 4 IR_IN I Infrared Input, from IR receiver. 231 XTLCLK_I I 27 MHz Clock Input. 232 XTLCLK_O O 27 MHz Clock Output. 2 RST_N I Reset Input, active low. 3 TEST I Manufacturing test pin, should always c onnect to ground. Table 26. Miscellaneous Interface Pins
8.14 Power and Ground
Table 27. Power and Ground
- 240-PIN MQFP PACKAGE SPECIFICATIONS
1) Dimensions are in millimeters, and controlling dimension is millimeter. 2) Package body dimensions do not include mold protrusion, which is 0.25 mm (0.010 in). 3) Pin 1 identiÞcation ma y be either ink dot or dimple. 4) Package top dimensions can be smaller than bottom dimensions by 0.20 mm (0.008 in). (at maximum material condition). 6) Ejector pin marks in molding are present on every package. 7) Drawing above does not reßect e xact package pin count. Figure 25. 240-Pin MQFP Package Drawing
10.1 Acronyms and Abbreviations
Table 28 lists abbreviations and acronyms used in this data sheet. Table 28. Acronyms and Abbreviatio ns
10.2 Units of Measurement
10.3 General Conventions
ber). Numbers not indicated by an “h”, 0x or quotation marks are decimal. Table 29. Units of Measurement Table 28. Acronyms and Abbreviations (Continued)
10.4 Pin Description Conventions
the pin number indicate that the pin is using a secondary function for that pin.
- ORDERING INFORMATION LEGEND
Here is the legend for understanding the ordering information listed above. Table 30. Pin Description Conventions