CS98100 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
/circle6 32-Bit RISC Processor, supported by RTOS, C/C++ compilers /circle6 32-bit DSP capable of AC-3, MPEG, DTS, MP3, and WMA /circle6 Progressive Scan (480p) with 3:2 pull down support or Interlaced (PAL/NTSC) video encoding, both modes with Macrovision encoding, via three 10-bit Video DACs /circle6 Serial DVD data interface for direct connection to low cost (track buffer-less) DVD loader /circle6 Flexible interface connects ATAPI, local bus or microcontroller-less DVD loaders without external logic /circle6 MPEG decoder supports VCD, VCD 3.0, SVCD, DVD video standards /circle6 Advanced subpicture unit handles DVD and SVCD, and PAL<->NTSC scaling /circle6 High quality video scaling for zoom and NTSC/PAL conversion /circle6 4-bit multi-region OSD and special video effects /circle6 Simultaneous 8 channels PCM audio output and IEC-958. /circle6 2-Channel PCM audio input for high-end karaoke
applications
/circle6 Three serial control/status ports /circle6 Low-power, ~0.5 W power dissipation
Description
Building on innovative, market-leading technology, Cirrus Logic presents the most complete DVD processor solu- tion available: CS98100. The CS98100 provides the high- performance typical of Cirrus Logic integrated circuits, and on-chip integration that allows for seamless integra- tion of functions. Among the integrated functions in this system-on-chip architecture is a high quality NTSC/PAL encoder with a triple 10-bit video DAC, allowing for a sig- nificant decrease in system cost. Not only is the CS98100 equipped with an intuitive on- screen display and user interface, but the CS98100 also offers progressive output, DTS decoding, HDCD sup- port, and MP3 plus WMA decoding. Other advanced features include karaoke down-mix. The low cost ex- tended feature set makes the CS98100 ideal for both low-end and high-end system manufacturers.
ORDERING INFORMATION
CS98100-CM 0° to 70° C 208-pin MQFP Memory Controller SDRAM Control FLASH Control RISC I-Cache D-Cache CPU Pipe MAC DSP Instruction Cache X, Y Data Memory CPU/MAC MPEG Decoder VLC Parser IDCT RAM MoCo Dataflow Engine DMA / BitBlit DMA #2 SRAM Buffer Subpicture Decoder Decoder Scaler System Sync STC Interrupts Video Processor On-Screen Display Video/Graphics Scaling Display Audio Interface PCM Out PCM In ADC IEC-958 System Controls PLLExternal Interface DVD ATAPI/ LBUS Interface Serial DVD Interface Infrared Input Programmable I/O 3/4 Wire Serial 2-Wire Serial NTSC/PAL Encoder Registers
3 DACs
JUL ‘02 DS552PP4
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com/en/contacts/sales. IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. “Advance” product information describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of anykind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being reli e do ni sc u r r e n ta n d complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this informationas the basis for manu- facture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organizationw i t hr e s p e ct to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this material and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH AP- PLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I2C system.
- CHARACTERISTICS AND SPECIFICATIONS
1.1 AC AND DC PARAMETRIC SPECIFICATIONS
(AGND, DGND=0V, all voltages with respect to 0V)
1.1.1 ABSOLUTE MAXIMUM RATING
CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS98000 devices operate at the settings described in the next table.
1.1.2 RECOMMENDED OPERATING CONDITIONS
1.1.3 ELECTRICAL CHARACTERISTICS
Symbol Description Min Max Unit VDDIO Power Supply Voltage on I/O ring -0.5 4.6 Volts VDDCORE Power Supply Voltage on core logic and PLL -0.5 2.5 Volts VI Digital Input Applied Voltage (power applied) -0.5 5.5 Volts II Digital Input Forced Current -10 10 mA IO Digital Output Forced Current -50 50 mA TSOL Lead Soldering Temperature 260 oC TVSOL Vapor Phase Soldering Temperature 235 oC TSTOR Storage Temperature (no power applied) -40 125 oC TAMB Ambient Temperature (power applied) 0 70 oC Ptotal Total Power consumption 2 W Parameter Symbol Min Typ Max Units Supply Voltage, IO V DD 3.0 3.3 3.6 Volts Supply Voltage, core and PLL V DD 1.62 1.8 1.98 Volts Ambient Temperature (power applied) T AMB 02 5 7 0 oC Parameter Symbol Conditions Min Typ Max Units Power Supply Supply Voltage, IO V DD 3.0 3.3 3.6 Volts Supply Voltage, core and PLL V DD 1.62 1.8 1.98 Volts Supply Current, IO I DD Normal Operating 45 mA Supply Current, core and PLL I DD Normal Operating 210 mA Digital Pins Input Voltage, High V IH 2.2 Volts Input Voltage, Low V IL 0.8 Volts
Input Current I IN VIN =V DD or VSS -1 +1 µA Input Pull up/down resistor R I 75 K Ω Output Voltage, High V OH @ buffer rating 2.4 Volts Output Voltage, Low V OL @ buffer rating 0.4 Volts High-Z-state Leakage I OZ VOUT =V SS or VDD -1 +1 µA Analog Video Pins Full Scale Current I FS RL =3 7 . 5Ω 34 mA Output Voltage Range V IO RL =3 7 . 5Ω 1.28 Volts DAC to DAC matching1 MAT 2 % Output Voltage Range V out RL= 37.5Ω 1.28 Volts Differential Gain DG 1 % Differential Phase DP 0.5 deg Signal to Noise SNR 74 dB Chrominance AM Noise AM 80 dB Chrominance PM Noise PM 75 dB Only applies each set of three. Parameter Symbol Conditions Min Typ Max Units
1.2 AC CHARACTERISTICS
1.2.1 ATAPI Interface
tween ATAPI device and the CS98100. See Table 1 for the ATAPI symbols and characterization data. Table 1. ATAPI Interface Characteristics Figure 1. ATAPI Interface Timing Diagram
1.2.2 SDRAM Interface
Table 2 show the interface pin timing. Figure 2 shows the refresh cycle performed by the CS98100. action. In both Figure 3 and Figure 4, CAS latency is programmed to 3. Table 2. SDRAM Interface Characteristics Figure 2. SDRAM Refresh Transaction
Figure 5. CS98100 SDRAM Read and Write
1.2.3 DVD Serial Interface Timing
Figure 6 and Table 3 illustrate the signal timing for the DVD serial interface input pins. Table 3. CS98100 DVD Interface Characteristics Figure 6. CS98100 DVD Serial Interface Timing Diagram
1.2.4 Digital Video Interface Timing
grammed as active high or active low. 2.It is recommanded that the output data should be taken at the opposite edge of the CLK27_O. Table 4. CS98100 Digital Video Interface Characteristics Figure 7. CS98100 Digital Video Interface Timing Diagram
1.2.5 Digital Audio Interface Timing
polarity to indicate the polarity is programmable. Table 5. Digital Audio In Characteristics Figure 8. Digital Audio In Timing Diagram
- Active clock edge is programmable. Timing is referenced from active edge.
Table 6. Digital Audio Out Characteristics 2.It is recommanded that the output data should be taken at the opposite edge of the AUD_BCK. Figure 9. Digital Audio Out Timing Diagram
- Active clock edge is programmable. Timing is referenced from active edge.
1.2.6 ROM/NVRAM Interface
Note:Read timing based on 10.5 ns memory clock and 4 programmed wait states. Table 7. RAM/NVROM Characteristics Figure 10. ROM/NVRAM Reading Timing
Figure 11. ROM/NVRAM Write Timing
1.2.7 Miscellaneous Timings
Table 8. Miscellaneous Timing Characteristics 1.XTLCLK must meet the requirement of external the video encoder for correct chroma (27 MHz ± 1 KHz). Figure 12. Miscellaneous Timings
Figure 13 shows an example of a complete high-end DVD solution using the CS98100.
2.1 CS98100 Device Summary
4 Kbyte instruction cache, 2 Kbyte data cache. Single cycle instructions run at 90 MHz. ply accumulate, 32-bit simple integer logic. Single cycle instructions run at 90 MHz.
- Memory Controller Supports SDRAM, and SGRAM, from 2 MBytes to 32 MBytes. Supports multiple banks of FLASH and ROM up to 32 MBytes. 32-bit data bus for DRAM, 8 or 16-bit data bus for ROM. DATA FLOW ENGINE Two DMA controllers – local memory based and direct memory-to-memory 2432 bytes of internal memory, DMA to/from main RAM into local SRAM. Supports endian conversion and byte, short,
Figure 13. CS98100 Application
long data formats on DMA. Supports block transfers for graphics bit blits. MPEG VIDEO DECODER Supports VCD1.0, 1.1, 2.0 and 3.0, SVCD, and DVD video standards. Supports trick features, including smooth 2x forward play. Special anti-tearing logic controls picture de- code and presentation. Advanced error concealment hardware. SYSTEM SYNCHRONIZATION System time clock (STC) for audio/video syn- chronization Flexible interrupt structure for controlling de- code and presentation times Hardware scheduling of sub-picture and high- light events AUDIO INTERFACE Supports 8 channels PCM, I 2Sa tu pt o2 4b i t s and 96 kHz output rate. Simultaneous IEC-958 output with program- mable channel status and user data Also supports S/PDIF receiver for high perfor- mance applications EXTERNAL INTERFACE 2-wire serial master and slave port, second 2- wire master port for controlling DVD device. 3- or 4-wire serial master/slave port. Large number of programmable bi-directional I/O pins. All pins not used for other function can be reas- signed as general purpose I/O pins 8 pins can be used as edge or level detection in- terrupt pins. Hardware-assisted support for infrared remote devices, such as remote control, infrared key- board, mouse, printer, and more. Programmable parallel host master interface supports formats including ATAPI, ISA, and more. IO channel interface supports standard DVD loader protocols Separate serial DVD interface to support low- cost (track buffer-less) loaders VIDEO PROCESSOR On screen display module supports 2-bit or 4- bit, pixel modes. It supports 3 separate regions and 16 transparency overlay levels High quality scaling using 16 tap polyphase programmable vertical and horizontal filters, to support any size image up to 768x576. Multiple video plain overlays (main video / subpicture / picture-in-picture / on-screen dis- play). Gamma Correction. Progressive scan video output VIDEO ENCODER Three 10-bit video DACs, drive 37.5Ω load di- rectly without external buffering Supports PAL (B,D,G,H,I,N) and NTSC Component (RBG or YUV) or composite + S- Video output Progressive or interlaced mode output Macrovision 7.1 support (interlaced) and Mac- rovision 1.03 support (progressive) Wide-screen signaling support (interlaced and progressive) and CGMS support Closed captioning support SUB-PICTURE PROCESSOR Run-length decode DVD sub-pictures and SVCD OGT formats Hardware vertical scaling supports NTSC-PAL format conversion 16 level alpha blending System Functions 208-pin MQFP package. All I/O pins are 3V with 5V tolerance. Advanced 0.18 micron CMOS technology. Chip runs at 90 MHz Supports Low power modes and clock shutoff.
- FUNCTIONAL DESCRIPTION
3.1 RISC Processor
The CS98100 includes a powerful, proprietary 32- bit RISC processor with optimizing C compiler support. The RISC has a MIPS-compatible instruc- tion set, as well as a MAC engine which performs multiply/accumulate in 2 cycles in a pipelined fash- ion with C support, effectively achieving single cy- cle throughout. The CS98100 fully supports many Real Time Operating Systems (RTOS). The RISC processor co-ordinates on-chip multi-threaded tasks, as well as supervises system activities such as remote control and VFD front panel control.
3.2 DSP Processor
The CS98100 contains a proprietary digital signal processor (DSP) which is optimized for audio ap- plications. The DSP performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. There are 32 general- purpose registers, and eight independent address generation registers, featuring: post-increment ALU, linear and circular buffer operations, bit re- verse ALU operations, and dual operand read from memory. The multiply-accumulator has single-cy- cle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking opera- tions. The interface to main memory is designed for bursting flexible block sizes and skip counts.
3.3 Memory Control
The DRAM Interface performs the SDRAM con- trol and arbitration functions for all the other mod- ules in the CS98100. The DRAM interface services and arbitrates a number of clients and stores their code and/or data within the local memory. This ar- bitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. The DRAM Interface supports up to 32 MByte. For a typical DVD player application, CS98100 requires 8 MByte of SDRAM and 1 MByte of FLASH. Sharing the same interface, the CS98100 also sup- ports flash ROM, OTP, or masked ROM interface. Code is stored in ROM. After the system is booted, the code is shadowed inside DRAM for execution. FLASH ROM interface is provided so that the code can be upgraded in field once the communication channel is established via, for example, CD-R or serial port. Utility software will be provided to de- bug and upgrade code for the system manufacturer.
3.4 Dataflow Control (DMA)
The DMA controller moves data between the exter- nal memory and an internal memory. The external memory address can be specified using a register, or in FIFO mode, using start and end address regis- ters. Separate start/end address registers are used for DMA read and write operations. The DMA in- terface also has a block transfer function, which al- lows for the transfer of one block of data from one external memory location to another external mem- ory location. In effect, combining a DMA read and write into one operation. In addition, the DMA write operation allows for byte, short, word, and other types of masking. A second dedicated DMA controller provides for fast memory-to-memory transfers.
3.5 System Control Functions
The system control functions are used to coordinate the activities of the multiple processors, and to pro- vide the supporting system operations. Four 32-bit communication registers are available inter-pro- cessor communication, and eight semaphore regis- ters are used for resource locking. Timers are available for general-purpose functions, as well as more specialized functions such as watchdog tim- ers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. Three separate serial interfaces, conforming to in- dustry-standard protocols, are available for a vari-
ety of system interface functions. Interrupts can be generated on specific or generic events. Infrared in- puts can be filtered of glitches or stored unfiltered into memory. Power-down control of the internal clocks is also possible. Internal PLLs are used to generate the internal system and memory clocks, and audio clocks of any widely used frequency.
3.6 DVD/ATAPI Interface
The CS98100 has a programmable interface port, which can be configured to connect to industry standard CD/DVD loaders without external glue logic. The CD/DVD interface fully supports a wide range of popular CD/DVD loaders. The interface consists of DVD control and data ports, and an op- tional CD control/data port. The CS98100 hard- ware manages the DVD interface and moving data to an arbitrary size input FIFO in DRAM. The same interface pins can be optionally config- ured as a generic 16-bit host master port. In this mode, the CS98100 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. The interface can be set up in ATAPI mode, to connect directly to any ATAPI DVD loader (using two chip selects). Si- multaneously, the other two chip selects can be configured to connect to other devices, such as a super I/O chip or hard disk. A third option is to configure the interface for mi- cro-less DVD loader operation, which may also be configured to connect without external glue logic.
3.7 Serial DVD Interface
The CS98100 has a 4-pin serial port which interfac- es to the data port of popular low-cost DVD load- ers. This type of loader provides for low system cost by eliminating the track buffer, interface FIFO, and flow control logic. The CS98100 con- tains a large internal SRAM to handle high burst data rates, without requiring reverse flow control. The track buffer resides in the CS98100 SDRAM, which reduces system complexity and simplifies the software architecture. The CS98100 performs error detection, sector number tracking, and inter- rupt generation.
3.8 MPEG Video Decoding
Compressed MPEG data is read from the DVD disk into an input FIFO in DRAM. The data flow (DMA) controller moves Video packets from the input FIFO into the MPEG decoder ’s input FIFO (also in DRAM). The DMA controller can also per- form advanced functions such as start code search, relieving the RISC processor. The System Sync function is used to control the timing of MPEG pic- ture decoding. The MPEG Video decoder process- es I, B and P frames, and writes to video frame buffers in DRAM, for output to the display. Special anti-tearing logic ensures currently displayed frame buffers are not overwritten.
3.9 Audio Processing
Compressed Audio data is read from the DVD disk into an input FIFO in DRAM. The data is decom- pressed, then written to a PCM output FIFO, also in DRAM. Presentation time stamps (PTS) are ex- tracted from the stream to update the STC, in order to maintain audio/video synchronization. The DMA and decompression stages of audio process- ing can be done with a combination of the DMA unit, DSP and RISC processors. The DSP is opti- mized for audio processing, so most common for- mats can be handled by the DSP alone, including AC-3, MPEG2 audio, and others. The DSP has enough reserve bandwidth to handle the Karaoke echo-mix and pitch shift, and AC-3 down-mix functions. The audio output data is written into a DRAM FIFO in 16, 18, 20 or 24-bit PCM format. A flexi- ble audio output stage can simultaneously output 8 channels of PCM data to audio DACs, plus an IEC- 958 encoded output, at up to 96 kHz. The IEC-958 output has fully programmable channel status (commercial), and provides a flexible solution to support all IEC-958 modes for User Data.
The audio interface also includes a flexible PCM input interface, which can input a wide range of protocols from IEC-958 receiver. Another, low- cost approach for audio input is the internal sigma- delta demodulator. This module inputs a digital PWM version of the audio input, which can be cre- ated on the board using an inexpensive ramp gener- ator and comparator. The sigma-delta demodulator uses a set of programmable filters to reconstruct 9- bit (mono) audio data at up to 12 kHz sampling fre- quency.
3.10 Video Processing
The CS98100 Video processor is a powerful, fully programmable video post processing engine that displays video on an interlaced TV or a progressive HDTV. A 16-tap polyphase vertical filter is fully programmable on a line-by-line basis, to provide high quality vertical scaling and interlaced field conversion. Horizontal filtering is done with a pro- grammable 16-tap polyphase filter. This advanced filter processing is used for de-interlacing, zoom, and frame size conversion. Source mode of interlaced or progressive is deter- mined from the disk type automatically. For pro- gressive source detection, 3:2 pulldown is detected from status flags in the video stream to ensure op- timized playback. Interlaced video source is fil- tered up to progressive size output using the bilinear vertical filter. This is visibly superior to simple line doubling. Each 240 line field being fil- tered and output at 480p. Progressive video source is output at the full progressive resolution. Each 480 line frame output at 480p. Source mode of in- terlaced or progressive is determined from the disk type. For progressive source detection, 3:2 pull- down is simply detected from status flags in the video stream. Zoom is fully programmable, from 1X to 500X zoom, with any value in between. Frame type con- version, from NTSC to PAL, or PAL to NTSC, is done with a the bilinear vertical filter, reducing flicker and jaggies. There is a programmable gamma-correction look- up table for the final output. Cirrus Logic provides some easy to use utilities in order to get the best ad- vantage of the powerful video filtering capabilities of the CS98100. The video encoder sends progres- sive or interlaced digital video data to the internal video encoder, and can output parallel digital data to an external video encoder. The video processor also allows multiple video plain overlay (main video / sub-picture / on-screen display). The sub-picture unit is a hardware-only solution which performs high-quality vertical scal- ing for PAL/NTSC conversion, and full support for DVD (sub-picture) and SVCD (OGT) modes. The on-screen display unit features 2-bit and 4-bit pix- els, 16 transparency levels, and three independent regions of up to full-screen size. The picture-in-pic- ture unit can place a 1/2 or 1/4 screen sized window anywhere on the screen. This feature can be used for special effects, such as snapshot freeze and zoom assist.
3.11 Video Encoder
The video encoder uses three 10-bit DACS to con- vert digital data to component (RGB or YP RPB)o r composite (composite plus S-Video) analog video. The output can be interlaced (PAL/NTSC) or high resolution progressive. In progressive mode, the video encoder will typically drive YPRPB to a 525- line television at 59.94 Hz, although other output modes are possible, such as 625 lines and RGB. The encoder performs the Macrovision copy pro- tection function for all modes (revision 7.1 for in- terlaced, revision 1.03 for progressive). Other features include built-in voltage reference, color bar generator, individual power-down control for each DAC, programmable baseband filters, col- or/contrast/tint controls, Closed Captioning (inter- laced modes), wide screen signalling (PAL mode), and Copy Generation Management System (NTSC and progressive modes).
4.1 Processor Memory Map
Table 10 lists the memory map as viewed by host slave port. Table 9. Memory Map - RISC Processor Table 10. Host Port Memory Map
4.3 Internal IO Space Map
the RISC processor debug port.
4.4 CS98100 Register Space
Table 12 lists the register groups, and how they are split among the main CS98100 functional blocks. read/write (R/W), read only (RO) or write only (WO). Table 11. Internal IO Space Map Table 12. CS98100 Register Map and Blocks
0 R/W General Command
10 R/W General InterProc_Comm_Register_0
14 R/W General InterProc_Comm_Register_1
18 R/W General InterProc_Comm_Register_2
20 R/W General Semaphore_Register_0
24 R/W General Semaphore_Register_1
28 R/W General Semaphore_Register_2
30 R/W General Semaphore_Register_4
34 R/W General Semaphore_Register_5
38 R/W General Semaphore_Register_6
40 RO General (Genio) GenIO_Read_Data
44 R/W General (Genio) GenIO_Write_Data
48 R/W General (Genio) GenIO_Three_State_Enable
50 R/W General (Genio) GenIO_Negative_Edge
54 R/W General (Genio) GenIO_Interrupt_Status
58 R/W General (Genio) GenIO_Positive_Edge_Mask
60 R/W General (Genio) GenIO_Level_Mask
1040 RO General (Genio) GenIO2_Read_Data
1044 R/W General (Genio) GenIO2_Write_Data
1048 R/W General (Genio) GenIO2_Three_State_Enable
1064 R/W General (Genio) GenIO2_Mode
1068 RO General (Genio) GenIODVD_Read_Data
Table 13. CS98100 Registers
1070 R/W General (Genio) GenIODVD_Three_State_Enable
1074 R/W General (Genio) GenIODVD_Mode
68 R/W General (Serial IF1) Ser1_Mstr_Byte_Read_Subaddress_Write
70 R/W General (Serial IF1) Ser1_Mstr_Write_2Bytes
74 R/W General (Serial IF1) Ser1_Mstr_Control
78 RO General (Serial IF1) Ser1_Mstr_Status
80 R/W General (Interrupt) RSK_Interrupt_Mask
84 WO General (Interrupt) RSK_Interrupt_Set
88 R/W General (Interrupt) RSK_Interrupt_Status
90 R/W General (Interrupt) DSP_Interrupt_Mask
94 WO General (Interrupt) DSP_Interrupt_Set
98 R/W General (Interrupt) DSP_Interrupt_Status
Table 13. CS98100 Registers (Continued)
1000 R/W General (DMA) DMA2_Source_Addr
1004 R/W General (DMA) DMA2_Dest_Addr
1008 R/W General (DMA) DMA2_Size
100 R/W Host Device_1_Control
104 R/W Host Device_2_Control
108 R/W Host Device_3_Control
110 R/W Host Write_Data_Port
114 RO Host Read_Data_Port
120 R/W Host Host_Start_Address
124 R/W Host Dram Start Address
128 R/W Host Stream_Transfer_Size
134 R/W General Ser1_Slave_Address
200 R/W Dram controller DRAM_Controller_Priority0
204 R/W Dram controller DRAM_Controller_Priority1
208 R/W Dram controller DRAM_Controller_Priority2
210 R/W Dram controller DRAM_Controller_Priority4
214 R/W Dram controller DRAM_Controller_Setup
218 R/W Dram controller DRAM_Command
300 WO DMA DMA_Enable
304 R/W DMA DMA_Control
308 RO DMA DMA_Status
310 R/W DMA Dram_Byte_Start_Addr
314 R/W DMA Sram_Byte_Start_Addr
318 R/W DMA Fifo_Start_Rd_Addr
328 R/W DMA Search_Control
330 R/W DMA Fifo_End_Rd_Addr
334 R/W DMA Fifo_End_Wr_Addr
338 R/W DMA Lines_and_Skip
400 R/W CD/DVD DVD_Control
404 R/W CD/DVD DVD_Fifo_Base_Address
408 R/W CD/DVD DVD_Fifo_Size
410 RO CD/DVD DVD_Start_of_Sector
414 RO CD/DVD DVD_Current_Dram_Address
418 R/W CD/DVD CD_Control
438 RO CD/DVD DVD_Status
440 R/W CD/DVD DCI_Control_Reg
444 RO CD/DVD DCI_Status
448 R/W CD/DVD DCI_Dram_Rd_Start_Addr
450 R/W CD/DVD DCI_Mbytes_Sent
454 R/W CD/DVD DCI_Mbytes_Switch
458 RO CD/DVD DCI_Diagnostic
500 R/W DVDS DVDS_Control
504 R/W DVDS DVDS_DataSwap _Mode
508 R/W DVDS DVDS_Flow_Control_Ref
510 R/W DVDS Track_Buffer_Base
514 R/W DVDS Track_Buffer_End
518 RO DVDS Track_Buffer_Current_Address
534 RO DVDS DVDS_Sector_ID
544 R/W DVDS Interrupt_Status
548 R/W DVDS Interrupt_Enable
550 R/W DVDS Input_Data_Counter
600 WO DSP DSP_Boot_Code_Start_Address
604 WO DSP DSP_Run_Enable
700 R/W Sync Control Audio_Sync_Control
704 R/W Sync Control Video_Sync_Control
708 RO Sync Control Video_Sync_Status
710 R/W Sync Control Frame_Period
714 R/W Sync Control STC_Interval
718 R/W Sync Control System_Time_Clock
720 R/W Sync Control Video_PTS_FIFO_Start_Address
724 R/W Sync Control Video_PTS_FIFO_End_Address
728 R/W Sync Control Video_PTS_FIFO_Write_Address
730 R/W Sync Control Subpicture_PTS_FIFO_Start_Address
734 R/W Sync Control Subpicture_PTS_FIFO_End_Address
738 R/W Sync Control Subpicture_PTS_FIFO_Write_Address
740 R/W Sync Control Highlight_Start_PTS
744 R/W Sync Control Highlight_End_PTS
748 R/W Sync Control Button_End_PTS
750 R/W Sync Control Video_PTS
754 R/W Sync Control Audio_PTS
758 RO Sync Control Subpicture_PTS
760 RO Sync Control Video_Sync_Debug
764 R/W Sync Control SP_DRC_VPTS_Debug
768 R/W Sync Control Frame_Count_Interrupt
770 RO Sync Control Sync_Interrupt_Status
774 R/W Sync Control Sync_Interrupt_Control
778 WO Sync Control Sync_Interrupt_Set
840 R/W MPEG Vid Decoder MPEG_P_Base_Register
844 R/W MPEG Vid Decoder MPEG_Dest_Control
848 RO MPEG Vid Decoder MPEG_Software_Flags
854 R/W MPEG Vid Decoder MPEG_AntiTearWindow
858 R/W MPEG Vid Decoder MPEG_Error_Pos
Table 14 lists the conventions used to identify the pin type and direction. Figure 14. CS98100 Pin Layout Table 14. Pin Type and Direction Legend
function and direction are also shown.
1 PLL_1V8 Pwr PLL Power
2 M_A11 O8 O DR_Addr[11] O NVM_Addr[11] O
3 M_A10 O8 O DR_Addr[10] O NVM_Addr[10] O
4 M_A9 O8 O DR_Addr[9] O NVM_Addr[9] O
5 M_D8 B8U I DR_Data[8] B NVM_Data[8] B
6 M_D7 B8U I DR_Data[7] B NVM_Data[7] B
7 M_D6 B8U I DR_Data[6] B NVM_Data[6] B
8 IO_GND Gnd I/O Ground
9 M_D5 B8U I DR_Data[5] B NVM_Data[5] B
10 IO_3V3 Pwr I/O Power
11 M_D4 B8U I DR_Data[4] B NVM_Data[4] B
12 M_D3 B8U I DR_Data[3] B NVM_Data[3] B
13 M_D2 B8U I DR_Data[2] B NVM_Data[2] B
14 M_D1 B8U I DR_Data[1] B NVM_Data[1] B
15 DIG_1V8 Pwr Core Power
16 M_D0 B8U I DR_Data[0] B NVM_Data[0] B
17 DR_CKE B8 O DR_CKE O
18 DIG_GND Gnd Core Ground
19 IO_GND Gnd I/O Ground
20 DR_CKO O8 O DR_CKO O
21 IO_3V3 Pwr I/O Power
22 GPIO1 B4U I GPIO[1] B 1
23 GPIO2 B4U I GPIO[2] B 1
24 GPIO3 B4U I GPIO[3] B 1
Table 15. Pin Assignments
25 GPIO4 B4U I GPIO[4] B 1
26 GPIO5 B4U I GPIO[5] B 1
27 Not used 2
28 Not used 2
29 Not used 2
30 Not used 2
31 Not used 2
32 Not used 2
33 Not used 2
34 Not used 2
35 M_BS_N O8 O DR_BS_N O
36 DIG_1V8 Pwr Core Power
37 DR_AP O8 O DR_AP O
38 DIG_GND Gnd Core Ground
39 IO_GND Gnd I/O Ground
40 DR_RAS_N O8 O DR_RAS_N O
41 IO_3V3 Pwr I/O Power
42 DR_CAS_N O8 O DR_CAS_N O
43 M_D31 B8U I DR_Data[31] B 3
44 M_D30 B8U I DR_Data[30] B 3
45 M_D29 B8U I DR_Data[29] B 3
46 M_D28 B8U I DR_Data[28] B 3
47 M_D27 B8U I DR_Data[27] B NVM_Addr[23] O 3
48 IO_GND Gnd I/O Ground
49 M_D26 B8U I DR_Data[26] B NVM_Addr[22] O 3
50 IO_3V3 Pwr I/O Power
51 M_D25 B8U I DR_Data[23] B NVM_Addr[21] O 3
Table 15. Pin Assignments (Continued)
52 M_D24 B8U I DR_Data[24] B NVM_Addr[20] O 3
53 M_D23 B8U I DR_Data[23] B NVM_Addr[19] O 3
54 M_D22 B8U I DR_Data[22] B NVM_Addr[18] O 3
55 M_D21 B8U I DR_Data[21] B NVM_Addr[17] O 3
56 GPIO6 B4U I GPIO[6] B 1
57 GPIO7 B4U I GPIO[7] B 1
58 IO_GND Gnd I/O Ground
59 NVM_CE_N O4 O NVM_CE_N O
60 NVM_OE_N O4 O NVM_OE_N O
61 NVM_WE_N O4 O NVM_WE_N O
62 IO_3V3 Pwr I/O Power
63 M_D20 B8U I DR_Data[20] B NVM_Addr[16] O 3
64 M_D19 B8U I DR_Data[19] B NVM_Addr[15] O 3
65 M_D18 B8U I DR_Data[18] B NVM_Addr[14] O 3
66 H_A2 B4 I Hst_Addr[2] O GPIO_D[25] B
67 H_A1 B4 I Hst_Addr[1] O GPIO_D{[24] B
68 H_A0 B4 I Hst_Addr[0] O GPIO_D[23] B
69 H_ALE B4U I Hst_ALE O GPIO_D[26] B
70 M_D17 B8U I DR_Data[17] B NVM_Addr[13] O 3
71 IO_GND Gnd I/O Ground
72 M_D16 B8U I DR_Data[16] B NVM_Addr[12] O 3
73 M_D15 B8U I DR_Data[15] B NVM_Data[15] B
74 M_D14 B8U I DR_Data[14] B NVM_Data[14] B
75 IO_3V3 Pwr I/O Power
76 M_D13 B8U I DR_Data[13] B NVM_Data[13] B
77 M_D12 B8U I DR_Data[12] B NVM_Data[12] B
78 M_D11 B8U I DR_Data[11] B NVM_Data[11] B
79 DIG_1V8 Pwr Core Power
80 M_D10 B8U I DR_Data[10] B NVM_Data[10] B
81 DIG_GND Gnd Core Ground
82 IO_GND Gnd I/O Ground
83 M_D9 B8U I DR_Data[9] B NVM_Data[9] B
84 M_A8 O8 O DR_Addr[8] O NVM_Addr[8] O
85 M_A7 O8 O DR_Addr[7] O NVM_Addr[7] O
86 IO_3V3 Pwr I/O Power
87 H_D3 B4 I Hst_Data[3] B GPIO_D[3] B DVD_Data[3] I
88 H_D2 B4 I Hst_Data[2] B GPIO_D[2] B DVD_Data[2] I
89 H_D1 B4 I Hst_Data[1] B GPIO_D[1] B DVD_Data[1] I
90 H_D0 B4 I Hst_Data[0] B GPIO_D[0] B DVD_Data[0] I
91 H_CS3 B4 I Hst_CS[3] O GPIO_D[21] B
92 H_CS2 B4 I Hst_CS[2] O GPIO_D[20] B
93 H_CS1 B4 I Hst_CS[1] O GPIO_D[19] B DVD_Error I
94 H_CS0 B4 I Hst_CS[0] O GPIO_D[18] B DVD_SOS I
95 IO_GND Gnd I/O Ground
96 M_A6 O8 O DR_Addr[6] O NVM_Addr[6] O
97 M_A5 O8 O DR_Addr[5] O NVM_Addr[5] O
98 M_A4 O8 O DR_Addr[4] O NVM_Addr[4] O
99 IO_3V3 Pwr I/O Power
100 M_A3 O8 O DR_Addr[3] O NVM_Addr[3] O
101 M_A2 O8 O DR_Addr[2] O NVM_Addr[2] O
102 M_A1 O8 O DR_Addr[1] O NVM_Addr[1] O
103 M_A0 O8 O DR_Addr[0] O NVM_Addr[0] O
104 IO_GND Gnd I/O Ground
105 VDAT0 B4 O Vid_Data[0] O GPIO_2[0] B
106 VDAT1 B4 O Vid_Data[1] O GPIO_2[1] B
107 VDAT2 B4 O Vid_Data[2] O GPIO_2[2] B
108 VDAT3 B4 O Vid_Data[3] O GPIO_2[3] B
109 VDAT4 B4 O Vid_Data[4] O GPIO_2[4] B
110 VDAT5 B4 O Vid_Data[5] O GPIO_2[5] B
111 VDAT6 B4 O Vid_Data[6] O GPIO_2[6] B
112 VDAT7 B4 O Vid_Data[7] O GPIO_2[7] B
113 HSYNC O8 O Vid_Hsync O
114 VSYNC O8 O Vid_Vsync O
115 SER_RDY B4U I SER_CS B GPIO_2[8] B
116 IO_3V3 Pwr I/O Power
117 SER_DO B4U I SER_Dout B GPIO_2[9] B
118 SER_DI B4U I SER_Din B GPIO_2[10] B
119 SER_CLK B4U I SER_Clock B GPIO_2[11] B
120 AUD_XCK B4U I AUD_XCK B
121 AUD_BCK B4U O AUD_BCK O GPIO_2[12]
122 AUD_LRCK O4 O AUD_LRCK O
123 H_WR B4 I Hst_Write O GPIO_D[17] B DVD_ENA I
124 H_RD B4 I Hst_Read O GPIO_D[16] B DVD_RDY O
125 MFG_TEST I I (Tie to ground) I
126 IO_GND Gnd I/O Ground
127 DIG_GND Gnd Core Ground
128 AUD_DO0 B4 O AUD_Dout[0] O
129 DIG_1V8 Pwr Core Power
130 AUD_DO1 B4U O AUD_Dout[1] O GPIO_2[13] B
131 AUD_DO2 B4U O AUD_Dout[2] O GPIO_2[14] B
132 AUD_DO3 B4U O AUD_Dout[3] O GPIO_2[15] B
133 Not used 2
134 AIN_DATA B4U I AIN_DATA I GPIO_2[16] B I
135 Not used 2
136 AIN_LRCK B4U I AIN_LRCK I GPIO_2[17] B
137 IEC958_O O4 O AUD_IEC958 O
138 GPIO0 B4U I GPIO[0] B 1
139 MS_SCL1 B4SU I M_SCL2 B GPIO_2[18] B
140 MS_SDA1 B4SU I M_SDA2 B GPIO_2[19] B
141 IO_3V3 Pwr I/O Power
142 M_SCL2 B4SU I M_CLK2 B GPIO_2[20] B
143 M_SDA2 B4SU I M_DAT2 B GPIO_2[21] B
144 DVDS_CLK IU I DVDS_CLK I
145 DVDS_DAT B4U I DVDS_DAT I GPIO_2[23] B
146 DVDS_VLD B4U I DVDS_VLD B GPIO_2[25] B
147 DVDS_SOS B4U I DVDS_SOS B GPIO_2[24] B
148 CLK27_O B4U O Vid_Clock O GPIO_2[22] B
149 Not used 2
150 Not used 2
151 Not used 2
152 IR_IN IS I Infrared I
153 IO_GND Gnd I/O Ground
154 RST_N IS I Reset_L I
155 Not used 2
156 PLL_1V8 Pwr PLL Power
157 PLL_GND Gnd PLL Ground
158 H_RDY B4S I Hst_Ready O GPIO_D[22] B DVD_STB I
159 DIG_GND Gnd Core Ground
160 H_D15 B4 I Hst_Data[15] B GPIO_D[15] B CD_DATA I
161 DIG_1V8 Pwr Core Power
162 H_D14 B4 I Hst_Data[14] B GPIO_D[14] B CD_LRCK I
163 H_D13 B4S I Hst_Data[13] B GPIO_D[13] B CD_BCLK I
164 H_D12 B4 I Hst_Data[12] B GPIO_D[12] B CD_C2P0 I
165 H_D11 B4 I Hst_Data[11] B GPIO_D[11] B DVDL_DI I
166 H_D10 B4 I Hst_Data[10] B GPIO_D[10] B DVDL_DO O
167 H_D9 B4 I Hst_Data[9] B GPIO_D[9] B DVDL_RDY I
168 H_D8 B4 I Hst_Data[8] B GPIO_D[8] B DVDL_CK O
169 IO_3V3 Pwr I/O Power
170 H_D7 B4 I Hst_Data[7] B GPIO_D[8] B DVD_Data[7] I
171 H_D6 B4 I Hst_Data[6] B GPIO_D[8] B DVD_Data[6] I
172 H_D5 B4 I Hst_Data[5] B GPIO_D[8] B DVD_Data[5] I
173 H_D4 B4 I Hst_Data[4] B GPIO_D[8] B DVD_Data[4] I
174 Not used 2
175 Not used 2
176 Not used 2
177 Not used 2
178 DAC_GND Gnd Analog Ground
179 DAC_1V8 Pwr Digital Power
180 DAC_DGND Gnd Digital Ground
181 U_B_C Analog Video Out O
182 DAC_3V3 Pwr Analog Power
183 DAC_GND Gnd Analog Ground
184 Y_G_Y Analog Video Out O
185 DAC_3V3 Pwr Analog Power
186 DAC_GND Gnd Analog Ground
187 V_R_YC Analog Video O
188 DAC_3V3 Pwr Analog Power
189 DAC_GND Gnd Analog Ground
190 COMP Analog Compensation O
191 RSET Analog Current Set B
192 VREF Analog Voltage Ref B
193 DAC_3V3 Pwr Analog Power
194 DAC_GND Gnd Analog Ground
195 DAC_GND Gnd Analog Ground
196 DAC_3V3 Pwr Analog Power
198 IO_GND Gnd I/O Ground
199 DR_WE_N O8 O DR_WE_N O
200 DR_DQM0 O8 O DR_DQM[0] O
201 DR_DQM1 O8 O DR_DQM[1] O
202 DR_DQM2 O8 O DR_DQM[2] O
203 DR_DQM3 O8 O DR_DQM[3] O
204 IO_3V3 Pwr I/O Power
207 IO_GND Gnd I/O Ground
208 PLL_GND Gnd PLL Ground
6.1 Miscellaneous Pins
These pins are used for used for basic functions, such as clocking, reset, and infrared receiver interface. 152 IR_IN I De-modulated infrared Input, from IR receiver.
205 XTLCLK_I I 27 MHz crystal input, or 27 MHz oscillator input
206 XTLCLK_O O 27 MHz crystal output
154 RST_N I Reset Input, active low. 125 MFG_TEST I Manufacturing test pin, should always connect to ground. Table 16. Miscellaneous Interface Pins
6.2 Serial Interface
139 MS_SCL1 B Clock for 2-wire serial port #1 (master/slave port)
140 MS_SDA1 B Data for 2-wire serial port #1 (master/slave port)
142 M_SCL2 B Clock for 2-wire serial port #2 (master)
143 M_SDA2 B Data for 2-wire serial port #2 (master)
119 SER_CLK B Clock for 4-wire serial port (output for master mode, input
117 SER_DO B Output data for 4-wire serial port – may function as bi-
directional data in 3-wire mode.
118 SER_DI B Input data for 4-wire serial port
115 SER_CS B Chip select for 4-wire serial port (output for master mode,
Table 17. Serial Interface Pin Assignments
6.3 SDRAM Interface
terface any particular configuration of SDRAM.
20 DR_CKO O Memory Clock
17 DR_CKE O Memory Clock Enable
35 DR_BS_N O Bank Selection. Always connect to RAM BS or BS0 pin. 37 DR_AP O Memory Auto Pre-charge. Always connect to RAM AP pin.
40 DR_RAS_N O Memory Row Address Strobe
42 DR_CAS_N O Memory Column Address Strobe
199 DR_WE_N O Memory Write Enable
Table 18. SDRAM Interface Pin Assignments
6.4 ROM/NVRAM Interface
28 M_A[11:0] O NVM_Addr[11:0], Memory Address Bus[11:0] (shared with
59 NVM_CE_N O ROM/NVRAM Chip Enable. 60 NVM_OE_N O ROM/NVRAM Output Enable. 43 M_D[31] O Copy of ROM/NVRAM Output Enable. 61 NVM_WE_N O NVRAM Write Enable. Table 19. ROM/NVRAM Interface Pin Assignments
6.5 Digital Video Output Interface
output on both edges of the clock. sync, for example to drive syncs to a VGA monitor.
113 HSYNC O Horizontal Sync output
114 VSYNC O Vertical or combined vertical/horizontal Sync output
148 CLK27_O O 27 MHz Clock Output. VDAT[7:0] O Video Data Output[7:0] in YCrCb format. Table 20. Video Output Interface Pin Assignments
6.6 Audio Output/Input Interface
output, it’s generated from CS98100 internal PLL. 122 AUD_LRCK O Audio Out Left/Right Clock to serial DAC.
128 AUD_DO0 O Audio Serial PCM Data Out[0] (Front)
130 AUD_DO1 O Audio Serial PCM Data Out[1] (Surround)
131 AUD_DO2 O Audio Serial PCM Data Out[2] (Center + LFE)
132 AUD_DO3 O Audio Serial PCM Data Out[3] (2-channel downmix)
137 IEC958_O O IEC-958 Output
134 AIN_DATA I This input can come from from an external comparator. Table 21. Audio Output Interface Pin Assignments
6.7 Host Master/ATAPI Interface
124 H_RD O Host Read Request. 123 H_WR O Host Write Request. Table 22. Host Master Interface Pin Assignments
6.8 DVD I/O Channel Interface
modes are mutually exclusive.
94 DVD_SOS I DVD data start sector signal from loader
93 DVD_Error I DVD data error signal from loader
124 H_RD O DVD_RDY, DVD data ready signal to loader
123 H_WR I DVD_ENA, DVD data enable signal from loader
158 H_RDY I DVD_STB, DVD data clock from loader
164 CD_C2P0 I CD error signal from loader
163 CD_BCLK I CD clock from loader
162 CD_LRCK I CD left/right clock from loader
160 CD_DATA I CD serial data from loader
168 DVDL_CK O Control port clock to loader
167 DVDL_RD
166 DVDL_DO O Control port serial command to loader
165 DVDL_DI I Control port serial status from loader
Table 23. DVD I/O Channel Interface Pin Assignments
6.9 DVD Serial Data Interface
144 DVDS_CLK I DVD clock input – rising edge is the active edge
145 DVDS_DAT I DVD serial data input (data can be input MSB or LSB first)
146 DVDS_VLD I DVD valid – a bit of data is clocked in when this pin is high
147 DVDS_SOS I DVD start of sector input – active high
Table 24. DVD Serial Data Interface Pin Assignments
6.10 Video Encoder Interface
181 U_B_C O Analog video output – U(YUV), B(RGB), C(Y/C/YC)
184 Y_G_Y O Analog video output – Y(YUV), G(RGB), Y(Y/C/YC)
187 V_R_YC O Analog video output – V(YUV), R(RGB), YC(Y/C/YC)
191 RSET B Current adjust pin, connect through 174 Ω,1% resistor to
Table 25. Video Encoder Interface Pin Assignments
6.11 General Purpose Input/Output (GPIO)
each with individual output three-state controls. either GPIO or normal function for the pin. Table 26. General Purpose I/O Interface Pin Assignments
6.12 Power and Ground
plications engineering for layout guidelines.
180 DAC_DGND Digital ground for video DAC
Table 27. Power and Ground
- 208 PIN MQFP PACKAGE SPECIFICATIONS
Figure 15. CS98100 208-Pin MQFP Package Drawing
- Notes