CS98000 CIRRUS | Alldatasheet
Document overview
- Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
- PDF pages: 46
Technical content
Features
l Powerful Dual 32-bit RISCs >160 MIPS l Software based on popular RTOS, C/C++ l MPEG video decoder supports DVD, VCD, VCD 3.0, and SVCD standards l Video input with Picture-in-Picture and zoom l 8-bit multi-region OSD w/vertical flicker filter l Universal subpicture unit for DVD and SVCD l PAL<->NTSC Scaling and Transcoding l Supports SDRAM and FLASH memories l Powerful 32-bit Audio DSP >80 MIPS l Decodes: AC-3, DTS, MPEG Stereo l Plays MP3 CDs l Karaoke echo mix and pitch shift l Optional 3-D Virtual, bass & treble control l Up to 8-channel PCM output l IEC-60958/61937 Out: AC-3, DTS, MPEG l Multi-Mode Serial Audio I/O: I2S & AC-Link l AV Bus or ATAPI interface or DVD/CD/HD l GPIO support for all common sub-circuits
Description
Overall the CS98000 Crystal DVD Processor is tar- geted as a market specific consumer entertainment processor that empowers new product classes with the inclusion of a DVD player as a fundamental fea- ture. You can use this integrated circuit with all the other Crystal mixed signal data converters, DSPs, and the CS98000’s high quality factory firmware to rapidly conceptualize, design, and market cutting- edge Internet age products such as:
- DVD A/V Mini-Systems
- DVD Players
- DVD Receivers
- Car/SUV Entertainment Units
ORDERING INFORMATION
CS98000-CM 0° to 70° C 208-pin Memory Controller SDRAM Control FLASH Control RISC-1 I-Cache D-Cache MMU MAC RISC-2 I-Cache D-Cache MMU MAC MPEG Decoder VLC Parser IDCT RAM MoCo Dataflow Engine DMA / BitBlit SRAM Buffer Subpicture Decode Scaler Video Input Filter Scaler Video Processor On-Screen Display Picture-in-Picture Video/Graphics Display Audio I/O PCM Out PCM In XMT958 Registers STC Interrupts System Controls Clock Manager External I/Os Remote Input GPIOs SDRAM A/V Bus ATAPI-IDE Local Bus 32- Bit DSP CPU / MAC I-Cache X,Y Data Memory NOV ‘01 DS525PP2
Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/ Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information de- scribes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All prod- ucts are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic web site or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which Purchase of I2C components of Cirrus Logic, Inc., or one of its sublicensed Associated Companies conveys a license under the Phillips I2C Patent Rights to use those components in a standard I2C system.
- CHARACTERISTICS AND SPECIFICATIONS
1.1 AC AND DC PARAMETRIC SPECIFICATIONS
(AGND, DGND=0V, all voltages with respect to 0V)
1.1.1 ABSOLUTE MAXIMUM RATING
CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS98000 devices operate at the settings described in the next table.
1.1.2 RECOMMENDED OPERATING CONDITIONS
Symbol Description Min Max Unit VDDIO Power Supply Voltage on I/O ring -0,5 4.6 Volts VDDCORE Power Supply Voltage on core logic and PLL -0.5 3.6 Volts VI Digital Input Applied Voltage (power applied) -0.5 5.5 Volts II Digital Input Forced Current -10 10 mA IO Digital Output Forced Current -50 50 mA TSOL Lead Soldering Temperature - 260 oC TVSOL Vapor Phase Soldering Temperature - 220 oC TSTOR Storage Temperature (no power applied) -40 125 oC TAMB Ambient Temperature (power applied) 0 70 oC PIO Power consumption on I/O ring (CL = 35 pF) - 57 mA PCORE Power consumption on the core logic - 620 mA PPLL Power consumption on the PLL logic - 15 mA Parameter Symbol Min Typ Max Units Supply Voltage, IO VDD 3.0 3.3 3.6 Volts Supply Voltage, core and PLL VDD 2.25 2.5 2.75 Volts Ambient Temperature(power applied) TAMB 0 25 70 oC
1.1.3 ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ Max Units Supply Current, IO IDD Normal Operating - 45 - mA Supply Current, core and PLL IDD Normal Operating - 550 - mA Input Voltage, High VIH 2.0 - 5.0 Volts Input Voltage, Low VIL - - 0.8 Volts Input Current IIN VIN = VDD or VSS -1 - +1 µA Input Pull up/down resistor RI - 75 - KΩ Output Voltage, High VOH @ buffer rating 2.4 - - Volts Output Voltage, Low VOL @ buffer rating - - 0.4 Volts Three-state Leakage IOZ VOUT = VSS or VDD -10 - +10 µA Input Capacitance CIN - 3 - pF Output Capacitance COUT 3 6 pF Bidirect Capacitance CBID 3 6 pF
1.2 DC CHARACTERISTICS
1.2.1 ATAPI Interface
between ATAPI device and CS98000. Committee on Information Technology Standards (NCITS).See http://www.t13.org/. 1.Values are guaranteed by design only. Table 1. ATAPI Interface Symbols / Characterization Data Figure 1. ATAPI Transactions - Read and Write
1.2.2 SDRAM Interface
terface timing. In both Figure3 and Figure4 , CAS latency is programmed to 3. 1.Values are guaranteed by design only. Table 2. SDRAM Interface Symbols and Characterization Data Figure 2. SDRAM Refresh Transaction Figure 3. SDRAM Burst Write Transaction
1.2.3 ROM/NVRAM Interface
1.Values are guaranteed by design only. Table 3. ROM/NVRAM Interface Symbols and Characterization Data Figure 6. ROM/RVRAM Timing
1.2.4 Video Output Interface
Figure 7. Video Output Timing Table 4. Video Output Interface Symbols and Characterization Data
1.2.5 Video Input Interface
Figure 8. Video Input Timing Table 5. Video Input Interface Symbols and Characterization Data
1.2.6 Audio Input Interface
Table 6. Audio Input Interface Symbols and Characterization Data Figure 9. Audio Input Timings
1.2.7 Audio Output Interface
Table 7. Audio Output Interface Symbols and Characterization Data Figure 10. Audio Output Timing
1.2.8 AC97/CODEC Interface
Figure 11. CODEC Timing Table 8. AC97/CODEC Interface Symbols and Characterization Data
1.2.9 Miscellaneous Interface Timing
1.XTLCLOCK must meet the requirement of external the video encoder for correct chroma. Table 9. Miscellaneous Interface Symbols and Characterization Data Figure 12. Miscellaneous Timing
The Figure13 shows a typical example of a complete Internet-DVD solution using the CS98000. Figure 13. CS98000 Typical Application
3.1 Block Diagram
The CS98000 block diagram is shown in Figure14 .
3.2 CS98000 Device Details
3.2.1 RISC-32 Processors
- Two Powerful 32-bit RISC processors (RISC0 and RISC1)
- Virtual memory support
- Optimizing C compiler
- Big or little endian data formats support
- MAC multiply/accumulate in 2 cycles with C support
- 4Kbyte instruction cache, 2Kbyte data cache
- Single cycle instructions, runs at 81Mhz
3.2.2 Powerful 24/32-Bit DSP
- Powerful 24/32 bit DSP processor, programmable through CS98000 API, See CS98000 Software API, (DS525UM1)
- 24-bit fixed point logic, with 54-bit accumulator
- Single-cycle throughput, 2-cycle latency multiply accumulate, 32-bit simple integer logic. 8-Kbyte in- struction cache, 8-Kbyte program visible local mem- ory
- Single cycle instructions, runs at 81Mhz
3.2.3 System Controls
- Includes several hardware lockable semaphore registers
- General-purpose register for inter-processor com- munication
- 32-bit timers for I/O and other uses, with program- mable interval rates
Figure 14. CS98000 Block Diagram
- Both hardware and software interrupts on data or debug
- Built in PLLs generate all required clocks from 27Mhz input clock
3.2.4 Memory Controller
- Supports SDRAM, and SGRAM, from 2Mbytes to 32Mbytes
- Supports multiple banks of FLASH and ROM up to 16Mbytes
- 32-bit data bus for DRAM, 8 or 16-bit data bus for ROM
3.2.5 Data Flow Engine
- 2432 bytes of internal memory
- DMA to/from main RAM into local SRAM
- Supports endian conversion and byte, short, long data formats on DMA
- Supports block transfers for graphics bit blits
3.2.6 MPEG Video Decoder
- Supports VCD, VCD 3.0, SVCD, DVD video stan- dards
- Supports trick features, including smooth 2x play and reverse play
- Special anti-tearing logic controls picture decode and presentation
- Advanced error concealment hardware
3.2.7 System Synchronization
- System time clock (STC) for audio/video synchroni- zation
- Flexible interrupt structure for controlling decode and presentation times
- Hardware scheduling of subpicture and highlight events
3.2.8 Audio Interface
- Supports PCM, I 2S and IEC-958 outputs at up to 96KHz output rate
- 8 output channels, 2 input channels
3.2.9 Video Input
- NTSC/PAL video decoder input interface
- Built in variable down scaling, handles CCIR 601 to QCIF input formats
- Video input image can be displayed in small win- dow, or as main picture
3.2.10 External Interface
- Serial I2C® master and slave port
- 29 independent fully programmable bi-directional I/O pins
- 8 edge or level detection interrupt pins
- Hardware assisted support for infrared remote de- vices, such as remote control, infrared keyboard, mouse, printer, and more
- Programmable parallel host master and slave inter- face supports many formats including ATAPI, ISA, and more
- IO channel interface supports standard DVD loader protocols
- Serial interface supports AC-97 and other standard MODEM CODEC protocols
3.2.11 Video Processor
- Supports 24-bit 4:2:0 and 4:2:2 video modes and 16-bit true color graphics modes.
- On screen display module supports 2-bit, 4-bit, or 8- bit pixel modes, while supporting 3 separate regions and 16 transparency overlay levels
- Picture-in-picture module includes horizontal and vertical downscaling with programmable output siz- es, positions, and borders
- Overlay mixer with RGB to YUV conversion and output formatting
- Supports 4:2:0, 4:2:2, YUV655, RGB565 and RGB555 frame buffer inputs
- Outputs 4:2:2 video in CCIR-601 or CCIR-656 for- mat
- High quality scaling using a vertical and a horizontal 16 taps polyphase programmable filter and sup- ports any size image up to 768x576
- Programmable sharpening and de-blocking filters
- 5 taps programmable adaptative anti-flicker filtering for graphics source
- Master or Slave video sync configuration
- Multiple video plains overlay (main video / video in- put / picture_in_picture / picture/on_screen / dis- play/cursor)
- Gamma correction
3.2.12 Sub-Picture Processor
- Run-length decode DVD sub-pictures and SVCD OGT formats
- Hardware vertical scaling supports NTSC-PAL for- mat conversion
- 16-level alpha blending
- Provides hardware cursor mode for non-DVD appli- cations
3.2.13 System Functions
- 208-pin PQFP packages
- All I/O pins are 3V with 5V tolerance
- Advanced 0.25 micron CMOS technology
- Internal processors run at 81MHz
- Supports Low Power modes and clock shutoff
3.3 RISC Processor
The CS98000 includes two powerful, proprietary 32-bit RISC processors, RISC0 and RISC1, with optimizing C compiler support and source level de- bugger. The RISC processors fully support many Real Time Operation Systems (RTOS). The DVD application user interface resides on RISC1 and is customer programmable. The real time control of low level DVD functions is performed by RISC0. RISC1 gains access to system resources controlled by RISC0 via calls through an Applications Pro- gramming Interface, (see the CS98000 Software API). All RISC0 firmware, API and sample appli- cation code are supplied with the CS98000. The RISC processors also have a MAC engine, which performs multiply/accumulate in 2 cycles in a pipelined fashion with C support, effectively achieving single cycle throughout. The RISC0 pro- cessor coordinates on-chip multi-threaded tasks, as well as system activities such as remote control and front panel control. The DVD application end-user interface resides on RISC1, and any modifications to that interface occur through the CS98000 API.
3.4 DSP Processor
The CS98000 contains a proprietary digital signal processor (DSP), which is optimized for audio ap- plications. The DSP performs 32-bit simple integer operations, and has a 24-bit fixed point logic unit, with a 54-bit accumulator. There are 32 general- purpose registers, and eight independent address generation registers, featuring: linear and circular buffer operations, and dual operand read from memory. The multiply-accumulator has single-cy- cle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking opera- tions. The interface to main memory is designed for handling flexible block sizes and skip counts.
3.5 Memory Control
The DRAM Interface performs the SDRAM con- trol and arbitration functions for all the other mod- ules in the CS98000. The DRAM interface services and arbitrates a number of clients and stores their code and/or data within the local memory. This ar- bitration and scheduling guarantees the allocation of sufficient bandwidth to the various clients. The DRAM Interface supports up to 32Mbytes. For a typical DVD player application, CS98000 requires 8Mbytes memory space. Sharing the same interface, CS98000 also supports FLASH ROM, OTP, or mask ROM interface. Code is stored in ROM. After the system is booted, the code is shadowed inside SDRAM for execution. The FLASH ROM interface is provided so that the code can be upgraded in the field once the commu- nications channel is established (via modem port, CD-R, or serial port). Utility software will be pro- vided to debug and upgrade code for the system manufacturer.
3.6 Dataflow Control (DMA)
The DMA controller moves data between the exter- nal memory and internal memory. The external memory address can be specified using a register, or in FIFO mode, using start and end address regis- ters. Separate start/end address registers are used for DMA read and write operations. The DMA in- terface also has a block transfer function, which al- lows for the transfer of one block of data from one external memory location to another external mem- ory location. In effect, this feature combines a DMA read and write into one operation. In addi- tion, the DMA write operation allows for byte, short, word, and other types of masking.
3.7 System Control Functions
The system control functions are used to coordinate the activities of the multiple processors, and to pro-
vide the supporting system operations. Four 32-bit communication registers are available for inter- processor communication, and eight semaphore registers are used for resource locking. Timers are available for general-purpose functions, as well as more specialized functions such as watchdog tim- ers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. An I2C master allows for control of other I 2C devices, such as a video encoder. An I 2C slave port shares the same pins, and can be used for debug functions. Inter- rupts can be generated on specific or generic events. Infrared inputs can be filtered to make them free of glitches or stored unfiltered into memory. Control of all the internal clocks is also possible. Internal PLLs are used to generate the internal sys- tem and memory clocks and audio clocks of any widely used frequency.
3.8 DVD/ATAPI Interface
The CS98000 has a programmable interface port which can be configured to connect to industry standard CD/DVD loaders without external glue logic. The CD/DVD interface fully supports many popular CD/DVD loaders. The interface consists of DVD control and data ports and an optional CD control/data port. The CS98000 hardware manages the DVD inter- face and moving data to an arbitrary size input FIFO in DRAM. The same interface pins can be optionally configured as a generic 16-bit host mas- ter port. In this mode, the CS98000 can control up to four devices (using 4 chip select outputs), each of which may use different protocol and timing. The interface can be set up in ATAPI mode, to con- nect directly to any ATAPI DVD loader (using two chip selects). Si- multaneously, the other two chip selects can be configured to connect to other devices, such as a super I/O chip or hard disk. A third option is to configure the interface for mi- cro-less DVD loader operation, which may also be configured to connect without external glue logic.
3.9 MPEG Video Decoding
Compressed MPEG data is read from the DVD disk into an input FIFO in DRAM. The data flow (DMA) controller moves Video packets from the input FIFO into the MPEG decoder’s input FIFO (also in DRAM). The DMA controller can also per- form advanced functions such as start code search, relieving the RISC processors. The System Syn- chronization function is used to control the timing of MPEG picture decoding. The MPEG Video de- coder processes I, B, and P frames, and writes to video frame buffers in DRAM for output to the dis- play. Special anti-tearing logic ensures that cur- rently displayed frame buffers are not overwritten.
3.10 Audio Processing
Compressed Audio data is read from the DVD disk into an input FIFO in DRAM. The data is decom- pressed, then written to a PCM output FIFO, also in DRAM. Presentation time stamps (PTS) are ex- tracted from the stream to update the STC, in order to maintain audio/video synchronization. The DMA and decompression stages of audio pro- cessing can be done with a combination of the DMA unit, DSP, and RISC processors. The DSP is optimized for audio processing, so most common formats can be handled by the DSP alone, includ- ing AC-3, DTS, MPEG2 audio, and MP3. The DSP has enough reserve bandwidth to handle the Karaoke echo-mix and pitch shift, and AC-3 down- mix functions. The audio output data is written into a DRAM FIFO in 16-, 18-, 20- or 24-bit PCM format. A flex- ible audio output stage can simultaneously output 8 channels of PCM data to audio DACs, or 6 chan- nels of audio data plus an IEC-958 encoded output, at up to 96 KHz. The audio interface also includes a flexible PCM input interface, which can input a
3.11 Soft Modem
a modem CODEC or an audio CODEC.
3.12 Video
picture_in_picture / on_screen display / cursor). tal, Brooktree, ADI, and AVS.
4.1 Processor Memory Map
4.2 Host Port Memory Map
4.3 Internal I/O Space Map
Table 10. Memory Map-RISC0 Processor
Table 11. Host Port Memory Map Table 12. Internal I/O Space Map
5.1 CS98000 Register Space
split among the main CS98000 functional blocks. Table 13. CS98000 Register Map and Blocks
000 R/W General Command
010 R/W General InterProc_Comm_Register_0
014 R/W General InterProc_Comm_Register_1
018 R/W General InterProc_Comm_Register_2
020 R/W General Semaphore_Register_0
024 R/W General Semaphore_Register_1
028 R/W General Semaphore_Register_2
030 R/W General Semaphore_Register_4
034 R/W General Semaphore_Register_5
Table 14. CS98000 Registers
038 R/W General Semaphore_Register_6
040 RO General GenIO_Read_Data
044 R/W General GenIO_Write_Data
048 R/W General GenIO_Three_State_Enable
050 R/W General GenIO_Negative_Edge
054 R/W General GenIO_Interrupt_Status
058 R/W General GenIO_Positive_Edge_Mask
060 R/W General GenIO_Level_Mask
064 R/W General GenIO_Mode Register
1040 RO General GenIOMIS_Read_Data
1044 R/W General GenIOMIS_Write_Data
1048 R/W General GenIOMIS_Three_State_Enable
1050 R/W General GenIOMIS_Negative_Edge
1054 R/W General GenIOMIS_Interrupt_Status
1058 R/W General GenIOMIS_Positive_Edge_Mask
1060 R/W General GenIOMIS_Level_Mask
1064 R/W General GenIOMIS_Mode Register
1068 RO General GenIODVD_Read_Data
1070 R/W General GenIODVD_Three_State_Enable
1074 RO General GenIOHST_Read_Data
1078 R/W General GenIOHST_Write_Data
068 R/W General I2C_Mstr_Read_Comand
070 R/W General I2C_Mstr_Write_2Bytes
074 R/W General I2C_Mstr_Control
078 RO General I2C_Mstr_Status
080 R/W General RSK0_Interrupt_Mask
084 WO General RSK0_Interrupt_Set
088 R/W General RSK0_Interrupt_Status
090 R/W General DSP_Interrupt_Mask
094 WO General DSP_Interrupt_Set
Table 14. CS98000 Registers (Continued)
098 R/W General DSP_Interrupt_Status
1080 R/W General RSK1_Interrupt_Mask
1084 WO General RSK1_Interrupt_Set
1088 R/W General RSK1_Interrupt_Status
100 R/W Host Device_1_Control
104 R/W Host Device_2_Control
108 R/W Host Device_3_Control
110 R/W Host Write_Data_Port
114 RO Host Read_Data_Port
120 R/W Host Host_Start_Address
124 R/W Host DRAM Start Address
128 R/W Host Stream_Transfer_Size
200 R/W DRAM controller DRAM_Controller_Priority0
204 R/W DRAM controller DRAM_Controller_Priority1
208 R/W DRAM controller DRAM_Controller_Priority2
210 R/W DRAM controller DRAM_Controller_Priority4
214 R/W DRAM controller DRAM_Controller_Setup
218 R/W DRAM controller DRAM_Command
220 R/W DRAM controller DRAM_Controller_Debug_Control
224 RO DRAM controller DRAM_Debug_Status
300 WO DMA DMA_Enable
304 R/W DMA DMA_Control
308 RO DMA DMA_Status
310 R/W DMA Dram_Byte_Start_Addr
314 R/W DMA Sram_Byte_Start_Addr
318 R/W DMA Fifo_Start_Rd_Addr
328 R/W DMA Search_Control
330 R/W DMA Fifo_End_Rd_Addr
334 R/W DMA Fifo_End_Wr_Addr
338 R/W DMA Lines_and_Skip
400 R/W CD/DVD DVD1 _Control
404 R/W CD/DVD DVD1 _Fifo_Base_Address
408 R/W CD/DVD DVD1_Fifo_Size
410 RO CD/DVD DVD1_Start_of_Sector
414 RO CD/DVD DVD1_Current_Dram_Address
418 R/W CD/DVD CD_Control
438 RO CD/DVD DVD1_Status
440 R/W SER/DCI DCI_Control_Reg
444 RO SER/DCI DCI_Status
448 R/W SER/DCI DCI_Dram_Rd_Start_Addr
450 R/W SER/DCI DCI_Nbytes_Sent
454 R/W SER/DCI DCI_Mbytes_Switch
458 RO SER/DCI DCI_Diagnostic
540 R/W SER/DCI Serial_Frame_Sync_Control
544 R/W SER/DCI Serial_Output_Input_Control
548 R/W SER/DCI AC97_Codec_Control
550 R/W SER/DCI Serial_Output_Fifo_Start_Address
554 R/W SER/DCI Serial_Output_Fifo_End_Address
558 R/W SER/DCI Serial_Input_Fifo_Start_Address
560 RO SER/DCI Serial_Output_Fifo_Read_Address
564 RO SER/DCI Serial_Input_Fifo_Write_Address
568 R/W SER/DCI Serial_Clock_Synthesis_Parameters
570 R/W SER/DCI Slot5_Register_Data
574 R/W SER/DCI Slot10_Register_Data
578 R/W SER/DCI Slot11_Register_Data
580 R/W SER/DCI Out_fifo_int
584 R/W SER/DCI In_fifo_int
588 R/W SER/DCI Rate_Control
600 WO DSP DSP_Boot_Code_Start_Address
604 WO DSP DSP_Run_Enable
700 R/W Synchronization Control Audio_Sync_Control
704 R/W Synchronization Control Video_Sync_Control
708 RO Synchronization Control Video_Sync_Status
710 R/W Synchronization Control Frame_Period
714 R/W Synchronization Control STC_Interval
718 R/W Synchronization Control System_Time_Clock
720 R/W Synchronization Control Video_PTS_FIFO_Start_Address
724 R/W Synchronization Control Video_PTS_FIFO_End_Address
728 R/W Synchronization Control Video_PTS_FIFO_Write_Address
730 R/W Synchronization Control Subpicture_PTS_FIFO_Start_Address
734 R/W Synchronization Control Subpicture_PTS_FIFO_End_Address
738 R/W Synchronization Control Subpicture_PTS_FIFO_Write_Address
740 R/W Synchronization Control Highlight_Start_PTS
744 R/W Synchronization Control Highlight_End_PTS
748 R/W Synchronization Control Button_End_PTS
750 R/W Synchronization Control Video_PTS
754 R/W Synchronization Control Audio_PTS
758 RO Synchronization Control Subpicture_PTS
760 RO Synchronization Control Video_Sync_Debug
764 R/W Synchronization Control SP_DRC_VPTS_Debug
768 R/W Synchronization Control Frame_Count_Interrupt
770 RO Synchronization Control Sync_Interrupt_Status
774 R/W Synchronization Control Sync_Interrupt_Control
778 WO Synchronization Control Sync_Interrupt_Set
800 R/W MPEG Video Decoder MPEG_Video_Control
804 R/W MPEG Video Decoder MPEG_Video_Setup
808 R/W MPEG Video Decoder MPEG_Video_FIFO_Start_Address
810 RO MPEG Video Decoder MPEG_Video_FIFO_Current_Address
814 RO MPEG Video Decoder MPEG_Video_Horiz_Pan_Vector
818 WO MPEG Video Decoder MPEG_Video_FIFO_Add_Bytes
820 R/W MPEG Video Decoder MPEG_Video_FIFO_Interrupt_Bytes
824 RO MPEG Video Decoder MPEG_Video_FIFO_Total_Bytes
828 RO MPEG Video Decoder MPEG_Video_Status
830 RO MPEG Video Decoder MPEG_Video_Debug
834 R/W MPEG Video Decoder MPEG_U_Offset
840 R/W MPEG Video Decoder MPEG_P_Base_Register
844 R/W MPEG Video Decoder MPEG_Dest_Control
848 RO MPEG Video Decoder MPEG_Software_Flags
854 R/W MPEG Video Decoder MPEG_AntiTearWindow
858 R/W MPEG Video Decoder MPEG_Error_Pos
900 R/W Video Input Scaler VIS_Control
904 R/W Video Input Scaler VIS_StartX
908 R/W Video Input Scaler VIS_EndX
910 R/W Video Input Scaler VIS_EndY
914 R/W Video Input Scaler VIS_Frame_Base
918 R/W Video Input Scaler VIS_U_Offset
920 R/W Video Input Scaler VIS_Frame_Size
Table15 lists the conventions used to identify the pin type and direction. Table 15. Pin Type Legend Figure 15. CS98000 Pinouts
6.1 Pin Assignments
2 M_A_11 O8 SDRAM Address[11] O ROM/NVRAM Address[11] O
3 M_A_10 O8 SDRAM Address[10] O ROM/NVRAM Address[10] O
4 GPIO_D18 B4U GenioDVD[18] B System Clock PLL Bypass I
5 M_A_9 O8 SDRAM Address[9] O ROM/NVRAM Address[9] O
6 M_A_8 O8 SDRAM Address[8] O ROM/NVRAM Address8] O
7 M_A_7 O8 SDRAM Address[7] O ROM/NVRAM Address[7] O
8 GPIO_D16 B4SU GenioDVD[16] B
9 M_A_6 O8 SDRAM Address[6] O ROM/NVRAM Address[6] O
10 M_A_5 O8 SDRAM Address[5] O ROM/NVRAM Address[5] O
11 M_A_4 O8 SDRAM Address[4] O ROM/NVRAM Address[4] O
12 GPIO_D17 B4U GenioDVD[17] B
13 M_A_3 O8 SDRAM Address[3] O ROM/NVRAM Address[3] O
14 M_A_2 O8 SDRAM Address[2] O ROM/NVRAM Address[2] O
15 M_A_1 O8 SDRAM Address[1] O ROM/NVRAM Address[1] O
16 M_A_0 O8 SDRAM Address[0] O ROM/NVRAM Address[0] O
17 GPIO_D19 B4U GenioDVD[19] B Memory Clock PLL Bypass I
18 VSS_IO Gnd I/O Ground I
19 M_CKO O8 SDRAM Clock O
21 M_BS_N O8 SDRAM Bank Select O
22 M_CKE B8 SDRAM Clock Enable O GenioMis(7) B
23 M_AP O8 SDRAM Auto Pre-charge O
24 M_RAS_N O8 SDRAM Row Strobe O
25 M_CAS_N O8 SDRAM Column Strobe O
26 GPIO_D20 B4U GenioDVD[20] B
27 M_WE_N O8 SDRAM Write Enable O
28 M_DQM_0 O8 SDRAM DQM[0] O
29 M_DQM_1 O8 SDRAM DQM[1] O
30 GPIO_D0 B4U GenioDVD[0] B
31 M_DQM_2 O8 SDRAM DQM[2] O
32 M_DQM_3 O8 SDRAM DQM[3] O
33 M_D_8 B8U SDRAM Data[8] B ROM/NVRAM Data[8] B
34 GPIO_D1 B4U GenioDVD[1] B
Table 16. 208-Pin Package Assignments
35 VSS_IO Gnd I/O Ground I
36 VSS_CORE Gnd Core Ground I
37 M_D_7 B8U SDRAM Data[7] B ROM/NVRAM Data[7] B
39 GPIO_D2 B4U GenioDVD[2] B
40 M_D_9 B8U SDRAM Data[9] B ROM/NVRAM Data[9] B
42 M_D_6 B8U SDRAM Data[6] B ROM/NVRAM Data[6] B
43 GPIO_D3 B4U GenioDVD[3] B
44 M_D_10 B8U SDRAM Data[10] B ROM/NVRAM Data[10] B
45 M_D_5 B8U SDRAM Data[5] B ROM/NVRAM Data[5] B
46 M_D_11 B8U SDRAM Data[11] B ROM/NVRAM Data[11] B
47 GPIO_D4 B4U GenioDVD[4] B
48 M_D_4 B8U SDRAM Data[4] B ROM/NVRAM Data[4] B
49 M_D_12 B8U SDRAM Data[12] B ROM/NVRAM Data[12] B
50 GPIO_D5 B4U GenioDVD[5] B
51 M_D_3 B8U SDRAM Data[3] B ROM/NVRAM Data[3] B
52 UNUSED may leave unconnected
53 UNUSED may leave unconnected
54 M_D_13 B8U SDRAM Data[13] B ROM/NVRAM Data[13] B
55 M_D_2 B8U SDRAM Data[2] B ROM/NVRAM Data[2] B
56 M_D_14 B8U SDRAM Data[14] B ROM/NVRAM Data[14] B
57 GPIO_D6 B4U GenioDVD[6] B
58 VSS_IO Gnd I/O Ground I
59 M_D_1 B8U SDRAM Data[1] B ROM/NVRAM Data[1] B
60 M_D_15 B8U SDRAM Data[15] B ROM/NVRAM Data[15] B
61 GPIO_D7 B4U GenioDVD[7] I B
62 M_D_0 B8U SDRAM Data[0] B ROM/NVRAM Data[0] B
63 VSS_CORE Gnd Core Ground I
64 M_D_24 B8U SDRAM Data[24] B ROM/NVRAM Address[20] O
65 GPIO_D11 B4U GenioDVD[11] B
67 M_D_23 B8U SDRAM Data[23] B ROM/NVRAM Address[19] O
68 M_D_25 B8U SDRAM Data[23] B ROM/NVRAM Address[21] O
69 GPIO_D10 B4U GenioDVD[10] B
70 M_D_22 B8U SDRAM Data[22] B ROM/NVRAM Address[18] O
71 M_D_26 B8U SDRAM Data[26] B ROM/NVRAM Address[22] O
72 M_D_21 B8U SDRAM Data[21] B ROM/NVRAM Address[17] O
73 GPIO_D9 B4U GenioDVD[9] B
74 M_D_27 B8U SDRAM Data[27] B ROM/NVRAM Address[23] O
Table 16. 208-Pin Package Assignments (Continued)
75 M_D_20 B8U SDRAM Data[20] B ROM/NVRAM Address[16] O
76 M_D_28 B8U SDRAM Data[28] B
77 GPIO_D8 B4U GenioDVD[8] B
78 M_D_19 B8U SDRAM Data[19] B ROM/NVRAM Address[15] O
79 M_D_29 B8U SDRAM Data[29] B
80 M_D_18 B8U SDRAM Data[18] B ROM/NVRAM Address[14] O
81 NV_WE_N B4U NVRAM Write Enable O GenioMis[8] B
82 VSS_CORE Gnd Core Ground I
83 M_D_30 B8U SDRAM Data[30] B ROM/NVRAM Decode Low O
85 H_ALE B4U Host Address Latch O GenioHst[13] B
86 M_D_17 B8U SDRAM Data[18] B ROM/NVRAM Address[13] O
87 M_D_31 B8U SDRAM Data[31] B ROM/NVRAM Decode High O
88 M_D_16 B8U SDRAM Data[16] B ROM/NVRAM Address[12] O
89 GPIO_H14 B4U GenioHst[14] B
90 NV_OE_N O4 ROM/NVRAM Output
92 H_RD B4S Host Read Strobe O DVD Data Strobe I 1
93 H_WR B4 Host Write Strobe O DVD Data Enable I 1
94 GPIO_H15 B4U GenioHst[15] B
95 H_RDY B4 Host Ready I DVD Data Ready O 1
96 VSS_IO Gnd I/O Ground I
97 H_A_2 B4 Host Address[2] O GenioHst[10] B 1
98 GPIO_H16 B4U GenioHst[16] B
99 H_A_1 B4 Host Address[1] O GenioHst[9] B 1
100 H_A_0 B4 Host Address[0] O GenioHst[8] B 1
101 H_CS_1 B4 Host Chip Select [1] O DVD Error I 1
102 H_A_4 B4 Host Address[4] O GenioHst[12] B 1
103 VSS_CORE Gnd Core Ground I
104 VSS_PLL Gnd PLL Ground I
106 H_CS_0 B4 Host Chip Select[0] O DVD Start Sector I 1
107 H_A_3 B4 Host Address[3] O GenioHst[11] B 1
109 H_D_15 B4 Host Data[15] B CD Data I 1, 2
110 H_D_14 B4 Host Data[14] B CD Left Right Clock I 1, 2
111 H_CS_3 B4 Host Chip Select[3] O GenioHst[18] B 1
112 H_D_13 B4S Host Data[13] B CD Clock I 1, 2
113 H_D_12 B4 Host Data[12] B CD Error I 1, 2
114 H_D_11 B4 Host Data[11] B DVD Control Data In I 1, 2
115 H_CS_2 B4 Host Chip Select[2] O GenioHst[17] B 1
116 H_D_10 B4 Host Data[10] B DVD Control Data Out O 1, 2
117 H_D_9 B4 Host Data[9] B DVD Control Ready I 1, 2
118 H_D_8 B4 Host Data[8] B DVD Control Clock O 1, 2
119 VSS_IO Gnd I/O Ground I
120 H_CKO B4 Host Clock O GenioHst[19] B 1
121 H_D_7 B4 Host Data[7] B DVD Data[7] I 1
122 H_D_6 B4 Host Data[6] B DVD Data[6] I 1
123 H_D_5 B4 Host Data[5] B DVD Data[5] I 1
124 AUD_BCK B4 Audio Out Bit Clock O GenioMis[3] B
125 H_D_4 B4 Host Data[4] B DVD Data[4] I 1
126 VSS_CORE Gnd Core Ground I
127 H_D_3 B4 Host Data[3] B DVD Data[3] I 1
128 AUD_LRCK O4 Audio Out LR Clock O
130 H_D_2 B4 Host Data[2] B DVD Data[2] I 1
132 H_D_1 B4 Host Data[1] B DVD Data[1] I 1
133 AUD_DO_2 B4 Audio Out Data[2] O GenioMis[2] B
134 H_D_0 B4 Host Data[0] B DVD Data[0] I 1
135 AUD_DO_0 O4 Audio Out Data[0] O
136 AUD_DO_1 B4 Audio Out Data[1] O GenioMis[1] B
137 AIN_BCK IU Audio In Bit Clock I
138 VSS_CORE Gnd Core Ground I
139 AIN_LRCK IU Audio In LR Clock I
140 AIN_DATA B4U Audio In Data I GenioMis[0] B
142 CDC_DI IU Serial CODEC Data In I
143 VSS_IO Gnd I/O Ground I
144 CDC_DO T4 Serial CODEC Data Out O
145 VIN_CLK IU Video Input Clock I
146 CDC_RST T4 Serial CODEC Reset O
147 CDC_CK IU Serial CODEC Bit Clock I
148 CDC_SY B4U Serial CODEC Sync B
149 GPIO_V10 B4U GenioMis[26] B
150 GPIO_D15 B4U GenioDvd[15] B
151 GPIO_D14 B4U GenioDvd[14] B
152 GPIO_D13 B4SU GenioDvd[13] B
153 VIN_VSNC B4U Video Input Vsync I GenioMis[25] B
154 CLK27_O B4U Video Output Clock O GenioMis[6] B
155 GPIO_D12 B4U GenioDvd[12] B
157 VSS_PLL Gnd PLL Ground I
158 VSS_CORE Gnd Core Ground I
159 HSYNC B4U Video Output Hsync O GenioMis[4] B
160 VIN_HSYNC B4U Video Input Hsync I GenioMis[24] B
162 VSYNC B4U Video Output Vsync O GenioMis[5] B
163 VDAT_0 O4 Video Output Data[0] O
164 VIN_D0 B4U Video Input Data[0] I GenioMis[16] B
165 VDAT_1 O4 Video Output Data[1] O
166 VDAT_2 O4 Video Output Data[2] O
167 VDAT_3 O4 Video Output Data[3] O
168 VIN_D1 B4U Video Input Data[1] I GenioMis[17] B
169 VDAT_4 O4 Video Output Data[4] O
170 VDAT_5 O4 Video Output Data[5] O
171 UNUSED may leave unconnected
172 VDAT_6 O4 Video Output Data[6] O
173 VDAT_7 O4 Video Output Data[7] O
174 GPIO_0 B4U General Purpose IO[0] B Audio PLL Input Bypass I
175 VIN_D2 B4U Video Input Data[2] I GenioMis[18] B
176 VSS_CORE Gnd Core Ground I
177 AUD_DO_3 B4U Audio Out Data[3] O General Purpose IO[1] B
179 VIN_D3 B4U Video Input Data[3] I GenioMis[19] B
181 GPIO_2 B4U General Purpose IO[2] B
182 VSS_IO Gnd I/O Ground I
183 GPIO_3 B4U General Purpose IO[3] B
184 VIN_D4 B4U Video Input Data[4] I GenioMis[20] B
185 GPIO_4 B4U General Purpose IO[4] B
186 SCL B4U I2C Clock B General Purpose IO[5] B
187 SDA B4U I2C Data B General Purpose IO[6] B
188 GPIO_7 B4U General Purpose IO[7] B
189 VIN_D5 B4U Video Input Data[5] I GenioMis[21] B
190 GPIO_8 B4U General Purpose IO[8] B
191 AUD_XCLK B4U Audio 256x/384x Clock B General Purpose IO[9] B
192 GPIO_10 B4U General Purpose IO[10] B
193 VIN_D6 B4U Video Input Data[6] I GenioMis[22] B
- H_D(15:8) pins may be reassigned as GenIOHst(7:0)
194 GPIO_11 B4U General Purpose IO[11] B
195 GPIO_12 B4U General Purpose IO[12] B
196 GPIO_13 B4U General Purpose IO[13] B
197 GPIO_14 B4U General Purpose IO[14] B
198 VIN_D7 B4U Video Input Data[7] I GenioMis[23] B
199 GPIO_15 B4U General Purpose IO[15] B
200 VSS_CORE Gnd Core Ground I
201 IR_IN IS Infrared input I
202 XTLCLOCK I 27 MHz Clock In I
204 SPDIF_O O4 S/PDIF Out O
205 RESET_N IS Reset In I
206 MFG_TEST I (Tie to ground) I
207 VIN_FLD ID Video Input Field I
208 VSS_PLL Gnd PLL Ground I
6.2 Miscellaneous Interface Pins
6.3 SDRAM Interface
particular configuration of SDRAM.
186 SCL B I2C Clock
187 SDA B I2C Data
201 IR_IN I Infrared Input, from IR receiver. 202 XTLCLOCK I 27 MHz Clock Input. 205 RESET_N I Reset Input, active low. 206 MFG_TEST I Manufacturing test pin, should always connect to ground. Table 17. Miscellaneous Interface Pins M_AP. Unused upper M_A pins unconnected.
19 M_CKO O Memory Clock
22 M_CKE O Memory Clock Enable
21 M_BS_N O Bank Selection. Always connect to RAM BS or BS0 pin. 23 M_AP O Memory Auto Pre-charge. Always connect to RAM AP pin.
24 M_RAS_N O Memory Row Address Strobe
25 M_CAS_N O Memory Column Address Strobe
27 M_WE_N O Memory Write Enable
Table 18. SDRAM Interface
6.4 ROM/NVRAM Interface
neously with the ROM/NVRAM interface.
6.5 Video Output Interface
16-bit data mode, M_D[26:16] is upper word address. For 8-bit data mode, M_D[27:16] is upper byte address. 83 M_D[30] O Address decode low. Copy of address MSB. 87 M_D[31] O Address decode high. Compliment of address MSB. 60 NVM_WE_N O NVRAM Write Enable. 62 NVM_OE_N O ROM/NVRAM Output Enable. Table 19. ROM/NVRAM Interface 154 CLK27_O O 27 Mhz Clock Output. master, input when the video encoder is master. ter, input when the video encoder is master. Table 20. Video Output Interface
6.6 Video Input Interface
6.7 Audio Output/Input Interface
145 VIN_CLK I Video Input Clock. 153 VIN_VSNC I Video Input Vertical Sync. 160 VIN_HSNC I Video Input Horizontal Sync. 207 VIN_FLD I Video Input Field. Table 21. Video Input Interface output, is generated from CS98000 internal PLL. 124 AUD_BCK O Audio Bit Clock output to serial DAC. 128 AUD_LRCK O Audio Out Left/Right Clock to serial DAC. 135 AUD_DO_0 O Audio Serial Data Out[0]. 136 AUD_DO_1 O Audio Serial Data Out[1]. 133 AUD_DO_2 O Audio Serial Data Out[2]. 177 AUD_DO_3 O Audio Serial Data Out[3].
204 SPDIF_O O S/PDIF Output
clock, in which case this pin is not required. erated LR clock, in which case this pin is not required. 140 AIN_DATA I Audio Input Data from Serial ADC. Table 22. Audio Input/Output Interface
6.8 AC97/CODEC Interface
signments for the AC97/CODEC Interface.
6.9 Host Master/ATAPI Interface
trolled by different chip selects.
142 CDC_DI I Serial Data Input from Modem CODEC
144 CDC_DO O Serial Data Output to Modem CODEC
146 CDC_RST O Reset Output to Modem CODEC
147 CDC_CK I Serial Bit Clock input from Modem CODEC
148 CDC_SY B Frame Sync, output when CS98000 is master, input when
Table 23. AC97/CODEC Interface 92 H_RD O Host Read Request. 93 H_WR O Host Write Request.
120 H_CKO O Host clock out, required for some synchronous slaves
Table 24. Host Master/ATAPI Interface
6.10 DVD I/O Channel Interface
two modes are mutually exclusive.
6.11 General Purpose Input/Output
may also be re-defined as GPIO’s.
118 H_D[8] O Control port clock to loader
117 H_D[9] I Control port ready signal from loader
116 H_D[10] O Control port serial command to loader
114 H_D[11] I Control port serial status from loader
113 H_D[12] I CD error signal from loader
112 H_D[13] I CD clock from loader
110 H_D[14] I CD left/right clock from loader
109 H_D[15] I CD serial data from loader
106 H_CS_0 I DVD data start sector signal from loader
101 H_CS_1 I DVD data error signal from loader
95 H_RDY O DVD data ready signal to loader
93 H_WR I DVD data enable signal from loader
92 H_RD I DVD data clock from loader
Table 25. DVD I/O Channel Interface
149 GPIO_V10 B General purpose I/O
174 GPIO_0 B General purpose I/O
Table 26. General Purpose I/O Interface
6.12 Power and Ground
Table 27. Power and Ground
Figure 16. 208-Pin Package Drawing