CS8952-CQ

CS8952 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

!Single-Chip IEEE 802.3 Physical Interface IC for 100BASE-TX, 100BASE-FX and 10BASE-T !Adaptive Equalizer provides Extended Length Operation (>160 m) with Superior Noise Immunity and NEXT Margin !Extremely Low Transmit Jitter (<400 ps) !Low Common Mode Noise on TX Driver for Reduced EMI Problems !Integrated RX and TX Filters for 10BASE-T !Compensation for Back-to-Back “Killer Packets” !Digital Interfaces Supported – Media Independent Interface (MII) for 100BASE-X and 10BASE-T – Repeater 5-bit code-group interface (100BASE-X) – 10BASE-T Serial Interface ! Register Set Compatible with DP83840A !IEEE 802.3 Auto-Negotiation with Next Page Support !Six LED drivers (LNK, COL, FDX, TX, RX, and SPD) !Low power (135 mA Typ) CMOS design operates on a single 5 V supply

Description

The CS8952 uses CMOS technology to deliver a high- performance, low-cost 100BASE-X/10BASE-T Physical Layer (PHY) line interface. It makes use of an adaptive equalizer optimized for noise and near end crosstalk (NEXT) immunity to extend receiver operation to cable lengths exceeding 160 m. In addition, the transmit cir- cuitry has been designed to provide extremely low transmit jitter (<400 ps) for improved link partner perfor- mance. Transmit driver common mode noise has been minimized to reduce EMI for simplified FCC certification. The CS8952 incorporates a standard Media Indepen- dent Interface (MII) for easy connection to a variety of 10 and 100 Mb/s Media Access Controllers (MACs). The CS8952 also includes a pseudo-ECL interface for use with 100Base-FX fiber interconnect modules.

ORDERING INFORMATION

CS8952-CQ 0 to 70 °C 100-pin TQFP CDB8952 Evaluation Board TX_EN TX_ER/TXD4 TXD[3:0] TX_CLK MDC MII_IRQ MDIO CRS COL RX_ER/RXD4 RX_DV RXD[3:0] RX_CLK RX_EN TX+, TX- TX_NRZ+, TX_NRZ- RX_NRZ+, RX_NRZ- RX+, RX- LED1 LED2 LED3 LED4 LED5 M U X 4B/5B Decoder Descrambler Manchester Encoder Scrambler Fiber NRZI Interface MLT-3 Encoder 10BaseT Filter Slew Rate Control M U X 4B/5B Encoder ECL Driver ECL Receiver Adaptive Eq. & Baseline Wander Compensation 10BaseT Filter LED Drivers 100BaseT Slicer 10BaseT Slicer Fiber NRZI Interface MLT-3 Decoder Manchester Decoder Auto Negotiation Timing Recovery MII Control/Status Registers Link Management CS8952 10BaseT/100Base-X Transceiver Media Independent Interface (MII) DS206PP3 OCT ‘01 CS8952 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

2 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advanceproduct infor- mation describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, including use of this information as the basis for manufacture or sale of any items, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and by furnishing this information, Cirrus Logic, Inc. grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights of Cirrus Logic, Inc. Cirrus Logic, Inc., copyright owner of the information contained herein, gives consent for copies to be made of the information only for use within your organization with respect to Cirrus Logic integrated circuits or other parts of Cirrus Logic, Inc. The same consent is given for similar information contained on any Cirrus Logic website or disk. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered insome

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 3

4 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

1. SPECIFICATIONS AND CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) QUARTZ CRYSTAL REQUIREMENTS (If a 25 MHz quartz crystal is used, it must meet the fol- lowing specifications.) Parameter Symbol Min Max Unit Power Supply V DD VDD_MII -0.3 -0.3 6.0 6.0 V Input Current Except Supply Pins - +/-10.0 mA Input Voltage -0.3 V DD +0 . 3 V Ambient Temperature Power Applied -55 +125 °C Storage Temperature -65 +150 °C Parameter Symbol Min Max Unit Power Supply Core MII VDD VDD_MII 4.75 3.0 5.25 5.25 V V Operating Ambient Temperature T A 07 0 °C Parameter Min Typ Max Unit Parallel Resonant Frequency - 25.0 - MHz Resonant Frequency Error (CL = 15 pF) -50 - +50 ppm Resonant Frequency Change Over Operating Temperature -40 - +40 ppm Crystal Load Capacitance - 15 - pF Motional Crystal Capacitance - 0.021 - pF Series Resistance - - 18 Ω Shunt Capacitance - - 7 pF

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 5 DC CHARACTERISTICS (Over recommended operating conditions) Parameter Symbol Min Typ Max Unit External Oscillator XTAL_I Input Low Voltage V IXH -0.3 - 0.5 V XTAL_I Input High Voltage V IXH 3.5 - VDD+0.5 V XTAL_I Input Low Current I IXL -40 - - µA XTAL_I Input High Current I IXH -- 4 0 µ A XTAL_I Input Capacitance C L -3 5 p F XTAL_I Input Cycle Time t IXC 39.996 - 40.004 ns XTAL_I Input Low Time t IXL 18 - 22 ns XTAL_I Input High Time t XH 18 - 22 ns Power Supply Power Supply Current 100BASE-TX (Note 1) 100BASE-FX (Note1) 10BASE-T (Note1) IDD - 135 145 mA Hardware Power-Down (Note 1)I DDHPDN -9 0 0- µ A Software Power-Down (Note 1)I DDSPDN -2 0- m A Low Power Power-Up (Note 1)I DDSLPUP -9 0 0- µ A Digital I/O Output Low Voltage CLK25, MII_IRQ, SPD10, SPD100 I OL =4 . 0 m A LED[4:0] I OL =1 0 . 0 m A VOL 0.4 0.4 V Output Low Voltage (MII_DRV = 1) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I OL =4 . 0 m A VDD_MII = 5V; IOL =4 3 . 0 m A VDD_MII = 3.3V, IOL =2 6 . 0 m A VOL 0.4 3.05 2.1 V Output Low Voltage (MII_DRV = 0) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I OL =4 . 0 m A VOL -- 0 . 4 V Output High Voltage CLK25, SPD10, SPD100 I OH =- 4 . 0 m A VOH 2.4 - - V Output High Voltage (MII_DRV = 1) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I OH =- 4 . 0 m A V D D _ M I I=5 V ;IOH =- 2 0 . 0 m A V D D _ M I I=3 . 3 V ,IOH =- 2 0 . 0 m A VOH 2.4 1.1 1.1 V

6 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Notes: 1. With digital outputs connected to CMOS loads. Output High Voltage (MII_DRV = 0) COL, CRS, MDIO, RXD[3:0], RX_CLK, RX_DV, RX_ER, TX_CLK I OH =- 4 . 0 m A VOH 2.4 - - V Input Low Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0] VIL -- 0 . 8 V Input High Voltage All Inputs Except AN[1:0], TCM, TXSLEW[1:0] VIH 2.0 - - V Tri-Level Input Voltages AN[1:0], TCM, TXSLEW[1:0] VIL VIM VIH 1/3 VDD_MII +2 0 % 2/3 VDD_MII +2 0 % 1/3 V DD_MII -2 0 % 2/3 VDD_MII -2 0 % V Input Low Current MDC, TXD[3:0], TX_CLK, TX_EN, TX_ER V I=0 . 0 V MDIO V I=0 . 0 V IIL -20 -3800 µA Input High Current MDC, TXD[3:0], TX_CLK, TX_EN, TX_ER V I=5 . 0 V MDIO V I=5 . 0 V IIH 200 µA Input Leakage Current All Other Inputs 0<=V<=V DD ILEAK -10 - +10 µA DC CHARACTERISTICS (CONTINUED) (Over recommended operating conditions) Parameter Symbol Min Typ Max Unit

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 7 10BASE-T CHARACTERISTICS Parameter Symbol Min Typ Max Unit 10BASE-T Interface Transmitter Differential Output Voltage (Peak) VOD 2.2 - 2.8 V Receiver Normal Squelch Level (Peak) V ISQ 300 - 525 mV Receiver Low Squelch Level (LoRxSquelch bit set) VSQL 125 - 290 mV 10BASE-T Transmitter TXD Pair Jitter into 100Ω Load t TTX1 --8 n s TXD Pair Return to≤50 mV after Last Positive Transition tTTX2 -- 4 . 5 µ s TXD Pair Positive Hold Time at End of Packet tTTX3 250 - - ns 10BASE-T Receiver Allowable Received Jitter at Bit Cell Center t TRX1 - - +/-13.5 ns Allowable Received Jitter at Bit Cell Boundary tTRX2 - - +/-13.5 ns 10BASE-T Link Integrity First Transmitted Link Pulse after Last Transmit- ted Packet t LN1 15 16 17 ms Time Between Transmitted Link Pulses t LN2 15 16 17 ms Width of Transmitted Link Pulses t LN3 60 - 200 ns Minimum Received Link Pulses Separation t LN4 257 m s Maximum Received Link Pulse Separation t LN5 25 52 150 ms Last Receive Activity to Link Fail (Link Loss Timer) tLN6 50 52 150 ms 10Base-T Jabber/Unjabber Timing Maximum Transmit Time - 105 - ms Unjabber Time - 406 - ms TXD± RXD± LINKLED tLN1 tLN3tLN2 tLN5tLN4 tLN6 RXD± tRTX1 tRTX2tRTX3 tRTX4 Carrier Sense (Internal) TXD± tTTX1 tTTX3 tTTX2

8 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Parameter Symbol Min Typ Max Unit 100BASE-TX Transmitter TX Differential Output Voltage (Peak) V OP 0.95 - 1.05 V Signal Amplitude Symmetry V SYM 98 - 102 % Signal Rise/Fall Time t RF 3.0 - 5.0 ns Rise/Fall Symmetry t RFS -- 0 . 5 n s Duty Cycle Distortion t DCD -- + / - 0 . 5 n s Overshoot/Undershoot t OS --5 % Transmit Jitter t JT - 400 1400 ps TX Differential Output Impedance Z OUT -1 0 0- o h m s 100BASE-TX Receiver Receive Signal Detect Assert Threshold - - 1.0 V p-p Receive Signal Detect De-assert Threshold 0.2 - - V p-p Receive Signal Detect Assert Time - - 1000 µs Receive Signal Detect De-assert Time - - 350 µs 100BASE-FX Transmitter TX_NRZ+/- Output Voltage - Low V TX_NRZ+/- Output Voltage - High V 2 -1.035 - -0.880 V Signal Rise/Fall Time T RF -- 1 . 6 n s 100Base-FX Receiver RX_NRZ+/- Input Voltage - Low V 3 -1.830 - -1.605 V RX_NRZ+/- Input Voltage - High V 4 -1.035 - -0.880 V Common Mode Input Range V CMIP -3 . 5 6- V VDD TX_NRZ+/- RX_NRZ+/- RX/TX Signaling for 100Base-FX

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 9 100BASE-TX MII RECEIVE TIMING - 4B/5B ALIGNED MODES Parameter Symbol Min Typ Max Unit RX_CLK Period t P -4 0- n s RX_CLK Pulse Width t WL, tWH -2 0- n s RXD[3:0],RX_ER/RXD4,RX_DV setup to rising edge of RX_CLK tSU 10 - - ns RXD[3:0],RX_ER/RXD4,RX_DV hold from rising edge of RX_CLK tHD 10 - - ns C R St oR X Dl a t e n c y 4 BA l i g n e d 5B Aligned tDLAT 2 3-6 3-6 BT “Start of Stream”to CRS asserted t CRS1 -1 0 1 1 B T “End of Stream”to CRS de-asserted t CRS2 -- 2 1 B T “Start of Stream”to COL asserted t COL1 -- 1 1 B T “End of Stream”to COL de-asserted t COL2 -- 2 1 B T RX_EN asserted to RX_DV, RXD[3:0] valid t EN -T B D- n s RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER/RXD4 in high impedance state tDIS -T B D- n s RX_CLK RXD[3:0], CRS tCRS1 tCOL2 tRLAT Start of Stream End of Stream RX_EN RX+/- RX_DV IN OUT IN OUT OUT OUT OUTCOL tCOL1 tCRS2 tHD tEN tDIS RX_ER/RXD4 tWL tWH tP tSU

10 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

100BASE-TX MII RECEIVE TIMING - 5B BYPASS ALIGN MODE Parameter Symbol Min Typ Max Unit RX_CLK Period t P -4 0- n s RX_CLK Pulse Width t WL, tWH -2 0- n s R X D [ 4 : 0 ]s e t u pt or i s i n ge d g eo fR X _ C L K tSU 10 - - ns RXD[4:0] hold after rising edge of RX_CLK t HD 10 - - ns Start of 5B symbol to symbol output on RX[4:0] 5B Mode tRLAT 5-9 B T RX_CLK RXD[4:0], tRLAT RX Symbol RX Symbol NRX+/- IN OUT OUT tHD tWL tWH tP tSU RX Symbol N-1 RX Data RX Data

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 11 100BASE-TX MII TRANSMIT TIMING - 4B/5B ALIGN MODES Parameter Symbol Min Typ Max Unit TXD[3:0] Setup to TX_CLK High t SU1 10 - - ns TX_EN Setup to TX_CLK High t SU2 10 - - ns TXD[3:0] Hold after TX_CLK High t HD1 0-- n s TX_ER Hold after TX_CLK High t HD2 0-- n s TX_EN Hold after TX_CLK High t HD3 0-- n s TX_EN “high”to CRS asserted latency t CRS1 -8 B T TX_EN “low”to CRS de-asserted latency t CRS2 -8 B T TX_EN “high”to TX+/- output (TX Latency) t LAT 678 B T TX_CLK TX_EN TXD[3:0], CRS TX+/- tSU2 tSU1 tHD2 tHD1 tCRS1 tCRS2 tLAT Input/Output Input Input Output Output TX_ER/TXD4 Data IN Symbol Out

12 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

100BASE-TX MII TRANSMIT TIMING - 5B BYPASS ALIGN MODE Parameter Symbol Min Typ Max Unit TXD[4:0] Setup to TX_CLK High t SU1 10 - - ns TXD[4:0] Hold after TX_CLK High t HD1 0-- n s TX_ER Hold after TX_CLK High t HD2 0-- n s TXD[4:0] Sampled to TX+/- output (TX Latency) tLAT -67 n s TX_CLK TXD[4:0] TX+/- tSU1 tHD1 tLAT Symbol OUT Input/Output Input Output Data IN

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 13 10BASE-T MII RECEIVE TIMING Parameter Symbol Min Typ Max Unit RX_CLK Period t P -4 0 0- n s RX_CLK Pulse Width t WL, tWH -2 0 0- n s R X D [ 3 : 0 ] ,R X _ E R ,R X _ D Vs e t u pt or i s i n ge d g eo f RX_CLK tSU 30 - - ns RXD[3:0], RX_ER, RX_DV hold from rising edge of RX_CLK tHD 30 - - ns RX data valid from CRS t RLAT -8 1 0 B T RX+/- preamble to CRS asserted t CRS1 -57 B T RX+/- end of packet to CRS de-asserted t CRS2 2.5 3 BT RX+/- preamble to COL asserted t COL1 0-7 B T RX+/- end of packet to COL de-asserted t COL2 --3 B T RX_EN asserted to RX_DV, RXD[3:0], RX_ER valid tEN - - 60 ns RX_EN de-asserted to RX_DV, RXD[3:0]. RX_ER in high impedance state tDIS - - 60 ns RX_CLK RXD[3:0], CRS tCRS1 tCOL2 tRLAT RX_EN RX+/- RX_DV IN OUT IN OUT OUT OUTCOL tCOL1 tCRS2 tHD tEN tDIS RX_ER tWL tWH tP tSU OUT

14 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

10BASE-T MII TRANSMIT TIMING Parameter Symbol Min Typ Max Unit TXD[3:0] Setup to TX_CLK High t SU1 10 - - ns TX_ER Setup to TX_CLK High t SU2 10 - - ns TX_EN Setup to TX_CLK High t SU3 10 - - ns TXD[3:0] Hold after TX_CLK High t HD1 0-- n s TX_ER Hold after TX_CLK High t HD2 0-- n s TX_EN Hold after TX_CLK High t HD3 0-- n s TX_EN “high”to CRS asserted latency t CRS1 0-4 B T TX_EN “low”to CRS de-asserted latency t CRS2 0- 1 6 B T TX_EN “high”to TX+/- output (TX Latency) t LAT 6- 1 4 B T SQE Timing COL (SQE) Delay after CRS de-asserted t COL 0.65 0.9 1.6 µs COL (SQE) Pulse Duration t COLP 0.65 1.0 1.6 µs TX_CLK TX_EN TX_ER TXD[3:0] CRS TX+/- tSU3 tSU2 tSU1 tHD3 tHD2 tHD1 tCRS1 tCRS2 tLAT Valid Data Input/Output Input Input Input Output Output TX_CLK tSQECOL tSQEP Input/Output Output SQE Timing 10BASE-T Transmit Timing

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 15 10BASE-T SERIAL RECEIVE TIMING Parameter Symbol Min Typ Max Unit RX+/- active to RXD[0] active t DATA - - 1200 ns RX+/- active to CRS active t CRS -- 6 0 0 n s RXD[0] setup from RX_CLK t RDS 35 - - ns RXD[0] hold from RX_CLK t RDH 50 - - ns RX_CLK hold after CRS off t RCH 5-- n s RXD[0] throughput delay t RD -- 2 5 0 n s CRS turn off delay t CRSOFF -- 4 0 0 n s RX_CLK RXD[0] CRS tCRS RX+/- IN OUT OUT tCRSOFF tHDtSU OUT tDATA tRD tRCH

16 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

10BASE-T SERIAL TRANSMIT TIMING Parameter Symbol Min Typ Max Unit TX_EN Setup from TX_CLK t EHCH 10 - - ns TX_EN Hold after TX_CLK t CHEL 10 - - ns TXD[0] Setup from TX_CLK t DSCH 10 - - ns TXD[0] Hold after TX_CLK t CHDU 10 - - ns Transmit start-up delay t STUD -- 5 0 0 n s Transmit throughput delay t TPD -- 5 0 0 n s TX_CLK TX_EN TXD[3:0] TX+/- tEHCH tDSCH tCHEL tCHDU tSTUD Valid Data Input/Output Input Input Output tPD

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 17 AUTO NEGOTIATION / FAST LINK PULSE TIMING Parameter Symbol Min Typ Max Unit FLP burst to FLP burst t BTB 15 16 17 ms FLP burst width t FLPW -2- m s Clock/Data pulses per burst - 17 - 33 ea. Clock/Data pulse width t PW -1 0 0- n s Clock pulse to Data pulse t CTD 55.5 64 69.5 µs Clock pulse to clock pulse t CTC 111 128 139 µs tFLPW tBTB Clock Pulse Data Pulse Clock Pulse tPW tCTD tCTC tPW TX+/- TX+/-

18 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

SERIAL MANAGEMENT INTERFACE TIMING Parameter Symbol Min Typ Max Unit MDC Period t p 60 - - ns MDC Pulse Width t WL,tWH 40 - 60 % MDIO Setup to MDC (MDIO as input) t MD1 10 - - ns MDIO Hold after MDC (MDIO as input) t MD2 10 - - ns MDC to MDIO valid (MDIO as output) t MD3 0 - 40 ns MDC MDIO MDIO Valid Data DIRECTION: IN or OUT of chip IN IN OUT tMD1 tMD2 tMD3 Valid Data Valid Data

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 19 2. INTRODUCTION The CS8952 is a complete physical-layer transceiv- er for 100BASE-TX and 10BASE-T applications. Additionally, the CS8952 can be used with an ex- ternal optical module for 100BASE-FX.

2.1 High Performance Analog

The highly integrated mixed-signal design of the CS8952 eliminates the need for external analog cir- cuitry such as external transmit or receive filters. The CS8952 builds upon Cirrus Logic’s experience in pioneering the high-volume manufacturing of 10BASE-T integrated circuits with “true” internal filters. The CS8952, CS8920, CS8904, and CS8900 include fifth-order, continuous-time But- terworth 10BASE-T transmit and receive filters, al- lowing those products to meet 10BASE-T wave shape, emission, and frequency content require- ments without external filters.

2.2 Low Power Consumption

The CS8952 is implemented in low power CMOS, consuming only 135 mA typically. Three low-pow- er modes are provided to make the CS8952 ideal for power sensitive applications such as CardBus.

2.3 Application Flexibility

The CS8952’s digital interface and operating modes can be tailored to efficiently support a wide variety of applications. For example, the Media In- dependent Interface (MII) supports 100BASE-TX, 100BASE-FX and 10BASE-T NIC cards, switch ports and router ports. Additionally, the low-laten- cy “repeater” interface mode minimizes data delay through the CS8952, facilitating system compli- ance with overall network delay budgets. To sup- port 10BASE-T applications, the CS8952 provides a 10BASE-T serial port (Seven-wire ENDEC inter- face).

2.4 Typical Connection Diagram

Figure 1illustrates a typical MII to CS8952 appli- cation with twisted-pair and fiber interfaces. Refer to the Analog Design Considerations section for detailed information on power supply requirements and decoupling, crystal and magnetics require- ments, and twisted-pair and fiber transceiver con- nections. 3. FUNCTIONAL DESCRIPTION The CS8952 is a complete physical-layer transceiv- er for 100BASE-TX and 10BASE-T applications. It provides a Physical Coding Sub-layer for com- munication with an external MAC (Media Access Controller). The CS8952 also includes a complete Physical Medium Attachment layer and a 100BASE-TX and 10BASE-T Physical Medium Dependent layer. Additionally, the CS8952 pro- vides a PECL interface to an external optical mod- ule for 100BASE-FX applications. The primary digital interface to the CS8952 is an enhanced IEEE 802.3 Media Independent Interface (MII). The MII supports parallel data transfer, ac- cess to the CS8952 Control and Status registers, and several status and control pins. The CS8952's operating modes can be tailored to support a wide variety of applications, including low-latency 100BASE-TX repeaters, switches and MII-based network interface cards. For 100BASE-TX applications, the digital data in- terface can be either 4-bit parallel (nibbles) or 5-bit parallel (code-groups). For 10BASE-T applica- tions, the digital data format can be either 4-bit par- allel (nibbles) or one-bit serial. The CS8952 is controlled primarily by configura- tion registers via the MII Management Interface. Additionally, a number of the most fundamental register bits can be set at power-up and reset time by connecting pull-up or pull-down resistors to ex- ternal pins. The CS8952's MII interface is enhanced beyond IEEE requirements by register extensions and the addition of pins for MII_IRQ ,R X _ E N ,a n dI S O - DEF signals. The MII_IRQpin provides an inter-

20 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

25 MHz

Figure 1. Typical Connection Diagram

for the system to poll the CS8952 for state changes. electrically isolates the CS8952's MII data path.

3.1 Major Operating Modes

100 Mb/s) is made using the auto-negotiation input

used to select a duplex mode (full or half duplex). or negotiated with the far-end link partner. Table 1. Speed and duplex selection are made through the AN[1:0] pins as shown in Table5. RX_CLK are nominally 25 MHz for 100BASE-X.

3.1.1.1 Symbol Encoding and Decoding

rate of the system (100 symbols/second).

22 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Table 2. 4B5B Symbol Encoding/Decoding

1. DATA code groups are indicated by RX_DV = 1
2. CONTROL code groups are inserted automatically during transmission in response to

TX_EN. They are not generated through any combination of TXD[3:0] or TX_ER.

1. IDLE is indicated by RX_DV = 0.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 23 T a b l e3 . 4 B 5 BC o d eV i o l a t i o nD e c o d i n g 3.1.1.2 100 Mb/s Loopback One of two internal 100BASE-TX loopback modes can be selected. Local loopback redirects the TXD[3:0] input data to RXD[3:0] data outputs through the 4B5B coders and scramblers. Local loopback is selected by asserting pin LPBK, by set- ting the LPBK bit (bit 14) in the Basic Mode Con- trol Register (address 00h) or by setting bits 8 and 11 in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) as shown in Table4. Remote loopback redirects the analog line interface inputs to the analog line driver outputs. Remote loopback is selected by setting bit 9 in the Loop- back, Bypass, and Receiver Error Mask Register (address 18h) as shown in Table4. When changing between local and non-loopback modes, the data on RXD[3:0] will be undefined for approximately 330 µs. 3.1.2 100BASE-X Repeater Application The CS8952 provides two low latency modes for repeater applications. These are selected by assert- ing either pin BPALIGN or BP4B5B. Both pins have the effect of bypassing the 4B5B encoder and decoder. Bypassing the coders decreases latency, and uses a 5-bit wide parallel code group interface on pins RXD[4:0] and TXD[4:0] instead of the 4- bit wide MII nibble interface on pins RXD[3:0] and TXD[3:0]. In repeater mode, pin RX_ER is rede- fined as the fifth receive data bit (RXD4), and pin TX_ER is redefined as the fifth transmit data bit (TXD4). BPALIGN can also be selected by setting bit 12 in Loopback, Bypass, and Receiver Error Mask Reg- ister (address 18h). BP4B5B can be selected by set- ting bit 14 of the same register. Pin BPALIGN causes more of the CS8952 to be bypassed than the BP4B5B pin. BPALIGN also by- passes the scrambler/descrambler, and the NRZI to NRZ converters (see Figure1). Also, for repeater applications, pin REPEATER should be asserted to redefine the function of the CRS (carrier sense) pin. The REPEATER function may also be invoked by setting bit 12 in the PCS Sublayer Configuration Register (address 17h). For repeater applications, the RX_EN pin can be used to gate the receive data pins (RXD[4:0], V6 01000 0110 or 0101 (Note 2)1 1 0 0 V7 01100 0110 or 0101 (Note 2)1 1 0 1 V8 10000 0110 or 0101 (Note 2)1 1 1 0 V9 11001 0110 or 0101 (Note 2) 1111 1. CONTROL code groups become violations when found in the data portion of the frame. 2. Invalid code groups are mapped to 5h unless the Code Error Report select bit in the Loopback, Bypass, and Receiver Error Mask Register (address 18h) is set, in which case invalid code groups are mapped to 6h. Code Violations (RX_ER = 1 or TX_ER = 1) Name 5-bit Symbol Normal Mode 4-bit Nibble Error Report Mode 4-bit Nibble Comments Remote Loopback (bit 9) PMD Loopback (bit 8) Function 0 0 No Loopback 0 1 Local Loopback (toward MII) 1 0 Remote Loopback (toward line) 1 1 Operation is undefined Table 4.

24 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

RX_CLK, RX_DV, COL, and CRS) onto a shared, external repeater system bus. 3.1.3 10BASE-T MII Application The digital interface used in this mode is the same as that used in the 100BASE-X MII mode except that TX_CLK and RX_CLK are nominally 2.5 MHz. The CS8952 includes a full-featured 10BASE-T in- terface, as described in the following sections.

3.1.3.1 Full and Half Duplex operation

The 10BASE-T function supports full and half du- plex operation as determined by pins AN[1:0] and/or the corresponding MII register bits. (See Ta- ble5).

3.1.3.2 Collision Detection

If half duplex operation is selected, the CS8952 de- tects a 10BASE-T collision whenever the receiver and transmitter are active simultaneously. When a collision is present, the collision is reported on pin COL. Collision detection is undefined for full-du- plex operation.

3.1.3.3 Jabber

The jabber timer monitors the transmitter and dis- ables the transmission if the transmitter is active for greater than approximately 105 ms. The transmitter stays disabled until approximately 406 ms after the internal transmit request is no longer enabled.

3.1.3.4 Link Pulses

To prevent disruption of network operation due to a faulty link segment, the CS8952 continually moni- tors the 10BASE-T receive pair (RXD+ and RXD-) for packets and link pulses. After each packet or link pulse is received, an internal Link-Loss timer is started. As long as a packet or link pulse is received before the Link-Loss timer finishes (between 50 and 100 ms), the CS8952 maintains normal operation. If no receive activity is detected, the CS8952 disables packet transmission to prevent “blind” transmis- sions onto the network (link pulses are still sent while packet transmission is disabled). To reactivate transmission, the receiver must detect a single pack- et (the packet itself is ignored), or two normal link pulses separated by more than 6 ms and no more than 50 ms. The CS8952 automatically checks the polarity of the receive half of the twisted pair cable. To detect a reversed pair, the receiver examines received link pulses and the End-of-Frame (EOF) sequence of incoming packets. If it detects at least one reversed link pulse and at least four frames in a row with negative polarity after the EOF, the receive pair is considered reversed. If the polarity is reversed and bit 1 of the 10BASE-T Configuration Register (ad- dress 1Ch), is set, the CS8952 automatically cor- rects a reversal. In the absence of transmit packets, the transmitter generates link pulses in accordance with Section 14.2.1.1 of the Ethernet standard. Trans- mitted link pulses are positive pulses, one bit time wide, typically generated at a rate of one every 16 ms. The 16 ms timer also starts whenever the transmitter completes an End-of-Frame (EOF) se- quence. Thus, a link pulse will be generated 16 ms after an EOF unless there is another transmitted packet.

3.1.3.5 Receiver Squelch

The 10BASE-T squelch circuit determines when valid data is present on the RXD+/RXD- pair. In- coming signals passing through the receive filter are tested by the squelch circuit. Any signal with amplitude less than the squelch threshold (either positive or negative, depending on polarity) is re- jected. 3.1.3.6 10BASE-T Loopback When Loopback is selected, the TXD[3:0] pins are looped back into the RXD[3:0] pins through the

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 25 Manchester Encoder and Decoder. Selection is made via: - setting bit 14 in the Basic Mode Control Register (address 00h) or - setting bits 8 and 11 in the Loopback, By- pass, and Receiver Error Mask Register (address 18h) or - asserting the LPBK pin.

3.1.3.7 Carrier Detection

The carrier detect circuit informs the MAC that val- id receive data is present by asserting the Carrier Sense signal (CRS) as soon it detects a valid bit pat- tern (1010b or 0101b for 10BASE-T). During nor- mal packet reception, CRS remains asserted while the frame is being received, and is de-asserted within 2.3 bit times after the last low-to-high tran- sition of the End-of-Frame (EOF) sequence. When- ever the receiver is idle (no receive activity), CRS is de-asserted. 3.1.4 10BASE-T Serial Application This mode is selected when pin 10BT_SERis as- serted during power-up or reset, and operates simi- lar to the 10BASE_T MII mode except that data is transferred serially on pins RXD0 and TXD0 using a1 0M H zR X _ C L Ka n dT X _ C L K .R e c e i v ed a t ai s framed by CRS rather than RX_DV.

3.2 Auto-Negotiation

The CS8952 supports auto-negotiation, which is the mechanism that allows the two devices on ei- ther end of an Ethernet link segment to share infor- mation and automatically configure both devices for maximum performance. When configured for auto-negotiation, the CS8952 will detect and auto- matically operate full-duplex at 100 Mb/s if the de- vice on the other end of the link segment also supports full-duplex, 100 Mb/s operation, and auto-negotiation. The CS8952 auto-negotiation ca- pability is fully compliant with the relevant por- tions of section 28 of the IEEE 802.3u standard. The CS8952 can auto-negotiate both operating speed (10 versus 100 Mb/s), duplex mode (half du- plex versus full duplex), and flow control (pause frames), or alternatively can be set not to negotiate. At power-up and reset times, the auto-negotiation mode is selected via the auto-negotiation input pins (AN[1:0]). This selection can later be changed us- ing the Auto-Negotiation Advertisement Register (address 04h). Pins AN[1:0] are three level inputs, and have the function shown in Table5.

26 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

Auto-Negotiation encapsulates information within a burst of closely spaced Link Integrity Test Pulses, referred to as a Fast Link Pulse (FLP) Burst. The FLP Burst consists of a series of Link Integrity Pulses which form an alternating clock / data se- quence. Extraction of the data bits from the FLP Burst yields a Link Code Word which identifies the capability of the remote device. In order to support legacy 10 and 100 Mb/s devic- es, the CS8952 also supports parallel detection. In parallel detection, the CS8952 monitors activity on the media to determine the capability of the link partner even without auto-negotiation having oc- curred.

3.3 Reset Operation

Reset occurs in response to six different conditions: 1) There is a chip-wide reset whenever the RE- SET pin is high for at least 200 ns. During a chip-wide reset, all circuitry and registers in the CS8952 are reset. 2) When power is applied, the CS8952 maintains reset until the voltage at the VDD supply pins reaches approximately 3.6 V. The CS8952 comes out of reset once VDD is greater than ap- proximately 3.6 V and the crystal oscillator has stabilized. 3) There is a chip-wide reset whenever the RE- SET bit (bit 15 of the Basic Mode Control Reg- ister (address 00h)) is set. 4) Digital circuitry is reset whenever bit 0 of the PCS Sub-Layer Configuration Register (ad- dress 17h) is set. Analog circuitry is unaffected. 5) Analog circuitry is reset and recalibrated when- ever the CS8952 enters or exits the power- down state, as requested by pin PWRDN. 6) Analog circuitry is reset and recalibrated when- ever the CS8952 changes between 10 Mb/s and 100 Mb/s modes. After a reset, the CS8952 latches the signals on var- ious input pins in order to initialize key registers and goes through a self configuration. This in- cludes calibrating on-chip analog circuitry. Time required for the reset calibration is typically 40 ms. External circuitry may access registers internal to the CS8952 during this time. Reset and calibration complete is indicated when bit 15 of the Basic Mode Control Register (address 00h) is clear.

3.4 LED Indicators

The LEDx , SPD100, and SPD10 output pins pro- vide status information that can be used to drive LEDs or can be used as inputs to external control circuitry. Indication options include: receive activ- ity, transmit activity, collision, carrier sense, polar- ity OK, descrambler synchronization status, auto- negotiation status, speed (10 vs. 100), and duplex mode. 4. MEDIA INDEPENDENT INTERFACE (MII) The Media Independent Interface (MII) provides a simple interconnect to an external Media Access Controller (MAC). This connection may be chip to chip, motherboard to daughterboard, or a connec- tion between two assemblies attached by a limited length of shielded cable and an appropriate connec- tor. The MII interface uses the following pins: AN1 AN0 Forced/ Auto Speed (Mb/s) Full/Half Duplex Low Floating Forced 10 Half High Floating Forced 10 Full Floating Low Forced 100 Half Floating High Forced 100 Full Floating Floating Auto-Neg 100/10 Full/Half Low Low Auto-Neg 10 Half Low High Auto-Neg 10 Full High Low Auto-Neg 100 Half High High Auto-Neg 100 Full Table 5.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 27 STATUS Pins - COL - Collision indication, valid only for half duplex modes. - CRS - Carrier Sense indication SERIAL MANAGEMENT Pins - MDIO - a bi-directional serial data path - MDC - clock for MDIO (16.7 MHz max) - MII_IRQ - Interrupt indicating change in the Interrupt Status Register (address 11h) RECEIVE DATA Pins - RXD[3:0] - Parallel data output path - RX_CLK - Recovered clock output - RX_DV - Indicates when receive data is present and valid - RX_ER - Indicates presence of error in re- ceived data - RX_EN - Can be used to tri-state receiver output pins TRANSMIT DATA Pins - TXD[3:0] - Parallel data input path - TX_CLK - Transmit clock - TX_EN - Indicates when transmit data is present and valid - TX_ER - Request to transmit a 100BASE- T HALT symbol, ignored for 10BASE-T operation. The interface uses TTL signal levels, which are compatible with devices operating at a nominal supply voltage of either 5.0 or 3.3 volts. It is capa- ble of supporting either 10 Mb/s or 100 Mb/s data rates transparently. That is, all signaling remains identical at either data rate; only the nominal clock frequency is changed.

4.1 MII Frame Structure

Data frames transmitted through the MII have the following format: Each frame is preceded by an inter-frame gap. The inter-frame gap is an unspecified time during which no data activity occurs on the media as indi- cated by the de-assertion of CRS for the receive path and TX_EN for the transmit path. The Preamble consists of seven bytes of 10101010. The Start of Frame Delimiter consists of a single byte of 10101011. Data may be any number of bytes. The End of Frame Delimiter is conveyed by the de- assertion of RX_DV and TX_EN for receive and transmit paths, respectively. Transmission and/or reception of each byte of data is done one nibble at a time in the following order:

4.2 MII Receive Data

The presence of recovered data on the RXD[3:0] bus is indicated by the assertion of RX_DV. RX_DV will remain asserted from the beginning of the preamble (or Start of Frame Delimiter if pream- ble is not used) to the End of Frame Delimiter. Once RX_DV is asserted, valid data will be driven Preamble (7 Bytes) Start of Frame Delimiter (1 Byte) Data End of Frame Delimiter MII LSB MSB Nibble Stream MAC’s Serial Bit StreamFirst Bit First Second NibbleNibble D1 D2 D3 D4 D5 D6 D7LSB MSB

28 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

rors, and Figure3 illustrates reception with errors.

4.3 MII Transmit Data

data is being presented to the MII. serted, data on TXD[3:0] is ignored. asserting TX_ER for one or more TX_CLK cycles.

4.4 MII Management Interface

plements an extended set of 16-bit MII registers. Figure 2. Reception without errors Figure 3. Reception with errors

enhanced monitoring and control capabilities. through the PHYAD[4:0] pins.

4.5 MII Management Frame Structure

keep MDIO pulled to a logic ONE. tern that it can use to establish synchronization. Sub-Layer Configuration Register (address 17h). The Start of Frame is indicated by a 01 bit pattern. Figure 4. Transmission without errors Figure 5. Transmission with errors Table 6. Format for Frame Transmitted through the MII Management Interface

30 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

A read transaction is indicated by an Opcode of 10 a n daw r i t eb y0 1 . The PHY Address is five bits, with the most signif- icant bit sent first. If the PHY address included in the frame is not 00000 or does not match the PHY- AD field of the Self Status Register (address 19h), the rest of the frame is ignored. The register address is five bits, with the most sig- nificant bit sent first, and indicates the CS8952 reg- ister to be written to/read from. The Turnaround time is a two bit time spacing be- tween when the MAC drives the last register ad- dress bit onto MDIO and the data field of a management frame in order to avoid contention during a read transaction. For a read transaction, the MAC should tri-state the MDIO pin beginning on the first bit time, and the CS8952 will begin driving the MDIO signal to a logic ZERO during the second bit time. During write transactions, since the MDIO direction does not need to be re- versed, the MAC will drive the MDIO to a logic ONE for the first bit time and a logic ZERO for the second. The data field is always 16 bits in length, with the most significant bit sent first. 5. CONFIGURATION The CS8952 can be configured in a variety of ways. All control and status information can be accessed via the MII Serial Management Interface. Addi- tionally, many configuration options can be set at power-up or reset times via individual control lines. Some configuration capabilities are available at any time via individual control lines.

5.1 Configuration At Power-up/Reset

At power-up and reset time, the following pins are

5.2 Configuration Via Control Pins

The following pins are for dedicated control signals and can be used at any time to configure the CS8952.

5.3 Configuration via the MII

The CS8952 supports configuration by software control through the use of 16-bit configuration and status registers accessed via the MDIO/MDC pins (MII Management Interface). The first seven regis- ters are defined by the IEEE 802.3 specification. Additional registers extend the register set to pro- vide enhanced monitoring and control capabilities. 6. CS8952 REGISTERS The CS8952 register set is comprised of the 16-bit status and control registers described below. A de- tailed description each register follows. Pin Name Function 10BT_SER Select 10BASE-T serial mode AN[1:0] Select auto-negotiation mode BP4B5B Bypass 4B5B coders BPALIGN Bypass 4B5B coders and scramblers BPSCR Bypass scramblers, enter FX mode ISODEF Electrically isolate MII after reset LPSTRT Start in low power mode PHYAD[4:0] Set MII PHY address REPEATER Control definition of CRS pin, enable carrier integrity monitor and SQE func- tion MII_DRV Set MII driver strength TCM Set TX_CLK mode TXSLEW[1:0] Set 100BASE-TX transmitter output slew rate Pin Name Function LPBK Enter loopback mode PWRDN Enter power-down mode RESET Reset Register Address Description Type 0h Basic Mode Control Register Read/Write 1h Basic Mode Status Register Read-Only

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 31 2h PHY Identifier #1 Read-Only 3h PHY Identifier #2 Read-Only 4h Auto-Negotiation Advertisement Register Read/Write 5h Auto-Negotiation Link Partner Ability Register Read-Only 6h Auto-Negotiation Expansion Register Read-Only 7h Auto-Negotiation Next Page Transmit Register Read/Write 8h through Fh Reserved by IEEE 802.3 Working Group - 10h Interrupt Mask Register Read/Write 11h Interrupt Status Register Read-Only 12h Disconnect Count Register Read-Only 13h False Carrier Count Register Read-Only 14h Scrambler Key Initialization Register Read/Write 15h Receive Error Count Register Read-Only 16h Descrambler Key Initialization Register Read/Write 17h PCS Sub-Layer Configuration Register Read/Write 18h Loopback, Bypass and Receiver Error Mask Register Read/Write 19h Self-Status Register Read/Write 1Ah Reserved - 1Bh 10BASE-T Status Register Read-Only 1Ch 10BASE-T Configuration Register Read/Write 1Dh through 1Fh Reserved - Register Address Description Type

32 CrystalLAN™ 100BASE-X and 10BASE-T Transceiver

6.1 Basic Mode Control Register - Address 00h

Enable Power Down Isolate Restart Auto-Neg Duplex Mode 76543210 Collision Test Reserved BIT NAME TYPE RESET DESCRIPTION 15 Software Reset Read/Set 0 Setting this bit performs a chip-wide reset. All status and control registers are set to their default states, and the analog circuitry is re-calibrated. This bit is an Act-Once bit which is cleared once the reset and re- calibration have completed. This bit will also be set automatically while the analog circuitry is reset and re-calibrated during mode changes.

14 Loopback Read/Write 0 When set, the CS8952 is placed in a loop back

mode. Any data sent on the transmit data path is returned on the receive data path. Loopback mode is entered regardless of whether 10 Mb/s or 100 Mb/s operation has been configured. This bit will be set upon the assertion of the LPBK pin, and will be automatically cleared upon its deas- sertion.

13 Speed Selection Read/Write If auto-negotiation

AN[1:0] pins, reset to 1; otherwise, reset to 0 When bit 12 is clear, setting this bit configures the CS8952 for 100 Mb/s operation. Clearing this bit sets the configuration at 10 Mb/s. When bit 12 is set, this bit is ignored.

12 Auto-Neg Enable Read/Write If auto-negotiation

AN[1:0] pins, reset to 1; otherwise, reset to 0 Setting this bit enables the auto-negotiation process. When this bit is set, bits 13 and 8 have no affect on the link configuration. The link configuration is deter- mined by the auto-negotiation process. Clearing this bit disables auto-negotiation.

11 Power Down Read/Write 0 When this bit is set, the CS8952 enters a low power

consumption state. Clearing this bit allows normal operation. Note: This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

10 Isolate Read/Write If PHYAD =

00000, reset to 1; otherwise reset to the value on the ISODEF pin Setting this bit causes the MII data path to be electri- cally isolated by tri-stating all data outputs (i.e. TX_CLK, RX_CLK, RX_DV, RX_ER, RXD[3:0], COL, and CRS). In addition the CS8952 will not respond to the TXD[3:0], TX_EN, and TX_ER inputs. It will, how- ever, respond to MDIO and MDC. Clearing this bit allows normal operation.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 33

9 Restart Auto-Neg Read/Set 0 Setting this bit causes auto-negotiation to be

restarted. It is an Act-Once bit which is cleared once auto-negotiation has begun. Clearing this bit has no effect on the auto-negotiation process.

8 Duplex Mode R/W If auto-negotiation

AN[1:0] pins, reset to 0; otherwise, reset to 1 When bit 12 is clear, this bit controls the Full- Duplex/Half-Duplex operation of the part. When set, the part is configured for Full-Duplex operation, and when clear the part is configured for Half Duplex operation. The setting of this bit is superseded by auto-negotiation, and thus has no effect if bit 12 is set.

7 Collision Test R/W 0 When set, the COL pin will be asserted within 10 bit

times in response to the assertion of TX_EN. Upon the deassertion of TX_EN, COL will be deasserted within 4 bit times. When Collision Test is clear, COL functions normally. 6:0 Reserved Read Only 000 0000 BIT NAME TYPE RESET DESCRIPTION

34 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.2 Basic Mode Status Register - Address 01h

Complete Remote Fault Auto-Neg Ability Link Status Jabber Detect Extended Capability BIT NAME TYPE RESET DESCRIPTION 15 100BASE-T4 Read Only 0 The CS8952 does not support 100BASE-T4 opera- tion, so this bit will always read 0. 14 100BASE-TX/Full Duplex Read Only 1 When this bit is set, it indicates that the CS8952 is capable of 100BASE-TX Full-Duplex operation. This bit reflects the status of the 100BASE-TX/Full-Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 13 100BASE-TX/Half Duplex Read Only 1 When this bit is set, it indicates that the CS8952 is capable of 100BASE-TX Half-Duplex operation. This bit reflects the status of the 100BASE-TX/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 12 10BASE-T/Full Duplex Read Only 1 When this bit is set, it indicates that the CS8952 is capable of 10BASE-T Full-Duplex operation. This bit reflects the status of the 10BASE-T/Full Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 11 10BASE-T/Half Duplex Read Only 1 When this bit is set, it indicates that the CS8952 is capable of 10BASE-T Half-Duplex operation. This bit reflects the status of the 10BASE-T/Half Duplex bit in the Auto-Negotiation Advertisement Register (address 04h). 10:7 Reserved Read Only 0000

6 MF Preamble Sup-

Read Only 1 When set, this bit indicates that the CS8952 is capa- ble of accepting management frames regardless of whether they are preceded by the preamble pattern. When clear, it indicates that the management frame must be preceded by the preamble pattern to be con- sidered valid. This bit reflects the status of the MR Preamble Enable bit in the PCS Sub-Layer Configu- ration Register (address 17h).

5 Auto-Neg Complete Read Only 0 This bit is set to a 1 when the auto-negotiation pro-

cess has completed. This is an indication that data is valid in the Auto-Negotiation Advertisement Register (address 04h), the Auto-Negotiation Link Partner Ability Register (address 05h), and the Auto-Negotia- tion Expansion Register (address 06h).

4 Remote Fault Read Only 0 When auto-negotiation is enabled, this bit is set if the

Remote Fault bit is set in the Auto-Negotiation Link Partner Ability Register (address 05h). When auto- negotiation is disabled, this bit will be set when a Far- End Fault Indication for 100BASE-TX is detected.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 35

3 Auto-Neg Ability Read Only 1 This bit indicates that the CS8952 has auto-negotia-

tion capability. Therefore this bit will always read back a value of 1.

2 Link Status Read Only 0 When set, this bit indicates that a valid link has been

established. Upon a link failure, this bit is cleared and latched. It will remain cleared until this register is read.

1 Jabber Detect Read Only 0 In 10BASE-T mode, if the last transmission is longer

than 105 ms, then the packet output is terminated by the jabber logic and this bit is set. If JabberiE (Inter- rupt Mask Register (address 10h), bit 3) is set, an MII Interrupt will be generated. This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this regis- ter, a read to the Interrupt Status Register (address 11h), or a reset. No jabber detect function has been defined for 100BASE-TX.

0 Extended Capability Read Only 1 This bit indicates that an extended register set may

be accessed (registers beyond address 01h). This bit always reads back a value of 1. BIT NAME TYPE RESET DESCRIPTION

36 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.3 PHY Identifier, Part 1 - Address 02h

Organizationally Unique Identifier: Bits[3:10] 76543210 Organizationally Unique Identifier: Bits[11:18] BIT NAME TYPE RESET DESCRIPTION 15:0 Organizationally Unique Identifier (bits 3:18) Read/Write 001Ah This identifier is assigned to PHY manufacturers by the IEEE. Its intention is to provide sufficient informa- tion to support 10/100 Management as defined in Clause 30.1.2 of the IEEE 802.3 specification. This register contains bits [3:18] of the OUI. Bit 3 of the OUI is located in bit 15 of the PHY Identifier, bit 4 of the OUI is in bit 14, and so on. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 37

6.4 PHY Identifier, Part 2 - Address 03h

Organizationally Unique Identifier - Bits[19:24] Part Number 76543210 Part Number Revision Number BIT NAME TYPE RESET DESCRIPTION 15:10 Organizationally Unique Identifier (bits 19:24) Read/Write 00 1000 This identifier is assigned to PHY manufacturers by the IEEE. Its intention is to provide sufficient informa- tion to support 10/100 Management as defined in Clause 30.1.2 of the IEEE 802.3 specification. This register contains bits [19:24] of the OUI. Bit 19 of the OUI is located in bit 15 of this register, bit 20 of the OUI is in bit 14, and so on. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 9:4 Part Number Read/Write 10 0000 These bits indicate the CS8952 part number. It has been set to a value of 100000. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 3:0 Revision Number Read/Write 0001 These bits indicate the CS8952 part revision. Rev. A 0000 Rev. B 0001 etc. Note: This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

38 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.5 Auto-Negotiation Advertisement Register - Address 04h

Next Page Acknowledge Remote Fault Technology Ability Field 76543210 Technology Ability Field Protocol Selector Field BIT NAME TYPE RESET DESCRIPTION

15 Next Page Read/Write 0 When set, this bit enables the ability to exchange

Next-Pages with the link partner. This bit should be cleared if it is not desired to engage in Next Page exchange. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

14 Acknowledge Read Only 0 When set, this bit indicates consistent reception of

the link partner’s data.

13 Remote Fault Read/Write 0 This bit may be used to indicate a fault condition to

the link partner. Setting this bit will signal to the link partner that a fault condition has occurred. 12:5 Technology Ability Field Read/Write 0000 1111 This field determines the advertised capabilities of the CS8952 as shown below. When the bit is set, the corresponding technology will be advertised during auto-negotiation. BIT Capability

12 Reserved

11 Reserved

10 PAUSE operation for full duplex links. Set only if supported by the host MAC. 9 100BASE-T4 (Note: this technology is not supported and can not be set. 8 100BASE-TX Full Duplex 7 100Base-TX Half Duplex 6 10BASE-T Full Duplex 5 10BASE-T Half Duplex 4:0 Protocol Selector Field Read/Write 0 0001 This field is used to identify the type of message being sent by auto-negotiation. This field defaults to a value of“00001”for IEEE 802.3 messages.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 39

6.6 Auto-Negotiation Link Partner Ability Register - Address 05h

Next Page Acknowledge Remote Fault Technology Ability Field 76543210 Technology Ability Field Protocol Selector Field BIT NAME TYPE RESET DESCRIPTION

15 Next Page Read Only 0 When set, this bit indicates that the link partner is

capable of participating in the Next Page exchange.

14 Acknowledge Read Only 0 When set, this bit indicates that the link partner has

received consistent data from the CS8952.

13 Remote Fault Read Only 0 This bit indicates that a fault condition occurred on

the far end. When this bit is set and auto-negotiation is enabled, the Remote Fault bit in the Basic Mode Status Register (address 01h) will also be set. 12:5 Technology Ability Field Read Only 0000 0000 This field indicates the advertised capabilities of the link partner as shown below. When the bit is set, the corresponding technology has been advertised dur- ing auto-negotiation. BIT Capability 10 PAUSE operation for full duplex links. 9 100BASE-T4 (Note: this technology is not 8 100BASE-TX Full Duplex 7 100Base-TX Half Duplex 6 10BASE-T Full Duplex 5 10BASE-T Half Duplex 4:0 Protocol Selector Field Read Only 0 0000 This field is used to identify the type of message being received during auto-negotiation.

40 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.7 Auto-Negotiation Expansion Register - Address 06h

Able Page Received Link Partner Auto-Neg Able BIT NAME TYPE RESET DESCRIPTION 15:5 Reserved Read Only 000 0000 0000

4 Parallel Detection

Read Only 0 When set, this bit indicates an error condition in which both the 10BASE-T and 100BASE-TX links came up valid, or that one of the technologies estab- lished a link but was unable to maintain the link. This bit is self-clearing.

3 Link Partner Next

Read Only 0 When set, this bit indicates that the link partner is capable of Next Page exchange.

2 Next Page Able Read Only 1 This bit is a status bit which indicates to the Manage-

ment Layer that the CS8952 supports Next Page capability. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

1 Page Received Read Only 0 When set, this bit indicates that a valid word of auto-

negotiation data has been received and its integrity verified. The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing.

0 Link Partner Auto-

Read Only 0 When set, this bit indicates that the link partner has auto-negotiation capability.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 41

6.8 Auto-Negotiation Next-Page Transmit Register - Address 07h

Next Page Acknowledge Message Page Acknowledge 2 Toggle Message/Unformatted Code Field 76543210 Message/Unformatted Code Field BIT NAME TYPE RESET DESCRIPTION

15 Next Page Read/Write 0 When set, this bit indicates that more Next Pages fol-

low. When clear, the current page is the last page of data to be sent. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. 14 Acknowledge Read Only 0 This bit is used for Link Code Word verification. When set, it indicates that consistent data has been successfully read from the link partner.

13 Message Page Read/Write 1 When set, this bit indicates that the data in the Mes-

sage/Unformatted Code Field is one of the pre- defined message pages. When low, the data is unformatted data. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

12 Acknowledge 2 Read/Write 0 When set, this bit indicates to the link partner that the

CS8952 can comply with the last received message. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

11 Toggle Read Only 0 This bit is used to maintain synchronization with the

link partner during Next Page exchange. 10:0 Message/Unformat- ted Code Field Read/Write 000 0000 0001 This field contains the 11 bit data for the Message or Unformatted Page. It defaults to the Null Message. Note:This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

42 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.9 Interrupt Mask Register - Address 10h

This register indicates which events will cause an interrupt event on the MII_IRQpin. Each bit acts as an enable to the interrupt. Thus, when set, the event will cause the MII_IRQp i nt ob ea s s e r t e d .W h e n clear, the event will not affect the MII_IRQpin, but the status will still be reported via the Interrupt Sta- tus Register (address 11h). 15 14 13 12 11 10 9 8 CIM Link Unstable Link Status Change Descrambler Lock Change Premature End Error DCR Rollover FCCR Rollover RECR Rollover Remote Loopback Fault 76543210 Reset Complete Jabber Detect Auto-Neg Complete Parallel Detection Fault Parallel Fail Remote Fault Page Received Reserved BIT NAME TYPE RESET DESCRIPTION

15 CIM Link Unstable Read/Write 0 When set, an interrupt will be generated if an unsta-

ble link condition is detected by the Carrier Integrity Monitor function. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

14 Link Status Change Read Write 1 When set, an interrupt will be generated each time

the CS8952 detects a change in the link status. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

13 Descrambler Lock

Read/Write 0 When set, an interrupt will be generated each time the 100BASE-TX receive descrambler loses or regains synchronization with the far-end. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

12 Premature End

Read/Write 0 When set, an interrupt will be generated when two consecutive IDLES are detected in a 100BASE-TX frame without the ESD sequence. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 43

11 DCR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in

the DCR counter becomes set. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

10 FCCR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in

the FCCR counter becomes set. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

9 RECR Rollover Read/Write 0 When set, an interrupt will be generated if the MSB in

the RECR counter becomes set. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

8 Remote Loopback

Read/Write 0 When set, an interrupt will be generated if the elastic buffer in the PMA is under-run or over-run during Remote Loopback. This should not occur for normal length 802.3 frames. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

7 Reset Complete Read/Write 1 When set, an interrupt will be generated once the

digital and analog sections have been reset, and a calibration cycle has been performed. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

6 Jabber Detect Read/Write 0 When set, an interrupt will be generated when a Jab-

ber condition is detected by the 10BASE-T MAU. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. BIT NAME TYPE RESET DESCRIPTION

44 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

5 Auto-Neg Complete Read/Write 0 When set, an interrupt will be generated once auto-

negotiation has completed successfully. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. Read/Write 0 When set, an interrupt will be generated if auto-nego- tiation determines that unstable legacy link signaling was received. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

3 Parallel Fail Read/Write 0 When set, an interrupt will be generated when paral-

lel detection has occurred for a technology that is not currently advertised by the local device. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

2 Remote Fault Read/Write 0 When set, an interrupt will be generated if a remote

fault condition is detected either by auto-negotiation or by the Far-End Fault Detect state machine. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

1 Page Received Read/Write 0 When set, an interrupt is generated each time a page

is received during auto-negotiation. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

0 Reserved Read Only 0

BIT NAME TYPE RESET DESCRIPTION

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 45

6.10 Interrupt Status Register - Address 11h

This register indicates which event(s) caused an interrupt event on the MII_IRQpin. All bits are self- clearing, and will thus be cleared upon readout. 15 14 13 12 11 10 9 8 CIM Link Unstable Link Status Change Descrambler Lock Change Premature End Error DCR Rollover FCCR Rollover RECR Rollover Remote Loopback Fault 76543210 Reset Complete Jabber Detect Auto-Neg Complete Parallel Detection Fault Parallel Fail Remote Fault Page Received Reserved BIT NAME TYPE RESET DESCRIPTION

15 CIM Link Unstable Read Only 0 When set, this bit indicates that an unstable link con-

dition was detected by the Carrier Integrity Monitor function.

14 Link Status Change Read Only 0 When set, this bit indicates that a change has

occurred to the status of the link. The Self Status Register (address 19h) may be read to determine the current status of the link. Read Only 0 When set, this bit indicates that a change has occurred in the status of the descrambler. The Self Status Register (address 19h) may be read to deter- mine the current status of the scrambler lock. Read Only 0 This bit is set when a premature end of frame is detected for 100 Mb/s operation. A premature end is defined as two consecutive IDLE patterns detected in a frame prior to the End of Stream Delimiter.

11 DCR Rollover Read Only 0 This bit is set when the MSB of the Disconnect Count

Register (address 12h) becomes set. This should provide ample warning to the management layer so that the DCR may be read before rolling over.

10 FCCR Rollover Read Only 0 This bit is set when the MSB of the False Carrier

Count Register (address 13h) becomes set. This should provide ample warning to the management layer so that the FCCR may be read before saturat- ing.

9 RECR Rollover Read Only 0 This bit is set when the MSB of the Receive Error

Count Register (address 15h) becomes set. This should provide ample warning to the management layer so that the RECR may be read before rolling over.

46 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

Read Only 0 When set, this bit indicates that the Elastic Buffer has detected an over-run or an under-run condition. In any case, the frame generating this fault will be ter- minated. This should never happen since the depth of the elastic buffer (10 bits) is greater than twice the maxi- mum number of bit times the receive and transmit clocks may slip during a maximum length packet assuming clock frequency tolerances of 100 ppm or less.

7 Reset Complete Read Only 0 When set, this bit indicates that the internal analog

calibration cycle has completed, and all analog and digital circuitry is ready for normal operation.

6 Jabber Detect Read Only 0 In 10BASE-T mode, if the last transmission is longer

than 105 ms, then the packet output is terminated by the jabber logic and this bit is set. This bit is implemented with a latching function so that the occurrence of a jabber condition causes it to become set until it is cleared by a read to this regis- ter, a read to the Basic Mode Status Register (address 01h), or a reset. No jabber detect function has been defined for 100BASE-TX. This bit is the same as in the Basic Mode Status Reg- ister (address 01h).

5 Auto-Neg Complete Read Only 0 This bit is set when the auto-negotiation process has

completed. This is an indication that the Auto-Negoti- ation Advertisement Register (address 04h), the Auto-Negotiation Link Partner Ability Register (address 05h), and the Auto-Negotiation Expansion Register (address 06h) are valid. This bit is the same as in the Basic Mode Status Reg- ister (address 01h). Read Only 0 When set, this bit indicates an error condition in which auto-negotiation has detected that unstable 10BASE-T or 100BASE-TX link signalling was received. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h)

3 Parallel Fail Read Only 0 When set, this bit indicates that a parallel detection

has occurred for a technology that is not currently advertised by the local device. BIT NAME TYPE RESET DESCRIPTION

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 47

2 Remote Fault Read Only 0 When auto-negotiation is enabled, this bit is set if the

Remote Fault bit is set in the Auto-Negotiation Link Partner Ability Register (address 05h). When auto- negotiation is disabled, this bit will be set when the Far-End Fault Indication for 100BASE-TX is detected. negotiation data has been received and its integrity verified. The first page of data will consist of the Base Page, and all successive pages will consist of Next Page data. This bit is self-clearing. This bit is the same as in the Auto-Negotiation Expansion Register (address 06h). BIT NAME TYPE RESET DESCRIPTION

48 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.11 Disconnect Count Register - Address 12h

BIT NAME TYPE RESET DESCRIPTION 15:0 Disconnect Counter Read/Write 0000h This field contains a count of the number of times the CS8952 has lost a Link OK condition. This counter is cleared upon readout and will roll-over to 0000h.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 49

6.12 False Carrier Count Register - Address 13h

BIT NAME TYPE RESET DESCRIPTION 15:0 False Carrier Counter Read Only 0000h This field contains a count of the number of times the CS8952 has detected a false-carrier -- that is, the reception of a poorly formed Start-of-Stream Delim- iter (SSD). The counter is incremented at the end of such events to prevent multiple increments. This counter is cleared upon readout and will saturate at FFFFh.

50 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.13 Scrambler Key Initialization Register - Address 14h

Load Reserved Scrambler Initialization Key 76543210 Scrambler Initialization Key BIT NAME TYPE RESET DESCRIPTION

15 Load Read/Set 0 When this bit is set, the scrambler will be loaded with

the value in the Scrambler Initialization Key field. When the load is complete, this bit will clear automat- ically. 14:11 Reserved Read Only 0000 These bits should be read as don ’t cares and, when written, should be written to 0. 10:0 Scrambler Initializa- tion Key Read/Write Reset value is dependent on the PHY Address field of the Self Status Register (address 19h). This field allows the Scrambler to be loaded with a user-definable key sequence. A value of 000h has the effect of bypassing the scrambler function. This is valuable for testing purposes to allow a deter- ministic response to test stimulus without a synchro- nization delay. Note:This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 51

6.14 Receive Error Count Register - Address 15h

BIT NAME TYPE RESET DESCRIPTION 15:0 Receive Error Counter Read Only 0000h This counter increments for each packet in which one or more receive errors is detected that is not due to a collision event. This counter is cleared upon readout and will roll-over to 0000h.

52 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.15 Descrambler Key Initialization Register - Address 16h

Load Reserved Descrambler Initialization Key 76543210 Descrambler Initialization Key BIT NAME TYPE RESET DESCRIPTION

15 Load Read/Set 0 When this bit is set, the descrambler will be loaded

with the value in the Descrambler Initialization Key field. When the load is complete, this bit will clear automatically. 14:11 Reserved Read Only 0000 These bits should be read as don ’t cares and, when written, should be written to 0. 10:0 Descrambler Initial- ization Key Read/Write Reset value is dependent on the PHY Address field of the Self Status Register (address 19h). This register allows the Descrambler to be loaded with a user-definable key sequence. A value of 000h has the effect of bypassing the descrambler function. This is valuable for testing purposes to allow a deter- ministic response to test stimulus without a synchro- nization delay. Note:This field is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 53

6.16 PCS Sub-Layer Configuration Register - Address 17h

Mode LED5 Mode Unlock Regs MR Preamble Enable Fast Test 76543210 CLK25 Disable Enable LT/100 CIM Disable Tx Disable Rx Disable LED1 Mode LED4 Mode Digital Reset BIT NAME TYPE RESET DESCRIPTION

15 NRZI Enable Read/Write 1 When this bit is set, the NRZI encoder and decoder

are enabled. When this bit is clear, NRZI encoding and decoding are disabled.

14 Time-Out Select Read/Write 0 When this bit is set, the time-out counter in the

receive descrambler is set to time-out after 2 ms without IDLES. When clear the counter is set to time- out after 722µs without IDLES.

13 Time-Out Disable Read/Write 0 When this bit is set, the time-out counter in the

receive descrambler is disabled. When this bit is clear, the time-out counter is enabled.

12 Repeater Mode Read/Write Reset to the value

REPEATER pin. This bit defines the mode of the Carrier Sense (CRS) signal. When this bit is set, CRS is asserted due to receive activity only. When this bit is clear, CRS is asserted due to either transmit or receive activity.

11 LED5 Mode Read/Write 0 This bit defines the mode of Pin LED5

. When this bit is set, pin LED5indicates the synchronization status of the 100BASE-TX descrambler. When this bit is clear, LED5 indicates a collision. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

10 Unlock Regs Read/Write 0 When set, this bit unlocks certain read only control

registers for factory testing. Leave clear for proper operation. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

54 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

Read/Write 0 When set, this bit will force all management frames (via MDIO, MDC) to be preceded by a 32 bit pream- ble pattern of contiguous ones to be considered valid. When cleared, it allows management frames with or without the preamble pattern. The status of this register is (inversely) reflected in the MF Pream- ble bit in the Basic Mode Status Register (address 01h). Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

8 Fast Test Read/Write 0 When set, internal timers are sped up significantly in

order to facilitate production test. Leave clear for proper operation. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

7 CLK25 Disable Read/Write When TCM pin is

low, reset to 1; otherwise, reset to Setting this bit will disable (tri-state) the CLK25 out- put pin, reducing digital noise and power consump- tion. 6 Enable LT/100 Read/Write 1 When set, normal link status checking is enabled. When clear, this bit forces the link status to Link OK (at 100 Mb/s), and will assert the LINK_OK LED.

5 CIM Disable Read/Write Reset to the logic

REPEATER pin. When set, this bit forces the Carrier Integrity Monitor function to be disabled. When low, the Carrier Integ- rity Monitor function is enabled, and detection of an unstable link will disable the receive and transmit functions.

4 Tx Disable Read/Write 0 When set, this bit forces the 10 Mb/s and 100 Mb/s

outputs to be inactive. When clear, normal transmis- sion is enabled. If Tx Disable is set while a packet is being transmit- ted, transmission is completed and no subsequent packets are transmitted until Tx Disable is cleared again. Also, if Tx Disable is cleared while TX_EN is high, the transmitter will remain disabled until TX_EN is deasserted. This prevents fragments from being transmitted onto the network. BIT NAME TYPE RESET DESCRIPTION

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 55

3 Rx Disable Read/Write 0 When set, the receiver is disabled and no incoming

packets pass through the receiver. The link will remain established and, if operating at 100 Mb/s, the descrambler will remain locked. When clear, the receiver is enabled. If Rx Disable is set while a packet is being received, reception is completed and no subsequent receive packets are allowed until Rx Disable is cleared again. Also, if Rx Disable is cleared while a packet is being received, the receiver will remain disabled until the end of the incoming packet. This prevents fragments from being sent to the MAC. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

2 LED1 Mode Read/Write 0 This bit defines the mode of Pin LED1

. When this bit is set, pin LED1indicates Carrier Integrity Monitor status as determined by the CIM Status bit in the Self Status Register (address 19h). When this bit is clear, LED1 indicates 10 Mb/s or 100 Mb/s transmission activity. 1 LED4 Mode Read/Write 0 This bit defines the mode of Pin LED4 . When this bit is set, pin LED4indicates full duplex mode for 10 Mb/s or 100 Mb/s. When this bit is clear, LED4 indicates Polarity in 10 Mb/s mode or full-duplex in 100 Mb/s mode.

0 Digital Reset Read/Write 0 When set, this bit will reset all digital logic and regis-

ters to their initial values. The analog circuitry will not be affected. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. BIT NAME TYPE RESET DESCRIPTION

56 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.17 Loopback, Bypass, and Receiver Error Mask Register - Address 18h

Strip PreambleAlternate FDX CRS Loopback Transmit Disable Code Error Report Select Premature End Error Report Select Link Error Report Enable Packet Error Report Enable Code Error Report Enable BIT NAME TYPE RESET DESCRIPTION

15 Bad SSD Enable Read/Write 1 When set, this bit enables the reporting of a bad SSD

(False-Carrier event) on the MII. These events will be reported by setting RX_ER=1, RX_DV=0, and RXD[3:0]=1110. If the 4B5B encoders are being bypassed, this event will be reported by setting RX_DV=0 and RXD[4:0]=11110. If symbol alignment is bypassed, the CS8952 does not detect carrier, and thus will not report bad SSD events.

14 Bypass 4B5B Read/Write Reset to the value

pin. When set, this bit causes the receive 5B4B decoder and the transmit 4B5B encoder to be bypassed.

13 Bypass Scrambler Read/Write Reset to the value

pin. When set, this bit causes the receive descrambler and the transmit scrambler blocks to be bypassed, and the CS8952 accepts NRZI data from an external 100BASE-FX optical module through pins RX_NRZ+ and RX_NRZ-.

12 Bypass Symbol

Read/Write Reset to the value on the BPALIGN pin. When set, this bit causes the following functions to be bypassed: receiver descrambling, symbol align- ment and decoding, transmit symbol encoding, and transmit scrambling.

11 ENDEC Loopback Read/Write 0 When set, the 10BASE-T internal Manchester

encoder output is connected to the decoder input. When clear, the CS8952 is configured for normal operation.

10 FX Drive Read/Write 0 This bit controls the drive strength of the 100BASE-

FX PECL interface drivers. When clear, the drivers are optimized for a 50Ω load. When set, the drivers are optimized for a 150Ω load.

9 Remote Loopback Read/Write 0 When set, data received from the link is looped back

at the MII and sent back out to the link. Received data will be presented on the MII pins. Transmit data at the MII will be ignored. Note:Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 57

8 PMD Loopback Read/Write 0 When set, the scrambled NRZI transmit data is con-

nected directly to the NRZI receive port on the descrambler. The loopback includes all of the 100BASE-TX functionality except for the MLT-3 encoding/decoding and the analog line-interface blocks. When clear, the CS8952 is configured for normal operation. Note:Setting Remote Loopback and PMD Loopback simultaneously will cause neither loopback mode to be entered, and should not be done.

7 Strip Preamble Read/Write 0 When set this bit causes the 7 bytes of MAC pream-

ble to be stripped off of incoming 100 Mb/s frames. The data received across the MII will begin with the 1 byte Start of Frame Delimiter (SFD). Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set.

6 Alternate FDX CRS Read/Write 0 This bit changes the behavior of the CRS pin only in

the full-duplex (FDX) mode of operation. When set, CRS will be asserted for transmit data only. When clear, CRS will be asserted only for receive data.

5 Loopback Transmit

Read/Write 1 This bit controls whether loopback data is transmitted onto the network. When set, any data transmitted during PMD or ENDEC loopback mode will NOT be transmitted onto the network. When clear, data will be transmitted on the TX+/- pins as well as looped back onto the MII pins.

4 Code Error Report

Read/Write 0 When set, this bit causes code errors to be reported by a value of 5h on RXD[3:0] and the assertion of RX_ER. When clear, this bit causes code errors to be reported by a value of 6h on RXD[3:0] and the asser- tion of RX_ER. This bit is superseded by the Code Error Report Enable bit.

3 Premature End

Read/Write 0 When set, this bit causes premature end errors to be reported by a value of 4h on RXD[3:0] and the asser- tion of RX_ER. When clear, this bit causes premature end errors to be reported by a value of 6h on RXD[3:0] and the assertion of RX_ER. A premature end error is caused by the detection of two IDLE symbols in the 100 Mb/s receive data stream prior to the End of Stream Delimiter. BIT NAME TYPE RESET DESCRIPTION

58 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

2L i n k E r r o r R e p o r t Enable Read/Write 0 When set, this bit causes link errors to be reported by a value of 3h on RXD[3:0] and the assertion of RX_ER. When clear, link errors are not reported across the MII.

1 Packet Error Report

Read/Write 0 When set, this bit causes packet errors to be reported by a value of 2h on RXD[3:0] and the asser- tion of RX_ER. When clear, packet errors are not reported across the MII.

0 Code Error Report

Read/Write 0 When set, code errors are reported and transmitted on RXD[3:0]. When clear, this bit enables the Code Error Report values on RXD[3:0] as selected by the Code Error Report Select bit and also causes the assertion of TX_ER to transmit a HALT code group. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit of the 10BASE-T Configuration Register (address 1Ch) is set. BIT NAME TYPE RESET DESCRIPTION

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 59

6.18 Self Status Register - Address 19h

Enable Status PAUSE FEFI Enable 76543210 Full Duplex 10BASE-T Mode CIM Status PHY Address BIT NAME TYPE RESET DESCRIPTION

15 Link OK Read Only 0 When set, this bit indicates that a valid link connec-

tion has been detected. The type of link established may be determined from bits 6, 7, and 9. When clear, this bit indicates that a valid link connection does not exist. This bit may be used to determine the current status of the link.

14 Power Down Read Only 1 When high, this bit indicates that the CS8952 is in a

low power state.

13 Receiving Data Read Only 0 This bit is high whenever the CS8952 is receiving

valid data. It is a direct copy of the state of the RX_DV pin accessible by software.

12 Descrambler Lock Read Only 0 When high, this bit indicates that the descrambler

has successfully locked to the scrambler seed of the far-end transmitter and is able to descramble received data.

11 Disable CRS on

Read/Write Reset to the logic inverse of the v a l u eo nt h e REPEATER pin. This bit controls the state of the CRS pin upon a descrambler time-out. When set, CRS will be forced low upon a descrambler time-out, and will not be released until the descrambler has re-acquired syn- chronization.

10 Auto-Neg Enable

Read Only If auto-negotiation is enabled via the AN[1:0] pins, reset to 1; otherwise, reset to 0. This bit reflects the value of bit 12 in the Basic Mode Control Register (address 00h). When set, it indi- cates that auto-negotiation has been enabled. When clear, this bit indicates that the mode of the CS8952 has been forced to that indicated by bits 6, and 7.

9 PAUSE Read Only 0 When set, this bit indicates that the Flow-Control

PAUSE function has been negotiated. This indicates that both the local device and the link partner have advertised this capability.

8 FEFI Enable Read/Write 0 This bit controls the Far-End Fault Generate and

Detect state machines. When this bit is set and auto- negotiation is disabled (bit 10 is clear), both state machines are enabled. When clear, this bit disables both state machines.

7 Full Duplex Read Only If a full duplex

via the AN[1:0] pins, reset to 1; otherwise, reset to When set, this bit indicates that the CS8952 has been configured for Full-Duplex operation. 6 10BASE-T Mode Read Only 0 When set, this bit indicates that the CS8952 has been configured for 10 Mb/s operation.

60 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

5 CIM Status Read Only 0 When clear, this bit indicates that a stable link con-

nection has been detected. When an unstable link is detected and the Carrier Integrity Monitor Disable bit in the PCS Sub-Layer Configuration Register (address 17h) is clear, this bit is set and latched. It will remain set until this register is read. 4:0 PHY Address Field Read/Write Reset to the val- ues on the PHYAD[4:0] pins. The value on pins PHYAD[4:0] are latched into this field at power-up or reset. These bits define the PHY address used by the management layer to address the PHY. The external logic must know this address in order to select this particular CS8952’s registers individually via the MDIO and MDC pins. BIT NAME TYPE RESET DESCRIPTION

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 61 6.19 10BASE-T Status Register - Address 1Bh 15 14 13 12 11 10 9 8 Reserved Polarity OK 10BASE-T Serial Reserved 76543210 Reserved BIT NAME TYPE RESET DESCRIPTION 15:11 Reserved Read Only 0 0000

10 Polarity OK Read Only 0 When high, the polarity of the receive signal (at the

RXD+/RXD- inputs) is correct. If clear, the polarity is reversed. If the Polarity Disable bit of 10BASE-T Configuration Register (address 1Ch) is clear, then the polarity is automatically corrected, if needed. The Polarity OK status bit shows the true state of the incoming polarity independent of the Polarity Disable bit. 9 10BASE-T Serial Read/Write Reset to the value on the 10BT_SER pin. When set, this bit selects 10BASE-T serial mode. When low, this bit selects 10BASE-T nibble mode. This bit will only affect the CS8952 if it has been con- figured for 10 Mb/s operation. 8:0 Reserved Read Only 0 0000 0000

62 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

6.20 10BASE-T Configuration Register - Address 1Ch 15 14 13 12 11 10 9 8 Reserved 76543210 National Compatibility Mode LED3 Blink Enable Enable LT/10 SQE Enable Reserved Low Rx Squelch Polarity Disable Jabber Enable BIT NAME TYPE RESET DESCRIPTION 15:8 Reserved Read Only 0000 0000

7 National Compati-

Read/Write 1 When set, registers and bits that are not compatible with the National DP83840 are disabled and writes to these registers are ignored.

6 LED3 Blink Enable Read/Write 0 When set, LED3

will blink during auto-negotiation and will indicate Link Good status upon completion of auto-negotiation. When clear, LED3 indicates Link Good status only. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit (bit 7) is set.

5 Enable LT/10 Read/Write 1 When set, this bit enables the transmission of link

pulses. When clear, link pulses are disabled and a good link condition is forced. If link pulses are disabled during

100 Mb/s operation with auto-negotiation enabled,

the CS8952 will go into 10 Mb/s mode. If operating in

100 Mb/s mode with no auto-negotiation, then clear-

i n gt h i sb i th a sn oe f f e c t .

4 SQE Enable Read/Write Reset to the logic

REPEATER pin. When set, and if the CS8952 is in half-duplex mode, this bit enables the 10BASE-T SQE function. When the part is in repeater mode, this bit is cleared and may not be set.

3 Reserved Read Only 1 This bit should be read as a don ’t care and, when

written, should be written to 1.

2 Low Rx Squelch Read/Write 0 When clear, the 10BASE-T receiver squelch thresh-

olds are set to levels defined by the ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approximately 6 dB. This is useful for operating with“quiet”cables that are longer than 100 meters.

1 Polarity Disable Read/Write 0 The 10BASE-T receiver automatically determines

the polarity of the received signal at the RXD+/RXD- input. When this bit is clear, the polarity is corrected, if necessary. When set, no effort is made to correct the polarity. Polarity correction will only be performed during 10BASE-T packet reception. Note:This bit is disabled, and writes to this bit are ignored when the National Compatibility Mode bit (bit 7) is set.

7.1 Twisted Pair Interface

Figure 6. Recommended Connection of Twisted-Pair Ports (Network Interface Card)

64 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

components should be placed close to the CS8952. ed if a fiber interface is not used.

7.3 Internal Voltage Reference

7.4 Clocking Schemes

Figure 7. Recommended Connection of Fiber Port

clock source supplied through the TX_CLK pin. have no vias, and run on the component side. selection for suitability in their specific design.

7.5 Recommended Magnetics

with transformers meeting these requirements. ics for suitability in their specific design.

7.6 Power Supply and Decoupling

all signal inputs should be referenced to +5.0V. all signal inputs should be referenced to +3.3 V. close to its corresponding power pin as possible. Connect ground pins directly to the ground plane. Figure 8. Biasing Resistor Connection and Layout

198 Van Vorst Street

12220 World Trade Drive

Table 7. Support Component Manufactures

66 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

7.7 General Layout Recommendations

The following PCB layout recommendations will help ensure reliable operation of the CS8952 and good EMC performance.  Use a multilayer Printed Circuit Board with at least one ground and one power plane. A typi- cal +5V MII application would be as follows: Layer 1: (top) Components and first choice sig- nal routing Layer 2: Ground Layer 3: Power (+5V) Layer 4: (bottom) Second choice signal rout- ing, bypass components Place transformer TI as close to the RJ45 connec- tor as possible with the secondary (network) side facing the RJ45 and the primary (chip) side facing the analog side (pins 76-100) of CS8952. Place t h eC S 8 9 5 2i nt u r na sc l o s et oT 1a sp o s sible.  Use the bottom layer for signal routing as a sec- ond choice. You may place all components on the top layer. However, bypass capacitors are optimally placed as close to the chip as possible and may be best located underneath the CS8952 on the bottom layer. Termination com- ponents at the RJ-45 and fiber transceiver may also be optimally placed on the bottom layer.  Connect a 0.1 µF bypass capacitor to each CS8952 VDD and VDD_MII pin. Place it as close to its corresponding power pin as possible and connect the other lead directly to the ground plane.  The 4.99K reference resistor should be placed as close to the RES pin as possible. Connect the other end of this resistor to the ground plane us- ing a via. Connect the adjacent VSS pins (pins 85 and 87) to the grounded end of the resistor forming a shield as illustrated in Figure8.  Controlled impedance is necessary for critical signals TX+/-, RX+/-, TX_NRZ+/-, and RX_NRZ+/-. These should be run as microstrip transmission lines (100Ω differential, 50Ω sin- gle-ended). The MII signals should be 68Ω mi- crostrip transmission lines. (For short MII signal paths one may standardize on a given trace width for all traces without significant degradation in signal integrity.)  Avoid routing traces other than the TX and RX signals under transformer T1 and the RJ45 con- nector. Signals may run on the bottom side un- derneath the CS8952 as long as they stay away from critical analog traces.  Connect all CS8952 ground and power pins di- rectly to the ground and power planes, respec- tively. Note: The VDD_MII power pins may need their own power plane or plane segment in +3.3 V MII applications.  Depending on the orientation and location of the transformer, the CS8952, and the RJ-45, and on whether the application is for a NIC or a s w i t c h ,t h eR Xa n dT Xp a i r sm a yn e e dt oc r o s s . This should be done by changing layers on a pair by pair basis only, using the minimum number of vias, and making sure that each trace within a pair “sees” the same path as its peer. Figure6 shows the CS8952 in a NIC or adapter configuration. It may be configured for a hub or repeater application by changing the wiring to the RJ-45 as shown in Table8.  Differential pair transmission lines should be routed close together (one trace width spacing edge-to-edge) and kept at least two trace widths away from other traces, components, etc. TX and RX pairs should be routed away from each other and may use opposite sides of the PCB as necessary, Each member of the differential pair should “see” the same PCB terrain as its peer.  Unused spaces on the signal layers should be filled with ground fill (pour). Vias should con- nect the ground patches to the ground plane. This is especially recommended (symmetrical-

ly) on both sides of the TX+/- traces.

1. This chassis plane should be separated from

2 KV capacitor or capacitors in order to mini-

Table 8. RJ-45 Wiring

68 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

1. PIN DESCRIPTIONS Pin Diagram VSS VDD VSS TX_NRZ- TX_NRZ+ RX_NRZ- RX_NRZ+ SIGNAL- SIGNAL+ VSS VDD VSS VSS RX_EN RESET REPEATER CLK25 VSS VDD VSS VDD_MII VSS 10BT_SER TEST0 TEST1 RSVD RSVD LED5 LED4 LED3 LED2 LED1 SPD10 SPD100 VDD_MII VSS PWRDN ISODEF BPSCR TXSLEW1 TXSLEW0 TCM AN1 AN0 BP4B5B VSS VDD VSS BPALIGN LPBK MII_IRQ MDIO MDC RXD3/PHYAD3 RXD2 RXD1/PHYAD1 RXD0 RX_DV/MII_DRV VDD_MII VSS RX_CLK RX_ER/RXD4/PHYAD4 TX_ER/TXD4 VSS VDD VSS TX_CLK TX_EN TXD0 TXD1 TXD2 TXD3 COL/PHYAD0 CRS/PHYAD2 LPSTRT VDD RSVD RSVD XTAL_O XTAL_I VSS VDD VSS RX- RX+ VSS VDD VDD VSS RES VSS RSVD VSS VDD TX- TX+ VDD VSS RSVD RSVD CS8952 100-pin TQFP (14 mm x 14 mm) 100

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 69 MII Interface Pins COL/PHYAD0 - Collision Detect/PHY Address 0. Input/Tri-State Output, Pin 48. Asserted active-high to indicate a collision on the medium during half-duplex operation. In full-duplex operation, COL is undefined and should be ignored. When configured for 10 Mb/s operation, COL is also used to indicate a Signal Quality Error (SQE) condition. At power-up or at reset, the logic value on this pin is latched into bit 0 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-up (> 150 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. CRS/PHYAD2 - Carrier Sense/PHY Address 2. Input/Tri-State Output, Pin 49. The operation of CRS is controlled by the REPEATER pin as follows: At power-up or at reset, the logic value of this pin is latched into bit 2 of the PHY Address Field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. MDC - Management Data Clock. Input, Pin 28. Input clock used to transfer serial data on MDIO. The maximum clock rate is 16.67 MHz. This clock may be asynchronous to RX_CLK and TX_CLK. MDIO - Management Data Input/Output. Bi-Directional, Pin 27. Bi-directional signal used to transfer management data between the CS8952 and the Ethernet controller. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the MDIO pin should have an external 1.5 KΩ pull-up resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external pull-up resistor may not be necessary. MII_IRQ - MII Interrupt. Open Drain Output, Pin 26. Asserted low to indicate the status corresponding to one of the unmasked interrupt status bits in the Interrupt Status Register (address 11h) has changed. It will remain low until the ISR is read, clearing all status bits. This open drain pin requires a 4.7 kΩ pull-up resistor. RX_CLK - Receive Clock. Tri-State Output, Pin 36 Continuous clock output used as a reference clock for sampling RXD[3:0], RX_ER, and RX_DV. RX_CLK will have the following nominal frequency: REPEATER pin DUPLEX mode CRS Indicates high don ’t care receive activity only low full duplex receive activity only low half duplex receive or transmit activity Speed 10BT_SER pin Nominal frequency

100 Mb/s n/a 25 MHz

10 Mb/s low (parallel) 2.5 MHz

10 Mb/s high (serial) 10 MHz

70 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_CLK pin should have an external 33Ω series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistor may not be necessary. RX_DV/MII_DRV - Receive Data Valid/MII Drive Strength. Input/Tri-State Output, Pin 33. Asserted high to indicate valid data nibbles are present on RXD[3:0]. At power-up or at reset, this pin is used as an input to determine the drive strength of the MII output drivers. When the pin is low, all MII output drivers will be standard 4 mA CMOS drivers. When high, additional drive strength will be added to the MII output drivers. This pin includes a weak internal pull- down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, this pin should be pulled high during power-up or reset and should have an external 33Ω series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, it may be possible to reduce overall power consumption by pulling the pin low at power-up or reset, and the external series resistor may not be necessary. RX_EN - Receive Enable. Input, Pin 14. When high, signals RXD[3:0], RX_CLK, RX_DV, and RX_ER are enabled. When low, these signals are tri-stated. RX_EN allows the received data signals of multiple PHY transceivers to share the same MII bus. This pin includes a weak internal pull-up (> 150 KΩ ), or the value may be set by an external 10 KΩ pull- up or pull-down resistor.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 71 RX_ER/PHYAD4/RXD4 - Receive Error/PHY Address 4/Receive Data 4. Input/Tri-State Output, Pin 37. During normal MII operation, this pin is defined as RX_ER (Receive Error). When RX_DV is high, RX_ER asserted high indicates that an error has been detected in the current receive frame. When RX_DV is low and RXD[3:0] =“1110”, RX_ER high indicates a False Carrier condition. If either BPALIGN or BP4B5B is asserted, then this pin is re-defined as RXD4 (Receive Data 4), the most-significant bit of the received five-bit code-group. If the 4B5B encoder is being bypassed, receive data is present when RX_DV is asserted. If alignment is being bypassed, data reception is continuous. At power-up or at reset, the logic value on this pin is latched into bit 4 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RX_ER pin should have an external 33Ω series resistor. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistor may not be necessary. RXD3/PHYAD3 - Receive Data 3/PHY Address 3. Tri-State Output, Pin 29. RXD2 - Receive Data 2. Tri-State Output, Pin 30. RXD1/PHYAD1 - Receive Data 1/PHY Address 1. Tri-State Output, Pin 31. RXD0 - Receive Data 0. Tri-State Output, Pin 32. Receive data output. Receive data is present when RX_DV is asserted. RXD0 is the least-significant bit. For MII modes, nibble-wide data (synchronous to RX_CLK) is transferred on pins RXD[3:0]. In 10 Mb/s serial mode, pin RXD0 is used as the serial output pin, and RXD[3:1] are ignored. When either BP4B5B or BPALIGN is selected, pin RXD4 contains the most-significant bit of the five-bit code-group. At power-up or at reset, the value on RXD1/PHYAD1 is latched into bit 1 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. At power-up or at reset, the logic value on RXD3/PHYAD3 is latched into bit 3 of the PHY Address field of the Self Status Register (address 19h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. In order to conform with Annex 22B of the IEEE 802.3u specification, the MII_DRV pin should be pulled high during power-up or reset, and the RXD[3:0] pins should have external 33Ω series resistors. For systems not required to drive external connectors and cables as described in the IEEE802.3u specification, the external series resistors may not be necessary. TX_CLK - Transmit Clock. Input/Tri-State Output, Pin 42. Continuous clock signal used by the CS8952 as a reference clock to sample TXD[3:0], TX_ER, and TX_EN. TX_CLK can be referenced either internally (Output Mode) or externally (Input Mode) based upon the value of the TCM pin at power-up or at reset. TCM pin TX_CLK mode CLK25 status high TX_CLK is input CLK25 pin is an output floating TX_CLK is input CLK25 is disabled low TX_CLK is output CLK25 is disabled

72 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

W h e nt h eT C Mp i ni sh i g ho np o w e r - u po rr e s e t ,t h eC L K 2 5p i nm a yb eu s e da sas o u r c ef o rt h e TX_CLK pin. When the TCM pin is floating on power-up or reset, TX_CLK must be supplied externally. TX_CLK should have the following nominal frequency: TX_EN - Transmit Enable. Input, Pin 43. Asserted high to indicate valid data nibbles are present on TXD[3:0]. When BPALIGN is selected, T X _ E Nm u s tb ep u l l e du pt oV D D _ M I I . TX_ER/TXD4 - Transmit Error Encoding/Transmit Data 4. Input, Pin 38. When high, TX_ER indicates to the CS8952 that a transmit error has occurred. If TX_ER is asserted simultaneously with TX_EN in 100 Mb/s mode, the CS8952 will ignore the data on the TXD[3:0] pins and transmit one or more 100 Mb/s HALT symbols in its place. In 10 Mb/s mode, TX_ER has no effect on the transmitted data. If BP4B5B or BPALIGN are set, TX_ER/TXD4 is used to transmit the most-significant bit of the five-bit code group. TXD[3:0] - Transmit Data. Input, Pins 47, 46, 45, and 44. Transmit data input pins. For MII modes, nibble-wide data (synchronous to TX_CLK) must be presented on pins TXD[3:0] when TX_EN is asserted high. TXD0 is the least significant bit. In 10 Mb/s serial mode, pin TXD0 is used as the serial input pin, and TXD[3:1] are ignored. When either BP4B5B or BPALIGN is selected, pin TXD4 contains the most significant bit of the five-bit code-group. Control and Status Pins 10BT_SER - 10 Mb/s Serial Mode Select. Input, Pin 23. When asserted high during power-up or reset and 10 Mb/s operation is selected, serial data will be transferred on pins RXD0 and TXD0. When low during power-up or reset and 10 Mb/s operation is selected, data is transferred a nibble at a time on RXD[3:0] and TXD[3:0]. This pin is ignored during 100 Mb/s operation.

10 Mb/s serial mode may also be entered under software control through bit 9 of the 10BASE-T Status

Register (address 1Bh). At power-up or at reset, the value on this pin is latched into bit 9 of the 10BASE-T Status Register (address 1Bh). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. AN[1:0] - Auto-Negotiate Control. Input, Pins 58 and 57. These three-level input pins are sampled during power-up or reset. They control the forced or advertised auto-negotiation operating modes. If one of these pins is left unconnected, internal logic pulls its signal to a mid-range value, 'M'. Speed 10BT_SER pin Nominal frequency 10 Mb/s low (parallel) 2.5 MHz AN1 pin AN0 pin Speed Forced/Auto Full/Half Duplex

0 M 10 Mb/s Forced Half

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 73 Auto-Negotiation may also be enabled and the advertised capabilities modified under software control through bit 8 of the Basic Mode Control Register (address 00h), and bits 5, 6, 7, 8, and 10 of the Auto- Negotiation Advertisement Register (address 04h). These pins are pulled to‘M ’ through weak internal resistors (> 150 KΩ ). Other values may be set by tying them directly to VDD_MII or VSS, or through external 10 KΩ pull-up or pull-down resistors.

1 M 10 Mb/s Forced Full

M M 100/10 Mb/s Auto-Neg Full/Half 0 0 10 Mb/s Auto-Neg Half 0 1 10 Mb/s Auto-Neg Full 1 0 100 Mb/s Auto-Neg Half 1 1 100 Mb/s Auto-Neg Full AN1 pin AN0 pin Speed Forced/Auto Full/Half Duplex

74 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

BP4B5B - Bypass 4B5B Coders. Input, Pin 56. When driven high during power-up or reset, the transmit 4B5B encoder and receiver 5B4B decoder are bypassed. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The 4B5B Coders may also be bypassed under software control through bit 14 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 14 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. BPALIGN - Bypass Symbol Alignment. Input, Pin 52. When driven high during power-up or reset, the following blocks are bypassed: 4B5B encoder, 5B4B decoder, scrambler, descrambler, NRZI encoder, and NRZI decoder. Five-bit code groups are output and input on pins RXD[4:0] and TXD[4:0]. The receiver will output five-bit data with no attempt to identify code-group boundaries; therefore, the data in one RXD[4:0] word may contain data from two code groups. Symbol alignment may also be bypassed under software control through bit 12 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 12 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. BPSCR - Bypass Scrambler. Input, Pin 62. When driven high during power-up or reset, the scrambler and descrambler is bypassed and NRZI FX mode is selected. The 100BASE-FX mode may also be entered under software control through bit 13 of the Loopback, Bypass, and Receiver Error Mask Register (address 18h). At power-up or at reset, the value on this pin is latched into bit 13 of the Loopback, Bypass and Receiver Error Mask Register (address 18h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor.

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 75 ISODEF - Isolate Default. Input, Pin 63. When asserted high during power-up or reset, the MII will power-up electrically isolated except for the MDIO and MDC pins. When low, the part will exit reset fully electrically connected to the MII. The MII may also be isolated under software control through bit 10 of the Basic Mode Control Register (address 00h). At power-up or at reset, the value on this pin is latched into bit 10 of the Basic Mode Control Register (address 00h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. LED1 - Transmit Active LED. Open Drain Output, Pin 69. This active-low output indicates transmit activity. It contains a pulse stretcher to insure that the transmit e v e n t sa r ev i s i b l ew h e nt h ep i ni su s e dt od r i v ea nL E D .T h ed e f i n i t i o no ft h i sp i nm a yb em o d i f i e dt o indicate Disconnect Detection (bit 5 of the Self Status Register (address 19h)) by setting bit 2 of the PCS Sub-layer Configuration Register (address 17h). This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED2 - Receive Activity LED. Open Drain Output, Pin 70. This active-low output indicates receive activity. It contains a pulse stretcher to insure that the receive events are visible when the pin is used to drive an LED. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED3 - Link Good LED. Open Drain Output, Pin 71. This active-low output indicates the CS8952 has detected a valid link. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED4 - Polarity/Full Duplex LED. Open Drain Output, Pin 72. This active-low output indicates: 1) for 100 Mb/s operation, the CS8952 is in full-duplex operation, 2) for 10 Mb/s operation, either good polarity exists or full duplex is selected (see bit 1 in the PCS Sub- layer Configuration Register (address 17h)). This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LED5 - Collision/Descrambler Lock LED. Open Drain Output, Pin 73. This active-low output is asserted when either the CS8952 detects a collision (bit 11 of the PCS Sub- Layer Configuration Register (address 17h) is clear), or the 100BASE-TX descrambler is synchronized (bit 11 of the PCS Sub-Layer Configuration Register (address 17h) is set). It contains a pulse stretcher to insure that the collision events are visible when the pin is used to drive an LED. This pin can be simultaneously connected to an LED and to a TTL-compatible, CMOS input pin. LPBK - Loopback Enable. Input, Pin 51. When this pin is asserted high and the CS8952 is operating in 100 Mb/s mode, the CS8952 will perform a local loopback inside the PMD block, routing the scrambled NRZI output to the NRZI input port on the descrambler. The loopback includes all CS8952 100 Mb/s functionality except the MLT-3 coders and the analog line interface blocks. When asserted high and the CS8952 is operating in 10 Mb/s mode, the CS8952 will perform a local ENDEC loopback.

76 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

LPSTRT - Low Power Start. Input, Pin 50. When this active-low input is asserted during power-up or reset, the CS8952 will exit reset in a low power configuration, where the only circuitry enabled is that necessary to maintain the media impedance. The CS8952 will remain in a low power state until RESET pin is asserted or the MDC pin toggles. This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. PWRDN - Power Down. Input, Pin 64. When this pin is asserted high, the CS8952 powers down all circuitry except that circuitry needed to maintain the network line impedance. This is the lowest power mode possible. The CS8952 will remain in low power mode until the PWRDN pin is deasserted. A slightly higher power power-down mode may also be entered under software control through bit 11 of the Basic Mode Control Register (address 00h).

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 77 REPEATER - REPEATER Mode Select. Input, Pin 16. This pin controls the operation of the CRS (Carrier Sense) pin as shown below: At power-up or at reset, the value on this pin is latched into bit 12 of the PCS Sub-Layer Configuration Register (address 17h). This pin includes a weak internal pull-down (> 20 KΩ ), or the value may be set by an external 4.7 KΩ pull-up or pull-down resistor. SPD10 - 10 Mb/s Speed Indication. Output, Pin 68. This pin is asserted high when the CS8952 is configured for 10 Mb/s operation. This pin can be used to drive a low-current LED to indicate 10 Mb/s operation. SPD100 - 100 Mb/s Speed Indication. Output, Pin 67. This pin is asserted high when the CS8952 is configured for 100 Mb/s operation. This pin can be used to drive a low-current LED to indicate 100 Mb/s operation. TCM - Transmit Clock Mode Initialization. Input, Pin 59. The logic value on this three-level pin during power-up or reset determines whether TX_CLK is used as an input or an output, and whether an external 25 MHz clock reference is provided on the CLK25 output pin. TEST[1:0] - Factory Test. Input, Pins 24 and 25. These pins are for factory test only. They include weak internal pull-downs (> 20 KΩ ), and should be tied directly to VSS for normal operation. REPEATER pin DUPLEX mode CRS Indicates high don ’t care receive activity only low full duplex receive activity only low half duplex receive or transmit activity TCM pin TX_CLK mode CLK25 status high TX_CLK is input CLK25 pin is an output floating TX_CLK is input CLK25 is disabled low TX_CLK is output CLK25 is disabled

78 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

TXSLEW[1:0] - Transmit Slew Rate Control. Input, Pins 61 and 60. These three-level pins allow adjustment to the rise and fall times of the 10BASE-TX transmitter output waveform. The rise and fall times are symmetric. Media Interface Pins RX+, RX- - 10/100 Receive. Differential Input Pair, Pins 91 and 92. Differential input pair receives 10 or 100 Mb/s data from the receive port of the transformer primary. TX+, TX- - 10/100 Transmit. Differential Output Pair, Pins 80 and 81. Differential output pair drives 10 or 100 Mb/s data to the transmit port of the transformer primary. RX_NRZ+, RX_NRZ- - FX Receive. Differential Input Pair, Pins 6 and 7. PECL output pair receives 100 Mb/s NRZI-encoded data from an external optical module. SIGNAL+, SIGNAL- - Signal Detect. Differential Input Pair, Pins 9 and 8. PECL input pair receives signal detection indication from an external optical module. TX_NRZ+, TX_NRZ- - FX Transmit. Differential Output Pair, Pins 5 and 4. PECL output pair drives 100 Mb/s NRZI-encoded data to an external optical module. General Pins C L K 2 5-2 5M H zC l o c k .O u t p u t ,P i n1 7 . A 25 MHz Clock is output on this pin when the CS8952 is configured to use an external reference transmit clock in TX_CLK IN MASTER mode. See the pin description for the Transmit Clock Mode Initialization pin (TCM) for more information on TX_CLK operating modes. CLK25 may also be enabled regardless of the TCM pin state by clearing bit 7 of the PCS Sub-layer Configuration Register (address 17h). RES - Reference Resistor. Input, Pin 86. This input should be connected to ground with a 4.99 kΩ +/-1% series resistor. The resistor is needed for the biasing of internal analog circuits. TXSLEW0 pin TXSLEW1 mode Rise/Fall time low low 0.5 ns low floating 1.0 ns low high 1.5 ns floating low 2.0 ns floating floating 2.5 ns floating high 3.0 ns high low 3.5 ns high floating 4.0 ns high high 4.5 ns

CrystalLAN™ 100BASE-X and 10BASE-T Transceiver 79 RESET - Reset. Input, Pin 15. This active high input initializes the CS8952, and causes the CS8952 to latch the input signal on the following pins: COL/PHYAD0, CRS/PHYAD2, RX_ER/PHYAD4/RXD4, 10BT_SER, BP4B5B, BPALIGN, BPSCR, ISODEF, REPEATER, RXD[1]/PHYAD1, and RXD[3]/PHYAD3. XTAL_I - Crystal Input, Pin 96. XTAL_O - Crystal Output, Pin 97. A 25 MHz crystal should be connected across pins XTAL_I and XTAL_O. If a crystal is not used, a 25 MHz CMOS level clock may be connected to XTAL_I and XTAL_O left open. NOTE: The XTAL_I pin capacitive load may be as high as 35pF . Any external clock source connected to this pin must be capable of driving larger capacitive loads. RSVD - Reserved. Pins 74, 75, 76, 77, 84, 98, and 99. These seven pins are reserved and should be tied to VSS. VDD_MII - MII Power. Pins 21, 34, and 66. These pins provide power to the CS8952 MII interface. Typically VDD_MII will be either +5V or +3.3V. VDD - Core Power. Pins 2, 11, 19, 40, 54, 79, 82, 88, 89, 94, and 100. These pins provide power to the CS8952 core. Typically, VDD should be +5V. VSS - Ground. Pins 1, 3, 10, 12, 13, 18, 20, 22, 35, 39, 41, 53, 55, 65, 78, 83, 85, 87, 90, 93, and 95. These pins provide a ground reference for the CS8952.

80 CrystalLAN ™ 100BASE-X and 10BASE-T Transceiver

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A1 0.002 0.006 0.05 0.15 B 0.007 0.011 0.17 0.27 D 0.618 0.642 15.70 16.30 D1 0.547 0.555 13.90 14.10 E 0.618 0.642 15.70 16.30 E1 0.547 0.555 13.90 14.10 e* 0.016 0.024 0.40 0.60 L 0.018 0.030 0.45 0.75 * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 100L TQFP PACKAGE DRAWING E D1D e L B A

• Notes