CS8900A-IQ3Z

CS8900A_07 CIRRUS | Alldatasheet

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Technical content

Copyright © Cirrus Logic, Inc. 2007 (All Rights Reserved) CS8900A Product Data Sheet Crystal LAN™ Ethernet Controller

FEATURES

z Single-Chip IEEE 802.3 Ethernet Controller with Direct ISA-Bus Interface z Maximum Current Consumption = 55 mA (5V Supply) z 3V o r 5V O p e r a t i o n z Industrial Temperature Range z Comprehensive Suite of Software Drivers Available z Efficient PacketPage™ Architecture Operates in I/O and Memory Space, and as DMA Slave z Full Duplex Operation z On-Chip RAM Buffers Transmit and Receive Frames z 10BASE-T Port with Analog Filters, Provides: - Automatic Polarity Detection and Correction z AUI Port for 10BASE2, 10BASE5 and 10BASE-F z Programmable Transmit Features: - Automatic Re-transmission on Collision - Automatic Padding and CRC Generation z Programmable Receive Features: - Stream Transfer™ for Reduced CPU Overhead - Auto-Switch Between DMA and On-Chip Memory - Early Interrupts for Frame Pre-Processing - Automatic Rejection of Erroneous Packets z EEPROM Support for Jumperless Configuration z Boot PROM Support for Diskless Systems z Boundary Scan and Loopback Test z LED Drivers for Link Status and LAN Activity z Standby and Suspend Sleep Modes

DESCRIPTION

The CS8900A is a low-cost Ethernet LAN Controller op- timized for the Industry Standard Architecture (ISA) bus and general purpose microcontroller busses. Its highly- integrated design eliminates the need for costly external components required by other Ethernet controllers. The CS8900A includes on-chip RAM, 10BASE-T transmit and receive filters, and a di rect ISA-Bus interface with 24 mA Drivers. In addition to high integration, the CS8900A offers a broad range of performance features and configuration- options. Its unique PacketPage architecture automatically adapts to changing network traffic pat- terns and available system resources. The result is increased system efficiency. The CS8900A is available in a 100-pin LQFP package ideally suited for small form-factor, cost-sensitive Ether- net applications. With the CS8900A, system engineers can design a complete Ethernet circuit that occupies less than 1.5 square inches (10 sq. cm) of board space.

ORDERING INFORMATION

CS8900A-CQ 0° to 70° C 5V LQFP-100 CS8900A-CQZ 0° to 70° C 5V LQFP-100 Lead free CS8900A-IQ -40° to 85° C 5V LQFP-100 CS8900A-IQZ -40° to 85° C 5V LQFP-100 Lead free CS8900A-CQ3 0° to 70° C 3.3V LQFP-100 CS8900A-CQ3Z 0° to 70° C 3.3V LQFP-100 Lead free CS8900A-IQ3 -40° to 85° C 3.3V LQFP-100 CS8900A-IQ3Z -40° to 85° C 3.3V LQFP-100 Lead free CRD8900A-1 Evaluation Kit EEPROM RJ-45 10BASE-T Attachment Unit Interface (AUI)

20 MHz

802.3 MAC Engine EEPROM Control Encoder/ Decoder PLL 10BASE-T RX Filters & Receiver 10BASE-T TX Filters & Transmitter AUI Transmitter AUI Collision AUI Receiver Clock Power Manager Boundary Scan Test Logic LED Control CS8900A ISA Ethernet Controller Host Host Bus DS271F4 AUG ‘07

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET TABLE OF CONTENTS

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

Table 1. Revision History Page 1: Changed package option from TQFP to LQFP. F4 August 2007 Added industrial te mperature range Pb-free devices. For all product questions and inquiries contact a Cirrus Logic Sales Representative. or for creating any work for resale. ARISE IN CONNECTION WITH THESE USES. be trademarks or service marks of their respective owners. I2C is a registered trademark of Philips Semiconductor.

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

1.0 INTRODUCTION

1.1 General Description

The CS8900A is a true single-chip, full-duplex, Ethernet solution, incorporating all of the ana- log and digital circuitry needed for a complete Ethernet circuit. Majo r functional blocks in- clude: a direct ISA-bu s interface; an 802.3 MAC engine; integrated buffer memory; a seri- al EEPROM interface; and a complete analog front end with both 10BASE-T and AUI.

1.1.1 General Purpose and ISA-Bus Inter-

Included in the CS8900A is a direct ISA-bus in- terface with full 24 mA drive capability. Its con- figuration options incl ude a choice of four interrupts and three DMA channels (one of each selected during initialization). In Memory Mode, it supports Sta ndard or Ready Bus cy- cles without introducing additional wait states. The bus can be configured to support many microcontroller and microcomputer busses.

1.1.2 Integrated Memory

The CS8900A incorporates a 4-Kbyte page of on-chip memory, elim inating the cost and board area associated wi th external memory chips. Unlike most othe r Ethernet controllers, the CS8900A buffers entire transmit and re- ceive frames on chip, eliminating the need for complex, inefficient memory management schemes. In addition, the CS8900A operates in either Memory space, I/O space, or with ex- ternal DMA controller s, providing maximum design flexibility. 1.1.3 802.3 Ethernet MAC Engine The CS8900A’s Ethernet Media Access Con- trol (MAC) engine is full y compliant with the IEEE 802.3 Ethernet standard (ISO/IEC 8802- 3, 1993), and supports full-duplex operation. It handles all aspects of Ethernet frame trans- mission and reception, including: collision de- tection, preamble gener ation and detection, and CRC generation and te st. Programmable MAC features include automatic retransmis- sion on collision, and automatic padding of transmitted frames.

1.1.4 EEPROM Interface

The CS8900A provides a simple and efficient serial EEPROM interface that allows configu- ration information to be stored in an optional EEPROM, and then loaded automatically at power-up. This eliminat es the need for costly and cumbersome switches and jumpers.

1.1.5 Complete Analog Front End

The CS8900A’s analog front end incorporates a Manchester encoder/decoder, clock recov- ery circuit, 10BASE-T transceiver, and com- plete Attachment Unit Interface (AUI). It provides manual and automatic selection of ei- ther 10BASE-T or AUI, and offers three on- chip LED drivers for link status, bus status, and Ethernet line activity. The 10BASE-T transceiv er includes drivers, receivers, and analog fi lters, allowing direct connection to low-cost isolation transformers. It supports 100, 120, and 150 Ω shielded and unshielded cables, extended cable lengths, and automatic receive polarity reversal detec- tion and correction. The AUI port provides a direct interface to 10BASE-2, 10BASE-5 and 10BASE-FL net- works, and is capable of driving a full 50-meter AUI cable.

1.2 System Applications

The CS8900A is designed to work well in ei- ther motherboard or adapter applications.

1.2.1 Motherboard LANs

The CS8900A requires the minimum number of external components needed for a full Ethernet node. Its small-footprint package and

• An EEPROM can be used to store node- specific information, such as the Ethernet Individual Address and node configuration.
• The 20 MHz crystal oscillator may be re- placed by a 20 MHz clock signal.

1.2.2 Ethernet Adapter Cards

• A Boot PROM can be added to support diskless applications.
• The 10BASE-T transmitter and receiver impedance can be adjusted to support 100, 120, or 150 Ohm twisted pair cables.
• An external Latchable-Address-bus de- code circuit can be added to operate the CS8900A in Upper-Memory space. RJ-45 10BASE-TCS8900A I S A EEPROM 20 MHz XTAL (2.0 sq. in.)

Figure 1. Complete Ethernet Motherboard Solution Figure 2. Full-Featured ISA Adapter Solution

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

• On-chip LED ports can be used for either optional LEDs, or as programmable out- puts.

1.3 Key Features and Benefits

1.3.1 Very Low Cost

The CS8900A is designed to provide the low- est-cost Ethernet solution available for embed- ded applications, portable motherboards, non- ISA bus systems and adapter cards. Cost-sav- ing features include:

• Integrated RAM elimi nates the need for ex- pensive external memory chips.
• On-chip 10BASE-T filters allow designers to use simple isolation transformers in- stead of more costly filter/transformer packages.
• The serial EEPROM por t, used for configu- ration and initialization, eliminates the need for expensive switches and jumpers.
• The CS8900A is designed to be used on a 2-layer circuit board instead of a more ex- pensive multilayer board.
• The 8900A-based solution offers the small- est footprint avail able, saving valuable printed circuit board area.
• A set of certified software drivers is avail- able at no charge, eliminating the need for costly software development.

1.3.2 High Performance

The CS8900A is a full 16-bit Ethernet control- ler designed to provide optimal system perfor- mance by minimizing time on the ISA bus and CPU overhead per frame. It offers equal or su- perior performance for less money when com- pared to other Ethernet controllers. The CS8900A’s PacketPage architecture allows software to select whichever access method is best suited to each particular CPU/ISA-bus configuration. When co mpared to older I/O- space designs, PacketPage is faster, simpler and more efficient. To boost performance further, the CS8900A includes several key f eatures that increase throughput and lower CPU overhead, includ- ing:

• StreamTransfer cuts up to 87% of inter- rupts to the host CPU during large block transfers.
• Auto-Switch DMA allows the CS8900A to maximize throughput while minimizing missed frames.
• Early interrupts allow the host to prepro- cess incoming frames.
• On-chip buffering of full frames cuts the amount of host bandwidth needed to man- age Ethernet traffic.

1.3.3 Low Power and Low Noise

For low power needs, the CS8900A offers three power-down options: Hardware Stand- by, Hardware Suspend, and Software Sus- pend. In Standby mode, the chip is powered down with the excepti on of the 10BASE-T re- ceiver, which is enabled to listen for link activ- ity. In either Hardwa re or Software Suspend mode, the receiver is disabled and power con- sumption drops to the micro-ampere range. In addition, the CS 8900A has been designed for very low noise emi ssion, thus shortening the time required for EMI testing and qualifica- tion.

1.3.4 Complete Support

The CS8900A comes with a suite of software drivers for immediate us e with most industry standard network operating systems. In addi- tion, complete evaluation kits and manufactur- ing packages are available, significantly reducing the cost and time required to produce new Ethernet products.

2 SLEEP TEST RES

10 BASE T

Figure 3. Typical ISA Bus Connection Diagram

5 Volt 3 Volt

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

2.0 PIN DESCRIPTION

(Q) Top View

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET ISA Bus Interface SA[0:19] - System Address Bus, Input PINS 37-48, 50-54, 58-60. Lower 20 bits of the 24-bit System Addr ess Bus used to decode accesses to CS8900A I/O and Memory space, and attached Boot PROM. SA0- SA15 are used for I/O Read and Write operations. SA0-SA19 are used in conj unction with external decode logic for Memory Read and Wr ite operations. SD[0:15] - System Data Bus, Bi-Directional with 3-State Output PINS 65-68, 71-74, 27- 24, 21-18. Bi-directional 16-bit System Data Bus us ed to transfer data bet ween the CS8900A and the host. RESET - Reset, Input PIN 75. Active-high asynchronous input used to reset the CS8900A. Must be stable for at least 400 ns before the CS8900A recognize s the signal as a valid reset. AEN - Address Enable, Input PIN 63. When TEST is high, this active-h igh input indicates to the CS8900A that the system DMA controller has control of the ISA bus. When AEN is high, the CS8900A will not perform slave I/O spac e operations. When TEST is low, this pin becomes the shift clock input for the Boundary Scan Test. AE N should be inactive when performing an IO or memory access and it s hould be active during a DMA cycle. MEMR - Memory Read, Input PIN 29. Active-low input indicates that the host is execut ing a Memory Read operation. MEMW - Memory Write, Input PIN 28. Active-low input indicates that the host is executin g a Memory Write operation. MEMCS16 - Memory Chip Select 16-bi t, Open Drain Output PIN 34. Open-drain, active-low outpu t generated by the CS8900A when it recognizes an address on the ISA bus that corresponds to its assi gned Memory space (CS8900A must be in Memory Mode with the MemoryE bit (Register 17, BusC TL, Bit A) set for MEMCS16 to go active). 3- Stated when not active. REFRESH - Refresh, Input PIN 49. Active-low input indicates to the CS8900A that a DRAM refresh cycle is in progress. When REFRESH is low, MEMR , MEMW , IOR , IOW , DMACK0 , DMACK1 , and DMACK2 are ignored. IOR - I/O Read, Input PIN 61. When IOR is low and a valid addr ess is detected, the CS 8900A outputs the contents of the selected 16-bit I/O register onto the System Data Bus. IOR is ignored if REFRESH is low.

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET IOW - I/O Write, Input PIN 62. When IOW is low and a valid addre ss is detected, the CS8900A writes the data on the System Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low. IOCS16 - I/O Chip Select 16-bit, Open Drain Output PIN 33. Open-drain, active-low outpu t generated by the CS8900A when it recognizes an address on the ISA bus that corresponds to its assigned I/O space. 3-Stated when not active. IOCHRDY - I/O Channel Ready, Open Drain Output PIN 64. When driven low, this open-drain, active -high output extends I/O Read and Memory Read cycles to the CS8900A. Th is output is functional w hen the IOCHRDYE bit in the Bus Control register (Register 17) is clea r. This pin is alwa ys 3-Stated when the IOCHRDYE bit is set. SBHE - System Bus High Enable, Input PIN 36. Active-low input indicates a data transfer on the high byte of the System Data Bus (SD8-SD15). After a hardware or a software reset, the CS8900A will be in 8-bit mode. Provide a HIGH to LO W and then LOW to HIGH transition on the SBHE signal before any 16-bit IO or memory access is done to the CS8900A. INTRQ[0:3] - Interrupt Requ est, 3-State PINS 30-32, 35. Active-high output indicates the presence of an interrupt event. Interrupt Request goes low once the Interrupt Status Queue (ISQ) is read as all 0's. Only one Interrupt Request output is used (one is selected during conf iguration). All non-selected Interrupt Request outputs are placed in a high-impedance state. (Section 3.2 on page 18 and Section 5.1 on page 78.) DMARQ[0:2] - DMA Request, 3-State PINS 11, 13, and 15. Active-high, 3-Stateable output used by the CS8900A to request a DMA transfer. Only one DMA Request out put is used ( one is selected during configuration). All non- selected DMA Request outputs are pl aced in a high-impedance state. DMACK[0:2] - DMA Acknowledge, Input PINS 12, 14, and 16. Active-low input indicates acknowledgment by the host of the corresponding DMA Request output. CHIPSEL - Chip Select , Input PIN 7. Active-low input generated by external Latchable Addr ess bus decode logic when a valid memory address is present on the ISA bus. If Memory Mode operation is not needed, CHIPSEL should be tied low. The CHIPSEL is ignored for IO and DMA mode of the CS8900A. EEPROM and Boot PROM Interface EESK - EEPROM Seri al Clock, PIN 4. Serial clock used to clock dat a into or out of the EEPROM.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET EECS - EEPROM Chip Select, PIN 3. Active-high output used to select the EEPROM. EEDataIn - EEPROM Data In, Input Internal Weak Pullup PIN 6. Serial input used to receiv e data from the EEPRO M. Connects to th e DO pin on the EEPROM. EEDataIn is also used to sense the presence of the EEPROM. ELCS - External Logic Chip Sel ect, Internal Weak Pullup PIN 2. Bi-directional signal used to configure exte rnal Latchable Address (LA) decode logic. If external LA decode logi c is not needed, ELCS should be tied low. EEDataOut - EEPROM Data Out, PIN 5. Serial output used to send data to the EEPROM. Connects to the DI pin on the EEPROM. When TEST is low, this pin becomes the output for the Boundary Scan Test. CSOUT - Chip Select for External Boot PROM, PIN 17. Active-low output used to select an exte rnal Boot PROM w hen the CS8900A decodes a valid Boot PROM memory address. 10BASE-T Interface TXD+/TXD- - 10BASE-T Transmit, Differential Output Pair PINS 87 and 88. Differential output pair drives 10 Mb/s Manchester-encoded data to the 10BASE-T transmit pair. RXD+/RXD- - 10BASE-T Recei ve, Differential Input Pair PINS 91 and 92. Differential input pair receives 10 Mb/s Manchester-encoded data from the 10BASE-T receive pair. Attachment Unit Interface (AUI) DO+/DO- - AUI Data Out, Differenti al Output Pair PINS 83 and 84. Differential output pair drives 10 Mb/s Manchester-encoded data to the AUI transmit pair. DI+/DI- - AUI Data In, Differentia l Input Pair PI NS 79 and 80. Differential input pair rece ives 10 Mb/s Manchester-enc oded data from t he AUI receive pair. CI+/CI- - AUI Collision In, Differ ential Input Pair PINS 81 and 82. Differential input pair connects to the AUI collision pair. A co llision is indicated by the presence of a 10 MHz ± 15% signal with duty cycl e no worse than 60/40.

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET General Pins XTAL[1:2] - Crystal, Input/Output PINS 97 and 98. A 20 MHz crystal should be connected across these pins. If a crystal is not used, a 20 MHz signal should be conn ected to XTAL1 an d XTAL2 should be left open. (See Section 7.3 on page 112 and Section 7.7 on page 122.) SLEEP - Hardware Sleep, Input Internal Weak Pullup PIN 77. Active-low input used to enable the tw o hardware sleep modes: Hardware Suspend and Hardware Standby. (See Section 3.7 on page 27.) LINKLED or HC0 - Link Good LED or Ho st Controlled Output 0, Open Drain Output PIN 99. When the HCE0 bit of t he Self Control regist er (Register 15) is clear, this active-low output is low when the CS8900A detects the presence of valid link pulses. When the HC0E bit is set, the host may drive this pin low by se tting the HCBO in the Self Control register. BSTATUS or HC1 - Bus Status or Host Controlled Output 1, Open Drain Output PIN 78. When the HC1E bit of t he Self Control regist er (Register 15) is clear, this active-low output is low when receive activity caus es an ISA bus access. When the HC1E bit is set, the host may driv e this pin low by setti ng the HCB1 in the Se lf Control register. LANLED - LAN Activity LED, Op en Drain Output PIN 100. During normal operation, this active-low output goes low fo r 6 ms whenever there is a receive packet, a transm it packet, or a collision. Duri ng Hardware St andby mode, this output is driven low w hen the receiver detects network activity. TEST - Test Enable, Input In ternal Weak Pullup PIN 76. Active-low input used to put the CS8900A in Boundary Scan Test mode. For normal operation, this pin should be high. RES - Reference Resistor, Input PIN 93. This input should be connected to a 4.99K Ω ± 1% resistor needed for biasing of internal analog circuits. DVDD[1:4] - Digital Power, Power PINS 9, 22, 56, and 69. Provides 5 V ± 5% power to the digital circ uits of the CS8900A. DVSS[1:4} and DVSS1A, DVSS3A - Digital Groun d, Ground PINS 8, 10, 23, 55, 57, and 70. Provides ground reference (0 V) to t he digital circuits of the CS8900A. AVDD[1:3] - Analog Power, Power PINS 90, 85, and 95. Provides 5 V ± 5% power to t he analog circuits of the CS8900A. AVSS[0:4] - Analog Ground, Gr ound PINS 1, 89, 86, 94, 96. Provide ground reference (0 V) to t he analog circuits of the CS8900A.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview

During normal operation, the CS8900A per- forms two basic functions: Ethernet packet transmission and recepti on. Before transmis- sion or reception is possible, the CS8900A must be configured.

3.1.1 Configuration

The CS8900A must be configured for packet transmission and reception at power-up or re- set. Various parameters must be written into its internal Configuration and Control registers such as Memory Base Address; Ethernet Physical Address; what frame types to re- ceive; and which media interface to use. Con- figuration data can eit her be written to the CS8900A by the host (across the ISA bus), or loaded automatically from an external EE- PROM. Operation can begin after configura- tion is complete. Section 3.3 on page 19 and Section 3.4 on page 21 describe the configuration process in detail. Section 4.4 on page 49 provides a de- tailed description of the bits in the Configura- tion and Control Registers.

3.1.2 Packet Transmission

Packet transmission occurs in two phases. In the first phase, the hos t moves the Ethernet frame into the CS8900A’s buffer memory. The first phase begins with the host issuing a Transmit Command. This informs the CS8900A that a frame is to be transmitted and tells the chip when to start transmission (i.e. af- ter 5, 381, 1021 or a ll bytes have been trans- ferred) and how the frame should be sent (i.e. with or without CRC , with or with out pad bits, etc.). The Host follows the Transmit Command with the Transmit Length, indicating how much buffer space is required. When buffer space is available, the host wr ites the Ethernet frame into the CS8900A’s internal memory, either as a Memory or I/O space operation. In the second phase of transmission, the CS8900A converts the frame into an Ethernet packet then transmits it onto the network. The second phase begins with the CS8900A trans- mitting the preamble a nd Start-of-Frame de- limiter as soon as the proper number of bytes has been transferred into its transmit buffer (5, 381, 1021 bytes or full frame, depending on configuration). The pr eamble and Start-of- Frame delimiter are followed by the Destina- tion Address, Source Address, Length field and LLC data (all supplied by the host). If the frame is less than 64 bytes, including CRC, the CS8900A adds pad bits if configured to do so. Finally, the CS8900A appends the proper 32- bit CRC value. The Section 5.6 on page 99 provides a de- tailed description of packet transmission.

3.1.3 Packet Reception

Like packet transmission, packet reception oc- curs in two phases. In the first phase, the CS8900A receives an Ethernet packet and stores it in on-chip memory. The first phase of packet reception begins with the receive frame passing through the analog front end and Manchester decoder w here Manchester data is converted to NRZ data. Next, the preamble and Start-of-Frame delim iter are stripped off and the receive frame is sent through the ad- dress filter. If the frame’s Destination Address matches the criteria pr ogrammed into the ad- dress filter, the packet is stored in the CS8900A’s internal memory. The CS8900A then checks the CRC, and depending on the configuration, informs the processor that a frame has been received. In the second phase, the host transfers the re- ceive frame across the ISA bus and into host memory. Receive frames can be transferred

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ations, or as DMA operations using host DMA. scription of packet reception.

3.2 ISA Bus Interface

added external “glue logic”. I/O space, or as a DMA slave.

3.2.1 Memory Mode Operation

Write operations by driving the MEMW pin low. Mode, see Section 4.9 on page 73.

3.2.2 I/O Mode Operation

I/O locations in the host system’s I/O space. CS8900A and is always enabled. for a Write, IOW must be low.

3.2.3 Interrupt Request Signals

four of the ISA bus In terrupt Request signals. pins are placed in a high-impedance state. page 78 for a description of the ISQ).

3.2.4 DMA Signals

Table 2. Interrupt Assignments

three 16-bit DMA channel s of the ISA bus. when connecting these pins to the ISA bus.

3.3 Reset and Initialization

3.3.1 Reset

3.3.1.1 External Reset, or ISA Reset

3.3.1.2 Power-Up Reset

3.3.1.3 Power-Down Reset

3.3.1.4 EEPROM Reset

3.3.1.5 Software Initiated Reset

SET bit (Register 15, SelfCTL, Bit 6) is set.

3.3.1.6 Hardware (HW) Standby or Suspend

3.3.1.7 Software (SW) Suspend

Table 3. DMA Assignments

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3.3.2 Allowing Time for Reset Operation

After a reset, the CS8900A goes through a self configuration. This includes calibrating on-chip analog circuitry, and reading EEPROM for va- lidity and configuration. Time required for the reset calibration is ty pically 10 ms. Software drivers should not access registers internal to the CS8900A during this time. When calibra- tion is done, bit INITD in the Self Status Regis- ter (register 16) is set indicating that initialization is complete, and the SIBUSY bit in the same register is cleared indicating the EE- PROM is no longer being read or pro- grammed.

3.3.3 Bus Reset Considerations

After reset, the CS8900A packet page pointer register (IObase+0Ah) is set to 3000h. The 3000h value can be us ed as part of the CS8900A signature when the system scans for the CS8900A. See Section 4.10 on page 75. After a reset, the ISA bus outputs INTRx and DMARQx are 3-Stated, thus avoiding any in- terrupt or DMA channel conflicts on the ISA bus at power-up time.

3.3.4 Initialization

After each reset (except EEPROM Reset), the CS8900A checks the sense of the EEDataIn pin to see if an external EEPROM is present. If EEDI is high, an EEPROM is present and the CS8900A automatically loads the configura- tion data stored in the EEPROM into its inter- nal registers (see next section). If EEDI is low, an EEPROM is not present and the CS8900A comes out of reset with the default configura- tion shown in Table 4. A low-cost serial EEPROM can be used to store configuration information that is automat- ically loaded into the CS8900A after each re- set (except EEPROM reset). The use of an EEPROM is optional. The CS8900A operates with any of six stan- dard EEPROM’s shown in Table 5.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

3.4 Configurations with EEPROM

3.4.1 EEPROM Interface

The interface to the EEPROM consists of the four signals shown in Table 6.

3.4.2 EEPROM Memory Organization

If an EEPROM is used to store initial configu- ration information for the CS8900A, the EE- PROM is organized in one or more blocks of 16-bit words. The first block in EEPROM, re- ferred to as the Configuration Block, is used to configure the CS8900A af ter reset. An exam- ple of a typical Configuration Block is shown in Table 7. Additional blocks containing user data

3.4.3 Reset Configuration Block

address 7Fh, depending on EEPROM size.

Contents

0020h 0300h I/O Base Address* 0022h XXXX XXXX XXXX X100 Interrupt Number 0024h XXXX XXXX XXXX XX11 DMA Channel 0026h 0000h DMA Start of Frame Offset 0028h X000h DMA Frame Count 002Ah 0000h DMA Byte Count 002Ch XXX0 0000h Memory Base Address 0030h XXX0 0000h Boot PROM Base Address 0034h XXX0 0000h Boot PROM Address Mask 0102h 0003h Register 3 - RxCFG 0104h 0005h Register 5 - RxCTL 0106h 0007h Register 7 - TxCFG 0108h 0009h Register 9 - TxCMD 010Ah 000Bh Register B - BufCFG 010Ch Undefined Reserved 010Eh Undefined Reserved 0110h Undefined Reserved 0112h 00013h Register 13 - LineCTL 0114h 0015h Register 15 - SelfCTL 0116h 0017h Register 17 - BusCTL 0118h 0019h Register 19 - TestCTL * I/O base address is unaffected by Software Suspend mode. Table 4. Default Configuration Table 5. Supported EEPROM Types Table 6. EEPROM Interface

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3.4.3.1 Reset Configuration Block Structure

3.4.3.2 Reset Configuration Block Header

00h A120h Configuration Block Header. 01h 2020h Group Header for first group of words. Three words to be loaded, beginning at 0020h in PacketPage memory. 05h 502Ch Group Header for second group of words. Six words to be loaded, beginning at 002Ch in PacketPage memory. 0Ch 2158h Group Header for third group of words. Three words to be loaded, beginning at 0158 in PacketPage memory. vides a pad to the word boundary.

• FFFFh is a special code indicating that there are no more words in the EEPROM.

Table 7. EEPROM Configuration Block Example

3.4.3.3 Determining the EEPROM Type

3.4.3.4 Checking EEPROM for presence of

3.4.3.5 Determining Nu mber of Bytes in the

3.4.4 Groups of Configuration Data

3.4.4.1 Group Header

Figure 4. Group Header

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Bits 8 through 0 of the Group Header specify a 9-bit PacketPage Addre ss. This address de- fines the PacketPage register that will be load- ed with the first word of configuration data from the group. Bits B though 9 of the Group Head- er are forced to 0, rest ricting the destination address range to the firs t 512 bytes of Pack- etPage memory. Figure 4 shows the format of the Group header.

3.4.5 Reset Configuration Block Check-

A checksum is stored in the high byte position of the word immediat ely following the last group of data in the Reset Configuration Block. (The EEPROM address of the checksum val- ue can be determined by dividing the value stored in the Link Byte by two). The checksum value is the 2’s complement of the 8-bit sum (any carry out of eighth bit is ignored) of all the bytes in the Reset Conf iguration Block, ex- cluding the checksum byte. This sum includes the Reset Configurati on Block header at ad- dress 00h. Since the checksum is calculated as the 2’s complement of the sum of all pre- ceding bytes in the Reset Configuration Block, a total of 0 should re sult when the checksum value is added to the sum of the previous bytes.

3.4.6 EEPROM Example

Table 7 shows an example of a Reset Config- uration Block stored in a C46 EEPROM. Note that little-endian word ordering is used, i.e., the least significant word of a multiword datum is located at the lowest address.

3.4.7 EEPROM Read-out

If the EEDI pin is a sserted high at the end of reset, the CS8900A reads the first word of EE- PROM data by: 1) Asserting EECS 2) Clocking out a Read- Register-00h com- mand on EEDO (EESK provides a 1MHz serial clock signal) 3) Clocking the data in on EEDI. If the EEDI pin is low at the end of the reset sig- nal, the CS8900A does no t perform an EE- PROM read-out (uses its default configuration).

3.4.7.1 Determining EEPROM Size

The CS8900A determines the size of the EE- PROM by checking the sense of EEDI on the tenth rising edge of EESK. If EEDI is low, the EEPROM is a ’C46 or ’CS46. If EEDI is high, the EEPROM is a ’C56, ’CS56, ’C66, or ’CS66.

3.4.7.2 Loading Configuration Data

The CS8900A reads in the first word from the EEPROM to determine if configuration data is contained in the EEPR OM. If configuration data is not stored in the EEPROM, the CS8900A terminates init ialization from EE- PROM and operates using its default configu- ration (See Table 4). If configuration data is stored in EEPROM, the CS8900A automati- cally loads all configurat ion data stored in the Reset Configuration Block into its internal PacketPage registers.

3.4.8 EEPROM Read-out Completion

Once all the configuration data are transferred to the appropriate Packe tPage registers, the CS8900A performs a checksum calculation to verify the Reset Configuration Blocks data are valid. If the resulting to tal is 0, the read-out is considered valid. Otherwise, the CS8900A ini- tiates a partial reset to restore the default con- figuration. If the read-out is va lid, the EEPROMOK bit (Register 16, SelfST, bit A) is set. EE- PROMOK is cleared if a checksum error is de- tected. In this case, the CS8900A performs a partial reset and is restored to its default. Once

3.5 Programming the EEPROM

3.5.1 EEPROM Commands

Write-All. They are described in Table 8.

3.5.2 EEPROM Command Execution

Figure 5. EEPROM Command Register Format [A] ELSEL External Logic Select: When clear, th e EECS pin is used to select the EEPROM. When set, the ELCS pin is used to select the external LA decode circuit. [9:8] OP1, OP0 Opcode: Indicates what comma nd is being executed (see next section). [7:0] AD7 to AD0 EEPROM Address: Address of EEPROM word being accessed. Table 8. EEPROM Commands

26 DS271F4

the host must wait again for SIBUSY to clear.

3.5.3 Enabling Access to the EEPROM

or erase any EEPROM memory location. wanted modification of the EEPROM.

3.5.4 Writing and Erasing the EEPROM

1) Issue an Erase/Wr ite Enable command. 4) Issue an Erase/Wr ite Disable command. writes FFh to the specified EEPROM location. writes FFh to all locations.

3.6 Boot PROM Operation

3.6.1 Accessing the Boot PROM

the data out onto the ISA bus.

3.6.2 Configuring the CS8900A for Boot

connected to the Boot PROM and ’245 driver. Mask are ignored and should be 000h. Figure 6. Boot PROM Connection Diagram

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET and the Address Mask is FC000h. This config- uration describes a 16-Kbyte (128 Kbit) PROM mapped into host me mory from D0000h to D3FFFh.

3.7 Low-Power Modes

For power-sensitive applications, the CS8900A supports thre e low-power modes: Hardware Standby, Hardware Suspend, and Software Suspend. All three low-power modes are controlled throug h the SelfCTL register (Register 15). See also Section 4.4.4 on page 51. An internal reset occurs when the CS8900A comes out of any suspend or standby mode. After a reset (internal or external), the CS8900A goes through a self configuration. This includes calibrat ing on-chip analog cir- cuitry, and reading EEPROM for validity and configuration. When the calibration is done, bit InitD in Register 16 (Self Status register) is set indicating that initiali zation is complete, and the SIBUSY bit in the same register is cleared (indicating that the EEPROM is no longer be- ing read or programmed. Time required for the reset calibration is ty pically 10 ms. Software drivers should not access registers internal to CS8900A during this time.

3.7.1 Hardware Standby

Hardware (HW) Standby is designed for use in systems, such as port able PC’s, that may be temporarily disconnected from the 10BASE-T cable. It allows the system to conserve power while the LAN is not in use, and then automat- ically restore Ethernet operation once the ca- ble is reconnected. In HW Standby mode, all analog and digital cir- cuitry in the CS8900A is turned off, except for the 10BASE-T receiver which remains active to listen for link activity. If link activity is detect- ed, the LANLED pin is driven low, providing an indication to the host that the network connec- tion is active. The host can then activate the CS8900A by deasserting the SLEEP pin. Dur- ing this mode, all ISA bus accesses are ig- nored. To enter HW Standby mode, the SLEEP pin must be low and the HWSleepE bit (Register 15, SelfCTL, Bit 9) and the HWStandbyE bit (Register 15, SelfCTL, Bit A) must be set. When the CS8900A enters HW Standby, all registers and circuits ar e reset except for the SelfCTL register. Upon exit from HW Standby, the CS8900A performs a complete reset, and then goes through normal initialization.

3.7.2 Hardware Suspend

During Hardware Suspend mode, the CS8900A uses the least amount of current of the three low-power modes. All internal circuits are turned off and the CS8900A’s core is elec- tronically isolated from the rest of the system. Accesses from the ISA bus and Ethernet activ- ity are both ignored. HW Suspend mode is entered by driving the SLEEP pin low and setti ng the HWSleepE bit (Register 15, SelfCTL, bit 9) while the HW- StandbyE bit (Register 15 , SelfCTL, bit A) is clear. To exit from this mode, the SLEEP pin must be driven high. U pon exit, the CS8900A performs a complete reset, and then goes through a normal initialization procedure.

3.7.3 Software Suspend

Software (SW) Suspend mode can be used to conserve power in appl ications, like adapter cards, that do not ha ve power management circuitry available. During this mode, all inter- nal circuits are shut off except the I/O Base Ad- dress register (PacketPage base + 0020h) and the SelfCTL register (Register 15). To enter SW Suspend mode, the host must set the SWSuspend bit (Register 15, SelfCTL, bit

28 DS271F4

a normal initialization procedure. Notes: 1. Both HW and HW Suspend take precedence over SW Suspend. Table 9. Low-Power Mode Operation

3.8 LED Outputs

can be used to control LEDs or external logic.

3.8.1 LANLED

a pulse lasting a minimum of 6 ms).

3.8.2 LINKLED or HC0

ble 10 summarizes this operation.

3.8.3 BSTATUS or HC1

(Register 15, SelfCTL, Bit D) must be clear.

3.8.4 LED Connection

3.9 Media Access Control

3.9.1 Overview

10 Pin configured as HC0:

11 Pin configured as HC0:

Table 10. LINKLED/HC0 Pin Operation

10 Pin configured as HC1

11 Pin configured as HC1:

Table 11. BSTATUS/HCI Pin Operation Figure 7. LED Connection Diagram

30 DS271F4

and, media access management.

3.9.2 Frame Encapsulation and Decapsu-

and receive frames are of legal minimum size.

3.9.2.1 Transmission

hibitCRC bit (Register 9, TxCMD, bit C). Figure 9 shows the Ethernet frame format.

3.9.2.2 Reception

Figure 8. MAC Interface Figure 9. Ethernet Frame Format

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET tire packet has been received, the MAC vali- dates the FCS. If an er ror is detected, the CRCerror bit (Register 4, RxEvent, Bit C) is set.

3.9.2.3 Enforcing Minimum Frame Size

The MAC provides minimum frame size en- forcement of both tr ansmit and receive pack- ets. When the TxPadD is bit (Register 9, TxCMD, Bit D) is clear, transmit frames will be padded with ad- ditional bits to ensure that the receiving station receives a legal fram e (64 bytes, including CRC). When TxPadDis is set, the CS8900A will not add pad bits and will transmit frames less that 64 bytes. If a frame is received that is less than 64 bytes (inc luding CRC), the Runt bit (Register 4, RxEvent, Bit D) will be set indi- cating the arrival of an illegal frame.

3.9.3 Transmit Error Detection and Han-

The MAC engine monitors Ethernet activity and reports and recovers from a number of er- ror conditions. For trans mission, the MAC re- ports the following er rors in the TxEvent register (Register 8) and BufEvent register (Register C):

3.9.3.1 Loss of Carrier

Whenever the CS8900A is transmitting on the AUI port, it expects to see its own transmission “looped back” to its receiver. If it is unable to monitor its transmission after the end of the preamble, the MAC reports a loss-of-carrier error by setting the Loss-of-CRS bit (Register 8, TxEvent, Bit 6). If the Loss-of-CRSiE bit (Register 7, TxCFG, Bit 6) is set, the host will be interrupted.

3.9.3.2 SQE Error

After the end of transmission on the AUI port, the MAC expects to see a collision within 64 bit times. If no collision is detected, the SQEerror bit (Register 8, TxEvent, Bit 7) is set. If the SQEerroriE bit is set (R egister 7, TxCFG, Bit 7), the host is interrupted. An SQE error may indicate a fault on the AUI cable or a faulty transceiver (it is assu med that the attached transceiver supports this function).

3.9.3.3 Out-of-Window (Late) Collision

If a collision is detecte d after the first 512 bits have been transmitted, the MAC reports a late collision by setting the Out-of-window bit (Reg- ister 8, TxEvent, Bit 9). The MAC then forces a bad CRC and terminates the transmission. If the Out-of-windowiE bi t (Register 7, TxCFG, Bit 9) is set, the host is interrupted. A late col- lision may indicate an illegal network configu- ration.

3.9.3.4 Jabber Error

If a transmission conti nues longer than about 26 ms, the MAC disables the transmitter and sets the Jabber bit (Register 8, TxEvent, Bit A). The output of the transmitter returns to idle and remains there until th e host issues a new Transmit Command. If the JabberiE bit (Regis- ter 7, TxCFG, Bit A) is set, the host is interrupt- ed. A Jabber condition indicates that there may be something wro ng with the CS8900A transmit function. To prevent possible network faults, the host should cl ear the transmit buff- er. Possible options include: Reset the chip with eit her software or hard- ware reset (see Section 3.3 on page 19). Issue a Force Transmit Command by setting the Force bit (Register 9, TxCMD, bit 8). Issue a Transmit Command with the TxLength field set to zero.

3.9.3.5 Transmit Collision

The MAC counts the number of times an indi- vidual packet must be retransmitted due to

32 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET network collisions. T he collision count is stored in bits B through E of the TxEvent reg- ister (Register 8). If the packet collides 16 times, transmission of that packet is terminat- ed and the 16coll bit (Register 8, TxEvent, Bit F) is set. If the 16colliE bit (Register 7, TxCFG, Bit F) is set, the host will be interrupted on the 16th collision. A running count of transmit col- lisions is recorded in the TxCOL register.

3.9.3.6 Transmit Underrun

If the CS8900A starts transmission of a packet but runs out of data before reaching the end of frame, the TxUnderrun bi t (Register C, BufE- vent, Bit 9) is set. The MAC then forces a bad CRC and terminates t he transmission. If the TxUnderruniE bit (Regist er B, BufCFG, Bit 9) is set, the host is interrupted.

3.9.4 Receive Error Detection and Han-

The following receive errors are reported in the RxEvent register (Register 4):

3.9.4.1 CRC Error

If a frame is receiv ed with a bad CRC, the CRCerror bit (Register 4, RxEvent, Bit C) is set. If the CRCerrorA bit (Register 5, RxCTL, Bit C) is set, the fr ame will be buffered by CS8900A. If the CRCerroriE bit (Register 3, RxCFG. Bit C) is set, the host is interrupted.

3.9.4.2 Runt Frame

If a frame is received t hat is shorter than 64 bytes, the Runt bit (Register 4, RxEvent, Bit D) is set. If the RuntA bit (Register 5, RxCTL, Bit D) is set, the frame will still be buffered by CS8900A. If the RuntiE bit (Register 3, Rx- CFG. Bit D) is set, the host is interrupted.

3.9.4.3 Extra Data

If a frame is received th at is longer than 1518 bytes, the Extradata bit (Register 4, RxEvent, Bit E) is set. If the Ex tradataA bit (Register 5, RxCTL, Bit E) is set, the first 1518 bytes of the frame will still be buff ered by CS8900A. If the ExtradataiE bit (Register 3, RxCFG. Bit E) is set, the host is interrupted.

3.9.4.4 Dribble Bits and Alignment Error

Under normal operating conditions, the MAC may detect up to 7 additional bits after the last full byte of a receive packet. These bits, known as dribble bits, are ignor ed. If dribble bits are detected, the Dribblebit bit (Register 4, Rx- Event, Bit 7) is set. If both the Dribblebits bit and CRCerror bit (Register 4, RxEvent, Bit C) are set at the same ti me, an alignment error has occurred.

3.9.5 Media Access Management

The Ethernet network topology is a single shared medium with several attached stations. The Ethernet protocol is designed to allow each station equal acce ss to the network at any given time. Any node can attempt to gain access to the network by first completing a de- ferral process (described below) after the last network activity, and then transmitting a pack- et that will be received by all other stations. If two nodes transmit simultaneously, a collision occurs and the colliding packets are corrupted. Two primary tasks of the MAC are to avoid net- work collisions, and then recover from them when they occur. In addition, when the CS8900A is using the AUI, the MAC must sup- port the SQE Test func tion described in sec- tion 7.2.4.6 of the Ethernet standard.

3.9.5.1 Collision Avoidance

The MAC continually moni tors network traffic by checking for the presence of carrier activity (carrier activity is indicated by the assertion of the internal Carrier Sense signal generated by the ENDEC). If carrier activity is detected, the network is assumed busy and the MAC must wait until the current pa cket is finished before

3.9.5.2 Two-Part Deferral

shortened due to a tem porary loss of carrier.

3.9.5.3 Simple Deferral

started whenever Carrier Sense is deasserted. agrams the simple deferral process. Figure 10. Two-Part Deferral

34 DS271F4

3.9.5.4 Collision Resolution

3.9.5.5 Normal Collisions

3.9.5.6 Late Collisions

3.9.5.7 Backoff

3.9.5.8 Standard Backoff

Figure 11. Simple Deferral

n is the number of retransmission attempts.

3.9.5.9 Modified Backoff

IPG time before starting transmission.

3.9.5.10 SQE Test

0.6 to 1.6 µs after t he end of transmission. section for more information).

3.10 Encoder/Decoder (ENDEC)

3.10.1 Encoder

Figure 12. ENDEC

36 DS271F4

tal are described in Section 7.7 on page 122.

3.10.2 Carrier Detection

0101b for 10BASE-T, and 1b or 0b for AUI).

3.10.3 Clock and Data Recovery

3.10.4 Interface Selection

12 describes the possible configurations.

3.10.4.2 AUI Only

3.10.4.3 Auto-Select

1 N/A AUI Only

01 A u t o - S e l e c t

Table 12. Interface Selection

3.11.2 Transmitter

3.11.3 Receiver

and correction circuit, and link pulse detector.

3.11.3.1 Squelch Circuit

ceive filter are tested by the squelch circuit. Figure 13. 10BASE-T Transceiver

38 DS271F4

depending on polarity) is rejected.

3.11.3.2 Extended Range

(Register 13, LineCTL, Bit E).

3.11.4 Link Pulse Detection

dependent of the link segment.

3.11.5 Receive Polarity Detection and Cor-

ity of the receive half of the twisted pair cable. Frame (EOF) sequence of incoming packets. Figure 14. Link Pulse Transmission

correction of the reversal is ignored.

3.11.6 Collision Detection

3.12 Attachment Unit Interface (AUI)

3.12.1 AUI Transmitter

of-CRS bit (Register 8, TxEvent, Bit 6) is set.

3.12.2 AUI Receiver

noise pulses and inco ming Ethernet packets. tion, while unwanted noise is rejected.

3.12.3 Collision Detection

10 MHz ± 15% signal with a duty cycle no

asserting the internal Collision signal. Figure 15. AUI

40 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

3.13 External Clock Oscillator

A 20-MHz quartz crystal or CMOS clock input is required by the CS8900A. If a CMOS clock input is used, it should be connected the to XTAL1 pin, with the XTAL2 pin left open. The clock signal should be 20 MHz ±0.01% with a duty cycle between 40% and 60%. The speci- fications for the crystal are described in Section 7.7 on page 122.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.0 PACKETPAGE ARCHITECTURE

4.1 PacketPage Overview

The CS8900A architecture is based on a unique, highly-efficien t method of accessing internal registers and buffer memory known as PacketPage. PacketPage provides a unified way of controlling the CS8900A in Memory or I/O space that mini mizes CPU overhead and simplifies software. It provides a flexible set of performance features and configuration op- tions, allowing designers to develop Ethernet circuits that meet th eir particular system re- quirements.

4.1.1 Integrated Memory

Central to the CS8900A architecture is a 4- Kbyte page of integrated RAM known as Pack- etPage memory. PacketPage memory is used for temporary storage of transmit and receive frames, and for internal registers. Access to this memory is done directly, through Memory space operations (Section 4.9 on page 73), or indirectly, through I/O space operations (Section 4.10 on page 75). In most cases, Memory Mode will provide the best overall per- formance, because IS A Memory operations require fewer cycles than I/O operations. I/O Mode is the CS8900A’s default configuration and is used when memory space is not avail- able or when special operations are required (e.g. waking the CS8900A from the Software Suspend State requires the host to write to the CS8900A’s assigned I/O space). The user-accessible por tion of PacketPage memory is organized into the following six sec- tions:

4.1.2 Bus Interface Registers

The Bus Interface registers are used to config- ure the CS8900A’s ISA-bus interface and to map the CS8900A into the host system’s I/O and Memory space. Most of these registers are written only during initialization, remaining unchanged while the CS8 900A is in normal operating mode. The exceptions to this are the DMA registers which are modified continually whenever the CS8900A is using DMA. These registers are described in more detail in Section 4.3 on page 44.

4.1.3 Status and Control Registers

The Status and Control registers are the pri- mary means of controlling and getting status of the CS8900A. They are described in more de- tail in Section 4.4 on page 49.

4.1.4 Initiate Transmit Registers

The TxCMD/TxLength registers are used to initiate Ethernet fram e transmission. These registers are described in more detail in Section 4.5 on page 69. (See Section 5.6 on page 99 for a description of frame transmis- sion.)

4.1.5 Address Filter Registers

The Filter registers st ore the Individual Ad- dress filter and Logical Address filter used by the Destination Address (DA) filter. These reg- isters are described in more detail in Section 4.6 on page 71. For a description of the DA filter, see Section 5.2.10 on page 87.

4.1.6 Receive and Transmit Frame Loca-

The Receive and Transmit Frame PacketPage locations are used to transfer Ethernet frames PacketPage Address 0000h - 0045h Bus Interface Registers 0100h - 013Fh Status and Control Registers 0140h - 014Fh Initiate Transmit Registers 0150h - 015Dh Address Filter Registers 0400h Receive Frame Location 0A00h Transmit Frame Location PacketPage Address

42 DS271F4

sible. See Section 4.7 on page 72.

4.2 PacketPage Memory Map

Notes: 1. All registers are accessed as words only.

1. Read operation from the reserved location provides undefined data. Writing to a reserved location or

undefined bits may result in unpredictable operation of the CS8900A. Table 13. PacketPage Memory Address Map

Notes: 1. All registers are accessed as words only.

1. Read operation from the reserved location provides undefined data. Writing to a reserved location or

undefined bits may result in unpredictable operation of the CS8900A. Table 13. PacketPage Memory Address Map (continued)

44 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.3 Bus Interface Registers

4.3.1 Product Identification Code

(Read only, Address: PacketPage base + 0000h) The Product Identification Code Register is located in the first four bytes of the PacketPage (0000h to 0003h). The register contains a unique 32-bit product ID code that identifies the chip as a CS8900A. The host can use this num- ber to determine which software driver to load and to check which features are available. Reset value is: 0000 1110 0110 0011 0000 0000 000X XXXX The X XXXX codes for the CS8900A are: Rev B: 0 0111 Rev C: 0 1000 Rev D: 0 1001 Rev F: 0 1010

4.3.2 I/O Base Address

(Read/Write, Address: PacketPage base + 0020h) The I/O Base Address Register describes the base address for the sixteen contiguous locations in the host system's I/O space, which are used to access the PacketPage registers. See Section 4.10 on page 75. The default location is 0300h. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0011 0000 0000

4.3.3 Interrupt Number

(Read/Write, Address: PacketPage base + 0022h) The Interrupt Number Register defines the interrupt pin selected by the CS8900A. In a typical application the follow- Address 0000h Address 0001h Address 0002h Address 00003h First byte of EISA registration number for Crystal Semiconductor Second byte of EISA registration number for Crystal Semiconductor First 8 bits of Product ID number Last 3 bits of the Product ID number (5 “X” bits are the revision number) Address 0021h Address 0020h Most significant byte of I/O Base Address Least significant byte of I/O Base Address Address 0023h Address 0022h 00h Interrupt number assignment: 0000 0000b= pin INTRQ0 0000 0001b= pin INTRQ1 0000 0010b= pin INTRQ2 0000 0011b= pin INTRQ3 0000 01XXb= All INTRQ pins high-impedance

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET ing bus signals are tied to the following pins: See Section 3.2 on page 18. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state, which corre- sponds to placing all the INTRQ pins in a high-impedance state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX X100

4.3.4 DMA Channel Number

(Read/Write, Address: PacketPage base + 0024h) The DMA Channel register defines the DMA pins selected by the CS8900A. In the typical application, the following bus signals are tied to the following pins: See Section 3.2 on page 18 and Section 5.3 on page 90. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state which corre- sponds to setting all DMRQ pins to high-impedance. If a EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX XX11

4.3.5 DMA Start of Frame

(Read only, Address: PacketPage base + 0026h) The DMA Start of Frame Register contains a 16-bit value which defines the offset from the DMA base address to the start of the most recently transferred received frame. See Section 5.3 on page 90. Bus signal Typical pin connection IRQ5 INTRQ3 IRQ10 INTRQ0 IRQ11 INTRQ1 IRQ12 INTRQ2 Address 0025h Address 0024h 00h DMA channel assignment: 0000 0000b= pin DMRQ0 and DMACK0 0000 0001b= pin DMRQ1 and DMACK1 0000 0010b= pin DMRQ2 and DMACK2 0000 0011b= All DMRQ pins high-impedance Bus signal Typical pin connection DRQ5 DACK5 DMRQ0 DMACK0 DRQ6 DACK6 DMRQ1 DMACK1 DRQ7 DACK7 DMRQ2 DMACK2 Address 0027h Address 0026h Most significant byte of offset value Least significant byte of offset value

46 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Reset value is: 0000 0000 0000 0000

4.3.6 DMA Frame Count

(Read only, Address: PacketPage base + 0028h) The lower 12 bits of the DMA Frame Count register define the number of valid frames transferred via DMA since the last readout of this register. The upper 4 bits are reserved. See Section 5.3 on page 90. Reset value is: XXXX 0000 0000 0000

4.3.7 RxDMA Byte Count

(Read only, Address: PacketPage base + 002Ah) The RxDMA Byte Count register describes the valid number of bytes DMAed since the last readout. See Section 5.3 on page 90. Reset value is: 0000 0000 0000 0000

4.3.8 Memory Base Address

(Read/Write, Address: PacketPage base + 002Ch) Memory Base Address: The lower three bytes (002Ch, 002Dh, and 002Eh) are used for the 20-bit memory base address. The upper three nibbles are reserved. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000

4.3.9 Boot PROM Base Address

(Read/Write, Address: PacketPage base + 0030h) Address 0029h Address 0028h Most significant byte of frame count (most-significant nibble always 0h) Least significant byte of frame count Address 002Bh Address 002Ah Most significant byte of byte count Least significant byte of byte count Address 002Fh Address 002Eh Address 002Dh Address 002Ch Reserved The most significant nibble of memory base address. The high-order nibble is reserved. Contains portion of memory base address. The least significant byte of the memory base address. Address 0033h Address 0032h Address 0031h Address 0030h Reserved The most significant nibble of Boot PROM base address. The high-order nibble is reserved. Contains portion of Boot PROM base address. The least significant byte of the Boot PROM base address.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET The lower three bytes (0030h, 0031h, and 0032h) of the Boot PROM Base Address register are used for the 20-bit Boot PROM base address. The upper three nibbles are reserved. See Section 3.6 on page 26. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000

4.3.10 Boot PROM Address Mask

(Read/Write, Address: PacketPage base + 0034h) The Boot PROM address mask register indicates the size of the attached Boot PROM and is limited to 4K bit incre- ments. The lower 12 bits of the Address Mask are ignored, and should be 000h. The next lowest-order bits describe the size of the PROM. The upper three nibbles are reserved. For example: See Section 3.6 on page 26. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000

4.3.11 EEPROM Command

(Read/Write, Address: PacketPage base + 0040h) This register is used to control the reading, writing and erasing of the EEPROM. See Section 3.5. ADD7-ADD0 Address of the EEPR OM word being accessed. OB1,OB0 Indicates the Opcode of the command being executed. See Table 8. ELSEL External logic select: When clear, the EECS pin is used to select the EEPROM. When set, the ELCS pin is used to select the external LA decode circuit. Reserved Reserved and must be written as 0. Address 0037h Address 0036h Address 0035h Address 0034h Reserved The most significant nibble of Boot PROM mask address. The high-order nibble is reserved. Contains portion of Boot PROM mask address. The lower-order nibble must be written as 0h. The least significant byte of the Boot PROM mask address. Must be written as 00h. Size of Boot PROM Register value 4k bits XXXX XXXX XXXX 1111 1111 0000 0000 0000 8k bits XXXX XXXX XXXX 1111 1110 0000 0000 0000 16k bits XXXX XXXX XXXX 1111 1100 0000 0000 0000 76543210 ADD7 to ADD0 FEDCBA9 8 Reserved ELSEL OB1 OB0

48 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Reset value is: XXXX XXXX XXXX XXXX

4.3.12 EEPROM Data

(Read/Write, Address: PacketPage base + 0042h) This register contains the word being written to, or read from, the EEPROM. See Section 3.5 on page 25. Reset value is: XXXX XXXX XXXX XXXX

4.3.13 Receive Frame Byte Counter

(Read only, Address: PacketPage base + 0050h) This register contains the count of the total number bytes received in the current received frame. This count contin- uously increments as more bytes in this frame are received. See Section 5.2.9 on page 86. Reset value is: XXXX XXXX XXXX XXXX Address 0043h Address 0042h Most significant byte of the EEPROM data. Least significant byte of the EEPROM data. Address 0051h Address 0050h Most significant byte of the byte count. Least significant byte of the byte count.

4.4 Status and Control Registers

tion/Control and Status/Event bits.

4.4.1 Configuration and Control Registers

• how frames will be transmitted and re- ceived;
• which frames will be transmitted and re- ceived;
• which events will cause interrupts to the host processor; and,
• how the Ethernet physi cal interface will be configured. These registers are r ead/write and are desig- nated by odd numbers (e.g. Register 1, Regis- ter 3, etc.). The Transmit Command Register (TxCMD) is a special type of regist er. It appears in two separate locations in the PacketPage memory map. The first locati on, PacketPage base + 0108h, is within the block of Configura- tion/Control Registers and is read-only. The second location, PacketPage base + 0144h, is where the actual tran smit commands are is- sued and is write-only . See Section 4.4.4 on page 51 (Register 9) and Section 5.6 on page 99 for a more detailed description of the TxCMD register.

4.4.2 Status and Event Registers

found in Section 5.1 on page 78.

10 Register Bits

Figure 16. Status and Control Register Format

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4.4.3 Status and Control Bit Definitions

detailed description of the bits in each register.

4.4.3.1 Act-Once Bits

take a certain action only once when set. 6), and SWint-X (Register B, BufCFG, Bit 6).

4.4.3.2 Temporal Bits

Rx128 are cleared when read by the host.

4.4.3.3 Interrupt Enable Bits and Events

terrupt to the host processor. are cleared upon read-out by the host. CMD Read/Write Command: Written once per frame to initiate transmit. events will cause interrupts. cal interface will be configured. Read-only Counters: Counts missed receive frames and collisions. Provides time domain for locating coax cable faults. Table 14. PacketPage Register Types

4.4.3.4 Accept Bits

receive frame is set to zero).

4.4.4 Status and Control Register Sum-

Table 15. Interrupt Enable Bits and Events

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Table 16. Status and Control Register Descriptions

4.4.5 Register 0: Interrupt Status Queue

Table 16. Status and Control Register Descriptions (continued)

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET RegNum The lower six bits describe which register (4, 8, C, 10 or 12) is contained in the ISQ. RegContent The upper ten bits cont ain the register data contents. Reset value is: 0000 0000 0000 0000

4.4.6 Register 3: Receiver Configuration

(RxCFG, Read/Write, Address: PacketPage base + 0102h) RxCFG determines how frames will be transferred to the host and what frame types will cause interrupts.

000011 These bits provide an internal address used by the CS8900A to identify this as the Receiver

Configuration Register. Skip_1 When set, this bit causes t he last committed received frame to be deleted from the receive buff- er. To skip another frame, the host must rewrite a “1” to this bit. This bit is not to be used if StreamE When set, StreamTransfer mode is used to transfer receive frames that are back-to-back and that pass the Destination Address filter (see Section 5.2.10 on page 87). When StreamE is clear, StreamTransfer mode is not used. This bit must not be set unless either bit AutoRxDMA or bit RXDMAonly is set. RxOKiE When set, there is an RxOK Interrupt if a frame is received without errors. RxOK interrupt is not generated when DMA mode is used for frame reception. RxDMAonly The Receive-DMA mode is used for all receive frames when this bit is set. AutoRxDMAE When set, the CS8900A will automatically switch to Receive-DMA mode if the conditions spec- ified in Section 5.4 on page 94 are met. RxDMAonly (Bit 9) has precedence over AutoRxD- MAE. BufferCRC When set, the received CRC is included with the data stored in the receive-frame buffer, and the four CRC bytes are included in the receive-frame length (PacketPage base + 0402h). When clear, neither the receive buffer nor the receive length include the CRC. CRCerroriE When set, there is a CRCerror Inte rrupt if a frame is received with a bad CRC. RuntiE When set, there is a Runt Interrupt if a fram e is received that is shorter than 64 bytes. The CS8900A always discards any frame that is shorter than 8 bytes. ExtradataiE When set, there is an Extradata Interrupt if a frame is received that is longer than 1518 bytes. The operation of this bit is independent of the received packet integrity (good or bad CRC). After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0000 0011 76543210 StreamE Skip_1 000011 FEDCBA9 8 ExtradataiE RuntiE CRCerroriE BufferCRC AutoRx DMAE RxDMA only RxOKiE

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.7 Register 4: Receiver Event

(RxEvent, Read-only, Address: PacketPage base + 0124h) Alternate meaning if bits 8 and 9 are both set (see Section 5.2.10 on page 87 for exception regarding Broadcast frames). RxEvent reports the status of the current received frame. 000100 These bits identify this as the Receiver Event Register. When reading this register, these bits will be 000100, where the LSB corresponds to Bit 0. IAHash If the received frame's Destinat ion Address is accepted by the hash filter, then this bit is set if, and only if IAHashA (Register 5, RxCTL, Bit 6) is set, and Hashed (Bit 9) is set. See Section 5.2.10 on page 87. Dribblebits If set, the received frame had from one to seven bits after the last received full byte. An "Align- ment Error" occurs when Dribblebits and CRCerror (Bit C) are both set. RxOK If set, the received frame had a good CRC and va lid length (i.e., there is not a CRC error, Runt error, or Extradata error). When RxOK is set, then the length of the received frame is contained at PacketPage base + 0402h. If RxOKiE (Register 3, RxCFG, Bit 8) is set, there is an interrupt. Hashed If set, the received frame had a Destination Ad dress that was accepted by the hash filter. If Hashed and RxOK (Bit 8) are set, Bits F through A of RxEvent become the Hash Table Index for this frame [See Section 5.2.10 on page 87 for an exception regarding broadcast frames!].If Hashed and RxOK are not both set, then Bits F through A are individual event bits as defined below. IndividualAdr If the received frame had a Destination Address which matched the Individual Address found at PacketPage base + 0158h, then this bit is set if, and only if, RxOK (Bit 8) is set and Individ- ualA (Register 5, RxCTL, Bit A) is set. Broadcast If the received frame had a Broadcast Address (FFFF FFFF FFFFh) as the Destination Ad- dress, then this bit is set if, and only if, RxOK is set and BroadcastA (Register 5, RxCTL, Bit B) is set. CRCerror If set, the received frame had a bad CRC. If CRCe rroriE (Register 3, RxCFG, Bit C) is set, there is an interrupt Runt If set, the received frame was shorter than 64 by tes. If RuntiE (Register 3, RxCFG, Bit D) is set, there is an interrupt. Extradata If set, the received frame was longer than 1518 bytes. All bytes beyond 1518 are discarded. If ExtradataiE (Register 3, RxCFG, Bit E) is set, there is an interrupt. Reset value is: 0000 0000 0000 0100 Notes: 3. All RxEvent bits are cleared upon readout. Th e host is responsible for processing all event bits. 4. RxStatus register (PacketPage base + 0400h) is th e same as the RxEvent register except RxStatus is not cleared when RxEvent is read. See Section 5.2 on page 78. The value in the RxEvent register is undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set. 76543210 Dribblebits IAHash 000100 FEDCBA9 8 Extradata Runt CRCerror Broadcast Individual Adr Hashed RxOK 76543210 Dribblebits IAHash 000100 FEDCBA9 8 Hash Table Index (see Section 5.2.10 on page 87) Hashed = 1 RxOK = 1

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4.4.8 Register 5: Receiver Control

(RxCTL, Read/Write, Address: PacketPage base +0104h) RxCTL has two functions: Bits 8, C, D, and E define what types of frames to accept. Bits 6, 7, 9, A, and B configure the Destination Address filter. See Section 5.2.10 on page 87.

000101 These bits provide an internal address used by the CS8900A to identify this as the Receiver

Control Register. For a received frame to be accepted, the Destination Address of that frame must pass the filter criteria found in Bits 6, 7, 9, A, and B (see Section 5.2.10 on page 87). IAHashA When set, receive frames are accepted when the Destination Address is an Individual Address that passes the hash filter. PromiscuousA Frames with any address are accepted when this bit is set. RxOKA When set, the CS8900A accepts frames with corr ect CRC and valid length (valid length is: 64 bytes <= length <= 1518 bytes). MulticastA When set, receive frames are accepted if the Destination Address is an Multicast Address that passes the hash filter. IndividualA When set, receive frames are accepted if the Destination Address matches the Individual Ad- dress found at PacketPage base + 0158h to PacketPage base + 015Dh. BroadcastA When set, receive frames are accepted if the Destination Address is FFFF FFFF FFFFh. CRCerrorA When set, receive frames that pass the Destination Address filter, but have a bad CRC, are ac- cepted. When clear, frames with bad CRC are discarded. See Note 5. RuntA When set, receive frames that are smaller than 64 bytes, and that pass the Destination Address filter are accepted. When clear, received frames less that 64 bytes in length are discarded. The CS8900A discards any frame that is less than 8 bytes. See Note 5. ExtradataA When set, receive frames longer than 1518 bytes and that pass the Destination Address filter are accepted. The CS8900A accepts only the first 1518 bytes and ignores the rest. When clear, frames longer than 1518 bytes are discarded. See Note 5. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 5.2.10 on page 87. Reset value is: 0000 0000 0000 0101 Notes: 5. Typically, when bits CRCerrorA, RuntA and Ex tradataA are cleared (meaning bad frames are being discarded), then the corresponding bits CRCerroriE, RuntiE and ExtradataiE should be set in register 3 (Receiver Configuration register) to allow the device driver to keep track of discarded frames. 76543210 PromiscuousA IAHashA 000101 FEDCBA9 8 ExtradataA RuntA CRCerrorA BroadcastA IndividualA MulticastA RxOKA

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.9 Register 7: Transmit Configuration

(TxCFG, Read/Write, Address: PacketPage base + 0106h) Each bit in TxCFG is an interrupt enable. When set, the interrupt is enabled as described below. When clear, there is no interrupt.

000111 These bits provide an internal address used by the CS8900A to identify this as the Transmit

Configuration Register. Loss-of-CRSiE If the CS8900A starts transmitting on the AUI and does not see the Carrier Sense signal at the end of the preamble, an interrupt is generated if this bit is set. Carrier Sense activity is reported by the CRS bit (Register 14, LineST, Bit E). SQErroriE When set, an interrupt is generated if ther e is an SQE error. (At the end of a transmission on the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen, there is an SQE error.) TxOKiE When set, an interrupt is genera ted if a packet is completely transmitted. Out-of-windowiE When set, an interrupt is generated if a late collision occurs (a late collision is a collision which occurs after the first 512 bit times). When this occurs, the CS8900A forces a bad CRC and ter- minates the transmission. JabberiE When set, an interrupt is generated if a transmission is longer than approximately 26 ms. AnycolliE When set, if one or more collisions occur during the transmission of a packet, an interrupt oc- curs at the end of the transmission 16colliE If the CS8900A encounters 16 normal collisions while attempting to transmit a particular packet, the CS8900A stops attempting to transmit that packet. When this bit is set, there is an interrupt upon detecting the 16th collision. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0000 0111 Notes: Bit 8 (TxOKiE) and Bit B (AnycolliE) are interrupts for normal transmit operation. Bits 6, 7, 9, A, and F Notes:are interrupts for abnormal transmit operation.

4.4.10 Register 8: Transmitter Event

(TxEvent, Read-only, Address: PacketPage base + 0128h) TxEvent gives the event status of the last packet transmitted. 76543210 SQE erroriE Loss-of-CRSiE 000111 FEDCBA9 8 16colliE AnycolliE JabberiE Out-of-window TxOKiE 76543210 SQEerror Loss-of-CRS 001000 FEDCBA9 8 16coll Number-of-Tx-collisions Jabber Out-of-window TxOK

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001000 These bits provide an internal address used by the CS8900A to identify this as the Transmitter

Event Register. Loss-of-CRS If the CS8900A is transmitting on the AUI and doesn't see Carrier Sense (CRS) at the end of the preamble, there is a Loss-of-Carrier error and this bit is set. If Loss-of-CRSiE (Register 7, TxCFG, Bit 6) is set, there is an interrupt. SQEerror At the end of a transmi ssion on the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen, there is an SQE error and this bit is set. If SQEerroriE (Register 7, TxCFG, Bit 7) is set, there is an interrupt. TxOK This bit is set if the last packet was comple tely transmitted (Jabber (Bit A), out-of-window-colli- sion (Bit 9), and 16Coll (Bit F) must all be clear). If TxOKiE (Register 7, TxCFG, Bit 8) is set, there is an interrupt. Out-of-Window This bit is set if a collisio n occurs more than 512 bit times after the first bit of the preamble. When this occurs, the CS8900A forces a bad CRC and terminates the transmission. If Out-of-window- iE (Register 7, TxCFG, Bit 9) is set, there is an interrupt Jabber If the last transmission is longer than 26 ms ec, then the packet output is terminated by the jab- ber logic and this bit is set. If JabberiE (Register 7, TxCFG, Bit A) is set, there is an interrupt. #-of-TX-collisions These bits give the number of transmit collisions that occurred on the last transmitted packet. Bit B is the LSB. If AnycolliE (Register 7, TxCFG, Bit B) is set, there is an interrupt when any collision occurs. 16coll This bit is set if the CS89 00A encounters 16 normal collisions while attempting to transmit a particular packet. When this happens, the CS8900A stops further attempts to send that packet. If 16colliE (Register 7, TxCFG, Bit F) is set, there is an interrupt. Reset value is: 0000 0000 0000 1000 Notes: 1.In any event register, like TxEvent, all bits are cleared upon readout. The host is responsible for processing all event bits. 2.TxOK (Bit 8) and the Number-of-Tx-Collisions (Bits E-B) are used in normal packet transmission.All other bits (6, 7, 9, A, and F) give the status of abnormal transmit operation.

4.4.11 Register 9: Transmit Command Status

(TxCMD, Read-only, Address: PacketPage base + 0108h) This register contains the latest transmit command which tells the CS8900A how the next packet should be sent. The command must be written to PacketPage base + 0144h in order to initiate a transmission. The host can read the command from register 9 (PacketPage base + 0108h). See Section 5.6 on page 99.

001001 These bits provide an internal address used by the CS8900A to identify this as the Transmit

Command Register. When reading this register, these bits will be 001001, where the LSB cor- responds to Bit 0. TxStart This pair of bits determines how many bytes are transferred to the CS8900A before the MAC starts the packet transmit process. 76543210 TxStart 001001 FEDCBA9 8 TxPadDis InhibitCRC Onecoll Force

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Bit 7 Bit 6 0 0 Start transmission after 5 bytes are in the CS8900A 0 1 Start transmission after 381 bytes are in the CS8900A 1 0 Start transmission after 1021 bytes are in the CS8900A 1 1 Start transmission after the entire frame is in the CS8900A Force When set in conjunction with a new transmit co mmand, any transmit frames waiting in the trans- mit buffer are deleted. If a previous packet has started transmission, that packet is terminated within 64 bit times with a bad CRC. Onecoll When this bit is set, any transmission will be terminated after only one collision. When clear, the CS8900A allows up to 16 normal collisions before terminating the transmission. InhibitCRC When set, the CRC is not appended to the transmission. TxPadDis When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC. When TxPadDis is set, the CS8900A allows the transmission of runt frames (a frame less than 64 bytes). If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the CS8900A does not append the CRC After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Register value is: 0000 0000 0000 1001 Notes: The CS8900A does not transmit a frame if TxLength < 3

4.4.12 Register B: Buffer Configuration

(BufCFG, Read/Write, Address: PacketPage base + 010Ah) Each bit in BufCFG is an interrupt enable. When set, the interrupt described below is enabled. When clear, there is no interrupt.

001011 These bits provide an internal address used by the CS8900A to identify this as the Buffer Con-

figuration Register. SWint-X When set, there is an interrupt requested by the host software. The CS8900A provides the in- terrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The CS8900A acts upon this com- mand at once. SWint-X is an Act-Once bit. To generate another interrupt, rewrite a "1" to this bit. RxDMAiE When set, there is an interrupt when a frame has been received and DMA is complete. With this interrupt, the RxDMAFrame bit (Register C, BufEvent, Bit 7) is set. Rdy4TxiE When set, there is an inte rrupt when the CS8900A is ready to accept a frame from the host for transmission. (See Section 5.6 on page 99 for a description of the transmit bid process.) TxUnderruniE When set, there is an interrupt if the CS890 0A runs out of data before it reaches the end of the frame (called a transmit underrun). When this happens, event bit TXUnderrun (Register C, BufEvent, Bit 9) is set and the CS8900A makes no further attempts to transmit that frame. If the 76543210 RxDMAiE SWint-X 001011 FEDCBA9 8 RxDestiE Miss OvfloiE TxCol OvfloiE R x128iE RxMissiE TxUnder runtiE Rdy4TxiE

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET host still wants to transmit that particular frame, the host must go through the transmit request process again. RxMissiE When set, there is an interr upt if one or more received frames is lost due to slow movement of receive data out of the receive buffer (called a receive miss). When this happens, the RxMiss bit (Register C, BufEvent, Bit A) is set. Rx128iE When set, there is an interrupt after the first 128 bytes of a frame have been received. This al- lows a host processor to examine the Destination Address, Source Address, Length, Sequence Number, and other information before the entire frame is received. This interrupt should not be used with DMA. Thus, if either AutoRxDMA (Register 3, RxCFG, Bit A) or RxDMAonly (Register 3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear. TxColOvfiE If set, there is an interrupt when the TxCOL counter increments from 1FFh to 200h. (The TxCOL counter (Register 18) is incremented whenever the CS8900A sees that the RXD+/RXD- pins (10BASE-T) or the CI+/CI- pins (AUI) go active while a packet is being transmitted.) MissOvfloiE If MissOvfloiE is set, ther e is an interrupt when the RxMISS counter increments from 1FFh to 200h. (A receive miss is said to have occurred if packets are lost due to slow movement of re- ceive data out of the receive buffers. When this happens, the RxMiss bit (Register C, BufEvent, Bit A) is set, and the RxMISS counter (Register 10) is incremented.) RxDestiE When set, there is an in terrupt when a receive frame passes the Destination Address filter cri- teria defined in the RxCTL register (Register 5). This bit provides an early indication of an in- coming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE is set, the BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from RxDest to Rx128. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state after reset. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0000 1011

4.4.13 Register C: Buffer Event

(BufEvent, Read-only, Address: PacketPage base + 012Ch) BufEvent gives the status of the transmit and receive buffers.

001100 These bits provide an internal address used by the CS8900A to identify this as the Buffer Event

Register. When reading this register, these bits will be 001100, where the LSB corresponds to Bit 0. SWint If set, there has been a software initiated interr upt. This bit is used in conjunction with the SWint- X bit (Register B, BufCFG, Bit 6). RxDMAFrame If set, one or more received frames have been transferred by slave DMA. If RxDMAiE (Register B, BufCFG, Bit 7) is set, there is an interrupt. Rdy4Tx If set, the CS8900A is ready to accept a fr ame from the host for transmission. If Rdy4TxiE (Reg- ister B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.6 on page 99 for a description of the transmit bid process.) 76543210 RxDMA frame SWint 001100 FEDCBA9 8 RxDest Rx128 RxMiss TxUnder run Rdy4Tx

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET TxUnderrun This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans- mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt. RxMiss If set, one or more receive frames have been lost due to slow movement of data out of the re- ceive buffers. If RxMissiE (Register B, BufCFG, Bit A) is set, there is an interrupt. Rx128 This bit is set after the first 128 bytes of an incoming frame have been received. This bit will allow the host the option of preprocessing frame data before the entire frame is received. If Rx128iE (Register B, BufCFG, Bit B) is set, there is an interrupt. RxDest When set, this bit sh ows that a receive frame has passed the Destination Address Filter criteria as defined in the RxCTL register (Register 5). This bit is useful as an early indication of an in- coming frame. It will be earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE (Register B, BufCFG, Bit F) is set, there is an interrupt. Reset value is: 0000 0000 0000 1100 Notes: With any event register, like BufEvent, all bits are cleared upon readout. The host is responsible for processing all event bits.

4.4.14 Register 10: Receiver Miss Counter

(RxMISS, Read-only, Address: PacketPage base + 0130h) The RxMISS counter (Bits 6 through F) records the number of receive frames that are lost (missed) due to the lack of available buffer space. If the MissOvfloiE bit (Register B, BufCFG, Bit D) is set, there is an interrupt when RxMISS increments from 1FFh to 200h. This interrupt provides the host with an early warning that the RxMISS counter should be read before it reaches 3FFh and starts over (by interrupting at 200h, the host has an additional 512 counts before RxMISS actually overflows). The RxMISS counter is cleared when read.

010000 These bits provide an internal address used by the CS8900A to identify this as the Receiver

Miss Counter. When reading this register, these bits will be 010000, where the LSB corre- sponds to Bit 0. MissCount The upper ten bits contain the number of missed frames. Register’s value is: 0000 0000 0001 0000

4.4.15 Register 12: Transmit Collision Counter

(TxCOL, Read-only, Address: PacketPage base + 0132h) The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) or AUI Collision Pair (CI+ / CI-) becomes active while a packet is being transmitted. If the TxColOvfiE bit (Register B, 76543210 MissCount 010000 FEDCBA9 8 MissCount 76543210 ColCount 010010 FEDCBA9 8 ColCount

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET BufCFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the host with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by inter- rupting at 200h, the host has an additional 512 counts before TxCOL actually overflows). The TxCOL counter is cleared when read.

010010 These bits provide an internal address used by the CS8900A to identify this as the Transmit

Collision Counter. When reading this register, these bits will be 010010, where the LSB corre- sponds to Bit 0. ColCount The upper ten bits cont ain the number of collisions. Reset value is: 0000 0000 0001 0010

4.4.16 Register 13: Line Control

(LineCTL, Read/Write, Address: PacketPage base + 0112h) LineCTL determines the configuration of the MAC engine and physical interface.

010011 These bits provide an internal address used by the CS8900A to identify this as the Line Control

Register. SerRxON When set, the receiver is enabled. When clear, no incoming packets pass through the receiver. If SerRxON is cleared while a packet is being received, reception is completed and no subse- quent receive packets are allowed until SerRxON is set again. SerTxON When set, the transmitter is enabled. When cl ear, no transmissions are allowed. If SerTxON is cleared while a packet is being transmitted, transmission is completed and no subsequent packets are transmitted until SerTxON is set again. AUIonly Bits 8 and 9 are used to select either the AUI or the 10BASE-T interface according to the fol- lowing: [Note: 10BASE-T transmitter will be inactive even when selected unless link pulses are detected or bit DisableLT (register 19) is set. AUIonly (Bit 8) AutoAUI/10BT (Bit 9) Physical Interface 1N / A A U I 0> 0 0BASE-T 0 1 Auto-Select AutoAUI/10BT See AUIonly (Bit 8) description above. ModBackoffE When clear, th e ISO/IEC standard backoff algorithm is used (see Section 3.9 on page 29). When set, the Modified Backoff algorithm is used. (The Modified Backoff algorithm extends the backoff delay after each of the first three Tx collisions.) PolarityDis The 10BASE-T rece iver automatically determines the polarity of the received signal at the RXD+/RXD- input (see Section 3.11 on page 36). When this bit is clear, the polarity is correct- ed, if necessary. When set, no effort is made to correct the polarity. This bit is independent of the PolarityOK bit (Register 14, LineST, Bit C), which reports whether the polarity is normal or reversed. 76543210 SerTxOn SerRxON 010011 FEDCBA9 8 LoRx Squelch 2-part DefDis PolarityDis Mod BackoffE Auto AUI/10BT AUIonly

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET 2-partDefDis Before a transmission can begin, the CS 8900A follows a deferral procedure. With the 2-part- DefDis bit clear, the CS8900A uses the standard two-part deferral as defined in ISO/IEC 8802- LoRxSquelch When clear, the 10BASE-T re ceiver squelch thresholds are set to levels defined by the ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approximately 6dB. This is use- ful for operating with "quiet" cables that are longer than 100 meters. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 0011

4.4.17 Register 14: Line Status

(LineST, Read-only, Address: PacketPage base + 0134h) LineST reports the status of the Ethernet physical interface.

010100 These bits provide an internal address used by the CS8900A to identify this as the Line Status

Register. When reading this register, these bits will be 010100, where the LSB corresponds to Bit 0. LinkOK If set, the 10BASE-T link has not failed. When clear, the link has failed, either because the CS8900A has just come out of reset, or because the receiver has not detected any activity (link pulses or received packets) for at least 50 ms. AUI If set, the CS8900A is using the AUI. 10BT If set, the CS8900A is using the 10BASE-T interface. PolarityOK If set, the polarity of the 10BASE-T receive signal (at the RXD+ / RXD- inputs) is correct. If clear, the polarity is reversed. If PolarityDis (Register 13, LineCTL, Bit C) is clear, the polarity is auto- matically corrected, if needed. The PolarityOK status bit shows the true state of the incoming polarity independent of the PolarityDis control bit. Thus, if PolarityDis is clear and PolarityOK is clear, then the receive polarity is inverted, and corrected. CRS This bit tells the host the status of an incoming frame. If CRS is set, a frame is currently being received. CRS remains asserted until the end of frame (EOF). At EOF, CRS goes inactive in about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered data. Reset value is: 0000 0000 0001 0100 76543210 LinkOK 010100 FEDCBA9 8 CRS PolarityOK 10BT AUI

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4.4.18 Register 15: Self Control

(SelfCTL, Read/Write, Address: PacketPage base + 0114h) SelfCTL controls the operation of the LED outputs and the lower-power modes.

010101 These bits provide an internal address used by the CS8900A to identify this as the Chip Self

Control Register. RESET When set, a chip-wid e reset is initiated immediately. RESET is an Act-Once bit. This bit is cleared as a result of the reset. SWSuspend When set, the CS8900A enters the software initiated Suspend mode. Upon entering this mode, there is a partial reset. All registers and circuits are reset except for the ISA I/O Base Address Register and the SelfCTL Register. There is no transmit nor receive activity in this mode. To come out of software Suspend, the host issues an I/O Write within the CS8900A's assigned I/O space (see Section 3.7 on page 27 for a complete description of the CS8900A's low-power modes). HWSleepE When set, the SLEEP input pin is enabled. If SLEEP is high, the CS8900A is "awake", or oper- ative (unless in SWSuspend mode, as shown above). If SLEEP is low, the CS8900A enters ei- ther the Hardware Standby or Hardware Suspend mode. When clear, the CS8900A ignores the SLEEP input pin (see Section 3.7 on page 27 for a complete description of the CS8900A's low- power modes). HWStandbyE If HWSleepE is set and the SLEEP input pin is low, then when HWStandbyE is set, the CS8900A enters the Hardware Standby mode. When clear, the CS8900A enters the Hardware Suspend mode (see Section 3.7 on page 27 for a complete description of the CS8900A's low- power modes). HC0E The LINKLED or HC0 output pin is selected with this control bit. When HC0E is clear, the output pin is LINKLED. When HC0E is set, the output pin is HC0 and the HCB0 bit (Bit E) controls the pin. HC1E The BSTATUS or HC1 output pin is selected with this control bit. When HC1E is clear, the out- put pin is BSTATUS and indicates receiver ISA Bus activity. When HC1E is set, the output pin is HC1 and the HCB1 bit (Bit F) controls the pin. HCB0 When HC0E (Bit C) is set, this bit controls the HC0 pin. If HCB0 is set, HC0 is low. If HCB0 is clear, HC0 is high. HC0 may drive an LED or a logic gate. When HC0E (Bit C) is clear, this con- trol bit is ignored. HCB1 When HC1E (Bit D) is set, this bit controls the HC1 pin. If HCB1 is set, HC1 is low. If HCB1 is clear, HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D) is clear, this con- trol bit is ignored. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 0101 76543210 RESET 010101 FEDCBA9 8 HCB1 HCB0 HC1E HC0E HW Standby HWSleepE SW Suspend

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.19 Register 16: Self Status

(SelfST, Read-only, Address: PacketPage base + 0136h) SelfST reports the status of the EEPROM interface and the initialization process.

010110 These bits provide an internal address used by the CS8900A to identify this as the Chip Self

Status Register. When reading this register, these bits will be 010110, where the LSB corre- sponds to Bit 0. 3,3VActive If the CS8900A is operating on a 3.3V supply, this bit is set. If the CS8900A is operating on a 5V supply, this bit is clear. INITD If set, the CS8900A initialization, incl uding read-in of the EEPROM, is complete. SIBUSY If set, the EECS output pin is high indicating that the EEPROM is currently being read or pro- grammed. The host must not write to PacketPage base + 0040h nor 0042h until SIBUSY is clear. EEPROMpresent If the EEDataIn pin is low after reset, there is no EEPROM present, and the EEPROMpresent bit is clear. If the EEDataIn pin is high after reset, the CS8900A "assumes" that an EEPROM is present, and this bit is set. EEPROMOK If set, the checksum of the EEPROM readout was OK. ELpresent If set, external logic for Latchable Address bus decode is present. EEsize This bit shows the size of the attached EEP ROM and is valid only if the EEPROMpresent bit (Bit 9) and EEPROMOK bit (Bit A) are both set. If clear, the EEPROM size is either 128 words ('C56 or 'CS56) or 256 words (C66 or 'CS66). If set, the EEPROM size is 64 words ('C46 or 'CS46). Reset value is: 0000 0000 0001 0110

4.4.20 Register 17: Bus Control

(BusCTL, Read/Write, Address: PacketPage base + 0116h) BusCTL controls the operation of the ISA-bus interface.

010111 These bits provide an internal address used by the CS8900A to identify this as the Bus Control

Register. 76543210 INITD 3.3V Active 010110 FEDCBA9 8 EEsize ELPresent EEPROM OK EEPROM present SIBUSY 76543210 Reset RxDMA 010111 FEDCBA9 8 EnableIRQ RxDMA size IOCH RDYE DMABurst MemoryE UseSA DMAextend

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET ResetRxDMA When set, the RxDMA offs et pointer at PacketPage base + 0026h is reset to zero. When the host sets this bit, the CS8900A does the following: 1.Terminates the current receive DMA activity, if any. 2.Clears all internal receive buffers. 3.Zeroes the RxDMA offset pointer. DMAextend When set, DMARQx goes in active on the falling edge of IORN instead of the rising edge of IORN-1. See Switching Characteristics, DMA Read, tDMAR5. Setting this bit also enables single transfer mode DMA. Normal operation is demand mode DMA in which DMACKx cannot deas- sert until after DMARQx deasserts, i.e. until a full ethernet frame is transferred. Single transfer mode allows DMACKx to deassert between each DMA read. UseSA When set, the MEMCS16 pin goes low whenever the address on SA bus [12..19] match the CS8900A's assigned Memory base address and the CHIPSEL pin is low (internal address de- code). When clear, MEMCS16 is driven low whenever CHIPSEL goes low. (external address decode). see Section 4.9 on page 73. For MEMCS16 pin to be enabled, the CS8900A must be in Memory Mode with the MemoryE bit (Register 17, BusCTL, Bit A) set. MemoryE When set, the CS8900A may operate in Memory Mode. When clear, Memory Mode is disabled. I/O Mode is always enabled. DMABurst When clear, the CS8900A performs continuo us DMA until the receive frame is completely transferred from the CS8900A to host memory. When set, each DMA access is limited to 28us, after which time the CS8900A gives up the bus for 1.3us before making a new DMA request. IOCHRDYE When set, the CS8900A does not use the IOCHRDY output pin, and the pin is always high-im- pedance. This allows external pull-up to force the output high. When clear, the CS8900A drives IOCHRDY low to request additional time during I/O Read and Memory Read cycles. IOCHRDY does not affect I/O Write, Memory Write, nor DMA Read. RxDMAsize This bit determines the size of the receive DM A buffer (located in host memory). When set, the DMA buffer size is 64 Kbytes. When clear, it is 16 Kbytes. EnableRQ When set, the CS8900A will generate an interrupt in response to an interrupt event (Section 5.1). When cleared, the CS8900A will not generate any interrupts. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register's initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 0111

4.4.21 Register 18: Bus Status

(BusST, Read-only, Address: PacketPage base + 0138h) BusST describes the status of the current transmit operation.

011000 These bits provide an internal address used by the CS8900A to identify this as the Bus Status

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Register. When reading this register, these bits will be 011000, where the LSB corresponds to Bit 0. TxBidErr If set, the host has command ed the CS8900A to transmit a frame that the CS8900A will not send. Frames that the CS8900A will not send are: 1) Any frame greater than 1514 bytes, provided that InhibitCRC (Register 9, TxCMD, Bit C) is clear. 2) Any frame greater than 1518 bytes. Note that this bit is not set when transmit frames are too short. Rdy4TxNOW Rdy4TxNOW signals the host that the CS890 0A is ready to accept a frame from the host for transmission. This bit is similar to Rdy4Tx (Register C, BufEvent, Bit 8) except that there is no interrupt associated with Rdy4TxNOW. The host can poll the CS8900A and check Rdy4TxNOW to determine if the CS8900A is ready for transmit. (See Section 5.6 on page 99 for a description of the transmit bid process.) Reset value is: 0000 0000 0001 1000

4.4.22 Register 19: Test Control

(TestCTL, Read/Write, Address: PacketPage base + 0118h) TestCTL controls the diagnostic test modes of the CS8900A.

011001 These bits provide an internal address used by the CS8900A to identify this as the Test Control

Register. DisableLT When set, the 10BASE-T interf ace allows packet transmission and reception regardless of the link status. DisableLT is used in conjunction with the LinkOK (Register 14, LineST, Bit 7) as fol- lows: LinkOK DisableLT 0 0 No packet transmission or reception allowed. Transmitter sends link pulses. 0 1 DisableLT overrides LinkOK to allow packet transmission and reception. 1 X Disable has no meaning if LinkOK = 1. ENDECloop When set, the CS8900A enters internal loopback mode where the internal Manchester encoder output is connected to the decoder input. The 10BASE-T and AUI transmitters and receivers are disabled. When clear, the CS8900A is configured for normal operation. AUIloop When set, the CS8900A allows reception while transmitting. This facilitates loopback tests for the AUI. When clear, the CS8900A is configured for normal AUI operation. 76543210 DisableLT 011001 FEDCBA9 8 FDX Disable Back- off AUIloop ENDEC loop

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Disable Backoff When set, the backoff algorithm is disabl ed. The CS8900A transmitter looks only for completion of the inter packet gap before starting transmission. When clear, the backoff algorithm is used. FDX When set, 10BASE-T full duplex mode is enabled and CRS (Register 14, LineST, Bit E) is ig- nored. This bit must be set when performing loopback tests on the 10BASE-T port. When clear, the CS8900A is configured for standard half-duplex 10BASE-T operation. At reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 19. Reset value is: 0000 0000 0001 1001

4.4.23 Register 1C: AUI Time Domain Reflectometer

(Read-only, Address: PacketPage base + 013Ch) The TDR counter (Bits 6 through F) is a time domain reflectometer useful in locating cable faults in 10BASE-2 and 10BASE-5 coax networks. It counts at a 10 MHz rate from the beginning of transmission on the AUI to when a col- lision or Loss-of-Carrier error occurs. The TDR counter is cleared when read.

011100 These bits provide an internal address used by the CS8900A to identify this as the Bus Status

Register. When reading this register, these bits will be 011100, where the LSB corresponds to Bit 0. AUI-Delay The upper ten bits contains the number of 10 MHz clock periods between the beginning of transmission on the AUI to when a collision or Loss-of-Carrier error occurs. Reset value is: 0000 0000 0001 1100 76543210 AUI Delay 011100 FEDCBA9 8 AUI Delay

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.5 Initiate Transmit Registers

4.5.1 Transmit Command Request - TxCMD

(Write-only, Address: PacketPage base + 0144h) The word written to PacketPage base + 0144h tells the CS8900A how the next packet should be transmitted. This PacketPage location is write-only, and the written word can be read from Register 9, at PacketPage base + 0108h. The CS8900A does not transmit a frame if TxLength (at PacketPage location base + 0146h) is less than 3. See Section 5.6 on page 99. Command Register. When reading this register, these bits will be 001001, where the LSB cor- responds to Bit 0. TxStart This pair of bits determines how many bytes are transferred to the CS8900A before the MAC starts the packet transmit process. Bit 7 Bit 6 0 0 Start transmissi on after 5 bytes are in the CS8900A 0 1 Start transmission after 381 bytes are in the CS8900A 1 0 Start transmission after 1021 bytes are in the CS8900A 1 1 Start transmission after the entire frame is in the CS8900A Force When set in conjunction with a new transmit co mmand, any transmit frames waiting in the trans- mit buffer are deleted. If a previous packet has started transmission, that packet is terminated within 64 bit times with a bad CRC. Onecoll When this bit is set, any transmission will be terminated after only one collision. When clear, the CS8900A allows up to 16 normal collisions before terminating the transmission. InhibitCRC When set, the CRC is not appended to the transmission. TxPadDis When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC. When TxPadDis is set, the CS8900A allows the transmission of runt frames (a frame less than 64 bytes). If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the CS8900A does not append the CRC. Since this register is write-only, it’s initial state after reset is undefined.

4.5.2 Transmit Length

(Write-only, Address: PacketPage base + 0146h) This register is used in conjunction with register 9, TxCMD. When a transmission is initiated via a command in Tx- 76543210 TxStart 001001 FEDCBA9 8 TxPadDis InhibitCRC Onecoll Force Address 0147h Address 0146h Most-significant byte of Transmit Frame Length Lea st-significant byte of Transmit Frame Length

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET CMD, the length of the transmitted frame is written into this register. The length of the transmitted frame may be modified by the configuration of the TxPadDis and InhibitCRC bits in the TxCMD register. See Table 36, and Section 5.6 on page 99. TxLength must be >3 and < 1519. Since this register is write-only, it’s initial state after reset is undefined.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.6 Address Filter Registers

4.6.1 Logical Address Filter (hash table)

(Read/Write, Address: PacketPage base + 0150h) The CS8900A hashing decoder circuitry compares its output with one bit of the Logical Address Filter Register. If the decoder output and the Logical Address Filter bit match, the frame passes the hash filter and the Hashed bit (Register 4, RxEvent, Bit 9) is set. See Section 5.2.10 on page 87. Reset value is: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

4.6.2 Individual Address (IEEE address)

(Read/Write, Address: PacketPage base + 0158h) The unique, IEEE 48-bit Individual Address (IA) begins at 0158h. The first bit of the IA (Bit IA[00]) must be "0". See Section 5.2.10 on page 87. The value of this register must be loaded from external storage, for example, from the EEPROM. See Section 3.3 on page 19. If the CS8900A is not able to load the IA from the EEPROM, then after a reset this register is undefined, and the driver must write an address to this register. Address 0157h Address 0156h Address 0155h Address 0154h Address 0153h Address 0152h Address 0151h Address 0150h Most-signifi- cant byte of hash filter. Least-signifi- cant byte of hash filter. Address 0015Dh Address 0015Ch Address 0015Bh Address 0015Ah Address 0159h Address 00158h Octet 5 of IA Octet 0 of IA

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4.7 Receive and Transmit Frame Locations

The Receive and Transmit Frame PacketPage locations are used to transfer Ethernet frames to and from the host. The host sequentially writes to and reads from these locations, and internal buffer memory is dynamically allocat- ed between transmit and receive as needed. One receive frame and one transmit frame are accessible at a time.

4.7.1 Receive PacketPage Locations

In IO mode, the receive status/length/frame lo- cations are read through repetitive reads from one IO port at the IO base address. See Section 4.10 on page 75. In memory mode, the receive sta- tus/length/frame locations are read using memory reads of a block of memory starting at memory base address + 0400h. Typically the memory locations are read sequentially using repetitive Move inst ructions (REP MOVS). See Section 4.9 on page 73. Random access is not needed. However, the first 118 bytes of the receive frame can be ac- cessed randomly if word reads, on even word boundaries, are used. Bey ond 118 bytes, the memory reads must be sequential. Byte reads, or reads on odd-word boundaries, can be per- formed only in sequential read mode. See Section 4.8 on page 72. The RxStatus word repor ts the status of the current received frame. RxEvent register 4 (PacketPage base + 0124h) has the same contents as the RxStatus register, except Rx- Event is cleared when RxEvent is read. The RxLength (receive length) word is the length, in bytes, of the data to be transferred to the host across the ISA bus. The register de- scribes the length from the start of Destination Address to the end of CRC, assuming that CRC has been selected (v ia Register 3 Rx- CFG, bit BufferCRC). If CRC has not been se- lected, then the length does not include the CRC, and the CRC is not present in the re- ceive buffer. After the RxLength has been read, the receive frame can be read. When some portion of the frame is read, the entire frame should be read before reading the RxEvent register either di- rectly or through the ISQ register. Reading the RxEvent register signals to the CS8900A that the host is finished with the current frame, and wants to start processing the next frame. In this case, the current fr ame will no longer be accessible to the host. The current frame will also become inaccessible if a Skip command is issued, or if the entire frame has been read. See Section 5.2 on page 78.

4.7.2 Transmit Locations

The host can write frames into the CS8900A buffer using Memory writes using REP MOVS to the TxFrame locati on. See Section 5.6 on page 99.

4.8 Eight and Sixteen Bit Transfers

A data transfer to or from the CS8900A can be done in either I/O or Memory space, and can be either 16 bits wide (word transfers) or 8 bits wide (byte transfers). Because the CS8900A’s internal architecture is based on a 16-bit data bus, word transfers are the most efficient. To transfer transmit fr ames to the CS8900A and receive frames from the CS8900A, the host may mix word and byte transfers, provid- ed it follows three rules: 1) The primary method used to access CS8900A memory is word access. 2) Word accesses to the CS8900A’s internal memory are kept on even-byte boundaries. 3) When switching from byte accesses to word accesses, a byte access to an even

4.8.1 Transferring Odd-Byte-Aligned Data

tions may be either even- or odd-byte aligned. address. It can then resume word transfers. An example of this is shown in Figure 17.

4.8.2 Random Access to CS8900A Mem-

are executed to even-byte boundaries.

4.9 Memory Mode Operation

a contiguous 4-kbyte block of host memory. CS8900A’s registers can be accessed directly. ducing additional wait states. base address is on a double word boundary.

4.9.1 Accesses in Memory Mode

Figure 17. Odd-Byte Aligned Data Table 17. Receive/Transmit Memory Locations

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• The address on the IS A System Address bus (SA0 - SA19) is within the Memory space range of the CS8900A or Boot PROM.
• The CHIPSEL input pin is low.
• Either the MEMR pin or the MEMW pin is low.

4.9.2 Configuring the CS8900A for Mem-

There are two different methods of configuring the CS8900A for Memory Mode operation. One method allows the CS8900A's internal memory to be mapped anywhere within the host system's 24-bit memory space. The other method limits memory ma pping to the first 1 Mbyte of host memory space. General Memory Mode Operation: Configuring the CS8900A so that its internal memory can be mapped anywhere within host Memory space requires the following:

• a simple circuit must be added to decode the Latchable Addre ss bus (LA20 - LA23) and the BALE signal.
• the host must configur e the external logic with the correct address range as follows: 1) Check to see if t he INITD bit (Register 16,SelfST, bit 7) is set, indicating that initialization is complete. 2) Check to see if t he ELpresent bit (Reg- ister 16, SelfST, bit B) is set. This bit in- dicates that external logic for the LA bus decode is present. 3) Set the ELSEL bit of the EEPROM Command Register to activate the ELCS pin for use with the external de- code circuit. 4) Configure the exter nal logic serially.
• the host must write the memory base ad- dress into the Memory Base Address reg- ister (PacketPage base + 002Ch);
• the host must set the MemoryE bit (Regis- ter 17, BusCTL, Bit A); and
• the host must set the UseSA bit (Register 17, BusCTL, Bit 9). Limiting Memory Mode to the First 1 Mbyte of Host Memory Space: Configuring the CS8900A so that its in ternal memory can be mapped only within the first 1 Mbyte of host memory space requires the following:
• the CHIPSEL pin must be tied low;
• the ISA-bus SMEMR si gnal must be con- nected to the MEMR pin;
• the ISA-bus SMEMW signal must be con- nected to the MEMW pin;
• the host must write the memory base ad- dress into the Memory Base Address reg- ister (PacketPage base + 002Ch);
• the host must set the MemoryE bit (Regis- ter 17, BusCTL, Bit A); and
• the host must clear the UseSA bit (Register 17, BusCTL, Bit 9).

4.9.3 Basic Memory Mode Transmit

Memory Mode transmit operations occur in the following order (using interrupts): 1) The host bids for storage of the frame by writing the Transmit Command to the TxC- MD register (memory base + 0144h) and the transmit frame l ength to the TxLength register (memory base + 0146h). If the transmit length is erroneous, the command is discarded and the TxBidErr bit (Register 18, BusST, Bit 7) is set. 2) The host reads the Bu sST register (Regis- ter 18, memory base + 0138h). If the Rdy4TxNOW bit (Bit 8) is set, the frame

4.9.4 Basic Memory Mode Receive

gering an enabled interrupt. 0402h) to learn the frame's length. CS8900A memory to host memory.

4.9.5 Polling the CS8900A in Memory

4.10 I/O Space Operation

300h is typically assigned to LAN peripherals).

4.10.1 Receive/Transmit Data Ports 0 and

32-bit operations (lower-order word in Port 0).

4.10.2 TxCMD Port

Table 18. I/O Mode Mapping

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Section 4.4 on page 49 for more information.

4.10.3 TxLength Port

4.10.4 Interrupt Status Queue Port

4.10.5 PacketPage Pointer Port

be auto-incremented to the next word location.

4.10.6 PacketPage Data Ports 0 and 1

operations (lower-order word in Port 0).

4.10.7 I/O Mode Operation

low, and for a Write, the IOW pin must be low. only I/O Mode and Receive DMA operation.

4.10.8 Basic I/O Mode Transmit

Figure 18. PacketPage Pointer

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET base + 000Ch). If Rdy4TxNOW is set, the frame can be written. If clear, the host must wait for CS8900A buffer memory to be- come available. If Rdy4TxiE (Register B, BufCFG, Bit 8) is set, the host will be inter- rupted when Rdy4Tx (Register C, BufE- vent, Bit 8) becomes set. If the TxBidErr bit (Register 18, BusST, Bit 7) is set, the trans- mit length is not valid. 3) Once the CS8900A is ready to accept the frame, the host executes repetitive write in- structions (REP OU T) to the Re- ceive/Transmit Data Port (I/O base + 0000h) to transfer t he entire frame from host memory to CS8900A memory. For a more detailed de scription of transmit, see Section 5.6 on page 99.

4.10.9 Basic I/O Mode Receive

I/O Mode receive operati ons occur in the fol- lowing order (In this ex ample, interrupts are enabled to signal the presence of a valid re- ceive frame): 1) A frame is received by the CS8900A, trig- gering an enabled interrupt. 2) The host reads the In terrupt Status Queue Port (I/O base + 0008h) and is informed of the receive frame. 3) The host reads the frame data by execut- ing repetitive read inst ructions (REP IN) from the Receiv e/Transmit Data Port (I/O base + 0000h) to tran sfer the frame from CS8900A memory to host memory. Pre- ceding the frame data are the contents of the RxStatus register (PacketPage base + 0400h) and the RxLength register (Pack- etPage base + 0402h). For a more detailed description of receive, see Section 5.2 on page 78.

4.10.10 Accessing Internal Registers

To access any of the CS8900A's internal reg- isters in I/O Mode, the host must first setup the PacketPage Pointer. It does this by writing the PacketPage address of th e target register to the PacketPage Pointer Port (I/O base + 000Ah). The contents of the target register is then mapped into the PacketPage Data Port (I/O base + 000Ch). If the host needs to access a sequential block of registers, the MSB of the PacketPage ad- dress of the first word to be accessed should be set to "1". The PacketPage Pointer will then move to the next word location automatically, eliminating the need to setup the PacketPage Pointer between successive accesses (see Figure 18).

4.10.11 Polling the CS8900A in I/O Mode

If interrupts are not used, the host can poll the CS8900A to check if receive frames are present and if memory sp ace is available for transmit.

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5.0 OPERATION

5.1 Managing Interrupts and Servicing the

The Interrupt Status Queue (ISQ) is used by the CS8900A to communicate Event reports to the host processor. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s) in one of five registers, maps the contents of that regis- ter to the ISQ, and drives the selected interrupt request pin high (if an earli er interrupt is wait- ing in the queue, the inte rrupt request pin will already be high). When t he host services the interrupt, it must first read the ISQ to learn the nature of the interrupt. It can then process the interrupt (the first read to the ISQ causes the interrupt request pin to go low.) Three of the registers mapped to the ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEve nt (Register C). The other two registers ar e counter-overflow re- ports: RxMISS (Register 10) and TxCOL (Reg- ister 12). There may be more than one RxEvent report and/or more than one TxEvent report in the ISQ at a time. However, there may be only one BufEvent report, one RxMISS report and one TxCOL repo rt in the ISQ at a time. Event reports stored in the ISQ are read out in the order of priority, with RxEvent first, fol- lowed by TxEvent, BufEvent, RxMiss, and then TxCOL. The host only needs to read from one location to get the interrupt currently at the front of the queue. In Memory Mode, the ISQ is located at PacketPage base + 0120h. In I/O Mode, it is located at I/O base + 0008h. Each time the host reads the ISQ, the bits in the cor- responding register are cleared and the next report in the queue moves to the front. When the host starts r eading the ISQ, it must read and process all Event reports in the queue. A read-out of a null word (0000h) indi- cates that all interrupts have been read. The ISQ is read as a 16-bit word. The lower six bits (0 through 5) cont ain the register number (4, 8, C, 10, or 12). The upper ten bits (6 through F) contain the register contents. The host must always read the entire 16-bit word. The active interrupt pi n (INTRQx) is selected via the Interrupt Number register (PacketPage base + 22h). As an additional option, all of the interrupt pins can be 3-Stated using the same register. see Section 4.3 on page 44. An event triggers an in terrupt only when the EnableIRQ bit of the Bus Control register (bit F of register 17) is set. After the CS8900A has generated an interrupt, the first read of the ISQ makes the INTRQ output pin go low (inactive). INTRQ remains low until the null word (0000h) is read from the ISQ, or for 1.6us, whichever is longer.

5.2 Basic Receive Operation

5.2.0.1 Overview

Once an incoming packet has passed through the analog front end and Manchester decoder, it goes through the fo llowing three-step re- ceive process: 1) Pre-Processing 2) Temporary Buffering 3) Transfer to Host Figure 20 shows the steps in frame reception. As shown in the figure, all receive frames go through the same pre-processing and tempo- rary buffering phases, regardless of transfer method Once a frame has been pre-processed and buffered, it can be accessed by the host in ei- ther Memory or I/O space. In addition, the CS8900A can transfer rece ive frames to host

An enabled interrupt occurs. (active) if not already high. Figure 19. Interrupt Status Queue

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5.2.1 Terminology: Packet, Frame, and

used extensively in the following sections.

5.2.1.1 Packet

shows the format of a packet.

5.2.1.2 Frame

mitted, or that has been received.

5.2.1.3 Transfer

across the ISA bus, to and from the CS8900A. padded for double word alignment.

5.2.2 Receive Configuration

• which physical interface to use;
• which types of frames to accept;
• which receive even ts cause interrupts; and,
• how received frames are transferred. YesNo Use DMA? Frame Held On Chip Frame DMAed to Host M emory Host Reads Frame from Host Memory Frame Pre- Processed Frame Temporarily Buffered Packet Received Preamble and Start-of-Frame Delimiter Removed Host Reads Frame from CS8900A Memory

Figure 20. Frame Reception

5.2.2.1 Configuring the Physical Interface

5.2.2.2 Choosing whic h Frame Types to Ac-

describes the configuration bits in this register.

5.2.2.3 Selecting which Events Cause Inter-

5.2.2.4 Choosing How to Transfer Frames

6 SerRxON When set, reception enabled.

8 AUIonly When set, AUI selected (takes

precedence over AutoAUI/10BT).

9 AutoAUI/10BT When set, automatic interface

reduced by approximately 6 dB. Table 19. Physical Interface Configuration

6 IAHashA When set, Individual Address frames

When set, all frames are accepted*.

8 RxOKA When set, frames with valid length

9 MulticastA When set, Multicast frames that pass

the hash filter are accepted*.

• Must also meet the criteria programmed into bits 8, C, D, and E.

Table 20. Frame Acceptance Criteria pass the DA filter are accepted.

8 RxOKiE When set, there is an interrupt if a

frame is received with bad CRC*.

• Must also pass the DA filter before there is an interrupt.
• Must also meet the criteria programmed into bits 8, C, D, and E.

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memory, as described in Table 23.

5.2.3 Receive Frame Pre-Processing

4) Normal Interrupt Generation.

5.2.3.1 Destination Address Filtering

description of DA filtering.

5.2.3.2 Early Interrupt Generation

• RxDest: The RxDest bit (Register C, BufE- vent, Bit F) is set as soon as the Destina- tion Address (DA) of the incoming frame passes the DA filter. If the RxDestiE bit (Register B, BufCFG, bit F) is set, the CS8900A generates a corresponding inter- rupt. Once RxDest is set, the host is al- lowed to read the incoming frame's DA (the first 6 bytes of the frame).
• Rx128: The Rx128 bit (Register C, BufE- vent, Bit B) is set as soon as the first 128 bytes of the incoming frame have been re- ceived. If the Rx128iE bit (Register B, BufCFG, bit B) is set, the CS8900A gener- ates a corresponding interrupt. Once the Rx128 bit is set, the RxDest bit is cleared and the host is allowed to read the first 128 bytes of the incoming frame. The Rx128 bit is cleared by the host reading the BufEvent register (either directly or through the Inter- rupt Status Queue) or by the CS8900A de- Register B, BufCFG Bit Bit Name Operation

7 RxDMAiE When set, there is an interrupt if

the RxMISS counter overflows. Table 22. Registers 3 and B Interrupt Configuration

7 StreamE When set, Stream Transfer

9 RxDMAonly When set, DMA slave opera-

Table 23. Receive Frame Pre-Processing

vides a diagram of the Early Interrupt process.

5.2.3.3 Acceptance Filtering

grammed into the RxCTL register (Register 5). Event register (Register 4).

5.2.3.4 Normal Interrupt Generation

memory via DMA is a DMAed receive frame. Figure 21. Receive Frame Pre-Processing

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Figure 22. Early Interrupt Generation

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET This section describes buffering and transfer- ring held receive fr ames. Section 5.3 on page 90 through Section 5.5 on page 96 de- scribe DMAed receive frames.

5.2.5 Buffering Held Receive Frames

If space is available, an incoming frame will be temporarily stored in on-chip RAM, where it awaits processing by the host. Although this receive frame now occupies on-chip memory, the CS8900A does not commit the memory space to it until one of the following two condi- tions is true: 1) The entire frame has been received and the host has learned about the frame by reading the RxEvent regi ster (Register 4), either directly or through the ISQ. Or: 2) The frame has been partially received, causing either the Rx Dest bit (Register C, BufEvent, Bit F) or the Rx128 bit (Register C, BufEvent, Bit B) to become set, and the host has learned about the receive frame by reading the BufEvent register (Register C), either directly or through the ISQ. When the CS8900A commits buffer space to a particular held receive frame (termed a com- mitted received frame), no data from subse- quent frames can be writ ten to that buffer space until the frame is freed from commit- ment. (The committed received frame may or may not have been received error free.) A received frame is freed from commitment by any one of the following conditions: 1) The host reads the entire frame sequential- ly in the order that it was received (first byte in, first byte out). Or: 2) The host reads part or none of the frame, and then issues a Skip command by set- ting the Skip_1 bit (Register 3, RxCFG, bit 6). Or: 3) The host reads part of the frame and then reads the RxEvent register (Register 5), ei- ther directly or through the ISQ, and learns of another receive frame. This condition is called an "implied Skip". Ensure that the host does not do “implied skips.” Both early interrupts are disabled whenever there is a committed re ceive frame waiting to be processed by the host.

5.2.6 Transferring Held Receive Frames

The host can read-out held receive frames in Memory or I/O space. To transfer frames in Memory space, the host executes repetitive Move instructions (REP MOVS) from Pack- etPage base + 0404h. To transfer frames in I/O space, the host execut es repetitive In in- structions (REP IN) from I/O base + 0000h, with status and length preceding the frame. There are three possibl e ways that the host can learn the status of a particular frame. It can: 1) Read the Interrupt Status Queue; 2) Read the RxEvent register directly (Register4); or 3) Read the RxStatus register (PacketPage base + 0400h).

5.2.7 Receive Frame Visibility

Only one receive frame is visible to the host at a time. The receive frame's status can be read from the RxStatus register (PacketPage base + 0400h), and its length can be read from the RxLength register (PacketPage base + 0402h). For more information about Memory space operation, see Section 4.9 on page 73. For more information about I/O space opera- tion, see Section 4.10 on page 75.

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5.2.8 Example of Memory Mode Receive

• The BufferCRC bit (Reg ister 3, RxCFG, Bit B) is set causing the 4-byte CRC to be buff- ered with the rest of the receive data.
• The RxOKA bit (Register 5, RxCTL, Bit 8) is set, causing the CS8900A to accept good frames (a good frame is one with le- gal length and valid CRC).
• The RxOKiE bit (Register 3, RxCFG, Bit 8) is set, causing an interrupt to be generated whenever a good frame is received. Then the transfer to the host would proceed as follows: 1) The CS8900A generates an RxOK inter- rupt to the host to si gnal the arrival of a good frame. 2) The host reads the ISQ (PacketPage base + 0120h) to assess the status of the re- ceive frame and sees the contents of the RxEvent register (Regi ster 4) with the RxOK bit (Bit 8) set. 3) The host reads the re ceive frame's length from the RxLength r egister (PacketPage base + 0402h). 4) The host reads the frame data by execut- ing 32 consecutive MOV instructions start- ing with PacketPage base + 0404h. The memory map of the 64-byte frame is given in Table 24.

5.2.9 Receive Frame Byte Counter

Table 24. Example Memory Map 0404h to 0409h 6-byte Source Address. 040Ah to 040Fh 6-byte Destination Address. 0410h to 0411h 2-byte Length or Type Field. 0412h to 043Fh 46 bytes of data.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET register can be read to determine the final frame status. The sequence is as follows: 1) At the start of a fr ame, the byte counter matches the incoming character counter. The byte counter will have an even value prior to the end of the frame. 2) At the end of the fram e, the final count, in- cluding the allowance for the CRC (if the BufferCRC option is enabled), is held until the byte counter is read. 3) When a read of the by te counter returns a count of zero, the previous count was the fi- nal count. The count may now have an odd value. 4) RxEvent should be re ad to obtain a final status of the frame, followed by a Skip command to complete the operation. Note that all RxEvent's should be processed before using the byte counter. The byte counter should be used following a BufEvent when RxDest or Rx128 interrupts are enabled.

5.2.10 Receive Frame Address Filtering

The CS8900A is equipped with a Destination Address (DA) filter used to determine which receive frames will be accepted. (A receive frame is said to be "accepted" by the CS8900A when the frame data ar e placed in either on- chip memory, or in host memory by DMA). The DA filter can be confi gured to accept the fol- lowing frame types:

5.2.10.1 Individual Address Frames

For all Individual Address frames, the first bit of the DA is a "0" (DA[0] = 0), indicating that the address is a Physical Address. The address filter accepts Individual Address frames whose DA matches the Individual Address (IA) stored at PacketPage base + 0158h, or whose hash- filtered DA matches one of the bits pro- grammed into the Logica l Address Filter (the hash filter is described later in this section).

5.2.10.2 Multicast Frames

For Multicast Frames, the first bit of the DA is a "1" (DA[0] = 1), indicating that the frame is a Logical Address. The ad dress filter accepts Multicast frames whose hash-filtered DA matches one of the bits programmed into the Logical Address Filter (the hash filter is de- scribed later is this section). As shown in Table 26, Broadcast Frames can be accepted as Multicast frames under a very specific set of conditions.

5.2.10.3 Broadcast Frames

Frames with DA equal to FFFF FFFF FFFFh are broadcast frames . In addition, the CS8900A can be config ured for Promiscuous Mode, in which case it will accept all receive frames, irrespective of DA.

5.2.11 Configuring the Destination

The DA filter is configured by programming five DA filter bits in the RxCTL register (Regis- ter 5): IAHashA, PromiscuousA, MulticastA, IndividualA, and BroadcastA. Four of these bits are associated with f our status bits in the RxEvent register (R egister 4): IAHash, Hashed, IndividualAdr, and Broadcast. The RxEvent register reports the results of the DA filter for a given receive frame. The bits asso- ciated with DA filtering are summarized below: Bit # RxCTL Register 5 RxEvent Register 4

6 IAHashA IAHash

(used only if IAHashA = 1)

7 PromiscuousA

9 MulticastA Hashed

A IndividualA IndividualAdr (used only if IndividualA = 1) B BroadcastA Broadcast (used only if BroadcastA = 1)

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or Individual Address frames are accepted. figuration options available for DA filtering. while the filter is being changed. 3) Set SerRxON to re -enable the receiver.

5.2.12 Hash Filter

frames should be accepted by the CS8900A.

5.2.12.1 Hash Filter Operation

Table 25. DA Filtering Options

5.2.13 Broadcast Frame Hashing Excep-

RxEvent contained a hash RxEvent. Figure 23. Hash Filter Operation LAF value corresponds to a Multicast Addresses of both all 1s and 03-00-00-00-00-01. and the following address filters were enabled: IAHashA and BroadcastA. Table 26. Contents of RxEvent Upon Various Conditions

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5.3 Receive DMA

5.3.1 Overview

receive frames to host memory via slave DMA. frames are transferred via DMA. needed to help prevent missed frames. the number of interrupts to the host. page 96 describes StreamTransfer.

5.3.2 Configuring the CS8900A for DMA

tion. These are described in Table 27. the RxDMAonly bit (Register 3, RxCFG, Bit 9). LAF value corresponds to a Multicast Addresses of both all 1s and 03-00-00-00-00-01. and the following address filters were enabled: IAHashA and BroadcastA. recently transferred received frame. Table 27. Receive DMA Registers

5.3.3 DMA Receive Buffer Size

5.3.4 Receive-DMA-Only Operation

and other peripherals access to the bus.

• updates the DMA Start-of-Frame register (PacketPage base + 0026h);
• updates the DMA Frame Count register (PacketPage base + 0028h);
• updates DMA Byte C ount register (Pack- etPage base + 002Ah);
• sets the RxDMAFrame bit (Register C, BufEvent, Bit 7); and,
• deallocates the buffer space used by the transferred frame. In addition, if the RxDMAiE bit (Register B, BufCFG, Bit 7) is set, a corresponding inter- rupt occurs. When the host processes DMAed frames, it must read the DMA Frame Count register. Whenever a receive frame is missed (lost) due to insufficient receive buffer space, the Rx- MISS counter (Register 10) is incremented. A missed receive frame causes the counter to in- crement in either DMA or non-DMA modes. 0028h DMA Frame Count: The lower 12 bits define the number of valid frames transferred via DMA since the last read-out of this register. The upper 4 bits are reserved and not applicable. 002Ah DMA Byte Count: Defines the num- ber of bytes that have been transferred via DMA since the last read-out of this register. PacketPage Address Register Description

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tents of the RxEvent register will return 0000h.

5.3.5 Committing Buffer Space to a

register (PacketPage base + 0028h). condition is termed an "implied Skip").

5.3.6 DMA Buffer Organization

length of the frame preceding the hole.

5.3.7 RxDMAFrame Bit

teria used to set and clear RxDMAFrame.

5.3.8 Receive DMA Example Without

memory by DMA without wrap-around.

5.3.9 Receive DMA Operation for RxDMA-

Table 28. RxDMAFrame Bit

Receive Frame interrupt is processed. driver should maintain a pointer (e.g. makes a second read of the DMA frame count. space described by the CDMA counter. Figure 24. Example of Frames Stored in DMA

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5.4 Auto-Switch DMA

5.4.1 Overview

due to slow processing by the host.

5.4.2 Configuring the CS8900A for Auto-

Configuring the CS8900A for DMA Operation). switching to slave DMA if necessary.

5.4.3 Auto-Switch DMA Operation

Figure 25. RxDMA Only Operation

96 DS271F4

BufEvent) associated with the missed frame.

5.4.5 Exit From DMA

• The host processes all RxEvent and BufE- vent reports pending in the ISQ.
• The host reads a zero value from the DMA Frame Count register (PacketPage base + 0028h).
• The CS8900A is not in the process of transferring a frame via DMA.

5.4.6 Auto-Switch DMA Example

5.5 StreamTransfer

5.5.1 Overview

5.5.2 Configuring the CS8900A for

ceiver Configurat ion (register 3).

5.5.3 StreamTransfer Operation

• delays the normal RxOK interrupt associat- ed with the first receive frame;
• switches to receive DMA mode;
• transfers up to eight receive frames into host memory via DMA; Register Name Bit Bit Name Value Register 3, RxCFG 7 StreamE 1 8R x O K i E 1 or A RxDMAonly or AutoRxDMA or Register 5, RxCTL 8 RxOKA 1 Register B, BufCFG 7 RxDMAiE 1 FR x D e s t i E 0 B Rx128iE 0

Table 29. Stream Transfer Configuration

Frame 3 starts to be received and passes the DA filter. This activates Auto-Switch DM A. bit and generates an interrupt. CS8900A updates the DMA registers. CS8900A exits DMA (assumes Frame 3 is still coming in). space for another complete large frame (1518 bytes). Frame 1 received and completely stored in on-chip RAM. Frame 2 received and completely stored in on-chip RAM. awaits processing by the host. DMA Frame Count (PacketPage base + 0028h) is zero. Figure 27. Example of Auto-Switch DMA

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• updates the DMA Star t-of-Frame register (PacketPage base + 0026h);
• updates the DMA Frame Count register (PacketPage base + 0028h);
• updates DMA Byte C ount register (Pack- etPage base + 002Ah);
• sets the RxDMAFrame bit (Register C, BufEvent, Bit 7); and,
• generates an RxDMAFrame interrupt.

5.5.4 Keeping StreamTransfer Mode

• all packets received ar e of legal length with valid CRC;
• each packet follows its predecessor by less than 52 ms; and,
• the DA of each packet passes the DA filter. If any of these conditi ons are not met, the CS8900A exits StreamTransfer by generating RxOK and RxDMA interrupts. The CS8900A then returns to either Memory, I/O, or DMA mode, depending on configuration.

5.5.5 Example of StreamTransfer

would be received with out StreamTransfer.

4 Back-to-Back Frames 5 Back-to-Back Frames

9 Interrupts for 9 "Good" Packets Time

Figure 28. Receive Example Without Stream Transfer

2 Interrupts for 9 "Good" Packets Time

Figure 29. Receive DMA Configuration Options

5.5.6 Receive DMA Summary

uration options supported by the CS8900A.

5.6 Transmit Operation

5.6.1 Overview

using either Memory or I/O space.

5.6.2 Transmit Configuration

and which transmit events cause interrupts.

5.6.2.1 Configuring the Physical Interface

1 NA 0 NA Receive DMA used for a ll receive frames, without

1 NA 1 NA Receive DMA used for all receive frames, with

and BufEvent interrupts possible. 0 0 NA NA Memory or I/O Mode only. Table 30. Receive DMA Configuration Options

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5.6.2.2 Selecting which Events Cause Inter-

5.6.3 Changing the Configuration

affect the packet currently being transmitted. 7 SerTxON When set, transmission enabled. precedence over AutoAUI/10BT). When clear, 10BASE-T selected. Table 31. Physical Interface Configuration

8 Rdy4TxiE When set, there is an interrupt

(used with a Transmit Request).

9 TxUnder

of data after transmit has started. Table 33. Transmit Interrupt Configuration

6 Loss-of-

7 SQErroriE When set, there is an interrupt

whenever there is an SQE error.

8 TxOKiE When set, there is an interrupt

whenever there is a collision. Table 32. Transmitting Interrupt Configuration

5.6.4 Enabling CRC Generation and Pad-

5.6.5 Individual Packet Transmission

the TxCMD register are described in Table 35. host must issue a complete Transmit Request.

5.6.6 Transmit in Poll Mode

following order and is shown in Figure 30. Table 34. CRC and Paddling Configuration

67 T x S t a r t

8 Force When set, the CS8900A dis-

rently in the transmit buffer.

9 Onecoll When set, the CS8900A will

any packet after a collision. Table 35. Tx Command Configuration

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET 1) The host bids for fram e storage by writing the Transmit Command to the TxCMD reg- ister (memory base+ 0144h in memory mode and I/O base + 0004h in I/O mode). 2) The host writes the transmit frame length to the TxLength register (memory base + 0146h in memory mode and I/O base + 0006h in I/O mode). If the transmit length is erroneous, the command is discarded and the TxBidErr bit (Register 18, BusST, Bit 7) is set. 3) The host reads the BusST register. This read is performed in memory mode by reading Register 18, at memory base + 0138h. In I/O mode, the host must first set the PacketPage Pointer at the correct loca- tion by writin g 0138h to the PacketPage Pointer Port (I/O base + 000Ah). The host can then read the BusST register from the PacketPage Data Port (I/O base + 000Ch). 4) After reading the register, the Rdy4TxNOW bit (Bit 8) is checked. If the bit is set, the frame can be written. If the bit is clear, the host must continue reading the BusST reg- ister (Register 18) and checking the Rdy4TxNOW bit (Bit 8) until the bit is set. When the CS8900A is re ady to accept the frame, the host transfers the entire frame from host memory to CS8900A memory using “REP” instruction (R EP MOVS starting at memory base + 0A00h in memory mode, and REP OUT to Receive/Transmit Data Port (I/O base + 0000h) in I/O mode).

5.6.7 Transmit in Interrupt Mode

In interrupt mode, Rdy4 TxiE bit (Register B, BufCFG, Bit 8) must be set for transmit opera- tion. Transmit operation occurs in the following order and is shown in Figure 31. 1) The host bids for fr ame storage by writing the Transmit Command to the TxCMD reg- ister (memory base + 0144h in memory mode and I/O base + 0004h in I/O mode). 2) The host writes the transmit frame length to the TxLength register (memory base + 0146h in memory mode and I/O base + 0006h in I/O mode). If the transmit length is erroneous, the command is discarded and the TxBidErr, bit 7, in BusST register is set. 3) The host reads the BusST register. This read is performed in memory mode by reading Register 18 , at memory base + 0138h. In I/O mode, the host must first set the PacketPage Pointer at the correct loca- tion by writing 0 138h to the PacketPage Pointer Port (I/O base + 000Ah), it than can read the BusST regist er from the Pack- etPage Data Port (I/O base + 000Ch).After reading the register, the Rdy4TxNOW bit is checked. If the bit is set, the frame can be written to CS8900A memory. If Rdy4TxNOW is clear, the host will have to wait for the CS8900A buffer memory to be- come available at which time the host will be interrupted. On interrupt, the host enters the interrupt service routine and reads ISQ register (Memory base + 0120h in memory mode and I/O base + 0008h in I/O) and checks the Rdy4Tx bit (bit 8). If Rdy4Tx is clear then the CS8900A waits for the next interrupt. If Rdy4Tx is set, then the CS8900A is ready to accept the frame. 4) When the CS8900A is ready to accept the frame, the host transfe rs the entire frame from host memory to CS8900A memory using REP instruct ion (REP MOVS to memory base + 0A00h in memory mode, and REP OUT to Receive/Transmit Data Port (I/O base + 0000h) in I/O mode).

5.6.8 Completing Transmission

generates a corresponding interrupt. Figure 30. Transmit Operation in Polling Mode

104 DS271F4

able when interrupts are not being used (i.e. Figure 31. Transmit Operation in Interrupt Mode

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET not set). Also, the Rdy4Tx bit is used with in- terrupts and requires the Rdy4TxiE bit be set. Figure 30 provides a diagram of error free transmission without collision.

5.6.10 Committing Buffer Space to a

When the host issues a transmit request, the CS8900A checks the l ength of the transmit frame to see if there is sufficient on-chip buffer space. If there is, the CS8900A sets the Rdy4TxNOW bit. If no t, and the Rdy4TxiE bit is set, the CS8900A wa its for buffer space to free up and then sets the Rdy4Tx bit. If Rdy4TxiE is not set, the CS8900A sets the Rdy4TxNOW bit when space becomes avail- able. Even though transmit buffer space may be available, the CS8900A does not commit buff- er space to a transmit frame until all of the fol- lowing are true: 1) The host must issues a Transmit Request; 2) The Transmit Request must be successful; and, 3) Either the host read s that the Rdy4TxNOW bit (Register 18, BusST, Bit 8) is set, or the host reads that the Rdy4Tx bit (Register C, BufEvent, bit 8) is set. If the CS8900A commits buffer space to a par- ticular transmit frame, it will not allow subse- quent frames to be written to that buffer space as long as the transmit frame is committed. After buffer space is committed, the frame is subsequently transmitted unless any of the fol- lowing occur: 1) The host completely writes the frame data, but transmission failed on the Ethernet line. There are three such failures, and these are indicated by three transmit error bits in the TxEvent register (Register 8): 16coll, Jabber, or Out-of-Window. Or: 2) The host aborts the transmission by setting the Force (Register 9, TxCMD, bit 8) bit. In this case, the committed transmit frame, as well as any yet-to-be-transmitted frames queued in the on-chip memory, are cleared and not transmitted. The host should make TxLength = 0 when using the Force bit. Or: 3) There is a transmit under-run, and the Tx- Underrun bit (Register C, BufEvent, Bit 9) is set. Successful transmission is indicated when the TxOK bit (Register 8, TxEvent, Bit 8) is set.

5.6.11 Transmit Frame Length

The length of the fram e transmitted is deter- mined by the value writ ten into the TxLength register (PacketPage base + 0146h) during the Transmit Request. The length of the trans- mit frame may be modified by the configura- tion of the TxPadDis bi t (Register 9, TxCMD, Bit D) and the InhibitCRC bit (Register 9, TxC- MD, Bit C). Table 36 defines how these bits af- fect the length of the transmit frame. In addition, it shows which frames the CS8900A will send.

5.7 Full duplex Considerations

The driver should not bid to transmit a long frame (i.e., a frame great er than 118 bytes) if the prior transmit frame is still being transmit- ted. The end of the trans mission of this prior frame is indicated by a TxOK bit being set in the TxEvent register (register 8).

5.8 Auto-Negotiation Considerations

When the CS8900A is connected to an auto negotiation hub, and if auto-media detection is selected (bits 8 and 9 of register 13), then the

106 DS271F4

in the following paragraphs. IEEE 802.3 NLP (Normal Link Pulses). sending FLPs to sending NLPs. length less than 60 bytes, the CS8900A pads.

1. The CS8900A will not send a frame with TxLength less than 3 bytes.

Table 36. Transmit Frame Length

6.0 TEST

6.1 TEST MODES

6.1.1 Loopback & Collision Diagnostic

6.1.2 Internal Tests

6.1.3 External Tests

6.1.4 Loopback Tests

6.1.6 AUI Loopback and Collision Tests

verify that 16coll (Register 8, TxEvent, Bit F) is set. and verify that the frame is received without error. (Register 8, TxEvent, Bit F) is set. Table 37. 10BASE-T Loopback and Collision Tests 1 1 Transmit a frame and verify that the frame is received without error. sine wave to Cl+/Cl- pins and observe collisions. Table 38. AUI Loopback and Collision Tests

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

6.2 Boundary Scan

Boundary Scan test mode provides an easy and efficient board-level test for verifying that the CS8900A has been installed properly. Boundary Scan will check to see if the orienta- tion of the chip is correct, and if there are any open or short circuits. Boundary Scan is controlled by the TEST pin. When TEST is high, the CS8900A is config- ured for normal operation. When TEST is low, the following occurs:

• the CS8900A enter s Boundary Scan test mode and stays in this mode as long as TEST is low;
• the CS8900A goes through an internal re- set and remains in internal reset as long as TEST is low;
• the AEN pin, normally the ISA bus Address Enable, is redefined to become the Bound- ary Scan shift clock input; and
• all digital outputs and bi-directional pins are placed in a high-impedance state (this electrically isolates the CS8900A digital outputs from the rest of the circuit board). For Boundary Scan to be enabled, AEN must be low before TEST is driven low. A complete Boundary Scan test is made up of two separate cycles. The first cycle, known as the Output Cycle, test s all digital output pins and all bi-directional pins. The second cycle, known as the Input Cycle, tests all digital input pins and all bi-directional pins.

6.2.1 Output Cycle

During the Output Cycle, the falling edge of AEN causes each of the 17 digital output pins and each of the 17 bi-directional pins to be driven low, one at a time. The cycle begins with LINKLED and advances in order counter- clockwise around the chip through all 34 pins. This test is referred to as a "walking 0" test. The following is a list of output pins and bi-di- rectional pins that are tested during the Output Cycle: The output pins not included in this test are:

6.2.2 Input Cycle

During the Input Cycle, the falling edge of AEN causes the state of each selected pin to be transferred to EEDataOut (that is, EEDataOut will be high or low depending on the input level of the selected pin). This cycle begins with SLEEP and advances clockwise through each of 33 input pins (all digital input pins except for AEN) and each of the 17 bi-directional pins, one pin at a time. The following is a list of input pins and bi-direc- tional pins that are tested during the Input Cy- cle: Pin Name Pin # Pin Name Pin # ELCS 2 INTRQ1 31 EECS 3 INTRQ0 32 EESK 4 IOCS16 33 EEDataOut 5 MEMCS16 34 DMARQ2 11 INTRQ3 35 DMARQ1 13 IOCHRDY 64 DMARQ0 15 SD0 - SD7 65-68, 71-74 CSOUT 17 BSTATUS 78 SD08-SD15 27-24, 21-18 LINKLED 99 INTRQ2 30 LANLED 100 Table 39. Pin Name Pin # Pin Name Pin # DO+ 83 TXD- 88 DO- 84 RES 93 TXD+ 87 XTAL2 98 Table 40. Pin Name Pin # Pin Name Pin # ELCS 2 SBHE 36 EEDataIn 6 SA0 - SA11 37-48 CHIPSEL 7 REFRESH 49 DMACK2 12 SA12 - SA19 50-54, 58-60 Table 41.

directional pins to a high-impedance state.

6.2.3 Continuity Cycle

Figure 33 shows Boundary Scan timing. Table 41. (continued)

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Figure 32. Boundary Scan Continuity Cycle

34 Clocks

50 Clocks

85 Clocks

Figure 33. Boundary Scan Timing

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

7.0 CHARACTERISTICS/SPECIFICATIONS - COMMERCIAL

7.1 ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) WARNING: Normal operation is no t guaranteed at these extremes.

7.2 RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS = 0 V, all voltages with respect

to 0 V.) 7.3 DC CHARACTERISTICS (TA = 25 °C; VDD = 5.0 V or VDD = 3.3V) Notes: 1. With digital outputs connected to CMOS loads. Parameter Symbol Min Max Unit Power Supply Digital Analog DVDD AVDD -0.3 -0.3 6.0 6.0 V V Input Current (Except Supply Pins) - ±10.0 mA Analog Input Voltage -0.3 ( AVDD+) + 0.3 V Digital Input Voltage -0.3 ( DVDD) + 0.3 V Ambient Temperature (Power Applied) -55 +125 °C Storage Temperature -65 +150 °C Parameter Symbol Min Max Unit 5.0V Power Supply CS8900A-CQ, -CQZ & -IQ, -IQZ Digital Analog DVDD AVDD 4.75 4.75 5.25 5.25 V V 3.3V Power Supply CS8900A-CQ3, -CQ3Z & -IQ3, -IQ3Z Digital Analog DVDD AVDD 3.135 3.135 3.465 3.465 V V Operating Ambient Temperature CS8900A-CQ, -CQZ & -CQ3, -CQ3Z T A 0+ 7 0 ° C Operating Ambient Temperature CS8900A-IQ, -IQZ & -IQ3, -IQ3Z T A -40 +85 °C Parameter Symbol Min Max Unit Crystal (when using external clock - square wave) XTAL1 Input Low Voltage V IXH -0.5 0.4 V XTAL1 Input High Voltage V IXH 3.5 DVDD + 0.5 V XTAL1 Input Low Current I IXL -40 - µA XTAL1 Input High Current I IXH -4 0 µ A Power Supply Hardware Standby Mode Current (Note 1) I DDSTNDBY -1 . 0 m A Hardware Suspend Mode Current (Note 1) I DDHWSUS -1 0 0 µ A Software Suspend Mode Current (Note 1) I DDSWSUS -1 . 0 m A

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET DC CHARACTERISTICS (Continued) Notes: 2. OD24: Open Drain Output with 24 mA Drive OD10: Open Drain Output with 10 mA Drive B24: Bi-Directional with 3-State Output and 24 mA Drive B4w: Bi-Directional with 3-State Output, Internal Weak Pullup, and 4 mA Drive O24ts: 3-State Output with 24 mA Drive O4: Output with 4 mA Drive I: Input Iw: Input with Internal Weak Pullup Parameter Symbol Min Typ Max Unit Digital Inputs and Outputs (Note 2) Power Supply Current while Active 5.0V I DD -9 5- m A Power Supply Current while Active 3.3V I DD -9 5- m A Output Low Voltage I OL = 24 mA OD24, B24, O24ts IOL = 10 mA OD10 IOL = 4 mA B4w, O4 VOL - 0.4 0.4 0.4 V V V Output Low Voltage (all outputs) V DD = 3.3V and TA = >70°C V OL 0.425 V Output High Voltage I OH = -12 mA B24 IOH = -2 mA B4w, O24ts, O4 VOH 2.4 2.4 V V Output Leakage Current 0 ≤ V OUT ≤ VCC OD24, OD10, B24, O24ts B4w ILL -10 -20 µA Input Low Voltage I, Iw V IL -- 0 . 8 V Input High Voltage I, Iw V IH 2.4 - - V Input Leakage Current 0 ≤ VIN ≤ VCC I Iw IL -10 -20 µA 10BASE-T Interface Transmitter Differential Output Voltage (Peak) V OD 2.2 - 2.8 V Receiver Normal Squelch Level (Peak) V ISQ 300 - 525 mV Receiver Low Squelch Level (LoRxSquelch bit set) V SQL 125 - 290 mV AUI Interface Transmitter Differential Output Voltage (DO+/DO- Peak) V AOD ±0.45 - ±1.2 V Transmitter Undershoot Voltage V AODU -- 1 0 0 m V Transmitter Differential Idle Voltage (DO+/DO- Peak) V IDLE -- 4 0 m V Receiver Squelch Level (DI+/DI- Peak) V AISQ 180 - 300 mV

114 DS271F4

Figure 34. 16-Bit I/O Read, IOCHRDY not used Figure 35. 16-Bit I/O Read, with IOCHRDY

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Figure 38. 16-Bit DMA Read Figure 39. 16-Bit I/O Write

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Figure 42. 10BASE-T Receive Figure 43. 10BASE-T Link Integrity

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Figure 47. External Boot PROM Access Figure 48. EEPROM

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET 7.5 10BASE-T WIRING

• If a center tap transformer is used on the RXD+ and RX D- inputs, replace the pair of Rr re- sistors with a single 2xRr resistor.
• The Rt and Rr resist ors are ±1% tolerance.
• The CS8900A suppor ts 100, 120, and 150 Ω unshielded twisted pair cables. The proper val- ues of Rt and Rr, for a given cable impedance, are shown below:
• Note: for 3.3V operation the turns ratio on TXD+ and TXD- is 1:2.5, rt is 8 Ω for 100Ω cable and the 68pF cap changes to 560pF. Cable Impedance (Ω)R t ( Ω) Rr ( Ω) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 Rt Rt CS8900A TD + TD - TXD + TXD - 1 : 2 RJ45 1 : 1 RD + RD - 0.01 µ F RXD+ RXD- Rr Rr0.01 µ F 68 pF

122 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

7.6 AUI WIRING

7.7 QUARTZ CRYSTAL REQUIREMENTS (If a 20 MHz quartz crystal is used, it must meet the fol-

lowing specifications) Parameter Min Typ Max Unit Parallel Resonant Frequency - 20 - MHz Resonant Frequency Error (CL = 18 pF) -50 - +50 ppm Resonant Frequency Change Over Operating Temperature -40 - +40 ppm Crystal Capacitance - - 18 pF Motional Crystal Capacitance - 0.022 - pF Series Resistance - - 50 Ohm Shunt Capacitance - - 7 pF CS8900A DO + DO - 1 : 1 DB15 Tx 1 : 1 13 6 +12 V CI + CI - 1 : 1 39.2 Ω 39.2 ΩCol 0.01 uF DI + DI - 39.2 Ω 39.2 ΩRx 0.01 uF

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

8.0 CHARACTERISTICS/SPECIFICATIONS - INDUSTRIAL

8.1 ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) WARNING: Normal operation is no t guaranteed at these extremes.

8.2 RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS = 0 V, all voltages with respect

to 0 V.) 8.3 DC CHARACTERISTICS (TA = 25 °C; VDD = 5.0 V or VDD = 3.3V) Notes: 1. With digital outputs connected to CMOS loads. Parameter Symbol Min Max Unit Power Supply Digital Analog DVDD AVDD -0.3 -0.3 6.0 6.0 V V Input Current (Except Supply Pins) - ±10.0 mA Analog Input Voltage -0.3 ( AVDD+) + 0.3 V Digital Input Voltage -0.3 ( DVDD) + 0.3 V Ambient Temperature (Power Applied) -55 +125 °C Storage Temperature -65 +150 °C Parameter Symbol Min Max Unit 5.0V Power Supply CS8900A-CQ, -CQZ & -IQ, -IQZ Digital Analog DVDD AVDD 4.75 4.75 5.25 5.25 V V 3.3V Power Supply CS8900A-CQ3, CQ3Z & -IQ3, -IQ3Z Digital Analog DVDD AVDD 3.135 3.135 3.465 3.465 V V Operating Ambient Temperature CS8900A-CQ, -CQZ & -CQ3, -CQ3Z T A 0+ 7 0 ° C Operating Ambient Temperature CS8900A-IQ, -IQZ & -IQ3, -IQ3Z T A -40 +85 °C Parameter Symbol Min Max Unit Crystal (when using external clock - square wave) XTAL1 Input Low Voltage V IXH -0.5 0.4 V XTAL1 Input High Voltage V IXH 3.5 DVDD + 0.5 V XTAL1 Input Low Current I IXL -40 - µA XTAL1 Input High Current I IXH -4 0 µ A Power Supply Hardware Standby Mode Current (Note 1) I DDSTNDBY -1 . 0 m A Hardware Suspend Mode Current (Note 1) I DDHWSUS -1 0 0 µ A Software Suspend Mode Current (Note 1) I DDSWSUS -1 . 0 m A

124 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET DC CHARACTERISTICS (Continued) Notes: 2. OD24: Open Drain Output with 24 mA Drive OD10: Open Drain Output with 10 mA Drive B24: Bi-Directional with 3-State Output and 24 mA Drive B4w: Bi-Directional with 3-State Output, Internal Weak Pullup, and 4 mA Drive O24ts: 3-State Output with 24 mA Drive O4: Output with 4 mA Drive I: Input Iw: Input with Internal Weak Pullup Parameter Symbol Min Typ Max Unit Digital Inputs and Outputs (Note 2) Power Supply Current while Active 5.0V I DD -9 5- m A Power Supply Current while Active 3.3V I DD -9 5- m A Output Low Voltage I OL = 24 mA OD24, B24, O24ts IOL = 10 mA OD10 IOL = 4 mA B4w, O4 VOL - 0.4 0.4 0.4 V V V Output Low Voltage (all outputs) V DD = 3.3V and TA = >70°C V OL 0.425 V Output High Voltage I OH = -12 mA B24 IOH = -2 mA B4w, O24ts, O4 VOH 2.4 2.4 V V Output Leakage Current 0 ≤ V OUT ≤ VCC OD24, OD10, B24, O24ts B4w ILL -10 -20 µA Input Low Voltage I, Iw V IL -- 0 . 8 V Input High Voltage I, Iw V IH 2.4 - - V Input Leakage Current 0 ≤ VIN ≤ VCC I Iw IL -10 -20 µA 10BASE-T Interface Transmitter Differential Output Voltage (Peak) V OD 2.2 - 2.8 V Receiver Normal Squelch Level (Peak) V ISQ 300 - 525 mV Receiver Low Squelch Level (LoRxSquelch bit set) V SQL 125 - 290 mV AUI Interface Transmitter Differential Output Voltage (DO+/DO- Peak) V AOD ±0.45 - ±1.2 V Transmitter Undershoot Voltage V AODU -- 1 0 0 m V Transmitter Differential Idle Voltage (DO+/DO- Peak) V IDLE -- 4 0 m V Receiver Squelch Level (DI+/DI- Peak) V AISQ 180 - 300 mV

126 DS271F4

Figure 51. 16-Bit Memory Read, IOCHRDY not used Figure 52. 16-Bit Memory Read, with IOCHRDY

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Figure 55. 16-Bit Memory Write Figure 56. 10BASE-T Transmit

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Figure 59. AUI Transmit Figure 60. AUI Receive Figure 61. AUI Collision

132 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET 8.5 10BASE-T WIRING

• If a center tap transformer is used on the RXD+ and RX D- inputs, replace the pair of Rr re- sistors with a single 2xRr resistor.
• The Rt and Rr resist ors are ±1% tolerance.
• The CS8900A supports 100, 120, and 150 Ω unshielded twisted pair cables. The proper val- ues of Rt and Rr, for a given cable impedance, are shown below:
• Note: for 3.3V operation the turns ratio on TXD+ and TXD- is 1:2.5, rt is 8 Ω for 100Ω cable and the 68pF cap changes to 560pF. Cable Impedance (Ω)R t ( Ω) Rr ( Ω) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 Rt Rt CS8900A TD + TD - TXD + TXD - 1 : 2 RJ45 1 : 1 RD + RD - 0.01 µ F RXD+ RXD- Rr Rr0.01 µ F 68 pF

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

8.6 AUI WIRING

8.7 QUARTZ CRYSTAL REQUIREMENTS (If a 20 MHz quartz crystal is used, it must meet the fol-

lowing specifications) Parameter Min Typ Max Unit Parallel Resonant Frequency - 20 - MHz Resonant Frequency Error (CL = 18 pF) -50 - +50 ppm Resonant Frequency Change Over Operating Temperature -40 - +40 ppm Crystal Capacitance - - 18 pF Motional Crystal Capacitance - 0.022 - pF Series Resistance - - 50 Ohm Shunt Capacitance - - 7 pF CS8900A DO + DO - 1 : 1 DB15 Tx 1 : 1 13 6 +12 V CI + CI - 1 : 1 39.2 Ω 39.2 ΩCol 0.01 uF DI + DI - 39.2 Ω 39.2 ΩRx 0.01 uF

134 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

9.0 PHYSICAL DIMENSIONS

A --- 1.60 A1 0.05 0.15 B 0 . 1 70 . 2 20 . 2 7 D 16.00 D1 14.00 E 16.00 E1 14.00 e* 0.50 L 0 . 4 50 . 6 00 . 7 5 ∝ 0.00° 7.00° * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 100L LQFP PACKAGE DRAWING E D1D e L B A

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

10.0 GLOSSARY OF TERMS

10.1 Acronyms

AUI Attachment Unit Interface CRC Cyclic Redundancy Check CS Carrier Sense CSMA/CD Carrier Sense Multiple Access with Collision Detection DA Destination Address EEPROM Electrically Erasable Programmable Read Only Memory EOF End-of-Frame FCS Frame Check Sequence FDX Full Duplex IA Individual Address IPG Inter-Packet Gap ISA Industry Standard Architecture LA ISA Latchable Addres s Bus (LA17 - LA23) LLC Logical Link Control MAC Media Access Control MAU Medium Attachment Unit MIB Management Information Base RX Receive SA Source Address or ISA System Addres s Bus (SA0 - SA19) SFD Start-of-Frame Delimiter SNMP Simple Network Management Protocol SOF Start-of-Frame SQE Signal Quality Error TDR Time Domain Reflectometer TX Transmit UTP Unshielded Twisted Pair

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Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

10.2 Definitions

The method used to compute t he 32-bit frame check sequence (FCS). Frame Check Sequence The 32-bit field at the end of a frame that contains the result of the cyclic redundancy check (CRC). Frame An Ethernet string of data bits that includes the Dest ination Address (DA), Source Address (SA), optional length fi eld, Logical Link Control data (LLC data), pad bits (if needed) and Frame C heck Sequence (FCS). Individual Address The specific Ethernet addre ss assigned to a device attac hed to the Ethernet media. Inter-Packet Gap Time interval between packets on t he Ethernet. Minimum in terval is 9.6 µ s. Jabber A condition that results when a Ethernet node transmits longer than between 20 ms and 150 ms. Packet An Ethernet string of data bits that includes the Preamble, Start- of-Frame Delimiter (SFD), Destination Address (DA), Source Address (SA), optional length field, Logical Link Control data (LLC data) , pad bits (if needed) and Frame Check Sequence (FCS). A packet is a frame pl us the Preamble and SFD. Receive Collision A receive collision occurs w hen the CI+/CI- inputs are ac tive while a packet is being received. Applies only to the AUI. Signal Quality Error When transmitting on the AUI, the MAC ex pects to see a collision signal on the CI+/CI- pair wi thin 64 bit times after the end of a tr ansmission. If no collision occurs, there is said to be an "SQE er ror". Applies only to the AUI. Slot Time Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot Time equals 512 bit times. Transmit Collision A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI- (AUI) are acti ve while a packet is being transmitted.

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

10.3 Acronyms Specific to the CS8900A

BufCFG Buffer Configur ation - Register B BufEvent Buffer Event - Register C BusCTL Bus Control - Register 17 BusST Bus State - Register 18 ENDEC Manchester encoder/decoder ISQ Interrupt Status Queue - register 0 LineCTL Ethernet Line C ontrol - Register 13 LineST Ethernet Line St atus - Register 14 RxCFG Receive Configur ation - Register 3 RxCTL Receive Control - Register 5 RxEvent Receive Event - Register 4 SelfCTL Self Control - Register 15 SelfST Self Status - Register 16 TestCTL Test Control - Register 19 TxCFG Transmit Configur ation - Register 7 TxCMD Transmit Command TxEvent Transmit Ev ent - Register 8

10.4 Definitions Specific to the CS8900A

A control bit that causes t he CS8900A to take a certain ac tion once when a logic "1" is written to that bit. To cause the acti on again, the host must rewrite a "1". Committed Receive Frame A receive frame is said to be "committed" after the fr ame has been buffered by the CS8900A, and the host has been not ified, but the frame has not yet been transferred by the host. Committed Transmit Frame A transmit frame is said to be "committed" after th e host has issued a Transmit Command, and the CS8900A has reserved buffer space and no tified the host that it is ready for transmit. Event or Interrupt Event The term "Event" is used in this document to refer to something that can trigger an interrupt. Items that are cons idered "Events" are reported in the three Event registers (RxEvent, TxEvent, or BufEvent) and in two counter-overflow bits (RxMISS and TxCOL). StreamTransfer A method used to significant ly reduce the number of inte rrupts to the host processor during block data tran sfers (Patent Pending). PacketPage A unified, highly-effi cient method of cont rolling and getting st atus of a peripheral controller in I/O or Memory space.

138 DS271F4

Crystal LAN™ Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Standby A feature of the CS8900A used to conserve power. Wh en in Standby mode, the CS8900A can be awakened either by 10B ASE-T activity or host command. Suspend A feature of the CS 8900A used to conserve power. When in Suspend mode, the CS8900A can be awakened only by host command. Transfer The term "transfer" refers to moving fram e data across the ISA bus to or from the CS8900A. Transmit Request A Transmit Request is issued by the host to initiate the st art of a new packet transmission. A Transmit Request consists of the following three steps in exactly the order shown: 1) The host writes a Transmit Command to the TxCMD register (PacketPage base + 0144h). 2) The host writes the transmit frame's lengt h to the TxLength register (PacketPage base + 0146h). 3) The host reads BusST (Register 18) to s ee in the Rdy4TxNOW bit (Bit 8) is set. 10.5 Suffixes Specific to the CS8900A. These terms have meaning only at the end of a term: A Accept CMD Command CFG Configure CTL Control Dis Disable E Enable h Indicates the number is hexadecimal iE Interrupt Enable ST Status