CS8900A

CS8900A_01 CIRRUS | Alldatasheet

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Technical content

Copyright  Cirrus Logic, Inc. 2001 (All Rights Reserved) CS8900A Product Data Sheet /G38/G85/G92/G86/G87/G68/G79/G3/G47/G36/G49™ ISA Ethernet Controller

FEATURES

I Single-Chip IEEE 802.3 Ethernet Controller with Direct ISA-Bus Interface I Maximum Current Consumption = 55 mA (5V Supply) I 3 V Operation I Industrial Temperature Range I Comprehensive Suite of Software Drivers Available I Efficient PacketPage™ Architecture Operates in I/O and Memory Space, and as DMA Slave I Full Duplex Operation I On-Chip RAM Buffers Transmit and Receive Frames I 10BASE-T Port with Analog Filters, Provides: — Automatic Polarity Detection and Correction I AUI Port for 10BASE2, 10BASE5 and 10BASE-F I Programmable Transmit Features: — Automatic Re-transmission on Collision — Automatic Padding and CRC Generation I Programmable Receive Features: — Stream Transfer™ for Reduced CPU Overhead — Auto-Switch Between DMA and On-Chip Memory — Early Interrupts for Frame Pre-Processing — Automatic Rejection of Erroneous Packets I EEPROM Support for Jumperless Configuration I Boot PROM Support for Diskless Systems I Boundary Scan and Loopback Test I LED Drivers for Link Status and LAN Activity I Standby and Suspend Sleep Modes

DESCRIPTION

The CS8900A is a low-cost Ethernet LAN Controller op- timized for Industry Standard Architecture (ISA) Personal Computers. Its highly-integrated design elimi- nates the need for costly external components required by other Ethernet controllers. The CS8900A includes on-chip RAM, 10BASE-T transmit and receive filters, and a direct ISA-Bus interface with 24 mA Drivers. In addition to high integration, the CS8900A offers a broad range of performance features and configuration- options. Its unique PacketPage architecture automatically adapts to changing network traffic pat- terns and available system resources. The result is increased system efficiency. The CS8900A is available in a 100-pin TQFP package ideally suited for small form-factor, cost-sensitive Ether- net applications. With the CS8900A, system engineers can design a complete Ethernet circuit that occupies less than 1.5 square inches (10 sq. cm) of board space.

ORDERING INFORMATION

CS8900A-CQ 0° to 70° C 5V TQFP-100 CS8900A-IQ -40 ° to 85° C 5V TQFP-100 CS8900A-CQ3 0° to 70° C 3.3V TQFP-100 CS8900A-IQ3 -40° to 85° C 3.3V TQFP-100 CRD8900A-1 Evaluation Kit EEPROM RJ-45 10BASE-T Attachment Unit Interface (AUI)

20 MHz

802.3 MAC Engine EEPROM Control Encoder/ Decoder PLL 10BASE-T RX Filters & Receiver 10BASE-T TX Filters & Transmitter AUI Transmitter AUI Collision AUI Receiver Clock Power Manager Boundary Scan Test Logic LED Control CS8900A ISA Ethernet Controller I S A DS271PP4 APR ‘01 CIRRUS LOGIC PRODUCT DATASHEET

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET TABLE OF CONTENTS

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

1.0 INTRODUCTION

1.1 General Description

The CS8900A is a true single-chip, full-duplex, Ethernet solution, incorporating all of the analog and digital circuitry needed for a complete Ethernet circuit. Major functional blocks include: a direct ISA-bus interface; an 802.3 MAC engine; integrat- ed buffer memory; a serial EEPROM interface; and a complete analog front end with both 10BASE-T and AUI.

1.1.1 Direct ISA-Bus Interface

Included in the CS8900A is a direct ISA-bus inter- face with full 24 mA drive capability. Its configu- ration options include a choice of four interrupts and three DMA channels (one of each selected dur- ing initialization). In Memory Mode, it supports Standard or Ready Bus cycles without introducing additional wait states.

1.1.2 Integrated Memory

The CS8900A incorporates a 4-Kbyte page of on- chip memory, eliminating the cost and board area associated with external memory chips. Unlike most other Ethernet controllers, the CS8900A buff- ers entire transmit and receive frames on chip, eliminating the need for complex, inefficient mem- ory management schemes. In addition, the CS8900A operates in either Memory space, I/O space, or with external DMA controllers, providing maximum design flexibility. 1.1.3 802.3 Ethernet MAC Engine The CS8900A’s Ethernet Media Access Control (MAC) engine is fully compliant with the IEEE

802.3 Ethernet standard (ISO/IEC 8802-3, 1993),

and supports full-duplex operation. It handles all aspects of Ethernet frame transmission and recep- tion, including: collision detection, preamble gen- eration and detection, and CRC generation and test. Programmable MAC features include automatic re- transmission on collision, and automatic padding of transmitted frames.

1.1.4 EEPROM Interface

The CS8900A provides a simple and efficient seri- al EEPROM interface that allows configuration in- formation to be stored in an optional EEPROM, and then loaded automatically at power-up. This eliminates the need for costly and cumbersome switches and jumpers.

1.1.5 Complete Analog Front End

The CS8900A’s analog front end incorporates a Manchester encoder/decoder, clock recovery cir- cuit, 10BASE-T transceiver, and complete Attach- ment Unit Interface (AUI). It provides manual and automatic selection of either 10BASE-T or AUI, and offers three on-chip LED drivers for link sta- tus, bus status, and Ethernet line activity. The 10BASE-T transceiver includes drivers, re- ceivers, and analog filters, allowing direct connec- tion to low-cost isolation transformers. It supports 100, 120, and 150 Ω shielded and unshielded ca- bles, extended cable lengths, and automatic receive polarity reversal detection and correction. The AUI port provides a direct interface to 10BASE-2, 10BASE-5 and 10BASE-FL networks, and is capable of driving a full 50-meter AUI cable.

1.2 System Applications

The CS8900A is designed to work well in either motherboard or adapter applications.

1.2.1 Motherboard LANs

The CS8900A requires the minimum number of external components needed for a full Ethernet node. Its small-footprint package and high level of integration allow System Engineers to design a complete Ethernet circuit that occupies as little as 1.5 square inches of PCB area (Figure 1). In addi- tion, the CS8900A’s power-saving features and CMOS design make it a perfect fit for power-sensi-

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Address and node configuration.

1.2.2 Ethernet Adapter Cards

150 Ohm twisted pair cables. tional LEDs, or as programmable outputs. Figure 1. Complete Ethernet Motherboard Solution Figure 2. Full-Featured ISA Adapter Solution

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

1.3 Key Features and Benefits

1.3.1 Very Low Cost

The CS8900A is designed to provide the lowest- cost Ethernet solution available for embedded ap- plications, portable motherboards, non-ISA bus systems and adapter cards. Cost-saving features in- clude:  Integrated RAM eliminates the need for expen- sive external memory chips.  On-chip 10BASE-T filters allow designers to use simple isolation transformers instead of more costly filter/transformer packages.  The serial EEPROM port, used for configura- tion and initialization, eliminates the need for expensive switches and jumpers.  The CS8900A is designed to be used on a 2- layer circuit board instead of a more expensive multilayer board.  The 8900A-based solution offers the smallest footprint available, saving valuable printed cir- cuit board area.  A set of certified software drivers is available at no charge, eliminating the need for costly soft- ware development.

1.3.2 High Performance

The CS8900A is a full 16-bit Ethernet controller designed to provide optimal system performance by minimizing time on the ISA bus and CPU over- head per frame. It offers equal or superior perfor- mance for less money when compared to other Ethernet controllers. The CS8900A ’s PacketPage architecture allows software to select whichever access method is best suited to each particular CPU/ISA-bus configuration. When compared to older I/O-space designs, PacketPage is faster, sim- pler and more efficient. To boost performance further, the CS8900A in- cludes several key features that increase throughput and lower CPU overhead, including:  StreamTransfer cuts up to 87% of interrupts to the host CPU during large block transfers.  Auto-Switch DMA allows the CS8900A to maximize throughput while minimizing missed frames.  Early interrupts allow the host to preprocess in- coming frames.  On-chip buffering of full frames cuts the amount of host bandwidth needed to manage Ethernet traffic.

1.3.3 Low Power and Low Noise

For low power needs, the CS8900A offers three power-down options: Hardware Standby, Hard- ware Suspend, and Software Suspend. In Standby mode, the chip is powered down with the exception of the 10BASE-T receiver, which is enabled to lis- ten for link activity. In either Hardware or Software Suspend mode, the receiver is disabled and power consumption drops to the micro-ampere range. In addition, the CS8900A has been designed for very low noise emission, thus shortening the time required for EMI testing and qualification.

1.3.4 Complete Support

The CS8900A comes with a suite of software driv- ers for immediate use with most industry standard network operating systems. In addition, complete evaluation kits and manufacturing packages are available, significantly reducing the cost and time required to produce new Ethernet products.

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10 BASE T

Figure 3. Typical Connection Diagram

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

2.0 PIN DESCRIPTION

Y SD1 SD5 SD4 SD3 SD2 DVSS4 DVDD4 SD6 SD7 LINKLED or HC0 RESET SA13 MEMW MEMR DVSS1 DVDD1 ELCS AVSS0 DVSS1A SD09 SA12 DVSS3A AVDD3 LANLED DO- DO+ DI- DI+ CI- CI+ CS8900A 100-pin TQFP (Q) Top View

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET ISA Bus Interface SA[0:19] - System Address Bus, Input PINS 37-48, 50-54, 58-60. Lower 20 bits of the 24-bit System Address Bus used to decode accesses to CS8900A I/O and Memory space, and attached Boot PROM. SA0-SA15 are used for I/O Read and Write operations. SA0-SA19 are used in conjunction with external decode logic for Memory Read and Write operations. SD[0:15] - System Data Bus, Bi-Directional with 3-State Output PINS 65-68, 71-74, 27-24, 21-18. Bi-directional 16-bit System Data Bus used to transfer data between the CS8900A and the host. RESET - Reset, Input PIN 75. Active-high asynchronous input used to reset the CS8900A. Must be stable for at least 400 ns before the CS8900A recognizes the signal as a valid reset. AEN - Address Enable, Input PIN 63. When TEST is high, this active-high input indicates to the CS8900A that the system DMA controller has control of the ISA bus. When AEN is high, the CS8900A will not perform slave I/O space operations. When TEST is low, this pin becomes the shift clock input for the Boundary Scan Test. AEN should be inactive when performing an IO or memory access and it should be active during a DMA cycle. MEMR - Memory Read, Input PIN 29. Active-low input indicates that the host is executing a Memory Read operation. MEMW - Memory Write, Input PIN 28. Active-low input indicates that the host is executing a Memory Write operation. MEMCS16 - Memory Chip Select 16-bit, Open Drain Output PIN 34. Open-drain, active-low output generated by the CS8900A when it recognizes an address on the ISA bus that corresponds to its assigned Memory space (CS8900A must be in Memory Mode with the MemoryE bit (Register 17, BusCTL, Bit A) set for MEMCS16 to go active). 3-Stated when not active. REFRESH - Refresh, Input PIN 49. Active-low input indicates to the CS8900A that a DRAM refresh cycle is in progress. When REFRESH is low, MEMR , MEMW , IOR , IOW , DMACK0 , DMACK1 , and DMACK2 are ignored. IOR - I/O Read, Input PIN 61. When IOR is low and a valid address is detected, the CS8900A outputs the contents of the selected 16-bit I/O register onto the System Data Bus. IOR is ignored if REFRESH is low. IOW - I/O Write, Input PIN 62. When IOW is low and a valid address is detected, the CS8900A writes the data on the System Data Bus into the selected 16-bit I/O register. IOW is ignored if REFRESH is low.

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET IOCS16 - I/O Chip Select 16-bit, Open Drain Output PIN 33. Open-drain, active-low output generated by the CS8900A when it recognizes an address on the ISA bus that corresponds to its assigned I/O space. 3-Stated when not active. IOCHRDY - I/O Channel Ready, Open Drain Output PIN 64. When driven low, this open-drain, active-high output extends I/O Read and Memory Read cycles to the CS8900A. This output is functional when the IOCHRDYE bit in the Bus Control register (Register 17) is clear. This pin is always 3-Stated when the IOCHRDYE bit is set. SBHE - System Bus High Enable, Input PIN 36. Active-low input indicates a data transfer on the high byte of the System Data Bus (SD8- SD15). After a hardware or a software reset, provide a HIGH to LOW and then LOW to HIGH transition on SBHE signal before any IO or memory access is done to the CS8900A. INTRQ[0:3] - Interrupt Request, 3-State PINS 30-32, 35. Active-high output indicates the presence of an interrupt event. Interrupt Request goes low once the Interrupt Status Queue (ISQ) is read as all 0 ’s. Only one Interrupt Request output is used (one is selected during configuration). All non-selected Interrupt Request outputs are placed in a high-impedance state. (Section 3.2 on page 17 and Section 5.1 on page 78.) DMARQ[0:2] - DMA Request, 3-State PINS 11, 13, and 15. Active-high, 3-Stateable output used by the CS8900A to request a DMA transfer. Only one DMA Request output is used (one is selected during configuration). All non-selected DMA Request outputs are placed in a high-impedance state. DMACK [0:2] - DMA Acknowledge, Input PINS 12, 14, and 16. Active-low input indicates acknowledgment by the host of the corresponding DMA Request output. CHIPSEL - Chip Select, Input PIN 7. Active-low input generated by external Latchable Address bus decode logic when a valid memory address is present on the ISA bus. If Memory Mode operation is not needed, CHIPSEL should be tied low. The CHIPSEL is ignored for IO and DMA mode of the CS8900A. EEPROM and Boot PROM Interface EESK - EEPROM Serial Clock, PIN 4. Serial clock used to clock data into or out of the EEPROM. EECS - EEPROM Chip Select, PIN 3. Active-high output used to select the EEPROM.

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET EEDataIn - EEPROM Data In, Input Internal Weak Pullup PIN 6. Serial input used to receive data from the EEPROM. Connects to the DO pin on the EEPROM. EEDataIn is also used to sense the presence of the EEPROM. ELCS - External Logic Chip Select, Internal Weak Pullup PIN 2. Bi-directional signal used to configure external Latchable Address (LA) decode logic. If external LA decode logic is not needed, ELCS should be tied low. EEDataOut - EEPROM Data Out,PIN 5. Serial output used to send data to the EEPROM. Connects to the DI pin on the EEPROM. When TEST is low, this pin becomes the output for the Boundary Scan Test. CSOUT - Chip Select for External Boot PROM, PIN 17. Active-low output used to select an external Boot PROM when the CS8900A decodes a valid Boot PROM memory address. 10BASE-T Interface TXD+/TXD- - 10BASE-T Transmit, Differential Output Pair PINS 87 and 88. Differential output pair drives 10 Mb/s Manchester-encoded data to the 10BASE-T transmit pair. RXD+/RXD- - 10BASE-T Receive, Differential Input Pair PINS 91 and 92. Differential input pair receives 10 Mb/s Manchester-encoded data from the 10BASE-T receive pair. Attachment Unit Interface (AUI) DO+/DO- - AUI Data Out, Differential Output Pair PINS 83 and 84. Differential output pair drives 10 Mb/s Manchester-encoded data to the AUI transmit pair. DI+/DI- - AUI Data In, Differential Input Pair PINS 79 and 80. Differential input pair receives 10 Mb/s Manchester-encoded data from the AUI receive pair. CI+/CI- - AUI Collision In, Differential Input Pair PINS 81 and 82. Differential input pair connects to the AUI collision pair. A collision is indicated by the presence of a 10 MHz ± 15% signal with duty cycle no worse than 60/40. General Pins XTAL[1:2] - Crystal, Input/Output PINS 97 and 98. A 20 MHz crystal should be connected across these pins. If a crystal is not used, a 20 MHz signal should be connected to XTAL1 and XTAL2 should be left open. (See Section 7.3 on page 110 and Section 7.7 on page 120.)

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET SLEEP - Hardware Sleep, Input Internal Weak Pullup PIN 77. Active-low input used to enable the two hardware sleep modes: Hardware Suspend and Hardware Standby. (See Section 3.7 on page 25.) LINKLED or HC0 - Link Good LED or Host Controlled Output 0, Open Drain Output PIN 99. When the HCE0 bit of the Self Control register (Register 15) is clear, this active-low output is low when the CS8900A detects the presence of valid link pulses. When the HC0E bit is set, the host may drive this pin low by setting the HCBO in the Self Control register. BSTATUS or HC1 - Bus Status or Host Controlled Output 1, Open Drain Output PIN 78. When the HC1E bit of the Self Control register (Register 15) is clear, this active-low output is low when receive activity causes an ISA bus access. When the HC1E bit is set, the host may drive this pin low by setting the HCB1 in the Self Control register. LANLED - LAN Activity LED, Open Drain Output PIN 100. During normal operation, this active-low output goes low for 6 ms whenever there is a receive packet, a transmit packet, or a collision. During Hardware Standby mode, this output is driven low when the receiver detects network activity. TEST - Test Enable, Input Internal Weak Pullup PIN 76. Active-low input used to put the CS8900A in Boundary Scan Test mode. For normal operation, this pin should be high. RES - Reference Resistor, Input PIN 93. This input should be connected to a 4.99K Ω ± 1% resistor needed for biasing of internal analog circuits. DVDD[1:4] - Digital Power, Power PINS 9, 22, 56, and 69. Provides 5 V ± 5% power to the digital circuits of the CS8900A. DVSS[1:4} and DVSS1A, DVSS3A - Digital Ground, Ground PINS 8, 10, 23, 55, 57, and 70. Provides ground reference (0 V) to the digital circuits of the CS8900A. A VDD[1:3] - Analog Power, Power PINS 90, 85, and 95. Provides 5 V ± 5% power to the analog circuits of the CS8900A. A VSS[0:4] - Analog Ground, Ground PINS 1, 89, 86, 94, 96. Provide ground reference (0 V) to the analog circuits of the CS8900A.

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

3.0 FUNCTIONAL DESCRIPTION

3.1 Overview

During normal operation, the CS8900A performs two basic functions: Ethernet packet transmission and reception. Before transmission or reception is possible, the CS8900A must be configured.

3.1.1 Configuration

The CS8900A must be configured for packet trans- mission and reception at power-up or reset. Various parameters must be written into its internal Config- uration and Control registers such as Memory Base Address; Ethernet Physical Address; what frame types to receive; and which media interface to use. Configuration data can either be written to the CS8900A by the host (across the ISA bus), or load- ed automatically from an external EEPROM. Oper- ation can begin after configuration is complete. Section 3.3 on page 18 and Section 3.4 on page 20 describe the configuration process in detail. Section 4.4 on page 46 provides a detailed descrip- tion of the bits in the Configuration and Control Registers.

3.1.2 Packet Transmission

Packet transmission occurs in two phases. In the first phase, the host moves the Ethernet frame into the CS8900A’s buffer memory. The first phase be- gins with the host issuing a Transmit Command. This informs the CS8900A that a frame is to be transmitted and tells the chip when to start trans- mission (i.e. after 5, 381, 1021 or all bytes have been transferred) and how the frame should be sent (i.e. with or without CRC, with or without pad bits, etc.). The Host follows the Transmit Command with the Transmit Length, indicating how much buffer space is required. When buffer space is available, the host writes the Ethernet frame into the CS8900A’s internal memory, either as a Mem- ory or I/O space operation. In the second phase of transmission, the CS8900A converts the frame into an Ethernet packet then transmits it onto the network. The second phase be- gins with the CS8900A transmitting the preamble and Start-of-Frame delimiter as soon as the proper number of bytes has been transferred into its trans- mit buffer (5, 381, 1021 bytes or full frame, de- pending on configuration). The preamble and Start- of-Frame delimiter are followed by the Destination Address, Source Address, Length field and LLC data (all supplied by the host). If the frame is less than 64 bytes, including CRC, the CS8900A adds pad bits if configured to do so. Finally, the CS8900A appends the proper 32-bit CRC value. The Section 5.7 on page 98 provides a detailed de- scription of packet transmission.

3.1.3 Packet Reception

Like packet transmission, packet reception occurs in two phases. In the first phase, the CS8900A re- ceives an Ethernet packet and stores it in on-chip memory. The first phase of packet reception begins with the receive frame passing through the analog front end and Manchester decoder where Manches- ter data is converted to NRZ data. Next, the pream- ble and Start-of-Frame delimiter are stripped off and the receive frame is sent through the address filter. If the frame ’s Destination Address matches the criteria programmed into the address filter, the packet is stored in the CS8900A ’s internal memo- ry. The CS8900A then checks the CRC, and de- pending on the configuration, informs the processor that a frame has been received. In the second phase, the host transfers the receive frame across the ISA bus and into host memory. Receive frames can be transferred as Memory space operations, I/O space operations, or as DMA operations using host DMA. Also, the CS8900A provides the capability to switch between Memory or I/O operation and DMA operation by using Auto-Switch DMA and StreamTransfer. The Section 5.2 on page 78 through Section 5.6 on page 95 provide a detailed description of packet re- ception.

3.2 ISA Bus Interface

a description of Receive DMA operation.

3.2.1 Memory Mode Operation

3.2.2 I/O Mode Operation

must be low, and for a Write, IOW must be low.

3.2.3 Interrupt Request Signals

3.2.4 DMA Signals

frames from CS8900A memory to host memory. DMA pins are placed in a high-impedance state. Table 1. Interrupt Assignments

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the start of a DMA transfer.

3.3 Reset and Initialization

3.3.1 Reset

reset its internal registers and circuits.

3.3.1.1 External Reset, or ISA Reset

all circuitry and registers in the CS8900A are reset.

3.3.1.2 Power-Up Reset

and the crystal oscillator has stabilized.

3.3.1.3 Power-Down Reset

crystal oscillator has stabilized.

3.3.1.4 EEPROM Reset

sum error is detected (see Section 3.4 on page 20).

3.3.1.5 Software Initiated Reset

(Register 15, SelfCTL, Bit 6) is set.

3.3.1.6 Hardware (HW) Standby or Suspend

3.3.1.7 Software (SW) Suspend

3.3.2 Allowing Time for Reset Operation

PROM is no longer being read or programmed.

3.3.3 Bus Reset Considerations

Table 2. DMA Assignments

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET After a reset, the ISA bus outputs INTRx and DMARQx are 3-Stated, thus avoiding any interrupt or DMA channel conflicts on the ISA bus at power- up time.

3.3.4 Initialization

After each reset (except EEPROM Reset), the CS8900A checks the sense of the EEDataIn pin to see if an external EEPROM is present. If EEDI is high, an EEPROM is present and the CS8900A au- tomatically loads the configuration data stored in the EEPROM into its internal registers (see next section). If EEDI is low, an EEPROM is not present and the CS8900A comes out of reset with the default configuration shown in Table 3. A low-cost serial EEPROM can be used to store configuration information that is automatically loaded into the CS8900A after each reset (except EEPROM reset). The use of an EEPROM is op- tional. The CS8900A operates with any of six standard EEPROM’s shown in Table 4. PacketPage Address Register

Contents

0020h 0300h I/O Base Address* 0022h XXXX XXXX XXXX X100 Interrupt Number 0024h XXXX XXXX XXXX XX11 DMA Channel 0026h 0000h DMA Start of Frame Offset 0028h X000h DMA Frame Count 002Ah 0000h DMA Byte Count 002Ch XXX0 0000h Memory Base Address 0030h XXX0 0000h Boot PROM Base Address 0034h XXX0 0000h Boot PROM Address Mask 0102h 0003h Register 3 - RxCFG 0104h 0005h Register 5 - RxCTL 0106h 0007h Register 7 - TxCFG 0108h 0009h Register 9 - TxCMD 010Ah 000Bh Register B - BufCFG 010Ch Undefined Reserved 010Eh Undefined Reserved 0110h Undefined Reserved 0112h 00013h Register 13 - LineCTL 0114h 0015h Register 15 - SelfCTL 0116h 0017h Register 17 - BusCTL 0118h 0019h Register 19 - TestCTL * I/O base address is unaffected by Software Suspend mode. Table 3. Default Configuration Table 4. Supported EEPROM Types

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3.4 Configurations with EEPROM

3.4.1 EEPROM Interface

3.4.2 EEPROM Memory Organization

taining user data may be stored in the EEPROM.

3.4.3 Reset Configuration Block

PROM). Address space 80h to AFh is reserved.

3.4.3.1 Reset Configuration Block Structure

in some cases) with an initial non-default value.

3.4.3.2 Reset Configuration Block Header

3.4.3.3 Determining the EEPROM Type

3.4.3.4 Checking EEPROM for presence of Reset

Table 5. EEPROM Interface

3.4.3.5 Determining Number of Bytes in the Reset

calculating the Link Byte value.

3.4.4 Groups of Configuration Data

data that are to be loaded into PacketPage registers. 00h A120h Configuration Block Header. 01h 2020h Group Header for first group of words. Three words to be loaded, beginning at 0020h in PacketPage memory. 05h 502Ch Group Header for second group of words. Six words to be loaded, beginning at 002Ch in PacketPage memory. 0Ch 2158h Group Header for third group of words. Three words to be loaded, beginning at 0158 in PacketPage memory. provides a pad to the word boundary.

• FFFFh is a special code indicating that there are no more words in the EEPROM.

Table 6. EEPROM Configuration Block Example

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3.4.4.1 Group Header

first word of configuration data from the group. shows the format of the Group header.

3.4.5 Reset Configuration Block Checksum

3.4.6 EEPROM Example

3.4.7 EEPROM Read-out

3) Clocking the data in on EEDI. out (uses its default configuration).

3.4.7.1 Determining EEPROM Size

Figure 4. Group Header

3.4.7.2 Loading Configuration Data

3.4.8 EEPROM Read-out Completion

sulting total is 0, the read-out is considered valid. restore the default configuration.

3.5 Programming the EEPROM

format of the EEPROM Command register.

3.5.1 EEPROM Commands

Erase/Write Disable, Erase-All, and Write-All. They are described in Table 7.

3.5.2 EEPROM Command Execution

Figure 5. EEPROM Command Register Format [A] ELSEL External Logic Select: When clear, the EECS pin is used to select the EEPROM. When set, the ELCS pin is used to select the external LA decode circuit. [9:8] OP1, OP0 Opcode: Indicates what command is being executed (see next section). [7:0] AD7 to AD0 EEPROM Address: Address of EEPROM word being accessed.

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location is written into the EEPROM Data register. transferred to or from the EEPROM Data register. host must wait again for SIBUSY to clear.

3.5.3 Enabling Access to the EEPROM

ed modification of the EEPROM.

3.5.4 Writing and Erasing the EEPROM

1) Issue an Erase/Write Enable command . 2) Load the data into the EEPROM Data register. 4) Issue an Erase/Write Disable command.

3.6 Boot PROM Operation

3.6.1 Accessing the Boot PROM

the data out onto the ISA bus.

3.6.2 Configuring the CS8900A for Boot PROM

Table 7. EEPROM Commands

host memory from D0000h to D3FFFh.

3.7 Low-Power Modes

3.7.1 Hardware Standby

Ethernet operation once the cable is reconnected. ISA bus accesses are ignored. reset, and then goes through normal initialization.

3.7.2 Hardware Suspend

bus and Ethernet activity are both ignored. Figure 6. Boot PROM Connection Diagram

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3.7.3 Software Suspend

do not have power management circuitry available. Notes: 1. Both HW and HW Suspend take precedence over SW Suspend. Table 8. Low-Power Mode Operation

3.8 LED Outputs

be used to control LEDs or external logic.

3.8.0.1 LANLED

3.8.0.2 LINKLED

bit (Register 15, SelfCTL, Bit C) must be clear. bit must be set. Table 9 summarizes this operation.

3.8.0.3 BSTATUS

3.8.1 LED Connection

3.9 Media Access Control

3.9.1 Overview

10 Pin configured as HC0

11 Pin configured as HC0:

Table 9. LINKLED/HC0 Pin Operation

10 Pin configured as HC1

11 Pin configured as HC1:

Table 10. BSTATUS/HCI Pin Operation Figure 7. LED Connection Diagram

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internal Manchester encoder/decoder (ENDEC). handling; and, media access management.

3.9.2 Frame Encapsulation and Decapsulation

frames are of legal minimum size.

3.9.2.1 Transmission

then transmits the Frame Check Sequence (FCS). CRC bit (Register 9, TxCMD, bit C). Figure 9 shows the Ethernet frame format.

3.9.2.2 Reception

er/decoder. It begins by checking for the SFD.

3.9.2.3 Enforcing Minimum Frame Size

Figure 8. MAC Interface Figure 9. Ethernet Frame Format

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET ment of both transmit and receive packets. When the TxPadDis bit (Register 9, TxCMD, Bit D) is clear, transmit frames will be padded with addition- al bits to ensure that the receiving station receives a legal frame (64 bytes, including CRC). When Tx- PadDis is set, the CS8900A will not add pad bits and will transmit frames less that 64 bytes. If a frame is received that is less than 64 bytes (includ- ing CRC), the Runt bit (Register 4, RxEvent, Bit D) will be set indicating the arrival of an illegal frame.

3.9.3 Transmit Error Detection and Handling

The MAC engine monitors Ethernet activity and reports and recovers from a number of error condi- tions. For transmission, the MAC reports the fol- lowing errors in the TxEvent register (Register 8) and BufEvent register (Register C):

3.9.3.1 Loss of Carrier

Whenever the CS8900A is transmitting on the AUI port, it expects to see its own transmission "looped back" to its receiver. If it is unable to monitor its transmission after the end of the preamble, the MAC reports a loss-of-carrier error by setting the Loss-of-CRS bit (Register 8, TxEvent, Bit 6). If the Loss-of-CRSiE bit (Register 7, TxCFG, Bit 6) is set, the host will be interrupted.

3.9.3.2 SQE Error

After the end of transmission on the AUI port, the MAC expects to see a collision within 64 bit times. If no collision is detected, the SQEerror bit (Regis- ter 8, TxEvent, Bit 7) is set. If the SQEerroriE bit is set (Register 7, TxCFG, Bit 7), the host is interrupt- ed. An SQE error may indicate a fault on the AUI cable or a faulty transceiver (it is assumed that the attached transceiver supports this function).

3.9.3.3 Out-of-Window (Late) Collision

If a collision is detected after the first 512 bits have been transmitted, the MAC reports a late collision by setting the Out-of-window bit (Register 8, Tx- Event, Bit 9). The MAC then forces a bad CRC and terminates the transmission. If the Out-of-window- iE bit (Register 7, TxCFG, Bit 9) is set, the host is interrupted. A late collision may indicate an illegal network configuration.

3.9.3.4 Jabber Error

If a transmission continues longer than about 26 ms, the MAC disables the transmitter and sets the Jabber bit (Register 8, TxEvent, Bit A). The output of the transmitter returns to idle and remains there until the host issues a new Transmit Com- mand. If the JabberiE bit (Register 7, TxCFG, Bit A) is set, the host is interrupted. A Jabber condition indicates that there may be something wrong with the CS8900A transmit function. To prevent possi- ble network faults, the host should clear the trans- mit buffer. Possible options include: Reset the chip with either software or hardware re- set (see Section 3.3 on page 18). Issue a Force Transmit Command by setting the Force bit (Register 9, TxCMD, bit 8). Issue a Transmit Command with the TxLength field set to zero.

3.9.3.5 Transmit Collision

The MAC counts the number of times an individual packet must be retransmitted due to network colli- sions. The collision count is stored in bits B through E of the TxEvent register (Register 8). If the packet collides 16 times, transmission of that packet is terminated and the 16coll bit (Register 8, TxEvent, Bit F) is set. If the 16colliE bit (Register 7, TxCFG, Bit F) is set, the host will be interrupted on the 16th collision. A running count of transmit collisions is recorded in the TxCOL register.

3.9.3.6 Transmit Underrun

If the CS8900A starts transmission of a packet but runs out of data before reaching the end of frame, the TxUnderrun bit (Register C, BufEvent, Bit 9) is set. The MAC then forces a bad CRC and termi- nates the transmission. If the TxUnderruniE bit

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET (Register B, BufCFG, Bit 9) is set, the host is inter- rupted.

3.9.4 Receive Error Detection and Handling

The following receive errors are reported in the Rx- Event register (Register 4):

3.9.4.1 CRC Error

If a frame is received with a bad CRC, the CRCer- ror bit (Register 4, RxEvent, Bit C) is set. If the CRCerrorA bit (Register 5, RxCTL, Bit C) is set, the frame will be buffered by CS8900A. If the CRCerroriE bit (Register 3, RxCFG. Bit C) is set, the host is interrupted.

3.9.4.2 Runt Frame

If a frame is received that is shorter than 64 bytes, the Runt bit (Register 4, RxEvent, Bit D) is set. If the RuntA bit (Register 5, RxCTL, Bit D) is set, the frame will still be buffered by CS8900A. If the RuntiE bit (Register 3, RxCFG. Bit D) is set, the host is interrupted.

3.9.4.3 Extra Data

If a frame is received that is longer than 1518 bytes, the Extradata bit (Register 4, RxEvent, Bit E) is set. If the ExtradataA bit (Register 5, RxCTL, Bit E) is set, the first 1518 bytes of the frame will still be buffered by CS8900A. If the ExtradataiE bit (Reg- ister 3, RxCFG. Bit E) is set, the host is interrupted.

3.9.4.4 Dribble Bits and Alignment Error

Under normal operating conditions, the MAC may detect up to 7 additional bits after the last full byte of a receive packet. These bits, known as dribble bits, are ignored. If dribble bits are detected, the Dribblebit bit (Register 4, RxEvent, Bit 7) is set. If both the Dribblebits bit and CRCerror bit (Register 4, RxEvent, Bit C) are set at the same time, an alignment error has occurred.

3.9.5 Media Access Management

The Ethernet network topology is a single shared medium with several attached stations. The Ether- net protocol is designed to allow each station equal access to the network at any given time. Any node can attempt to gain access to the network by first completing a deferral process (described below) af- ter the last network activity, and then transmitting a packet that will be received by all other stations. If two nodes transmit simultaneously, a collision oc- curs and the colliding packets are corrupted. Two primary tasks of the MAC are to avoid network col- lisions, and then recover from them when they oc- cur. In addition, when the CS8900A is using the AUI, the MAC must support the SQE Test function described in section 7.2.4.6 of the Ethernet stan- dard.

3.9.5.1 Collision Avoidance

The MAC continually monitors network traffic by checking for the presence of carrier activity (carrier activity is indicated by the assertion of the internal Carrier Sense signal generated by the ENDEC). If carrier activity is detected, the network is assumed busy and the MAC must wait until the current packet is finished before attempting transmission. The CS8900A supports two schemes for determin- ing when to initiate transmission: Two-Part Defer- ral, and Simple Deferral. Selection of the deferral scheme is determined by the 2-partDefDis bit (Register 13, LineCTL, Bit D). If the 2-partDefDis bit is clear, the MAC uses a two-part deferral pro- cess defined in section 4.2.3.2.1 of the Ethernet standard (ISO/IEC 8802-3, 1993). If the 2-partDef- Dis bit is set, the MAC uses a simplified deferral scheme. Both schemes are described below:

3.9.5.2 Two-Part Deferral

In the two-part deferral process, the 9.6 µs Inter Packet Gap (IPG) timer is started whenever the in- ternal Carrier Sense signal is deasserted. If activity is detected during the first 6.4 µs of the IPG timer, the timer is reset and then restarted once the activi- ty has stopped. If there is no activity during the first 6.4 µs of the IPG timer, the IPG timer is allowed to time out (even if network activity is detected during

Backoff (Backoff is described later in this section). grams the two-part deferral process.

3.9.5.3 Simple Deferral

ure 11 diagrams the simple deferral process.

3.9.5.4 Collision Resolution

3.9.5.5 Normal Collisions

mits the jam sequence, and then initiates Backoff. plus 15 retransmissions) due to normal collisions. packet without attempting any retransmission. Figure 10. Two-Part Deferral

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3.9.5.6 Late Collisions

Out-of-Window Error in this section.

3.9.5.7 Backoff

3.9.5.8 Standard Backoff

number of retransmission attempts.

3.9.5.9 Modified Backoff

number of retransmission attempts. the network for the first three retries.

3.9.5.10 SQE Test

Figure 11. Simple Deferral

3.10 Encoder/Decoder (ENDEC)

data from incoming Manchester-encoded data.

3.10.1 Encoder

3.10.2 Carrier Detection

Bit E) reports the state of the Carrier Sense signal.

3.10.3 Clock and Data Recovery

Figure 12. ENDEC

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3.10.4 Interface Selection

scribes the possible configurations. ENDEC are active, and the AUI is powered down.

3.10.4.2 AUI Only

10BASE-T transceiver is powered down.

3.10.4.3 Auto-Select

ed, the CS8900A switches back to 10BASE-T. Section 7.5 on page 119 for a connection diagram).

1 N/A AUI Only

Table 11. Interface Selection Figure 13. 10BASE-T Transceiver

3.11.2 Transmitter

plified and driven out of the TXD+/TXD- pins. the operation of the Link Pulse Generator. (Test Control register) is set to one.

3.11.3 Receiver

correction circuit, and link pulse detector.

3.11.3.1 Squelch Circuit

3.11.3.2 Extended Range

imum length specified by the Ethernet standard). (Register 13, LineCTL, Bit E).

3.11.4 Link Pulse Detection

Figure 14. Link Pulse Transmission

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receive packets independent of the link segment.

3.11.5 Receive Polarity Detection and Correction

bit is set, the CS8900A does not correct a reversal.

3.11.6 Collision Detection

Section 3.9 on page 27 for collision handling).

3.12 Attachment Unit Interface (AUI)

10BASE5, and 10BASE-FL Ethernet transceivers. of driving a full 50-meter AUI cable. the previous section (Section 3.10.4 on page 34). Figure 15 provides a block diagram of the AUI.

3.12.1 AUI Transmitter

Figure 15. AUI

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET sion, or if the Carrier Sense signal is deasserted before the end of the transmission, there is a Loss- of-Carrier error and the Loss-of-CRS bit (Register 8, TxEvent, Bit 6) is set.

3.12.2 AUI Receiver

The AUI receiver is a differential pair circuit that connects directly to the DI+/DI- pins. It is designed to distinguish between transient noise pulses and incoming Ethernet packets. Incoming packets with proper amplitude and pulse width are passed on to the ENDEC section, while unwanted noise is re- jected.

3.12.3 Collision Detection

The AUI collision circuit is a differential pair re- ceiver that detects the presence of collision signals on the CI+/CI- pins. The collision signal is generat- ed by an external Ethernet transceiver whenever a collision is detected on the Ethernet segment. (Sec- tion 7.3.1.2 of ISO/IEC 8802-3, 1993, defines the collision signal as a 10 MHz ± 15% signal with a duty cycle no worse than 60/40). When a collision is present, the AUI Collision circuit informs the MAC by asserting the internal Collision signal.

3.13 External Clock Oscillator

A 20-MHz quartz crystal or CMOS clock input is required by the CS8900A. If a CMOS clock input is used, it should be connected the to XTAL1 pin, with the XTAL2 pin left open. The clock signal should be 20 MHz ±0.01% with a duty cycle be- tween 40% and 60%. The specifications for the crystal are described in Section 7.7 on page 120.

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.0 PACKETPAGE ARCHITECTURE

4.1 PacketPage Overview

The CS8900A architecture is based on a unique, highly-efficient method of accessing internal regis- ters and buffer memory known as PacketPage. PacketPage provides a unified way of controlling the CS8900A in Memory or I/O space that mini- mizes CPU overhead and simplifies software. It provides a flexible set of performance features and configuration options, allowing designers to devel- op Ethernet circuits that meet their particular sys- tem requirements.

4.1.1 Integrated Memory

Central to the CS8900A architecture is a 4-Kbyte page of integrated RAM known as PacketPage memory. PacketPage memory is used for tempo- rary storage of transmit and receive frames, and for internal registers. Access to this memory is done directly, through Memory space operations (Section 4.9 on page 73), or indirectly, through I/O space operations (Section 4.10 on page 75). In most cases, Memory Mode will provide the best overall performance, because ISA Memory opera- tions require fewer cycles than I/O operations. I/O Mode is the CS8900A ’s default configuration and is used when memory space is not available or when special operations are required (e.g. waking the CS8900A from the Software Suspend State re- quires the host to write to the CS8900A’s assigned I/O space). The user-accessible portion of PacketPage memory is organized into the following six sections:

4.1.2 Bus Interface Registers

The Bus Interface registers are used to configure the CS8900A’s ISA-bus interface and to map the CS8900A into the host system ’s I/O and Memory space. Most of these registers are written only dur- ing initialization, remaining unchanged while the CS8900A is in normal operating mode. The excep- tions to this are the DMA registers which are mod- ified continually whenever the CS8900A is using DMA. These registers are described in more detail in Section 4.3 on page 41.

4.1.3 Status and Control Registers

The Status and Control registers are the primary means of controlling and getting status of the CS8900A. They are described in more detail in Section 4.4 on page 46.

4.1.4 Initiate Transmit Registers

The TxCMD/TxLength registers are used to initiate Ethernet frame transmission. These registers are described in more detail in Section 4.5 on page 70. (See Section 5.7 on page 98 for a description of frame transmission.)

4.1.5 Address Filter Registers

The Filter registers store the Individual Address fil- ter and Logical Address filter used by the Destina- tion Address (DA) filter. These registers are described in more detail in Section 4.6 on page 71. For a description of the DA filter, see Section 5.3 on page 86.

4.1.6 Receive and Transmit Frame Locations

The Receive and Transmit Frame PacketPage loca- tions are used to transfer Ethernet frames to and from the host. The host simply writes to and reads from these locations and internal buffer memory is dynamically allocated between transmit and re- ceive as needed. This provides more efficient use of buffer memory and better overall network per- formance. As a result of this dynamic allocation, only one receive frame (starting at PacketPage base + 0400h) and one transmit frame (starting at Pack- PacketPage Address 0000h - 0045h Bus Interface Registers 0100h - 013Fh Status and Control Registers 0140h - 014Fh Initiate Transmit Registers 0150h - 015Dh Address Filter Registers 0400h Receive Frame Location 0A00h Transmit Frame Location

4.2 PacketPage Memory Map

Notes: 1. All registers are accessed as words only.

1. Read operation from the reserved location provides undefined data. Writing to a reserved location or

undefined bits may result in unpredictable operation of the CS8900A. Table 12. PacketPage Memory Address Map

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Notes: 1. All registers are accessed as words only.

1. Read operation from the reserved location provides undefined data. Writing to a reserved location or

undefined bits may result in unpredictable operation of the CS8900A. Table 12. PacketPage Memory Address Map (continued)

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.3 Bus Interface Registers

4.3.1 Product Identification Code

(Read only, Address: PacketPage base + 0000h) The Product Identification Code Register is located in the first four bytes of the PacketPage (0000h to 0003h). The register contains a unique 32-bit product ID code that identifies the chip as a CS8900A. The host can use this num- ber to determine which software driver to load and to check which features are available. Reset value is: 0000 1110 0110 0011 0000 0000 000X XXXX The X XXXX codes for the CS8900A are: Rev B: 0 0111 Rev C: 0 1000 Rev D: 0 1001

4.3.2 I/O Base Address

(Read/Write, Address: PacketPage base + 0020h) The I/O Base Address Register describes the base address for the sixteen contiguous locations in the host system’s I/O space, which are used to access the PacketPage registers. See Section 4.10 on page 75. The default location is 0300h. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0011 0000 0000 Address 0000h Address 0001h Address 0002h Address 00003h First byte of EISA registration number for Crystal Semiconductor Second byte of EISA registration number for Crys- tal Semiconductor First 8 bits of Product ID number Last 3 bits of the Product ID number (5 “X” bits are the revi- sion number) Address 0021h Address 0020h Most significant byte of I/O Base Address Least significant byte of I/O Base Address

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.3.3 Interrupt Number

(Read/Write, Address: PacketPage base + 0022h) The Interrupt Number Register defines the interrupt pin selected by the CS8900A. In a typical application the follow- ing bus signals are tied to the following pins: See Section 3.2 on page 17. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state, which corre- sponds to placing all the INTRQ pins in a high-impedance state. If an EEPROM is found, then the register ’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: XXXX XXXX XXXX X100

4.3.4 DMA Channel Number

(Read/Write, Address: PacketPage base + 0024h) The DMA Channel register defines the DMA pins selected by the CS8900A. In the typical application, the following bus signals are tied to the following pins: See Section 3.2 on page 17 and Section 5.4 on page 89. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state which corre- sponds to setting all DMRQ pins to high-impedance. If a EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: XXXX XXXX XXXX XX11 Address 0023h Address 0022h 00h Interrupt number assignment: 0000 0000b= pin INTRQ0 0000 0001b= pin INTRQ1 0000 0010b= pin INTRQ2 0000 0011b= pin INTRQ3 0000 01XXb= All INTRQ pins high-impedance Bus signal Typical pin connection IRQ5 INTRQ3 IRQ10 INTRQ0 IRQ11 INTRQ1 IRQ12 INTRQ2 Address 0025h Address 0024h 00h DMA channel assignment: 0000 0000b= pin DMRQ0 and DMACK0 0000 0001b= pin DMRQ1 and DMACK1 0000 0010b= pin DMRQ2 and DMACK2 0000 0011b= All DMRQ pins high-impedance Bus signal Typical pin connection DRQ5 DACK5 DMRQ0 DMACK0 DRQ6 DACK6 DMRQ1 DMACK1 DRQ7 DACK7 DMRQ2 DMACK2

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.3.5 DMA Start of Frame

(Read only, Address: PacketPage base + 0026h) The DMA Start of Frame Register contains a 16-bit value which defines the offset from the DMA base address to the start of the most recently transferred received frame. See Section 5.4 on page 89. Reset value is: 0000 0000 0000 0000

4.3.6 DMA Frame Count

(Read only, Address: PacketPage base + 0028h) The lower 12 bits of the DMA Frame Count register define the number of valid frames transferred via DMA since the last readout of this register. The upper 4 bits are reserved. See Section 5.4 on page 89. Reset value is: XXXX 0000 0000 0000

4.3.7 RxDMA Byte Count

(Read only, Address: PacketPage base + 002Ah) The RxDMA Byte Count register describes the valid number of bytes DMAed since the last readout. See Section 5.4 on page 89. Reset value is: 0000 0000 0000 0000

4.3.8 Memory Base Address

(Read/Write, Address: PacketPage base + 002Ch) Memory Base Address: The lower three bytes (002Ch, 002Dh, and 002Eh) are used for the 20-bit memory base address. The upper three nibbles are reserved. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000 Address 0027h Address 0026h Most significant byte of offset value Least significant byte of offset value Address 0029h Address 0028h Most significant byte of frame count (most-significant nibble always 0h) Least significant byte of frame count Address 002Bh Address 002Ah Most significant byte of byte count Least significant byte of byte count Address 002Fh Address 002Eh Address 002Dh Address 002Ch Reserved The most significant nibble of memory base address. The high-order nibble is reserved. Contains portion of memory base address. The least significant byte of the memory base address.

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.3.9 Boot PROM Base Address

(Read/Write, Address: PacketPage base + 0030h) The lower three bytes (0030h, 0031h, and 0032h) of the Boot PROM Base Address register are used for the 20-bit Boot PROM base address. The upper three nibbles are reserved. See Section 3.6 on page 24. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000

4.3.10 Boot PROM Address Mask

(Read/Write, Address: PacketPage base + 0034h) The Boot PROM address mask register indicates the size of the attached Boot PROM and is limited to 4K bit incre- ments. The lower 12 bits of the Address Mask are ignored, and should be 000h. The next lowest-order bits describe the size of the PROM. The upper three nibbles are reserved. For example: See Section 3.6 on page 24. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: XXXX XXXX XXXX 0000 0000 0000 0000 0000 Address 0033h Address 0032h Address 0031h Address 0030h Reserved The most significant nibble of Boot PROM base address. The high-order nibble is reserved. Contains portion of Boot PROM base address. The least significant byte of the Boot PROM base address. Address 0037h Address 0036h Address 0035h Address 0034h Reserved The most significant nibble of Boot PROM mask address. The high-order nibble is reserved. Contains portion of Boot PROM mask address. The lower-order nibble must be written as 0h. The least significant byte of the Boot PROM mask address. Must be written as 00h. Size of Boot PROM Register value 4k bits XXXX XXXX XXXX 1111 1111 0000 0000 0000 8k bits XXXX XXXX XXXX 1111 1110 0000 0000 0000 16k bits XXXX XXXX XXXX 1111 1100 0000 0000 0000

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.3.11 EEPROM Command

(Read/Write, Address: PacketPage base + 0040h) This register is used to control the reading, writing and erasing of the EEPROM. See Section 3.5. ADD7-ADD0 Address of the EEPROM word being accessed. OB1,OB0 Indicates the Opcode of the command being executed. See Table 7. ELSEL External logic select: When clear, the EECS pin is used to select the EEPROM. When set, the ELCS pin is used to select the external LA decode circuit. Reserved Reserved and must be written as 0. Reset value is: XXXX XXXX XXXX XXXX

4.3.12 EEPROM Data

(Read/Write, Address: PacketPage base + 0042h) This register contains the word being written to, or read from, the EEPROM. See Section 3.5 on page 23. Reset value is: XXXX XXXX XXXX XXXX

4.3.13 Receive Frame Byte Counter

(Read only, Address: PacketPage base + 0050h) This register contains the count of the total number bytes received in the current received frame. This count contin- uously increments as more bytes in this frame are received. See Section 5.2.9 on page 86. Reset value is: XXXX XXXX XXXX XXXX 76543210 ADD7 to ADD0 FEDCBA9 8 Reserved ELSEL OB1 OB0 Address 0043h Address 0042h Most significant byte of the EEPROM data. Least significant byte of the EEPROM data. Address 0051h Address 0050h Most significant byte of the byte count. Least significant byte of the byte count.

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4.4 Status and Control Registers

(Bit 0 = 1) or a Status/Event Register (Bit 0 = 0). that describes the exact function of the register.

4.4.1 Configuration and Control Registers

by odd numbers (e.g. Register 1, Register 3, etc.). a more detailed description of the TxCMD register.

4.4.2 Status and Event Registers

read-only and are designated by even numbers (e.g. Register 2, Register 4, etc.). when responding to an Interrupt. found in Section 5.1 on page 78. tain more information about these counters.

4.4.3 Status and Control Bit Definitions

bit types used in the Status and Control registers.

10 Register Bits

Figure 16. Status and Control Register Format

scription of the bits in each register.

4.4.3.1 Act-Once Bits

4.4.3.2 Temporal Bits

4.4.3.3 Interrupt Enable Bits and Events

generates an interrupt to the host processor. located in three Event registers and two counters. sociated Event are identified in Table 14.

4.4.3.4 Accept Bits

CMD Read/Write Command: Written once per frame to initiate transmit. events will cause interrupts. cal interface will be configured. Read-only Counters: Counts missed receive frames and collisions. Provides time domain for locating coax cable faults. Table 13. PacketPage Register Types

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more detail in Section 5.2 on page 78.

4.4.4 Status and Control Register Summary

description of each Status and Control register. Table 14. Interrupt Enable Bits and Events

Table 15. Status and Control Register Descriptions

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Table 15. Status and Control Register Descriptions (continued)

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.5 Register 0: Interrupt Status Queue

(ISQ, Read-only, Address: PacketPage base + 0120h) The Interrupt Status Queue Register is used in both Memory Mode and I/O Mode to provide the host with interrupt information. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appropriate bit(s) in one of five registers, maps the contents of that register to the ISQ register, and drives an IRQ pin high. Three of the registers mapped to ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register C). The other two registers are counter-overflow reports: RxMISS (Register 10) and TxCOL (Register 12). In Mem- ory Mode, ISQ is located at PacketPage base + 120h. In I/O Mode, ISQ is located at I/O Base + 0008h. See Section 5.1 on page 78. RegNum The lower six bits describe which register (4, 8, C, 10 or 12) is contained in the ISQ. RegContent The upper ten bits contain the register data contents. Reset value is: 0000 0000 0000 0000 76543210 RegContent RegNum FEDCBA9 8 RegContent

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.6 Register 3: Receiver Configuration

(RxCFG, Read/Write, Address: PacketPage base + 0102h) RxCFG determines how frames will be transferred to the host and what frame types will cause interrupts.

000011 These bits provide an internal address used by the CS8900A to identify this as the Receiver

Configuration Register. Skip_1 When set, this bit causes the last committed received frame to be deleted from the receive buff- er. To skip another frame, the host must rewrite a “1” to this bit. This bit is not to be used if StreamE When set, StreamTransfer mode is used to transfer receive frames that are back-to-back and that pass the Destination Address filter (see Section 5.3 on page 86). When StreamE is clear, StreamTransfer mode is not used. This bit must not be set unless either bit AutoRxDMA or bit RXDMAonly is set. RxOKiE When set, there is an RxOK Interrupt if a frame is received without errors. RxOK interrupt is not generated when DMA mode is used for frame reception. RxDMAonly The Receive-DMA mode is used for all receive frames when this bit is set. AutoRxDMAE When set, the CS8900A will automatically switch to Receive-DMA mode if the conditions spec- ified in Section 5.5 on page 92 are met. RxDMAonly (Bit 9) has precedence over AutoRxD- MAE. BufferCRC When set, the received CRC is included with the data stored in the receive-frame buffer, and the four CRC bytes are included in the receive-frame length (PacketPage base + 0402h). When clear, neither the receive buffer nor the receive length include the CRC. CRCerroriE When set, there is a CRCerror Interrupt if a frame is received with a bad CRC. RuntiE When set, there is a Runt Interrupt if a frame is received that is shorter than 64 bytes. The CS8900A always discards any frame that is shorter than 8 bytes. ExtradataiE When set, there is an Extradata Interrupt if a frame is received that is longer than 1518 bytes. The operation of this bit is independent of the received packet integrity (good or bad CRC). After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0000 0000 0011 76543210 StreamE Skip_1 000011 FEDCBA9 8 ExtradataiE RuntiE CRCerroriE BufferCRC AutoRx DMAE RxDMA only RxOKiE

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.7 Register 4: Receiver Event

(RxEvent, Read-only, Address: PacketPage base + 0124h) Alternate meaning if bits 8 and 9 are both set (see Section 5.3 on page 86 for exception regarding Broadcast frames). RxEvent reports the status of the current received frame. 000100 These bits identify this as the Receiver Event Register. When reading this register, these bits will be 000100, where the LSB corresponds to Bit 0. IAHash If the received frame ’s Destination Address is accepted by the hash filter, then this bit is set if, and only if IAHashA (Register 5, RxCTL, Bit 6) is set, and Hashed (Bit 9) is set. See Section 5.3 on page 86. Dribblebits If set, the received frame had from one to seven bits after the last received full byte. An "Align- ment Error" occurs when Dribblebits and CRCerror (Bit C) are both set. RxOK If set, the received frame had a good CRC and valid length (i.e., there is not a CRC error, Runt error, or Extradata error). When RxOK is set, then the length of the received frame is contained at PacketPage base + 0402h. If RxOKiE (Register 3, RxCFG, Bit 8) is set, there is an interrupt. Hashed If set, the received frame had a Destination Address that was accepted by the hash filter. If Hashed and RxOK (Bit 8) are set, Bits F through A of RxEvent become the Hash Table Index for this frame [See Section 5.3 on page 86 for an exception regarding broadcast frames!].If Hashed and RxOK are not both set, then Bits F through A are individual event bits as defined below. IndividualAdr If the received frame had a Destination Address which matched the Individual Address found at PacketPage base + 0158h, then this bit is set if, and only if, RxOK (Bit 8) is set and Individ- ualA (Register 5, RxCTL, Bit A) is set. Broadcast If the received frame had a Broadcast Address (FFFF FFFF FFFFh) as the Destination Ad- dress, then this bit is set if, and only if, RxOK is set and BroadcastA (Register 5, RxCTL, Bit B) is set. CRCerror If set, the received frame had a bad CRC. If CRCerroriE (Register 3, RxCFG, Bit C) is set, there is an interrupt Runt If set, the received frame was shorter than 64 bytes. If RuntiE (Register 3, RxCFG, Bit D) is set, there is an interrupt. Extradata If set, the received frame was longer than 1518 bytes. All bytes beyond 1518 are discarded. If ExtradataiE (Register 3, RxCFG, Bit E) is set, there is an interrupt. Reset value is: 0000 0000 0000 0100 Notes: 3. All RxEvent bits are cleared upon readout. The host is responsible for processing all event bits. 4. RxStatus register (PacketPage base + 0400h) is the same as the RxEvent register except RxStatus is not cleared when RxEvent is read. See Section 5.2 on page 78. The value in the RxEvent register is undefined when RxDMAOnly bit (Bit 9, Register 3, RxCFG) is set. 76543210 Dribblebits IAHash 000100 FEDCBA9 8 Extradata Runt CRCerror Broadcast Individual Adr Hashed RxOK 76543210 Dribblebits IAHash 000100 FEDCBA9 8 Hash Table Index (see Section 5.3 on page 86) Hashed = 1 RxOK = 1

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4.4.8 Register 5: Receiver Control

(RxCTL, Read/Write, Address: PacketPage base +0104h) RxCTL has two functions: Bits 8, C, D, and E define what types of frames to accept. Bits 6, 7, 9, A, and B configure the Destination Address filter. See Section 5.3 on page 86.

000101 These bits provide an internal address used by the CS8900A to identify this as the Receiver

Control Register. For a received frame to be accepted, the Destination Address of that frame must pass the filter criteria found in Bits 6, 7, 9, A, and B (see Section 5.3 on page 86). IAHashA When set, receive frames are accepted when the Destination Address is an Individual Address that passes the hash filter. PromiscuousA Frames with any address are accepted when this bit is set. RxOKA When set, the CS8900A accepts frames with correct CRC and valid length (valid length is: 64 bytes <= length <= 1518 bytes). MulticastA When set, receive frames are accepted if the Destination Address is an Multicast Address that passes the hash filter. IndividualA When set, receive frames are accepted if the Destination Address matches the Individual Ad- dress found at PacketPage base + 0158h to PacketPage base + 015Dh. BroadcastA When set, receive frames are accepted if the Destination Address is FFFF FFFF FFFFh. CRCerrorA When set, receive frames that pass the Destination Address filter, but have a bad CRC, are ac- cepted. When clear, frames with bad CRC are discarded. See Note 5. RuntA When set, receive frames that are smaller than 64 bytes, and that pass the Destination Address filter are accepted. When clear, received frames less that 64 bytes in length are discarded. The CS8900A discards any frame that is less than 8 bytes. See Note 5. ExtradataA When set, receive frames longer than 1518 bytes and that pass the Destination Address filter are accepted. The CS8900A accepts only the first 1518 bytes and ignores the rest. When clear, frames longer than 1518 bytes are discarded. See Note 5. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 5.3 on page 86. Reset value is: 0000 0000 0000 0101 Notes: 5. Typically, when bits CRCerrorA, RuntA and ExtradataA are cleared (meaning bad frames are being discarded), then the corresponding bits CRCerroriE, RuntiE and ExtradataiE should be set in register 3 (Receiver Configuration register) to allow the device driver to keep track of discarded frames. 76543210 PromiscuousA IAHashA 000101 FEDCBA9 8 ExtradataA RuntA CRCerrorA BroadcastA IndividualA MulticastA RxOKA

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4.4.9 Register 7: Transmit Configuration

(TxCFG, Read/Write, Address: PacketPage base + 0106h) Each bit in TxCFG is an interrupt enable. When set, the interrupt is enabled as described below. When clear, there is no interrupt.

000111 These bits provide an internal address used by the CS8900A to identify this as the Transmit

Configuration Register. Loss-of-CRSiE If the CS8900A starts transmitting on the AUI and does not see the Carrier Sense signal at the end of the preamble, an interrupt is generated if this bit is set. Carrier Sense activity is reported by the CRS bit (Register 14, LineST, Bit E). SQErroriE When set, an interrupt is generated if there is an SQE error. (At the end of a transmission on the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen, there is an SQE error.) TxOKiE When set, an interrupt is generated if a packet is completely transmitted. Out-of-windowiE When set, an interrupt is generated if a late collision occurs (a late collision is a collision which occurs after the first 512 bit times). When this occurs, the CS8900A forces a bad CRC and ter- minates the transmission. JabberiE When set, an interrupt is generated if a transmission is longer than approximately 26 ms. AnycolliE When set, if one or more collisions occur during the transmission of a packet, an interrupt oc- curs at the end of the transmission 16colliE If the CS8900A encounters 16 normal collisions while attempting to transmit a particular packet, the CS8900A stops attempting to transmit that packet. When this bit is set, there is an interrupt upon detecting the 16th collision. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0000 0000 0111 Notes: Bit 8 (TxOKiE) and Bit B (AnycolliE) are interrupts for normal transmit operation. Bits 6, 7, 9, A, and F Notes:are interrupts for abnormal transmit operation. 76543210 SQE erroriE Loss-of-CRSiE 000111 FEDCBA9 8 16colliE AnycolliE JabberiE Out-of-window TxOKiE

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4.4.10 Register 8: Transmitter Event

(TxEvent, Read-only, Address: PacketPage base + 0128h) TxEvent gives the event status of the last packet transmitted.

001000 These bits provide an internal address used by the CS8900A to identify this as the Transmitter

Event Register. Loss-of-CRS If the CS8900A is transmitting on the AUI and doesn ’t see Carrier Sense (CRS) at the end of the preamble, there is a Loss-of-Carrier error and this bit is set. If Loss-of-CRSiE (Register 7, TxCFG, Bit 6) is set, there is an interrupt. SQEerror At the end of a transmission on the AUI, the CS8900A expects to see a collision within 64 bit times. If this does not happen, there is an SQE error and this bit is set. If SQEerroriE (Register 7, TxCFG, Bit 7) is set, there is an interrupt. TxOK This bit is set if the last packet was completely transmitted (Jabber (Bit A), out-of-window-colli- sion (Bit 9), and 16Coll (Bit F) must all be clear). If TxOKiE (Register 7, TxCFG, Bit 8) is set, there is an interrupt. Out-of-Window This bit is set if a collision occurs more than 512 bit times after the first bit of the preamble. When this occurs, the CS8900A forces a bad CRC and terminates the transmission. If Out-of-window- iE (Register 7, TxCFG, Bit 9) is set, there is an interrupt Jabber If the last transmission is longer than 26 msec, then the packet output is terminated by the jab- ber logic and this bit is set. If JabberiE (Register 7, TxCFG, Bit A) is set, there is an interrupt. #-of-TX-collisions These bits give the number of transmit collisions that occurred on the last transmitted packet. Bit B is the LSB. If AnycolliE (Register 7, TxCFG, Bit B) is set, there is an interrupt when any collision occurs. 16coll This bit is set if the CS8900A encounters 16 normal collisions while attempting to transmit a particular packet. When this happens, the CS8900A stops further attempts to send that packet. If 16colliE (Register 7, TxCFG, Bit F) is set, there is an interrupt. Reset value is: 0000 0000 0000 1000 Notes: 1.In any event register, like TxEvent, all bits are cleared upon readout. The host is responsible for processing all event bits. 2.TxOK (Bit 8) and the Number-of-Tx-Collisions (Bits E-B) are used in normal packet transmission.All other bits (6, 7, 9, A, and F) give the status of abnormal transmit operation. 76543210 SQEerror Loss-of-CRS 001000 FEDCBA9 8 16coll Number-of-Tx-collisions Jabber Out-of-window TxOK

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4.4.11 Register 9: Transmit Command Status

(TxCMD, Read-only, Address: PacketPage base + 0108h) This register contains the latest transmit command which tells the CS8900A how the next packet should be sent. The command must be written to PacketPage base + 0144h in order to initiate a transmission. The host can read the command from register 9 (PacketPage base + 0108h). See Section 5.7 on page 98.

001001 These bits provide an internal address used by the CS8900A to identify this as the Transmit

Command Register. When reading this register, these bits will be 001001, where the LSB cor- responds to Bit 0. TxStart This pair of bits determines how many bytes are transferred to the CS8900A before the MAC starts the packet transmit process. Bit 7 Bit 6 0 0 Start transmission after 5 bytes are in the CS8900A 0 1 Start transmission after 381 bytes are in the CS8900A 1 0 Start transmission after 1021 bytes are in the CS8900A 1 1 Start transmission after the entire frame is in the CS8900A Force When set in conjunction with a new transmit command, any transmit frames waiting in the trans- mit buffer are deleted. If a previous packet has started transmission, that packet is terminated within 64 bit times with a bad CRC. Onecoll When this bit is set, any transmission will be terminated after only one collision. When clear, the CS8900A allows up to 16 normal collisions before terminating the transmission. InhibitCRC When set, the CRC is not appended to the transmission. TxPadDis When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC. When TxPadDis is set, the CS8900A allows the transmission of runt frames (a frame less than 64 bytes). If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the CS8900A does not append the CRC After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Register value is: 0000 0000 0000 1001 Notes: The CS8900A does not transmit a frame if TxLength < 3 76543210 TxStart 001001 FEDCBA9 8 TxPadDis InhibitCRC Onecoll Force

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4.4.12 Register B: Buffer Configuration

(BufCFG, Read/Write, Address: PacketPage base + 010Ah) Each bit in BufCFG is an interrupt enable. When set, the interrupt described below is enabled. When clear, there is no interrupt.

001011 These bits provide an internal address used by the CS8900A to identify this as the Buffer Con-

figuration Register. SWint-X When set, there is an interrupt requested by the host software. The CS8900A provides the in- terrupt, and sets the SWint (Register C, BufEvent, Bit 6) bit. The CS8900A acts upon this com- mand at once. SWint-X is an Act-Once bit. To generate another interrupt, rewrite a "1" to this bit. RxDMAiE When set, there is an interrupt when a frame has been received and DMA is complete. With this interrupt, the RxDMAFrame bit (Register C, BufEvent, Bit 7) is set. Rdy4TxiE When set, there is an interrupt when the CS8900A is ready to accept a frame from the host for transmission. (See Section 5.7 on page 98 for a description of the transmit bid process.) TxUnderruniE When set, there is an interrupt if the CS8900A runs out of data before it reaches the end of the frame (called a transmit underrun). When this happens, event bit TXUnderrun (Register C, BufEvent, Bit 9) is set and the CS8900A makes no further attempts to transmit that frame. If the host still wants to transmit that particular frame, the host must go through the transmit request process again. RxMissiE When set, there is an interrupt if one or more received frames is lost due to slow movement of receive data out of the receive buffer (called a receive miss). When this happens, the RxMiss bit (Register C, BufEvent, Bit A) is set. Rx128iE When set, there is an interrupt after the first 128 bytes of a frame have been received. This al- lows a host processor to examine the Destination Address, Source Address, Length, Sequence Number, and other information before the entire frame is received. This interrupt should not be used with DMA. Thus, if either AutoRxDMA (Register 3, RxCFG, Bit A) or RxDMAonly (Register 3, RxCFG, Bit 9) is set, the Rx128iE bit must be clear. TxColOvfiE If set, there is an interrupt when the TxCOL counter increments from 1FFh to 200h. (The TxCOL counter (Register 18) is incremented whenever the CS8900A sees that the RXD+/RXD- pins (10BASE-T) or the CI+/CI- pins (AUI) go active while a packet is being transmitted.) MissOvfloiE If MissOvfloiE is set, there is an interrupt when the RxMISS counter increments from 1FFh to 200h. (A receive miss is said to have occurred if packets are lost due to slow movement of re- ceive data out of the receive buffers. When this happens, the RxMiss bit (Register C, BufEvent, Bit A) is set, and the RxMISS counter (Register 10) is incremented.) RxDestiE When set, there is an interrupt when a receive frame passes the Destination Address filter cri- teria defined in the RxCTL register (Register 5). This bit provides an early indication of an in- coming frame. It is earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE is set, the BufEvent could be RxDest or Rx128. After 128 bytes are received, the BufEvent changes from RxDest to Rx128. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state after reset. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0000 0000 1011 76543210 RxDMAiE SWint-X 001011 FEDCBA9 8 RxDestiE Miss OvfloiE TxCol OvfloiE Rx128iE RxMissiE TxUnder runtiE Rdy4TxiE

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4.4.13 Register C: Buffer Event

(BufEvent, Read-only, Address: PacketPage base + 012Ch) BufEvent gives the status of the transmit and receive buffers.

001100 These bits provide an internal address used by the CS8900A to identify this as the Buffer Event

Register. When reading this register, these bits will be 001100, where the LSB corresponds to Bit 0. SWint If set, there has been a software initiated interrupt. This bit is used in conjunction with the SWint- X bit (Register B, BufCFG, Bit 6). RxDMAFrame If set, one or more received frames have been transferred by slave DMA. If RxDMAiE (Register B, BufCFG, Bit 7) is set, there is an interrupt. Rdy4Tx If set, the CS8900A is ready to accept a frame from the host for transmission. If Rdy4TxiE (Reg- ister B, BufCFG, Bit 8) is set, there is an interrupt. (See Section 5.7 on page 98 for a description of the transmit bid process.) TxUnderrun This bit is set if CS8900A runs out of data before it reaches the end of the frame (called a trans- mit underrun). If TxUnderruniE (Register B, BufCFG, Bit 9) is set, there is an interrupt. RxMiss If set, one or more receive frames have been lost due to slow movement of data out of the re- ceive buffers. If RxMissiE (Register B, BufCFG, Bit A) is set, there is an interrupt. Rx128 This bit is set after the first 128 bytes of an incoming frame have been received. This bit will allow the host the option of preprocessing frame data before the entire frame is received. If Rx128iE (Register B, BufCFG, Bit B) is set, there is an interrupt. RxDest When set, this bit shows that a receive frame has passed the Destination Address Filter criteria as defined in the RxCTL register (Register 5). This bit is useful as an early indication of an in- coming frame. It will be earlier than Rx128 (Register C, BufEvent, Bit B). If RxDestiE (Register B, BufCFG, Bit F) is set, there is an interrupt. Reset value is: 0000 0000 0000 1100 Notes: With any event register, like BufEvent, all bits are cleared upon readout. The host is responsible for processing all event bits. 76543210 RxDMA frame SWint 001100 FEDCBA9 8 RxDest Rx128 RxMiss TxUnder run Rdy4Tx

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4.4.14 Register 10: Receiver Miss Counter

(RxMISS, Read-only, Address: PacketPage base + 0130h) The RxMISS counter (Bits 6 through F) records the number of receive frames that are lost (missed) due to the lack of available buffer space. If the MissOvfloiE bit (Register B, BufCFG, Bit D) is set, there is an interrupt when RxMISS increments from 1FFh to 200h. This interrupt provides the host with an early warning that the RxMISS counter should be read before it reaches 3FFh and starts over (by interrupting at 200h, the host has an additional 512 counts before RxMISS actually overflows). The RxMISS counter is cleared when read.

010000 These bits provide an internal address used by the CS8900A to identify this as the Receiver

Miss Counter. When reading this register, these bits will be 010000, where the LSB corre- sponds to Bit 0. MissCount The upper ten bits contain the number of missed frames. Register’s value is: 0000 0000 0001 0000 76543210 MissCount 010000 FEDCBA9 8 MissCount

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4.4.15 Register 10: Transmit Collision Counter

(TxCOL, Read-only, Address: PacketPage base + 0132h) The TxCOL counter (Bits 6 through F) is incremented whenever the 10BASE-T Receive Pair (RXD+ / RXD-) or AUI Collision Pair (CI+ / CI-) becomes active while a packet is being transmitted. If the TxColOvfiE bit (Register B, BufCFG, Bit C) is set, there is an interrupt when TxCOL increments from 1FFh to 200h. This interrupt provides the host with an early warning that the TxCOL counter should be read before it reaches 3FFh and starts over (by inter- rupting at 200h, the host has an additional 512 counts before TxCOL actually overflows). The TxCOL counter is cleared when read.

010010 These bits provide an internal address used by the CS8900A to identify this as the Transmit

Collision Counter. When reading this register, these bits will be 010010, where the LSB corre- sponds to Bit 0. ColCount The upper ten bits contain the number of collisions. Reset value is: 0000 0000 0001 0010 76543210 ColCount 010010 FEDCBA9 8 ColCount

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4.4.16 Register 13: Line Control

(LineCTL, Read/Write, Address: PacketPage base + 0112h) LineCTL determines the configuration of the MAC engine and physical interface.

010011 These bits provide an internal address used by the CS8900A to identify this as the Line Control

Register. SerRxON When set, the receiver is enabled. When clear, no incoming packets pass through the receiver. If SerRxON is cleared while a packet is being received, reception is completed and no subse- quent receive packets are allowed until SerRxON is set again. SerTxON When set, the transmitter is enabled. When clear, no transmissions are allowed. If SerTxON is cleared while a packet is being transmitted, transmission is completed and no subsequent packets are transmitted until SerTxON is set again. AUIonly Bits 8 and 9 are used to select either the AUI or the 10BASE-T interface according to the fol- lowing: [Note: 10BASE-T transmitter will be inactive even when selected unless link pulses are detected or bit DisableLT (register 19) is set. AUIonly (Bit 8) AutoAUI/10BT (Bit 9) Physical Interface

1 N/A AUI

0> 0 10BASE-T 0 1 Auto-Select AutoAUI/10BT See AUIonly (Bit 8) description above. ModBackoffE When clear, the ISO/IEC standard backoff algorithm is used (see Section 3.9 on page 27). When set, the Modified Backoff algorithm is used. (The Modified Backoff algorithm extends the backoff delay after each of the first three Tx collisions.) PolarityDis The 10BASE-T receiver automatically determines the polarity of the received signal at the RXD+/RXD- input (see Section 3.11 on page 34). When this bit is clear, the polarity is correct- ed, if necessary. When set, no effort is made to correct the polarity. This bit is independent of the PolarityOK bit (Register 14, LineST, Bit C), which reports whether the polarity is normal or reversed. 2-partDefDis Before a transmission can begin, the CS8900A follows a deferral procedure. With the 2-part- DefDis bit clear, the CS8900A uses the standard two-part deferral as defined in ISO/IEC 8802- LoRxSquelch When clear, the 10BASE-T receiver squelch thresholds are set to levels defined by the ISO/IEC 8802-3 specification. When set, the thresholds are reduced by approximately 6dB. This is use- ful for operating with "quiet" cables that are longer than 100 meters. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0000 0001 0011 76543210 SerTxOn SerRxON 010011 FEDCBA9 8 LoRx Squelch 2-part DefDis PolarityDis Mod BackoffE Auto AUI/10BT AUIonly

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4.4.17 Register 14: Line Status

(LineST, Read-only, Address: PacketPage base + 0134h) LineST reports the status of the Ethernet physical interface.

010100 These bits provide an internal address used by the CS8900A to identify this as the Line Status

Register. When reading this register, these bits will be 010100, where the LSB corresponds to Bit 0. LinkOK If set, the 10BASE-T link has not failed. When clear, the link has failed, either because the CS8900A has just come out of reset, or because the receiver has not detected any activity (link pulses or received packets) for at least 50 ms. AUI If set, the CS8900A is using the AUI. 10BT If set, the CS8900A is using the 10BASE-T interface. PolarityOK If set, the polarity of the 10BASE-T receive signal (at the RXD+ / RXD- inputs) is correct. If clear, the polarity is reversed. If PolarityDis (Register 13, LineCTL, Bit C) is clear, the polarity is auto- matically corrected, if needed. The PolarityOK status bit shows the true state of the incoming polarity independent of the PolarityDis control bit. Thus, if PolarityDis is clear and PolarityOK is clear, then the receive polarity is inverted, and corrected. CRS This bit tells the host the status of an incoming frame. If CRS is set, a frame is currently being received. CRS remains asserted until the end of frame (EOF). At EOF, CRS goes inactive in about 1.3 to 2.3 bit times after the last low-to-high transition of the recovered data. Reset value is: 0000 0000 0001 0100 76543210 LinkOK 010100 FEDCBA9 8 CRS PolarityOK 10BT AUI

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4.4.18 Register 15: Self Control

(SelfCTL, Read/Write, Address: PacketPage base + 0114h) SelfCTL controls the operation of the LED outputs and the lower-power modes.

010101 These bits provide an internal address used by the CS8900A to identify this as the Chip Self

Control Register. RESET When set, a chip-wide reset is initiated immediately. RESET is an Act-Once bit. This bit is cleared as a result of the reset. SWSuspend When set, the CS8900A enters the software initiated Suspend mode. Upon entering this mode, there is a partial reset. All registers and circuits are reset except for the ISA I/O Base Address Register and the SelfCTL Register. There is no transmit nor receive activity in this mode. To come out of software Suspend, the host issues an I/O Write within the CS8900A’s assigned I/O space (see Section 3.7 on page 25 for a complete description of the CS8900A’s low-power modes). HWSleepE When set, the SLEEP input pin is enabled. If SLEEP is high, the CS8900A is "awake", or oper- ative (unless in SWSuspend mode, as shown above). If SLEEP is low, the CS8900A enters ei- ther the Hardware Standby or Hardware Suspend mode. When clear, the CS8900A ignores the SLEEP input pin (see Section 3.7 on page 25 for a complete description of the CS8900A’s low- power modes). HWStandbyE If HWSleepE is set and the SLEEP input pin is low, then when HWStandbyE is set, the CS8900A enters the Hardware Standby mode. When clear, the CS8900A enters the Hardware Suspend mode (see Section 3.7 on page 25 for a complete description of the CS8900A’s low- power modes). HC0E The LINKLED or HC0 output pin is selected with this control bit. When HC0E is clear, the output pin is LINKLED. When HC0E is set, the output pin is HC0 and the HCB0 bit (Bit E) controls the pin. HC1E The BSTATUS or HC1 output pin is selected with this control bit. When HC1E is clear, the out- put pin is BSTATUS and indicates receiver ISA Bus activity. When HC1E is set, the output pin is HC1 and the HCB1 bit (Bit F) controls the pin. HCB0 When HC0E (Bit C) is set, this bit controls the HC0 pin. If HCB0 is set, HC0 is low. If HCB0 is clear, HC0 is high. HC0 may drive an LED or a logic gate. When HC0E (Bit C) is clear, this con- trol bit is ignored. HCB1 When HC1E (Bit D) is set, this bit controls the HC1 pin. If HCB1 is set, HC1 is low. If HCB1 is clear, HC1 is high. HC1 may drive an LED or a logic gate. When HC1E (Bit D) is clear, this con- trol bit is ignored. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0000 0001 0101 76543210 RESET 010101 FEDCBA9 8 HCB1 HCB0 HC1E HC0E HW Standby HWSleepE SW Suspend

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4.4.19 Register 16: Self Status

(SelfST, Read-only, Address: PacketPage base + 0136h) SelfST reports the status of the EEPROM interface and the initialization process.

010110 These bits provide an internal address used by the CS8900A to identify this as the Chip Self

Status Register. When reading this register, these bits will be 010110, where the LSB corre- sponds to Bit 0. 3,3VActive If the CS8900A is operating on a 3.3V supply, this bit is set. If the CS8900A is operating on a 5V supply, this bit is clear. INITD If set, the CS8900A initialization, including read-in of the EEPROM, is complete. SIBUSY If set, the EECS output pin is high indicating that the EEPROM is currently being read or pro- grammed. The host must not write to PacketPage base + 0040h nor 0042h until SIBUSY is clear. EEPROMpresent If the EEDataIn pin is low after reset, there is no EEPROM present, and the EEPROMpresent bit is clear. If the EEDataIn pin is high after reset, the CS8900A "assumes" that an EEPROM is present, and this bit is set. EEPROMOK If set, the checksum of the EEPROM readout was OK. ELpresent If set, external logic for Latchable Address bus decode is present. EEsize This bit shows the size of the attached EEPROM and is valid only if the EEPROMpresent bit (Bit 9) and EEPROMOK bit (Bit A) are both set. If clear, the EEPROM size is either 128 words (’C56 or ’CS56) or 256 words (C66 or ’CS66). If set, the EEPROM size is 64 words (’C46 or ’CS46). Reset value is: 0000 0000 0001 0110 76543210 INITD 3.3V Active 010110 FEDCBA9 8 EEsize ELPresent EEPROM OK EEPROM present SIBUSY

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4.4.20 Register 17: Bus Control

(BusCTL, Read/Write, Address: PacketPage base + 0116h) BusCTL controls the operation of the ISA-bus interface.

010111 These bits provide an internal address used by the CS8900A to identify this as the Bus Control

Register. ResetRxDMA When set, the RxDMA offset pointer at PacketPage base + 0026h is reset to zero. When the host sets this bit, the CS8900A does the following: 1.Terminates the current receive DMA activity, if any. 2.Clears all internal receive buffers. 3.Zeroes the RxDMA offset pointer. DMAextend When set, DMARQx goes inactive on the falling edge of IORN instead of the rising edge of IORN-1. See Switching Characteristics, DMA Read, tDMAR5. Setting this bit also enables single transfer mode DMA. Normal operation is demand mode DMA in which DMACKx cannot deas- sert until after DMARQx deasserts, i.e. until a full ethernet frame is transferred. Single transfer mode allows DMACKx to deassert between each DMA read. UseSA When set, the MEMCS16 pin goes low whenever the address on SA bus [12..19] match the CS8900A’s assigned Memory base address and the CHIPSEL pin is low (internal address de- code). When clear, MEMCS16 is driven low whenever CHIPSEL goes low. (external address decode). see Section 4.9 on page 73. For MEMCS16 pin to be enabled, the CS8900A must be in Memory Mode with the MemoryE bit (Register 17, BusCTL, Bit A) set. MemoryE When set, the CS8900A may operate in Memory Mode. When clear, Memory Mode is disabled. I/O Mode is always enabled. DMABurst When clear, the CS8900A performs continuous DMA until the receive frame is completely transferred from the CS8900A to host memory. When set, each DMA access is limited to 28us, after which time the CS8900A gives up the bus for 1.3us before making a new DMA request. IOCHRDYE When set, the CS8900A does not use the IOCHRDY output pin, and the pin is always high-im- pedance. This allows external pull-up to force the output high. When clear, the CS8900A drives IOCHRDY low to request additional time during I/O Read and Memory Read cycles. IOCHRDY does not affect I/O Write, Memory Write, nor DMA Read. RxDMAsize This bit determines the size of the receive DMA buffer (located in host memory). When set, the DMA buffer size is 64 Kbytes. When clear, it is 16 Kbytes. EnableRQ When set, the CS8900A will generate an interrupt in response to an interrupt event (Section 5.1). When cleared, the CS8900A will not generate any interrupts. After reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0000 0001 0111 76543210 Reset RxDMA 010111 FEDCBA9 8 EnableIRQ RxDMA size IOCH RDYE DMABurst MemoryE UseSA DMAextend

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.21 Register 18: Bus Status

(BusST, Read-only, Address: PacketPage base + 0138h) BusST describes the status of the current transmit operation.

011000 These bits provide an internal address used by the CS8900A to identify this as the Bus Status

Register. When reading this register, these bits will be 011000, where the LSB corresponds to Bit 0. TxBidErr If set, the host has commanded the CS8900A to transmit a frame that the CS8900A will not send. Frames that the CS8900A will not send are: 1) Any frame greater than 1514 bytes, provided that InhibitCRC (Register 9, TxCMD, Bit C) is clear. 2) Any frame greater than 1518 bytes. Note that this bit is not set when transmit frames are too short. Rdy4TxNOW Rdy4TxNOW signals the host that the CS8900A is ready to accept a frame from the host for transmission. This bit is similar to Rdy4Tx (Register C, BufEvent, Bit 8) except that there is no interrupt associated with Rdy4TxNOW. The host can poll the CS8900A and check Rdy4TxNOW to determine if the CS8900A is ready for transmit. (See Section 5.7 on page 98 for a description of the transmit bid process.) Reset value is: 0000 0000 0001 1000 76543210 TxBidErr 011000 FEDCBA9 8 Rdy4Tx NOW

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4.4.22 Register 19: Test Control

(TestCTL, Read/Write, Address: PacketPage base + 0118h) TestCTL controls the diagnostic test modes of the CS8900A.

011001 These bits provide an internal address used by the CS8900A to identify this as the Test Control

Register. DisableLT When set, the 10BASE-T interface allows packet transmission and reception regardless of the link status. DisableLT is used in conjunction with the LinkOK (Register 14, LineST, Bit 7) as fol- lows: LinkOK DisableLT 0 0 No packet transmission for reception allowed. Transmitter sends link impulses. 0 1 DisableLT overrides LinkOK to allow packet transmission and reception. Transmitter does not send link pulses. 1 N/A Disable has no meaning if LinkOK = 1. ENDECloop When set, the CS8900A enters internal loopback mode where the internal Manchester encoder output is connected to the decoder input. The 10BASE-T and AUI transmitters and receivers are disabled. When clear, the CS8900A is configured for normal operation. AUIloop When set, the CS8900A allows reception while transmitting. This facilitates loopback tests for the AUI. When clear, the CS8900A is configured for normal AUI operation. Disable Backoff When set, the backoff algorithm is disabled. The CS8900A transmitter looks only for completion of the inter packet gap before starting transmission. When clear, the backoff algorithm is used. FDX When set, 10BASE-T full duplex mode is enabled and CRS (Register 14, LineST, Bit E) is ig- nored. This bit must be set when performing loopback tests on the 10BASE-T port. When clear, the CS8900A is configured for standard half-duplex 10BASE-T operation. At reset, if no EEPROM is found by the CS8900A, then the register has the following initial state. If an EEPROM is found, then the register’s initial value may be set by the EEPROM. See Section 3.3 on page 18. Reset value is: 0000 0000 0001 1001 76543210 DisableLT 011001 FEDCBA9 8 FDX Disable Back- off AUIloop ENDEC loop

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.4.23 Register 1C: AUI Time Domain Reflectometer

(Read-only, Address: PacketPage base + 013Ch) The TDR counter (Bits 6 through F) is a time domain reflectometer useful in locating cable faults in 10BASE-2 and 10BASE-5 coax networks. It counts at a 10 MHz rate from the beginning of transmission on the AUI to when a col- lision or Loss-of-Carrier error occurs. The TDR counter is cleared when read.

011100 These bits provide an internal address used by the CS8900A to identify this as the Bus Status

Register. When reading this register, these bits will be 011100, where the LSB corresponds to Bit 0. AUI-Delay The upper ten bits contains the number of 10 MHz clock periods between the beginning of transmission on the AUI to when a collision or Loss-of-Carrier error occurs. Reset value is: 0000 0000 0001 1100 76543210 AUI Delay 011100 FEDCBA9 8 AUI Delay

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4.5 Initiate Transmit Registers

4.5.1 Transmit Command Request - TxCMD

(Write-only, Address: PacketPage base + 0144h) The word written to PacketPage base + 0144h tells the CS8900A how the next packet should be transmitted. This PacketPage location is write-only, and the written word can be read from Register 9, at PacketPage base + 0108h. The CS8900A does not transmit a frame if TxLength (at PacketPage location base + 0146h) is less than 3. See Section 5.7 on page 98. Command Register. When reading this register, these bits will be 001001, where the LSB cor- responds to Bit 0. TxStart This pair of bits determines how many bytes are transferred to the CS8900A before the MAC starts the packet transmit process. Bit 7 Bit 6 0 0 Start transmission after 5 bytes are in the CS8900A 0 1 Start transmission after 381 bytes are in the CS8900A 1 0 Start transmission after 1021 bytes are in the CS8900A 1 1 Start transmission after the entire frame is in the CS8900A Force When set in conjunction with a new transmit command, any transmit frames waiting in the trans- mit buffer are deleted. If a previous packet has started transmission, that packet is terminated within 64 bit times with a bad CRC. Onecoll When this bit is set, any transmission will be terminated after only one collision. When clear, the CS8900A allows up to 16 normal collisions before terminating the transmission. InhibitCRC When set, the CRC is not appended to the transmission. TxPadDis When TxPadDis is clear, if the host gives a transmit length less than 60 bytes and InhibitCRC is set, then the CS8900A pads to 60 bytes. If the host gives a transmit length less than 60 bytes and InhibitCRC is clear, then the CS8900A pads to 60 bytes and appends the CRC. When TxPadDis is set, the CS8900A allows the transmission of runt frames (a frame less than 64 bytes). If InhibitCRC is clear, the CS8900A appends the CRC. If InhibitCRC is set, the CS8900A does not append the CRC. Since this register is write-only, it’s initial state after reset is undefined.

4.5.2 Transmit Length

(Write-only, Address: PacketPage base + 0146h) This register is used in conjunction with register 9, TxCMD. When a transmission is initiated via a command in Tx- CMD, the length of the transmitted frame is written into this register. The length of the transmitted frame may be modified by the configuration of the TxPadDis and InhibitCRC bits in the TxCMD register. See Table 35, and Section 5.7 on page 98. TxLength must be >3 and < 1519. Since this register is write-only, it’s initial state after reset is undefined. 76543210 TxStart 001001 FEDCBA9 8 TxPadDis InhibitCRC Onecoll Force Address 0147h Address 0146h Most-significant byte of Transmit Frame Length Least-significant byte of Transmit Frame Length

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

4.6 Address Filter Registers

4.6.1 Logical Address Filter (hash table)

(Read/Write, Address: PacketPage base + 0150h) The CS8900A hashing decoder circuitry compares its output with one bit of the Logical Address Filter Register. If the decoder output and the Logical Address Filter bit match, the frame passes the hash filter and the Hashed bit (Register 4, RxEvent, Bit 9) is set. See Section 5.3 on page 86. Reset value is: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000

4.6.2 Individual Address (IEEE address)

(Read/Write, Address: PacketPage base + 0158h) The unique, IEEE 48-bit Individual Address (IA) begins at 0158h. The first bit of the IA (Bit IA[00]) must be "0". See Section 5.3 on page 86. The value of this register must be loaded from external storage, for example, from the EEPROM. See Section 3.3 on page 18. If the CS8900A is not able to load the IA from the EEPROM, then after a reset this register is undefined, and the driver must write an address to this register. Address 0157h Address 0156h Address 0155h Address 0154h Address 0153h Address 0152h Address 0151h Address 0150h Most-signifi- cant byte of hash filter. Least-signifi- cant byte of hash filter. Address 0015Dh Address 0015Ch Address 0015Bh Address 0015Ah Address 0159h Address 00158h Octet 5 of IA Octet 0 of IA

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4.7 Receive and Transmit Frame Locations

The Receive and Transmit Frame PacketPage loca- tions are used to transfer Ethernet frames to and from the host. The host sequentially writes to and reads from these locations, and internal buffer memory is dynamically allocated between transmit and receive as needed. One receive frame and one transmit frame are accessible at a time.

4.7.1 Receive PacketPage Locations

In IO mode, the receive status/length/frame loca- tions are read through repetitive reads from one IO port at the IO base address. See Section 4.10 on page 75. In memory mode, the receive status/length/frame locations are read using memory reads of a block of memory starting at memory base address + 0400h. Typically the memory locations are read sequen- tially using repetitive Move instructions (REP MOVS). See Section 4.9 on page 73. Random access is not needed. However, the first 118 bytes of the receive frame can be accessed ran- domly if word reads, on even word boundaries, are used. Beyond 118 bytes, the memory reads must be sequential. Byte reads, or reads on odd-word boundaries, can be performed only in sequential read mode. See Section 4.8 on page 72. The RxStatus word reports the status of the current received frame. RxEvent register 4 (PacketPage base + 0124h) has the same contents as the RxSta- tus register, except RxEvent is cleared when Rx- Event is read. The RxLength (receive length) word is the length, in bytes, of the data to be transferred to the host across the ISA bus. The register describes the length from the start of Destination Address to the end of CRC, assuming that CRC has been selected (via Register 3 RxCFG, bit BufferCRC). If CRC has not been selected, then the length does not in- clude the CRC, and the CRC is not present in the receive buffer. After the RxLength has been read, the receive frame can be read. When some portion of the frame is read, the entire frame should be read before read- ing the RxEvent register either directly or through the ISQ register. Reading the RxEvent register sig- nals to the CS8900A that the host is finished with the current frame, and wants to start processing the next frame. In this case, the current frame will no longer be accessible to the host. The current frame will also become inaccessible if a Skip command is issued, or if the entire frame has been read. See Section 5.2 on page 78.

4.7.2 Transmit Locations

The host can write frames into the CS8900A buffer using Memory writes using REP MOVS to the Tx- Frame location. See Section 5.7 on page 98.

4.8 Eight and Sixteen Bit Transfers

A data transfer to or from the CS8900A can be done in either I/O or Memory space, and can be ei- ther 16 bits wide (word transfers) or 8 bits wide (byte transfers). Because the CS8900A ’s internal architecture is based on a 16-bit data bus, word transfers are the most efficient. To transfer transmit frames to the CS8900A and re- ceive frames from the CS8900A, the host may mix word and byte transfers, provided it follows three rules: 1) The primary method used to access CS8900A memory is word access. 2) Word accesses to the CS8900A ’s internal memory are kept on even-byte boundaries. 3) When switching from byte accesses to word ac- cesses, a byte access to an even byte address must be followed by a byte access to an odd- byte address before the host may execute a word access (this will realign the word transfers to even-byte boundaries). On the other hand, a byte access to an odd-byte address may be fol- lowed by a word access.

4.8.1 Transferring Odd-Byte-Aligned Data

ing odd address. It can then resume word transfers. An example of this is shown in Figure 17.

4.8.2 Random Access to CS8900A Memory

only sequential access of received data is allowed.

4.9 Memory Mode Operation

word and byte transfers must be used with a 286.

4.9.1 Accesses in Memory Mode

range of the CS8900A or Boot PROM.  Either the MEMR pin or the MEMW pin is low.

4.9.2 Configuring the CS8900A for Memory

Figure 17. Odd-Byte Aligned Data Table 16. Receive/Transmit Memory Locations

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET memory space. The other method limits memory mapping to the first 1 Mbyte of host memory space. General Memory Mode Operation: Configuring the CS8900A so that its internal memory can be mapped anywhere within host Memory space re- quires the following:  a simple circuit must be added to decode the Latchable Address bus (LA20 - LA23) and the BALE signal.  the host must configure the external logic with the correct address range as follows: 1) Check to see if the INITD bit (Register 16, SelfST, bit 7) is set, indicating that initial- ization is complete. 2) Check to see if the ELpresent bit (Register 16, SelfST, bit B) is set. This bit indicates that external logic for the LA bus decode is present. 3) Set the ELSEL bit of the EEPROM Com- mand Register to activate the ELCS pin for use with the external decode circuit. 4) Configure the external logic serially.  the host must write the memory base address into the Memory Base Address register (Pack- etPage base + 002Ch);  the host must set the MemoryE bit (Register 17, BusCTL, Bit A); and  the host must set the UseSA bit (Register 17, BusCTL, Bit 9). Limiting Memory Mode to the First 1 Mbyte of Host Memory Space: Configuring the CS8900A so that its internal memory can be mapped only within the first 1 Mbyte of host memory space requires the following:  the CHIPSEL pin must be tied low;  the ISA-bus SMEMR signal must be connected to the MEMR pin;  the ISA-bus SMEMW signal must be connect- ed to the MEMW pin;  the host must write the memory base address into the Memory Base Address register (Pack- etPage base + 002Ch);  the host must set the MemoryE bit (Register 17, BusCTL, Bit A); and  the host must clear the UseSA bit (Register 17, BusCTL, Bit 9).

4.9.3 Basic Memory Mode Transmit

Memory Mode transmit operations occur in the fol- lowing order (using interrupts): 1) The host bids for storage of the frame by writ- ing the Transmit Command to the TxCMD reg- ister (memory base + 0144h) and the transmit frame length to the TxLength register (memory base + 0146h). If the transmit length is errone- ous, the command is discarded and the Tx- BidErr bit (Register 18, BusST, Bit 7) is set. 2) The host reads the BusST register (Register 18, memory base + 0138h). If the Rdy4TxNOW bit (Bit 8) is set, the frame can be written. If clear, the host must wait for CS8900A buffer memory to become available. If Rdy4TxiE (Register B, BufCFG, Bit 8) is set, the host will be interrupt- ed when Rdy4Tx (Register C, BufEvent, Bit 8) becomes set. 3) Once the CS8900A is ready to accept the frame, the host executes repetitive memory-to- memory move instructions (REP MOVS) to memory base + 0A00h to transfer the entire frame from host memory to CS8900A memory. For a more detailed description of transmit, see Section 5.7 on page 98.

4.9.4 Basic Memory Mode Receive

Memory Mode receive operations occur in the fol- lowing order (interrupts used to signal the presence of a valid receive frame):

0400h) to learn the status of the receive frame. 0402h) to learn the frame’s length.

4.9.5 Polling the CS8900A in Memory Mode

and if memory space is available for transmit.

4.10 I/O Space Operation

default value of the I/O base address is set at 300h.

4.10.1 Receive/Transmit Data Ports 0 and 1

4.10.2 TxCMD Port

to this port at the start of each transmit operation.

4.10.3 TxLength Port

4.10.4 Interrupt Status Queue Port

tion of the ISQ, see Section 5.1 on page 78.

4.10.5 PacketPage Pointer Port

Table 17. I/O Mode Mapping

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the structure of the PacketPage Pointer.

4.10.6 PacketPage Data Ports 0 and 1

4.10.7 I/O Mode Operation

I/O Mode and Receive DMA operation.

4.10.8 Basic I/O Mode Transmit

length to the TxLength Port (I/O base + 0006h). 7) is set, the transmit length is not valid.

4.10.9 Basic I/O Mode Receive

Figure 18. PacketPage Pointer

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET host memory. Preceding the frame data are the contents of the RxStatus register (PacketPage base + 0400h) and the RxLength register (Pack- etPage base + 0402h). For a more detailed description of receive, see Section 5.2 on page 78.

4.10.10 Accessing Internal Registers

To access any of the CS8900A ’s internal registers in I/O Mode, the host must first setup the Pack- etPage Pointer. It does this by writing the Pack- etPage address of the target register to the PacketPage Pointer Port (I/O base + 000Ah). The contents of the target register is then mapped into the PacketPage Data Port (I/O base + 000Ch). If the host needs to access a sequential block of reg- isters, the MSB of the PacketPage address of the first word to be accessed should be set to "1". The PacketPage Pointer will then move to the next word location automatically, eliminating the need to set- up the PacketPage Pointer between successive ac- cesses (see Figure 18).

4.10.11 Polling the CS8900A in I/O Mode

If interrupts are not used, the host can poll the CS8900A to check if receive frames are present and if memory space is available for transmit.

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5.0 OPERATION

5.1 Managing Interrupts and Servicing the

The Interrupt Status Queue (ISQ) is used by the CS8900A to communicate Event reports to the host processor. Whenever an event occurs that triggers an enabled interrupt, the CS8900A sets the appro- priate bit(s) in one of five registers, maps the con- tents of that register to the ISQ, and drives the selected interrupt request pin high (if an earlier in- terrupt is waiting in the queue, the interrupt request pin will already be high). When the host services the interrupt, it must first read the ISQ to learn the nature of the interrupt. It can then process the inter- rupt (the first read to the ISQ causes the interrupt request pin to go low.) Three of the registers mapped to the ISQ are event registers: RxEvent (Register 4), TxEvent (Register 8), and BufEvent (Register C). The other two reg- isters are counter-overflow reports: RxMISS (Reg- ister 10) and TxCOL (Register 12). There may be more than one RxEvent report and/or more than one TxEvent report in the ISQ at a time. However, there may be only one BufEvent report, one Rx- MISS report and one TxCOL report in the ISQ at a time. Event reports stored in the ISQ are read out in the order of priority, with RxEvent first, followed by TxEvent, BufEvent, RxMiss, and then TxCOL. The host only needs to read from one location to get the interrupt currently at the front of the queue. In Memory Mode, the ISQ is located at PacketPage base + 0120h. In I/O Mode, it is located at I/O base + 0008h. Each time the host reads the ISQ, the bits in the corresponding register are cleared and the next report in the queue moves to the front. When the host starts reading the ISQ, it must read and process all Event reports in the queue. A read- out of a null word (0000h) indicates that all inter- rupts have been read. The ISQ is read as a 16-bit word. The lower six bits (0 through 5) contain the register number (4, 8, C, 10, or 12). The upper ten bits (6 through F) contain the register contents. The host must always read the entire 16-bit word. The active interrupt pin (INTRQx) is selected via the Interrupt Number register (PacketPage base + 22h). As an additional option, all of the interrupt pins can be 3-Stated using the same register. see Section 4.3 on page 41. An event triggers an interrupt only when the En- ableIRQ bit of the Bus Control register (bit F of register 17) is set. After the CS8900A has generat- ed an interrupt, the first read of the ISQ makes the INTRQ output pin go low (inactive). INTRQ re- mains low until the null word (0000h) is read from the ISQ, or for 1.6us, whichever is longer.

5.2 Basic Receive Operation

5.2.0.1 Overview

Once an incoming packet has passed through the analog front end and Manchester decoder, it goes through the following three-step receive process: 1) Pre-Processing 2) Temporary Buffering 3) Transfer to Host Figure 20 shows the steps in frame reception. As shown in the figure, all receive frames go through the same pre-processing and temporary buffering phases, regardless of transfer method Once a frame has been pre-processed and buffered, it can be accessed by the host in either Memory or I/O space. In addition, the CS8900A can transfer receive frames to host memory via host DMA. This section describes receive frame pre-processing and Memory and I/O space receive operation. Section 5.4 on page 89 through Section 5.5 on page 92 describe DMA operation.

An enabled interrupt occurs. (active) if not already high. Figure 19. Interrupt Status Queue

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5.2.1 Terminology: Packet, Frame, and Transfer

5.2.1.1 Packet

5.2.1.2 Frame

to be transmitted, or that has been received.

5.2.1.3 Transfer

5.2.2 Receive Configuration

 how received frames are transferred.

5.2.2.1 Configuring the Physical Interface

(Register 13) and is described in Table18.

5.2.2.2 Choosing which Frame Types to Accept

Figure 20. Frame Reception

5.2.2.3 Selecting which Events Cause Interrupts

5.2.2.4 Choosing How to Transfer Frames

6 SerRxON When set, reception enabled.

8 AUIonly When set, AUI selected (takes

precedence over AutoAUI/10BT).

9 AutoAUI/10BT When set, automatic interface

reduced by approximately 6 dB. Table 18. Physical Interface Configuration

6 IAHashA When set, Individual Address frames

When set, all frames are accepted*.

8 RxOKA When set, frames with valid length

9 MulticastA When set, Multicast frames that pass

the hash filter are accepted*. pass the DA filter are accepted. Table 19. Frame Acceptance Criteria

8 RxOKiE When set, there is an interrupt if a

frame is received with bad CRC*.

• Must also pass the DA filter before there is an interrupt.

7 RxDMAiE When set, there is an interrupt if

the RxMISS counter overflows. Table 21. Registers 3 and B Interrupt Configuration

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5.2.3 Receive Frame Pre-Processing

4) Normal Interrupt Generation.

5.2.3.1 Destination Address Filtering

a more detailed description of DA filtering.

7 StreamE When set, Stream Transfer

9 RxDMAonly When set, DMA slave opera-

Table 22. Receive Frame Pre-Processing Figure 21. Receive Frame Pre-Processing

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

5.2.3.2 Early Interrupt Generation

The CS8900A support the following two early in- terrupts that can be used to inform the host that a frame is being received:  RxDest: The RxDest bit (Register C, BufEvent, Bit F) is set as soon as the Destination Address (DA) of the incoming frame passes the DA fil- ter. If the RxDestiE bit (Register B, BufCFG, bit F) is set, the CS8900A generates a corre- sponding interrupt. Once RxDest is set, the host is allowed to read the incoming frame's DA (the first 6 bytes of the frame).  Rx128: The Rx128 bit (Register C, BufEvent, Bit B) is set as soon as the first 128 bytes of the incoming frame have been received. If the Rx128iE bit (Register B, BufCFG, bit B) is set, the CS8900A generates a corresponding inter- rupt. Once the Rx128 bit is set, the RxDest bit is cleared and the host is allowed to read the first 128 bytes of the incoming frame. The Rx128 bit is cleared by the host reading the BufEvent register (either directly or through the Interrupt Status Queue) or by the CS8900A de- tecting the incoming frame's End-of-Frame (EOF) sequence. Like all Event bits, RxDest and Rx128 are set by the CS8900A whenever the appropriate event oc- curs. Unlike other Event bits, RxDest and Rx128 may be cleared by the CS8900A without host inter- vention. All other event bits are cleared only by the host reading the appropriate event register, either directly or through the Interrupt Status Queue (ISQ). (RxDest and Rx128 can also be cleared by the host reading the BufEvent register, either di- rectly or through the Interrupt Status Queue). Fig- ure 22 provides a diagram of the Early Interrupt process.

5.2.3.3 Acceptance Filtering

The third step of pre-processing is to determine whether or not to accept the frame by comparing the frame with the criteria programmed into the Rx- CTL register (Register 5). If the receive frame passes the Acceptance filter, the frame is buffered, either on chip or in host memory via DMA. If the frame fails the Acceptance filter, it is discarded. The results of the Acceptance filter are reported in the RxEvent register (Register 4).

5.2.3.4 Normal Interrupt Generation

The final step of pre-processing is to generate any enabled interrupts that are triggered by the incom- ing frame. Interrupt generation occurs when the en- tire frame has been buffered (up to the first 1518 bytes). For more information about interrupt gener- ation, see Section 5.1 on page 78. 5.2.4 Held vs. DMAed Receive Frames All accepted frames are either held in on-chip RAM until processed by the host, or stored in host memory via DMA. A receive frame that is held in on-chip RAM is referred to as a held receive frame. A frame that is stored in host memory via DMA is a DMAed receive frame. This section describes buffering and transferring held receive frames. Section 5.4 on page 89 through Section 5.6 on page 95 describe DMAed receive frames.

5.2.5 Buffering Held Receive Frames

If space is available, an incoming frame will be temporarily stored in on-chip RAM, where it awaits processing by the host. Although this re- ceive frame now occupies on-chip memory, the CS8900A does not commit the memory space to it until one of the following two conditions is true: 1) The entire frame has been received and the host has learned about the frame by reading the Rx- Event register (Register 4), either directly or through the ISQ. Or: 2) The frame has been partially received, causing either the RxDest bit (Register C, BufEvent, Bit F) or the Rx128 bit (Register C, BufEvent, Bit B) to become set, and the host has learned about

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Figure 22. Early Interrupt Generation

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET the receive frame by reading the BufEvent reg- ister (Register C), either directly or through the ISQ. When the CS8900A commits buffer space to a par- ticular held receive frame (termed a committed re- ceived frame), no data from subsequent frames can be written to that buffer space until the frame is freed from commitment. (The committed received frame may or may not have been received error free.) A received frame is freed from commitment by any one of the following conditions: 1) The host reads the entire frame sequentially in the order that it was received (first byte in, first byte out). Or: 2) The host reads part or none of the frame, and then issues a Skip command by setting the Skip_1 bit (Register 3, RxCFG, bit 6). Or: 3) The host reads part of the frame and then reads the RxEvent register (Register 5), either direct- ly or through the ISQ, and learns of another re- ceive frame. This condition is called an "implied Skip". Ensure that the host does not do “implied skips.” Both early interrupts are disabled whenever there is a committed receive frame waiting to be processed by the host.

5.2.6 Transferring Held Receive Frames

The host can read-out held receive frames in Mem- ory or I/O space. To transfer frames in Memory space, the host executes repetitive Move instruc- tions (REP MOVS) from PacketPage base + 0404h. To transfer frames in I/O space, the host ex- ecutes repetitive In instructions (REP IN) from I/O base + 0000h, with status and length preceding the frame. There are three possible ways that the host can learn the status of a particular frame. It can: 1) Read the Interrupt Status Queue; 2) Read the RxEvent register directly (Register4); or 3) Read the RxStatus register (PacketPage base + 0400h).

5.2.7 Receive Frame Visibility

Only one receive frame is visible to the host at a time. The receive frame's status can be read from the RxStatus register (PacketPage base + 0400h), and its length can be read from the RxLength reg- ister (PacketPage base + 0402h). For more infor- mation about Memory space operation, see Section 4.9 on page 73. For more information about I/O space operation, see Section 4.10 on page 75.

5.2.8 Example of Memory Mode Receive Opera-

A common length for short frames is 64 bytes, in- cluding the 4-byte CRC. Suppose that such a frame has been received with the CS8900A configured as follows:  The BufferCRC bit (Register 3, RxCFG, Bit B) is set causing the 4-byte CRC to be buffered with the rest of the receive data.  The RxOKA bit (Register 5, RxCTL, Bit 8) is set, causing the CS8900A to accept good frames (a good frame is one with legal length and valid CRC).  The RxOKiE bit (Register 3, RxCFG, Bit 8) is set, causing an interrupt to be generated when- ever a good frame is received. Then the transfer to the host would proceed as fol- lows: 1) The CS8900A generates an RxOK interrupt to the host to signal the arrival of a good frame. 2) The host reads the ISQ (PacketPage base +

86 DS271PP4

(Register 4) with the RxOK bit (Bit 8) set.

5.2.9 Receive Frame Byte Counter

ter can be read to determine the final frame status. of zero, the previous count was the final count. The count may now have an odd value.

5.3 Receive Frame Address Filtering

0404h to 0409h 6-byte Source Address. 040Ah to 040Fh 6-byte Destination Address. 0410h to 0411h 2-byte Length or Type Field. 0412h to 043Fh 46 bytes of data. Table 23. Example Memory Map

5.3.0.1 Individual Address Frames

5.3.0.2 Multicast Frames

5.3.0.3 Broadcast Frames

will accept all receive frames, irrespective of DA.

5.3.1 Configuring the Destination Address Filter

6 IAHashA IAHash

7 PromiscuousA

9 MulticastA Hashed

Table 24. DA Filtering Options

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the filter is being changed. PacketPage base + 0158h, if necessary. 3) Set SerRxON to re-enable the receiver.

5.3.2 Hash Filter

frames should be accepted by the CS8900A.

5.3.2.1 Hash Filter Operation

CRC are latched into the 6-bit hash register (HR).

5.3.3 Broadcast Frame Hashing Exception

ing bits F-A contain the Hash Table Index). Figure 23. Hash Filter Operation

5.4 Receive DMA

5.4.1 Overview

needed to help prevent missed frames. number of interrupts to the host.

5.4.2 Configuring the CS8900A for DMA Opera-

description of the CS8900A’s DMA interface). Four 16-bit registers are used for DMA operation. These are described in Table 26. RxDMAonly bit (Register 3, RxCFG, Bit 9). CS8900A is in DMA mode for all receive frames.

5.4.3 DMA Receive Buffer Size

in a circular buffer located in host memory space. LAF value corresponds to a Multicast Addresses of both all 1s and 03-00-00-00-00-01. and the following address filters were enabled: IAHashA and BroadcastA. Table 25. Contents of RxEvent Upon Various Conditions

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RxDMAsize bit (Register 17, BusCTL, Bit D).

5.4.4 Receive-DMA-Only Operation

read the DMA Frame Count register. recently transferred received frame. bits are reserved and not applicable. Table 26. Receive DMA Registers

5.4.5 Committing Buffer Space to a DMAed

register (PacketPage base + 0028h). ter (PacketPage base + 0028h).

5.4.6 DMA Buffer Organization

5.4.7 RxDMAFrame Bit

reading the BufEvent register (Register C).

5.4.8 Receive DMA Example Without Wrap-

ory by DMA without wrap-around.

5.4.9 Receive DMA Operation for RxDMA-Only

address filter, and must be completely received. Receive Frame interrupt is processed. Table 27. RxDMAFrame Bit

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DMA frame count read is zero.

5.5 Auto-Switch DMA

5.5.1 Overview

Figure 24. Example of Frames Stored in DMA Buffer

5.5.2 Configuring the CS8900A for Auto-Switch

ble, only switching to slave DMA if necessary. the CS8900A uses DMA for all receive frames.

5.5.3 Auto-Switch DMA Operation

Figure 25. RxDMA Only Operation

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set, a corresponding interrupt occurs. BufEvent) associated with the missed frame.

5.5.5 Exit From DMA

Figure 26. Conditions for Switching to DMA

5.5.6 Auto-Switch DMA Example

5.6 StreamTransfer

5.6.1 Overview

CPU overhead associated with frame reception.

5.6.2 Configuring the CS8900A for

the Rx128iE bit both be clear.

5.6.3 StreamTransfer Operation

 generates an RxDMAFrame interrupt.

5.6.4 Keeping StreamTransfer Mode Active

Table 28. Stream Transfer Configuration

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Frame 3 starts to be received and passes the DA filter. This activates Auto-Switch DMA. bit and generates an interrupt. CS8900A updates the DMA registers. CS8900A exits DMA (assumes Frame 3 is still coming in). space for another complete large frame (1518 bytes). Frame 1 received and completely stored in on-chip RAM. Frame 2 received and completely stored in on-chip RAM. awaits processing by the host. DMA Frame Count (PacketPage base + 0028h) is zero. Figure 27. Example of Auto-Switch DMA

 the DA of each packet passes the DA filter.

5.6.5 Example of StreamTransfer

5.6.6 Receive DMA Summary

tion options supported by the CS8900A.

4 Back-to-Back Frames 5 Back-to-Back Frames

9 Interrupts for 9 "Good" Packets Time

Figure 28. Receive Example Without Stream Transfer

2 Interrupts for 9 "Good" Packets Time

Figure 29. Receive DMA Configuration Options

1 NA 0 NA Receive DMA used for all receive frames, without

1 NA 1 NA Receive DMA used for all receive frames, with

and BufEvent interrupts possible. 0 0 NA NA Memory or I/O Mode only. Table 29. Receive DMA Configuration Options

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5.7 Transmit Operation

5.7.1 Overview

gins with the host issuing a Transmit Command. nal memory, using either Memory or I/O space.

5.7.2 Transmit Configuration

5.7.2.1 Configuring the Physical Interface

ister (Register 13) and is described in Table 30.

5.7.2.2 Selecting which Events Cause Interrupts

able (iE) bits in these registers.

5.7.3 Changing the Configuration

CFG or BufCFG registers, it may do so at any time. The effects of the change are noticed immediately. 7 SerTxON When set, transmission enabled. precedence over AutoAUI/10BT). When clear, 10BASE-T selected. Table 30. Physical Interface Configuration

5.7.4 Enabling CRC Generation and Padding

5.7.5 Individual Packet Transmission

TxLength register (PacketPage base + 0146h). tells the CS8900A how to transmit the next frame.

6 Loss-of-

7 SQErroriE When set, there is an interrupt

whenever there is an SQE error.

8 TxOKiE When set, there is an interrupt

whenever there is a collision. Table 31. Transmitting Interrupt Configuration

8 Rdy4TxiE When set, there is an interrupt

(used with a Transmit Request).

9 TxUnder

of data after transmit has started. Table 32. Transmit Interrupt Configuration Table 33. CRC and Paddling Configuration

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register are described in Table 34.

5.7.6 Transmit in Poll Mode

I/O base + 0004h in I/O mode). (Register 18, BusST, Bit 7) is set. PacketPage Pointer Port (I/O base + 000Ah). the PacketPage Data Port (I/O base + 000Ch). Data Port (I/O base + 0000h) in I/O mode).

5.7.7 Transmit in Interrupt Mode

BufCFG, Bit 8) must be set for transmit operation. I/O base + 0004h in I/O mode).

67 T x S t a r t

8 Force When set, the CS8900A dis-

rently in the transmit buffer.

9 Onecoll When set, the CS8900A will

any packet after a collision. Table 34. Tx Command Configuration

Figure 30. Transmit Operation in Polling Mode

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET the correct location by writing 0138h to the PacketPage Pointer Port (I/O base + 000Ah), it than can read the BusST register from the Pack- etPage Data Port (I/O base + 000Ch).After reading the register, the Rdy4TxNOW bit is checked. If the bit is set, the frame can be writ- ten to CS8900A memory. If Rdy4TxNOW is clear, the host will have to wait for the CS8900A buffer memory to become available at which time the host will be interrupted. On interrupt, the host enters the interrupt service routine and reads ISQ register (Memory base + 0120h in memory mode and I/O base + 0008h in I/O) and checks the Rdy4Tx bit (bit 8). If Rdy4Tx is clear then the CS8900A waits for the next interrupt. If Rdy4Tx is set, then the CS8900A is ready to accept the frame. 4) When the CS8900A is ready to accept the frame, the host transfers the entire frame from host memory to CS8900A memory using REP instruction (REP MOVS to memory base + 0A00h in memory mode, and REP OUT to Re- ceive/Transmit Data Port (I/O base + 0000h) in I/O mode).

5.7.8 Completing Transmission

When the CS8900A successfully completes trans- mitting a frame, it sets the TxOK bit (Register 8, TxEvent, Bit 8). If the TxOKiE bit (Register 7, Tx- CFG, bit 8) is set, the CS8900A generates a corre- sponding interrupt. 5.7.9 Rdy4TxNOW vs. Rdy4Tx The Rdy4TxNOW bit (Register 18, BusST, bit 8) is used to tell the host that the CS8900A is ready to accept a frame for transmission. This bit is used during the Transmit Request process or after the Transmit Request process to signal the host that space has become available when interrupts are not being used (i.e. the Rdy4TxiE bit (Register B, BufCFG, Bit 8) is not set). Also, the Rdy4Tx bit is used with interrupts and requires the Rdy4TxiE bit be set. Figure 30 provides a diagram of error free trans- mission without collision.

5.7.10 Committing Buffer Space to a Transmit

When the host issues a transmit request, the CS8900A checks the length of the transmit frame to see if there is sufficient on-chip buffer space. If there is, the CS8900A sets the Rdy4TxNOW bit. If not, and the Rdy4TxiE bit is set, the CS8900A waits for buffer space to free up and then sets the Rdy4Tx bit. If Rdy4TxiE is not set, the CS8900A sets the Rdy4TxNOW bit when space becomes available. Even though transmit buffer space may be avail- able, the CS8900A does not commit buffer space to a transmit frame until all of the following are true: 1) The host must issues a Transmit Request; 2) The Transmit Request must be successful; and, 3) Either the host reads that the Rdy4TxNOW bit (Register 18, BusST, Bit 8) is set, or the host reads that the Rdy4Tx bit (Register C, BufE- vent, bit 8) is set. If the CS8900A commits buffer space to a particu- lar transmit frame, it will not allow subsequent frames to be written to that buffer space as long as the transmit frame is committed. After buffer space is committed, the frame is sub- sequently transmitted unless any of the following occur: 1) The host completely writes the frame data, but transmission failed on the Ethernet line. There are three such failures, and these are indicated by three transmit error bits in the TxEvent reg- ister (Register 8): 16coll, Jabber, or Out-of- Window. Or: 2) The host aborts the transmission by setting the Force (Register 9, TxCMD, bit 8) bit. In this case, the committed transmit frame, as well as

TxOK bit (Register 8, TxEvent, Bit 8) is set. Figure 31. Transmit Operation in Interrupt Mode

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5.7.11 Transmit Frame Length

5.8 Full duplex Considerations

5.9 Auto-Negotiation Considerations

the hub will put the CS8900A into Link-OK. length less than 60 bytes, the CS8900A pads.

1. The CS8900A will not send a frame with TxLength less than 3 bytes.

Table 35. Transmit Frame Length

6.0 TEST MODES

6.0.1 Loopback & Collision Diagnostic Tests

6.0.2 Internal Tests

the transmitter and receiver are disabled.

6.0.3 External Tests

6.0.4 Loopback Tests

6.0.6 AUI Loopback and Collision Tests

verify that 16coll (Register 8, TxEvent, Bit F) is set. and verify that the frame is received without error. 16coll (Register 8, TxEvent, Bit F) is set. Table 36. 10BASE-T Loopback and Collision Tests 1 1 Transmit a frame and verify that the frame is received without error. signal, an SQE error will occur). sine wave to Cl+/Cl- pins and observe collisions. Table 37. AUI Loopback and Collision Tests

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

6.1 Boundary Scan

Boundary Scan test mode provides an easy and ef- ficient board-level test for verifying that the CS8900A has been installed properly. Boundary Scan will check to see if the orientation of the chip is correct, and if there are any open or short circuits. Boundary Scan is controlled by the TEST pin. When TEST is high, the CS8900A is configured for normal operation. When TEST is low, the fol- lowing occurs:  the CS8900A enters Boundary Scan test mode and stays in this mode as long as TEST is low;  the CS8900A goes through an internal reset and remains in internal reset as long as TEST is low;  the AEN pin, normally the ISA bus Address Enable, is redefined to become the Boundary Scan shift clock input; and  all digital outputs and bi-directional pins are placed in a high-impedance state (this electri- cally isolates the CS8900A digital outputs from the rest of the circuit board). For Boundary Scan to be enabled, AEN must be low before TEST is driven low. A complete Boundary Scan test is made up of two separate cycles. The first cycle, known as the Out- put Cycle, tests all digital output pins and all bi-di- rectional pins. The second cycle, known as the Input Cycle, tests all digital input pins and all bi-di- rectional pins.

6.1.1 Output Cycle

During the Output Cycle, the falling edge of AEN causes each of the 17 digital output pins and each of the 17 bi-directional pins to be driven low, one at a time. The cycle begins with LINKLED and ad- vances in order counterclockwise around the chip through all 34 pins. This test is referred to as a "walking 0" test. The following is a list of output pins and bi-direc- tional pins that are tested during the Output Cycle: The output pins not included in this test are:

6.1.2 Input Cycle

During the Input Cycle, the falling edge of AEN causes the state of each selected pin to be trans- ferred to EEDataOut (that is, EEDataOut will be high or low depending on the input level of the se- lected pin). This cycle begins with SLEEP and ad- vances clockwise through each of 33 input pins (all digital input pins except for AEN) and each of the 17 bi-directional pins, one pin at a time. The following is a list of input pins and bi-direc- tional pins that are tested during the Input Cycle: Pin Name Pin # Pin Name Pin # ELCS 2 INTRQ1 31 EECS 3 INTRQ0 32 EESK 4 IOCS16 33 EEDataOut 5 MEMCS16 34 DMARQ2 11 INTRQ3 35 DMARQ1 13 IOCHRDY 64 DMARQ0 15 SD0 - SD7 65-68, 71-74 CSOUT 17 BSTATUS 78 SD08-SD15 27-24, 21-18 LINKLED 99 INTRQ2 30 LANLED 100 Table 38. Pin Name Pin # Pin Name Pin # DO+ 83 TXD- 88 DO- 84 RES 93 TXD+ 87 XTAL2 98 Table 39. Pin Name Pin # Pin Name Pin # ELCS 2 SBHE 36 EEDataIn 6 SA0 - SA11 37-48 CHIPSEL 7 REFRESH 49 DMACK2 12 SA12 - SA19 50-54, 58-60 DMACK1 14 IOR 61 DMACK0 16 IOW 62 SD08-SD15 27-24, 21-18 SD0 - SD7 65-68, 71-74 MEMW 28 RESET 75 MEMR 29 SLEEP 77 Table 40.

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET The input pins not included in this test are: After the Input Cycle is complete, one more cycle of AEN returns all digital output pins and bi-direc- tional pins to a high-impedance state.

6.1.3 Continuity Cycle

The combination of a complete Output Cycle, a complete Input Cycle, and an additional AEN cycle is called a Continuity Cycle. Each Continuity Cycle lasts for 85 AEN clock cycles. The first Continuity Cycle can be followed by additional Continuity Cycles by keeping TEST low and continuing to cy- cle AEN. When TEST is driven high, the CS8900A exits Boundary Scan mode and AEN is again used as the ISA-bus Address Enable. Figure 32 shows a complete Boundary Scan Conti- nuity Cycle. Figure 33 shows Boundary Scan timing. Pin Name Pin # Pin Name Pin # AEN 63 Cl- 82 TEST 76 RXD+ 91 Dl+ 79 RXD- 92 Dl- 80 XTAL1 97 Cl+ 81 Table 41.

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Figure 32. Boundary Scan Continuity Cycle

34 Clocks

50 Clocks

85 Clocks

Figure 33. Boundary Scan Timing

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

7.0 CHARACTERISTICS/SPECIFICATIONS - COMMERCIAL

7.1 ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) WARNING: Normal operation is not guaranteed at these extremes.

7.2 RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS = 0 V, all voltages with

respect to 0 V.) 7.3 DC CHARACTERISTICS (TA = 25 °C; VDD = 5.0 V or VDD = 3.3V) Notes: 1. With digital outputs connected to CMOS loads. Parameter Symbol Min Max Unit Power Supply Digital Analog DVDD AVDD -0.3 -0.3 6.0 6.0 V V Input Current (Except Supply Pins) - ±10.0 mA Analog Input Voltage -0.3 ( AVDD+) + 0.3 V Digital Input Voltage -0.3 ( DVDD) + 0.3 V Ambient Temperature (Power Applied) -55 +125 °C Storage Temperature -65 +150 °C Parameter Symbol Min Max Unit 5.0V Power Supply CS8900A-CQ & -IQ Digital Analog DVDD AVDD 4.75 4.75 5.25 5.25 V V 3.3V Power Supply CS8900A-CQ3 & -IQ3 Digital Analog DVDD AVDD 3.135 3.135 3.465 3.465 V V Operating Ambient Temperature CS8900A-CQ & -CQ3 T A 0+ 7 0 °C Operating Ambient Temperature CS8900A-IQ & -IQ3 T A -40 +85 °C Parameter Symbol Min Max Unit Crystal (when using external clock - square wave) XTAL1 Input Low Voltage V IXH -0.5 0.4 V XTAL1 Input High Voltage V IXH 3.5 DVDD + 0.5 V XTAL1 Input Low Current I IXL -40 - µA XTAL1 Input High Current I IXH -4 0 µ A Power Supply Power Supply Current while Active 5.0V I DD -5 5 m A Power Supply Current while Active 3.3V I DD -4 5 m A Hardware Standby Mode Current (Note 1) I DDSTNDBY -1 . 0 m A Hardware Suspend Mode Current (Note 1) I DDHWSUS -1 0 0 µ A Software Suspend Mode Current (Note 1) I DDSWSUS -1 . 0 m A

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET DC CHARACTERISTICS (Continued) Notes: 2. OD24: Open Drain Output with 24 mA Drive OD10: Open Drain Output with 10 mA Drive B24: Bi-Directional with 3-State Output and 24 mA Drive B4w: Bi-Directional with 3-State Output, Internal Weak Pullup, and 4 mA Drive O24ts: 3-State Output with 24 mA Drive O4: Output with 4 mA Drive I: Input Iw: Input with Internal Weak Pullup Parameter Symbol Min Typ Max Unit Digital Inputs and Outputs (Note 2) Output Low Voltage I OL = 24 mA OD24, B24, O24ts IOL = 10 mA OD10 IOL = 4 mA B4w, O4 VOL - 0.4 0.4 0.4 V V V Output Low Voltage (all outputs) V DD = 3.3V and TA = >70°CV OL 0.425 V Output High Voltage I OH = -12 mA B24 IOH = -2 mA B4w, O24ts, O4 VOH 2.4 2.4 V V Output Leakage Current 0 ≤ VOUT ≤ VCC OD24, OD10, B24, O24ts B4w ILL -10 -20 µA Input Low Voltage I, Iw V IL -- 0 . 8 V Input High Voltage I, Iw V IH 2.4 - - V Input Leakage Current 0 ≤ VIN ≤ VCC I Iw IL -10 -20 µA 10BASE-T Interface Transmitter Differential Output Voltage (Peak) V OD 2.2 - 2.8 V Receiver Normal Squelch Level (Peak) V ISQ 300 - 525 mV Receiver Low Squelch Level (LoRxSquelch bit set) V SQL 125 - 290 mV AUI Interface Transmitter Differential Output Voltage (DO+/DO- Peak) V AOD ±0.45 - ±1.2 V Transmitter Undershoot Voltage V AODU -- 1 0 0 m V Transmitter Differential Idle Voltage (DO+/DO- Peak) V IDLE -- 4 0 m V Receiver Squelch Level (DI+/DI- Peak) V AISQ 180 - 300 mV

112 DS271PP4

Figure 34. 16-Bit I/O Read, IOCHRDY not used Figure 35. 16-Bit I/O Read, with IOCHRDY

114 DS271PP4

Figure 38. 16-Bit DMA Read Figure 39. 16-Bit I/O Write

116 DS271PP4

Figure 42. 10BASE-T Receive Figure 43. 10BASE-T Link Integrity

118 DS271PP4

Figure 47. External Boot PROM Access Figure 48. EEPROM

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET 7.5 10BASE-T WIRING  If a center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr resistors with a single 2xRr resistor.  The Rt and Rr resistors are ±1% tolerance.  The CS8900A supports 100, 120, and 150 Ω unshielded twisted pair cables. The proper values of Rt and Rr, for a given cable impedance, are shown below:  Note: for 3.3V operation the turns ratio on TXD+ and TXD- is 1:2.5, rt is 8 Ω for 100Ω cable and the 68pF cap changes to 560pF. Cable Impedance (Ω)R t ( Ω) Rr ( Ω) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 Rt Rt CS8900A TD + TD - TXD + TXD - 1 : 2 RJ45 1 : 1 RD + RD - 0.01 µF RXD+ RXD- Rr Rr0.01 µ F 68 pF

120 DS271PP4

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

7.6 AUI WIRING

7.7 QUARTZ CRYSTAL REQUIREMENTS (If a 20 MHz quartz crystal is used, it must meet the

following specifications) Parameter Min Typ Max Unit Parallel Resonant Frequency - 20 - MHz Resonant Frequency Error (C L = 18 pF) -50 - +50 ppm Resonant Frequency Change Over Operating Temperature -40 - +40 ppm Crystal Capacitance - - 18 pF Motional Crystal Capacitance - 0.022 - pF Series Resistance - - 50 Ohm Shunt Capacitance - - 7 pF CS8900A DO + DO - 1 : 1 DB15 Tx 1 : 1 13 6 +12 V CI + CI - 1 : 1 39.2 Ω 39.2 ΩCol 0.01 uF DI + DI - 39.2 Ω 39.2 ΩRx 0.01 uF

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

8.0 CHARACTERISTICS/SPECIFICATIONS - INDUSTRIAL

8.1 ABSOLUTE MAXIMUM RATINGS (AVSS, DVSS = 0 V, all voltages with respect to 0 V.) WARNING: Normal operation is not guaranteed at these extremes.

8.2 RECOMMENDED OPERATING CONDITIONS (AVSS, DVSS = 0 V, all voltages with

respect to 0 V.) 8.3 DC CHARACTERISTICS (TA = 25 °C; VDD = 5.0 V or VDD = 3.3V) Notes: 1. With digital outputs connected to CMOS loads. Parameter Symbol Min Max Unit Power Supply Digital Analog DVDD AVDD -0.3 -0.3 6.0 6.0 V V Input Current (Except Supply Pins) - ±10.0 mA Analog Input Voltage -0.3 ( AVDD+) + 0.3 V Digital Input Voltage -0.3 ( DVDD) + 0.3 V Ambient Temperature (Power Applied) -55 +125 °C Storage Temperature -65 +150 °C Parameter Symbol Min Max Unit 5.0V Power Supply CS8900A-CQ & -IQ Digital Analog DVDD AVDD 4.75 4.75 5.25 5.25 V V 3.3V Power Supply CS8900A-CQ3 & -IQ3 Digital Analog DVDD AVDD 3.135 3.135 3.465 3.465 V V Operating Ambient Temperature CS8900A-CQ & -CQ3 T A 0+ 7 0 °C Operating Ambient Temperature CS8900A-IQ & -IQ3 T A -40 +85 °C Parameter Symbol Min Max Unit Crystal (when using external clock - square wave) XTAL1 Input Low Voltage V IXH -0.5 0.4 V XTAL1 Input High Voltage V IXH 3.5 DVDD + 0.5 V XTAL1 Input Low Current I IXL -40 - µA XTAL1 Input High Current I IXH -4 0 µ A Power Supply Power Supply Current while Active 5.0V I DD -5 5 m A Power Supply Current while Active 3.3V I DD -4 5 m A Hardware Standby Mode Current (Note 1) I DDSTNDBY -1 . 0 m A Hardware Suspend Mode Current (Note 1) I DDHWSUS -1 0 0 µ A Software Suspend Mode Current (Note 1) I DDSWSUS -1 . 0 m A

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET DC CHARACTERISTICS (Continued) Notes: 2. OD24: Open Drain Output with 24 mA Drive OD10: Open Drain Output with 10 mA Drive B24: Bi-Directional with 3-State Output and 24 mA Drive B4w: Bi-Directional with 3-State Output, Internal Weak Pullup, and 4 mA Drive O24ts: 3-State Output with 24 mA Drive O4: Output with 4 mA Drive I: Input Iw: Input with Internal Weak Pullup Parameter Symbol Min Typ Max Unit Digital Inputs and Outputs (Note 2) Output Low Voltage I OL = 24 mA OD24, B24, O24ts IOL = 10 mA OD10 IOL = 4 mA B4w, O4 VOL - 0.4 0.4 0.4 V V V Output Low Voltage (all outputs) V DD = 3.3V and TA = >70°CV OL 0.425 V Output High Voltage I OH = -12 mA B24 IOH = -2 mA B4w, O24ts, O4 VOH 2.4 2.4 V V Output Leakage Current 0 ≤ VOUT ≤ VCC OD24, OD10, B24, O24ts B4w ILL -10 -20 µA Input Low Voltage I, Iw V IL -- 0 . 8 V Input High Voltage I, Iw V IH 2.4 - - V Input Leakage Current 0 ≤ VIN ≤ VCC I Iw IL -10 -20 µA 10BASE-T Interface Transmitter Differential Output Voltage (Peak) V OD 2.2 - 2.8 V Receiver Normal Squelch Level (Peak) V ISQ 300 - 525 mV Receiver Low Squelch Level (LoRxSquelch bit set) V SQL 125 - 290 mV AUI Interface Transmitter Differential Output Voltage (DO+/DO- Peak) V AOD ±0.45 - ±1.2 V Transmitter Undershoot Voltage V AODU -- 1 0 0 m V Transmitter Differential Idle Voltage (DO+/DO- Peak) V IDLE -- 4 0 m V Receiver Squelch Level (DI+/DI- Peak) V AISQ 180 - 300 mV

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Figure 51. 16-Bit Memory Read, IOCHRDY not used Figure 52. 16-Bit Memory Read, with IOCHRDY

126 DS271PP4

Figure 55. 16-Bit Memory Write Figure 56. 10BASE-T Transmit

128 DS271PP4

Figure 59. AUI Transmit Figure 60. AUI Receive Figure 61. AUI Collision

130 DS271PP4

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET 8.5 10BASE-T WIRING  If a center tap transformer is used on the RXD+ and RXD- inputs, replace the pair of Rr resistors with a single 2xRr resistor.  The Rt and Rr resistors are ±1% tolerance.  The CS8900A supports 100, 120, and 150 Ω unshielded twisted pair cables. The proper values of Rt and Rr, for a given cable impedance, are shown below:  Note: for 3.3V operation the turns ratio on TXD+ and TXD- is 1:2.5, rt is 8 Ω for 100Ω cable and the 68pF cap changes to 560pF. Cable Impedance (Ω)R t ( Ω) Rr ( Ω) 100 24.3 49.9 120 30.1 60.4 150 37.4 75 Rt Rt CS8900A TD + TD - TXD + TXD - 1 : 2 RJ45 1 : 1 RD + RD - 0.01 µF RXD+ RXD- Rr Rr0.01 µ F 68 pF

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

8.6 AUI WIRING

8.7 QUARTZ CRYSTAL REQUIREMENTS (If a 20 MHz quartz crystal is used, it must meet the

following specifications) Parameter Min Typ Max Unit Parallel Resonant Frequency - 20 - MHz Resonant Frequency Error (C L = 18 pF) -50 - +50 ppm Resonant Frequency Change Over Operating Temperature -40 - +40 ppm Crystal Capacitance - - 18 pF Motional Crystal Capacitance - 0.022 - pF Series Resistance - - 50 Ohm Shunt Capacitance - - 7 pF CS8900A DO + DO - 1 : 1 DB15 Tx 1 : 1 13 6 +12 V CI + CI - 1 : 1 39.2 Ω 39.2 ΩCol 0.01 uF DI + DI - 39.2 Ω 39.2 ΩRx 0.01 uF

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9.0 PHYSICAL DIMENSIONS

A1 0.002 0.006 0.05 0.15 B 0.007 0.011 0.17 0.27 D 0.618 0.642 15.70 16.30 D1 0.547 0.555 13.90 14.10 E 0.618 0.642 15.70 16.30 E1 0.547 0.555 13.90 14.10 e* 0.016 0.024 0.40 0.60 L 0.018 0.030 0.45 0.75 * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS026 100L TQFP PACKAGE DRAWING E D1D e L B A

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

10.0 GLOSSARY OF TERMS

10.1 Acronyms

AUI Attachment Unit Interface CRC Cyclic Redundancy Check CS Carrier Sense CSMA/CD Carrier Sense Multiple Access with Collision Detection DA Destination Address EEPROM Electrically Erasable Programmable Read Only Memory EOF End-of-Frame FCS Frame Check Sequence FDX Full Duplex IA Individual Address IPG Inter-Packet Gap ISA Industry Standard Architecture LA ISA Latchable Address Bus (LA17 - LA23) LLC Logical Link Control MAC Media Access Control MAU Medium Attachment Unit MIB Management Information Base RX Receive SA Source Address or ISA System Address Bus (SA0 - SA19) SFD Start-of-Frame Delimiter SNMP Simple Network Management Protocol SOF Start-of-Frame SQE Signal Quality Error TDR Time Domain Reflectometer TX Transmit UTP Unshielded Twisted Pair

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10.2 Definitions

The method used to compute the 32-bit frame check sequence (FCS). Frame Check Sequence The 32-bit field at the end of a frame that contains the result of the cyclic redundancy check (CRC). Frame An Ethernet string of data bits that includes the Destination Address (DA), Source Address (SA), optional length field, Logical Link Control data (LLC data), pad bits (if needed) and Frame Check Sequence (FCS). Individual Address The specific Ethernet address assigned to a device attached to the Ethernet media. Inter-Packet Gap Time interval between packets on the Ethernet. Minimum interval is 9.6 µs. Jabber A condition that results when a Ethernet node transmits longer than between 20 ms and 150 ms. Packet An Ethernet string of data bits that includes the Preamble, Start-of-Frame Delimiter (SFD), Destination Address (DA), Source Address (SA), optional length field, Logical Link Control data (LLC data), pad bits (if needed) and Frame Check Sequence (FCS). A packet is a frame plus the Preamble and SFD. Receive Collision A receive collision occurs when the CI+/CI- inputs are active while a packet is being received. Applies only to the AUI. Signal Quality Error When transmitting on the AUI, the MAC expects to see a collision signal on the CI+/CI- pair within 64 bit times after the end of a transmission. If no collision occurs, there is said to be an "SQE error". Applies only to the AUI. Slot Time Time required for an Ethernet Frame to cross a maximum length Ethernet network. One Slot Time equals 512 bit times. Transmit Collision A transmit collision occurs when the receive inputs, RXD+/RXD- (10BASE-T) or CI+/CI- (AUI) are active while a packet is being transmitted.

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

10.3 Acronyms Specific to the CS8900A

BufCFG Buffer Configuration - Register B BufEvent Buffer Event - Register C BusCTL Bus Control - Register 17 BusST Bus State - Register 18 ENDEC Manchester encoder/decoder ISQ Interrupt Status Queue - register 0 LineCTL Ethernet Line Control - Register 13 LineST Ethernet Line Status - Register 14 RxCFG Receive Configuration - Register 3 RxCTL Receive Control - Register 5 RxEvent Receive Event - Register 4 SelfCTL Self Control - Register 15 SelfST Self Status - Register 16 TestCTL Test Control - Register 19 TxCFG Transmit Configuration - Register 7 TxCMD Transmit Command - Register 9 TxEvent Transmit Event - Register 8

10.4 Terms Specific to the CS8900A

A control bit that causes the CS8900A to take a certain action once when a logic "1" is written to that bit. To cause the action again, the host must rewrite a "1". Committed Receive Frame A receive frame is said to be "committed" after the frame has been buffered by the CS8900A, and the host has been notified, but the frame has not yet been transferred by the host. Committed Transmit Frame A transmit frame is said to be "committed" after the host has issued a Transmit Command, and the CS8900A has reserved buffer space and notified the host that it is ready for transmit. Event or Interrupt Event The term "Event" is used in this document to refer to something that can trigger an interrupt. Items that are considered "Events" are reported in the three Event registers (RxEvent, TxEvent, or BufEvent) and in two counter-overflow bits (RxMISS and TxCOL). StreamTransfer A method used to significantly reduce the number of interrupts to the host processor during block data transfers (Patent Pending). PacketPage A unified, highly-efficient method of controlling and getting status of a peripheral controller in I/O or Memory space.

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Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET Standby A feature of the CS8900A used to conserve power. When in Standby mode, the CS8900A can be awakened either by 10BASE-T activity or host command. Suspend A feature of the CS8900A used to conserve power. When in Suspend mode, the CS8900A can be awakened only by host command. Transfer The term "transfer" refers to moving frame data across the ISA bus to or from the CS8900A. Transmit Request A Transmit Request is issued by the host to initiate the start of a new packet transmission. A Transmit Request consists of the following three steps in exactly the order shown: 1) The host writes a Transmit Command to the TxCMD register (PacketPage base + 0144h). 2) The host writes the transmit frame ’s length to the TxLength register (PacketPage base + 0146h). 3) The host reads BusST (Register 18) to see in the Rdy4TxNOW bit (Bit 8) is set. 10.5 Suffixes Specific to the CS8900A. These terms have meaning only at the end of a term: A Accept CMD Command CFG Configure CTL Control Dis Disable E Enable h Indicates the number is hexadecimal iE Interrupt Enable ST Status

Crystal LAN™ ISA Ethernet Controller CIRRUS LOGIC PRODUCT DATASHEET

11.0 REVISION HISTORY

12 APR 2001

Page 13 /G44/G49/G55/G53/G52/G62/G19/G29/G21/G64 changed to/G44/G49/G55/G53/G52/G62/G19/G17/G17/G22/G64 Page 41 Added bit definitions for Revisions C and D Page 56 /G51/G68/G70/G78/G72/G87/G51/G68/G74/G72/G3/G69/G68/G86/G72/G3/G14/G3/G19/G21/G20/G27/G75 changed to /G51/G68/G70/G78/G72/G87/G51/G68/G74/G72/G3/G69/G68/G86/G72/G3/G14/G3/G19/G20/G21/G27/G75 Page 81 Table 19: /G53/G72/G74/G76/G86/G87/G72/G85/G3/G24/G15/G47/G53/G91/G38/G55/G47 changed to /G53/G72/G74/G76/G86/G87/G72/G85/G3/G24/G15/G53/G91/G38/G55/G47 Page 86 Table 23: /G19/G23/G20/G19/G75/G3/G87/G82/G3/G19/G20/G20/G75 changed to /G19/G23/G20/G19/G75/G3/G87/G82/G3/G19/G23/G20/G20/G75