CS8427-CSZ

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 Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF-compatible Transceiver  +5.0 V Analog Supply (VA+)  +3.3 V or +5.0 V Digital Interface (VL+)  Flexible 3-wire Serial Digital I/O Ports  Adjustable Sample Rate up to 96 kHz  Low-jitter Clock Recovery  Pin and Microcontroller Read/Write Access to Channel Status and User Data  Microcontroller and Standalone Modes  Differential Cable Driver and Receiver  On-chip Channel Status and User Data Buffer Memories Permit Block Reads & Writes  OMCK System Clock Mode  Decodes Audio CD Q Sub-code General Description The CS8427 is a stereo digital audio transceiver with AES3 and serial digital aud io inputs, AES3 and serial digital audio outputs, and includes comprehensive con- trol ability through a 4-wire microcontroller port. Channel status and user data are assembled in block-sized buff- ers, making read/modify/write cycles easy. A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream. Target applications inclu de A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, effects processors, set-top boxes, and computer and au- tomotive audio systems. The CS8427 is available in 28-pin SOIC and TSSOP packages in Commercial (-10°C to +70°C) and Automo- tive (-40°C to +85°C) grades. The CDB8427 Customer Demonstration Board is also available for device evalu- ation and implementation suggestions. Please see “Ordering Information” on page 49 for complete details. I Serial Audio Input Clock & Data Recovery Misc. Control AES3 S/PDIF Encoder Serial Audio Output Receiver AES3 S/PDIF Decoder C&Ub i t Data Buffer Control Port & Registers Output Clock Generator RXN RXP ILRCK ISCLK SDIN OLRCK OSCLK SDOUT TXP TXN RST OMCK EMPH U TCBL SDA/ CDOUT SCL/ CCLK AD1/ CDIN AD0/ CS INT VA+ AGND FILT RERR VL+ DGND H/S RMCK Driver OCT ‘09 DS477F4

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1. APPENDIX A: EXTERNAL AES3/SPDIF/IEC60958 TRANSMITTER AND RECEIVER COMPO-

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1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. SPECIFIED OPERATING CONDITIONS AGND, DGND = 0 V, all voltages with respect to 0 V. Notes: 1. I²C protocol is supported only in VL+ = 5.0 V mode. ABSOLUTE MAXIMUM RATINGS AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent dam- age to the device. Normal operation is not guaranteed at these extremes. Notes: 2. Transient currents of up to 100 mA will not cause SCR latch-up. Parameter Symbol Min Typ Max Units Power Supply Voltage (Note 1) VA+ VL+ 4.5 2.85 5.0 3.3 or 5.0 5.5 5.5 V V Ambient Operating Temperature: ‘-CS’, ‘CSZ’ & ‘-CZ’ ‘-DS’ & ‘-DZ’ TA -10 -40 +70 +85 Parameter Symbol Min Max Units Power Supply Voltage VL+,VA+ - 6.0 V Input Current, Any Pin Except Supplies (Note 2) I in -± 1 0 m A Input Voltage V in -0.3 (VL+) + 0.3 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C

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DC ELECTRICAL CHARACTERISTICS AGND = DGND = 0 V; all voltages with respect to 0 V. Notes: 3. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 4. Normal operation is defined as RST = HI. DIGITAL INPUT CHARACTERISTICS DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. TRANSMITTER CHARACTERISTICS Parameters Symbol Min Typ Max Units Power-down Mode (Note 3) Supply Current in power down VA+ VL+ = 3.3 V VL+ = 5.0 V μA μA μA Normal Operation (Note 4) Supply Current at 48 kHz frame rate VA+ VL+ = 3.3 V VL+ = 5.0 V 6.3 30.1 46.5 mA mA mA Supply Current at 96 kHz frame rate VA+ VL+ = 3.3 V VL+ = 5.0 V 6.6 44.8 76.6 mA mA mA Parameters Symbol Min Typ Max Units Input Leakage Current I in -± 1 ± 1 0 μA Differential Input Voltage, RXP0 to RXN V TH -2 0 0- m V Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN V OH (VL+) - 1.0 - V Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN V OL -0 . 4 V High-Level Output Voltage, TXP , TXN (23 mA at VL+ = 5.0 V) (15.2 mA at VL+ = 3.3 V) (VL+) - 0.7 (VL+) - 0.7 V V Low-Level Output Voltage, TXP , TXN (23 mA at VL+ = 5.0 V) (15.2 mA at VL+ = 3.3 V) 0.7 0.7 V V High-Level Input Voltage, except RXP , RXN V IH 2.0 (VL+) + 0.3 V Low-Level Input Voltage, except RXP , RXN (Note 5) V IL -0.3 0.4/0.8 V Parameters Symbol Min Typ Max Units TXP Output Resistance VL+ = 5.0 V VL+ = 3.3 V RTXP - Ω Ω TXN Output Resistance VL+ = 5.0 V VL+ = 3.3 V RTXN - Ω Ω

Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Notes: 6. Cycle-to-cycle locking to RXP/RXN using 32 to 96 kHz external PLL filter components. 7. PLL is bypassed (RXD1:0 bits in the Clock Source Co ntrol register set to 10b), clock is input to the RMCK pin. Parameter Symbol Min Typ Max Units RST pin Low Pulse Width 200 - - μs OMCK Frequency for OMCK = 512 * Fso 4.1 - 55.3 MHz OMCK Low and High Width for OMCK = 512 * Fso 7.2 - - ns OMCK Frequency for OMCK = 384 * Fso 3.1 - 41.5 MHz OMCK Low and High Width for OMCK = 384 * Fso 10.8 - - ns OMCK Frequency for OMCK = 256 * Fso 2.0 - 27.7 MHz OMCK Low and High Width for OMCK = 256 * Fso 14.4 - - ns PLL Clock Recovery Sample Rate Range 8.0 - 108.0 kHz RMCK output jitter (Note 6) - 200 - ps RMS RMCK output duty cycle 40 50 60 % RMCK Input Frequency (Note 7) 1.8 - 27.7 MHz RMCK Input Low and High Width (Note 7) 14.4 - - ns AES3 Transmitter Output Jitter - - 1 ns

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Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Notes: 8. The active edges of ISCLK and OSCLK are programmable.

1. When OSCLK, OLRCK, ISCLK, and ILRCK are derive d from OMCK they are clocked from its rising

edge. When these signals are derived from RMCK, they are clocked from its falling edge.

1. The polarity of ILRCK and OLRCK is programmable.
2. No more than 128 SCLK per frame.
3. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
4. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has

Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing

Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate. 1.024 MHz should be safe for all possible conditions.

1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 3. SPI Mode timing

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Note 17, Inputs: Logic 0 = 0 V, Logic 1 = VL+; CL = 20 pF. Notes: 17. I²C protocol is supported only in VL+ = 5.0 V mode.

1. Data must be held for sufficient time to bridge the 25 ns transition time of SCL.

Figure 4. I²C Mode timing

1. TYPICAL CONNECTION DIAGRAM

capacitor between VA+ and AGND. Figure 5. Recommended Connection Diagram for Software Mode

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1. GENERAL DESCRIPTION The CS8427 is an AES3 transceiver intended to be used in digital audio systems. Such systems in- clude digital mixing consoles, effects processors, digital recorders, and computer multimedia sys- tems.

3.1 Audio Input/Output Ports

The CS8427 has the following Audio ports:

• Serial Audio Input Port
• Serial Audio Output Port
• AES3 or S/PDIF Receiver
• AES3 or S/PDIF Transmitter The Serial Audio ports use a three-wire format. This consists of a serial audio data stream, a left- right clock defining the boundaries of the audio sample frames, and a serial clock signal clocking the data bits. A Serial Audio port may operate in either Master or Slave mode. When a port is a Master, it supplies the left-right clock and the serial clock to the exter- nal device that is sending or receiving the serial data. A port in slave mode must have its left-right clock and its serial clock supplied by an external device so that it may send or receive serial audio data. The input sample rate is determined by the stream applied to the Serial Audio Input or to the AES3 Re- ceiver. A phase-locked loop recovers RMCK, the input master clock signal , from the chosen input stream. The output from the device may be through the Se- rial Audio Output, the AES3 Transmitter, or from both simultaneously. In some configurations, all audio ports of the device may be in use at the same time.

3.2 Serial Control Port

Besides the functional bl ocks already described, the device also has a control port that allows the user to read and write the control registers that configure the part. The control port is capable of operating in either SPI or I²C serial mode. This port also has access to buffer memory that allows the user to control what is transmitted in the Channel Status and User bits of the outgoing AES3 stream. The control port is clock ed by the serial clock sig- nal that the user's microcontroller sends it. The MCU can read and write the registers even when the RMCK and OMCK clocks are not running. The Channel Status and User bit buffer memories de- pend on clocking from RMCK and OMCK. They will not function unless the clocks are running, and the RUN bit in the Clock Source Control register is set. There is also an interrupt signal associated with the Serial Control Port and the internal registers. The format of the interrupt may be chosen by a reg- ister setting. There are two interrupt status regis- ters and their associated interrupt mask registers.

3.3 Channel Status and User bit Memory

The memory architecture consists of three buffers to handle the Channel Status information, and an- other three buffers to handle the User bits. The data recovery logic extracts the Channel Status and User bits from the AES3 stream and places them in their respective D buffers. Each buffer con- tains 384 bits. This is enough memory to hold a complete block of Channel Status bits from both A and B channels and a complete block of User bits. When the D buffers are full, the chip transfers their contents into the E buffers. While in the E buffers the Channel Status and User bits may be read or written through the control port. This allows the user to alter them to suit the needs of the applica- tion. The control bit BSEL, in the Channel Status Data Buffer Control register, determines whether the control port has access to the Channel Status bits or the User bits. The AES3 encoder reads the Channel Status and User bits from the F buffers and inserts them into the outgoing AES3 stream. After the F buffers bits are transmitted, the device transfers the current contents of the E buffers into the F buffers. In applications using AES3 in and AES3 out, the CS8427 can automatically transceive user data that conforms to the IEC60958 format. The CS8427 also gives the user access to the bits nec- essary to comply with the serial copy management system (SCMS). In applications where the user want to read/modi- fy/write the Channel Status information that re- quires a microcontroller to actively manage the

3.4 AES3 and S/PDIF Standards

not be considered a substitute for the standards.

1. DATA I/O FLOW AND CLOCKING

Figure 6. CS8427 Internal Block Diagram

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clock routing and the associated control register bits. The clock routing constraints determine which data routing options are actually usable. Users should note that not all the possible data flow switch setting combinations are valid, because of the clock distribution architecture. The AESBP switch, shown in Figure 7 , allows a TTL level bi-phase, mark-encoded data stream connected to RXP to be routed to the TXP and TXN pin drivers. The TXOFF switch causes the TXP and TXN outputs to be driven to ground. There are two possible clock sources. The first, designated the recovered clock, is the output of the PLL, and is output through the RMCK pin. The in- put to the PLL can be either the incoming AES3 data stream or the ILRCK word rate clock from the serial audio input port. The second clock is input through the OMCK pin and would normally be a crystal derived stable clock. The Clock Source Control Register bits determine which clock is used to operate the CS8427. The CS8427 has another constraint related to the state machine that governs the startup of the part. The startup state machine doesn’t complete its process until the PLL has locked unless one is in the transmitter dataflow (See Figure 10). The con- sequence of this is that the transmitter will not transmit until the PLL has locked. If you wish to use the part in transceiver mode and this constraint is a problem, there is a work around. Start the part up in its default configuration and allow the PLL to lock to a signal on the ILRCK pin, then without stopping the part, reconfigure it to the transceiver mode. By studying the following drawings and appropri- ately setting the Data Flow Control and Clock Source Control register bits, the CS8427 can be configured to fit a variety of customer require- ments. Please note that applications implementing both the Serial Audio Output Port and the AES3 Transmitter must operate at the same sample rate because they are both controlled by the same clock source. Figure 9 shows the entire data path clocked by the PLL generated recovered clock. Figure 10 illus- trates a standard AES3 receiver function. Figure 11 shows a standard AES3 transmitter function without PLL. Figure 12 shows a standard AES3 transmitter function with PLL.

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1. AES3 RECEIVER The CS8427 includes an AES3 digital audio re- ceiver and an AES3 digital audio transmitter. A comprehensive buffering scheme provides read/write access to the channel status and user data. This buffering scheme is described in “ Ap- pendix B: Channel Status and User Data Buffer Management”. The AES3 receiver ac cepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver consists of a differential input stage, accessed through pins RXP and RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. External components are used to terminate and isolate the incoming data cables from the CS8427. These components are detailed in “Appendix A: External AES3/SPDIF/IE C60958 Transmitter and Receiver Components” on page 50.

6.1 OMCK System Clock Mode

A special mode is available that allows the clock that is being input through the OMCK pin to be out- put through the RMCK pin. This feature is con- trolled by the SWCLK bit in control register 1. When the PLL loses lock, the frequency of the VCO drops to 300 kHz. The SWCLK function al- lows the clock from RMCK to be used as a clock in the system without any disruption when input is re- moved from the Receiver. This clock switching is performed glitch free. None of the internal circuitry that is clocked from the PLL is driven by the OMCK being output from RMCK. This function is available only in software mode.

6.2 PLL, Jitter Attenuation, and

Please see Appendix C for general description of the PLL, selection of recommended PLL filter com- ponents, and layout considerations. Figure 5 shows the recommended configuration of the two capacitors and one resistor that comprise the PLL filter.

6.3 Error Reporting and Hold Function

While decoding the incoming AES3 data stream, the CS8427 can identify several kinds of error, in- dicated in the Receiver Error register. The UN- LOCK bit indicates whether the PLL is locked to the incoming AES3 data. The V bit reflects the cur- rent validity bit status. The BIP (bi-phase) error bit indicates an error in incoming bi-phase coding. The PAR (parity) bit indicates a received parity er- ror. The error bits are “sticky”: they are set on the first occurrence of the associated error and will remain set until the user reads the register through the control port. This enables the register to log all un- masked errors that occurred since the last time the register was read. The Receiver Error Mask register allows masking of individual errors. The bits in this register serve as masks for the corresponding bits of the Receiv- er Error Register. If a mask bit is set to 1, the error is unmasked, which implies the following: its occur- rence will be reported in the receiver error register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio sample according to the status of the HOLD bits. The HOLD bits allow a choice of holding the previ- ous sample, replacing the current sample with zero (mute), or not changing the current audio sample. If a mask bit is set to 0, the error is masked, which implies the following: its occurrence will not be re- ported in the receiver error register, will not induce a pulse on RERR or generate a RERR interrupt, and will not affect the current audio sample. The QCRC and CCRC errors do not affect the current audio sample, even if unmasked

6.4 Channel Status Data Handling

The first two bytes of the Channel Status block are decoded into the Receiver Channel Status regis- ter. The setting of the CHS bit in the Channel Sta- tus Data Buffer Control register determines whether the channel status decodes are from the A channel (CHS = 0) or B channel (CHS = 1). The PRO (professional) bit is extracted directly. For consumer data, the COPY (copyright) bit is ex- tracted, and the category code and L bits are de- coded to determine SCMS status, indicated by the ORIG (original) bit. If the category code is set to

General on the incoming AES3 stream, copyright will always be indicated even when the stream in- dicates no copyright. Finally, the AUDIO bit is ex- tracted and used to set an AUDIO indicator, as described in the Non-Audio Auto-Detection section below. If 50/15 µs pre-emphasis is detected, the state of the EMPH pin is adjusted accordingly. The encoded channel status bits which indicate sample word length are decoded according to AES3-1992 or IEC 60958. Audio data routed to the serial audio output port is unaffected by the word length settings - all 24 bits are passed on as re- ceived. “Appendix B: Channel Status and User Data Buffer Management” on page 52 describes the overall handling of Channel Status and User bit data.

6.5 User Data Handling

The incoming user data is buffered in a user acces- sible buffer. Various automatic modes of re-trans- mitting received User data are provided. The Appendix: Channel Status and User Data Buffer Management describes the overall handling of CS and U data. Received User data may also be output to the U pin, under the control of a control register bit. De- pending on the data flow and clocking options se- lected, there may not be a clock available to qualify the U data output. Figure 13 illustrates the timing. If the incoming user data bits have been encoded as Q-channel subcode, the data is decoded and presented in ten consecutive register locations. An interrupt may be enabled to indicate the decoding of a new Q-channel block, which may be read through the control port.

6.6 Non-Audio Auto Detection

An AES3 data stream may be used to convey non- audio data, thus it is important to know whether the incoming AES3 data stream is digital audio or not. This information is typica lly conveyed in channel status bit 1 (AUDIO), which is extracted automati- cally by the CS8427. However, certain non-audio sources, such as AC3  or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8427 AES3 receiver can detect such non-audio data. This is accomplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync code is detected, an inter- nal AUTODETECT signal will be asserted. If no ad- ditional sync codes are detected within the next 4096 frames, AUTODETECT will be de-asserted until another sync code is detected. The AUDIO bit in the Receiver Channel Status register is the logi- cal OR of AUTODETECT and the received chan- nel status bit 1. If non-audio data is detected, the data is still processed exactly as if it were normal audio. It is up to the user to mute the outputs as re- quired.

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1. AES3 TRANSMITTER The AES3 transmitter encodes and transmits au- dio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase, mark encoded. The result- ing bit stream is driven to an output connector ei- ther directly or through a transformer. The transmitter clock may be derived from the clock input pin OMCK, or from the incoming data. If OMCK is asynchronous to the data source, an in- terrupt bit (TSLIP) is provided that will go high ev- ery time a data sample is dropped or repeated. Be aware that the pattern of slips does not have hys- teresis and so the occurrence of the interrupt con- dition is not deterministic. The channel status (C) and user channel (U) bits in the transmitted data stream are taken from storage areas within the CS8427. The user can manually access the internal storage or configure the CS8427 to run in one of several automatic modes. The Appendix: Channel Status and User Data Buffer Management provides detailed descriptions of each automatic mode and describes methods of manually accessing the storage areas. The trans- mitted user data can optionally be input through the U pin, under the control of a control port regis- ter bit. Figure 13 shows the timing requirements for clocking U data through the U pin.

7.1 Transmitted Frame and Channel

The TCBL pin is used to control or indicate the start of transmitted channel status block boundaries and may be used as an input or output. In some applications, it may be necessary to con- trol the precise timing of the transmitted AES3 frame boundaries. This may be achieved in three ways: 1) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a new channel status block start. 2) If the AES3 output comes from the AES3 input, setting TCBL as output will cause AES3 output frame boundaries to align with AES3 input frame boundaries. 3) If the AES3 output comes from the serial audio input port while the port is in slave mode and TCBL is set to output, the start of the A channel sub-frame will be aligned with the leading edge of IL-CK.

7.2 TXN and TXP Drivers

The line drivers are low skew, low impedance, dif- ferential outputs capable of driving cables directly. Both drivers are set to ground during reset (RST = low), when no AES3 transmit clock is pro- vided, and optionally under the control of a register bit. The CS8427 also allows immediate mute of the AES3 transmitter audio data through a control reg- ister bit. External components are used to terminate and isolate the external cable from the CS8427. These components are detailed in Appendix A: External AES3/SPDIF/IEC60958 Transmitter and Receiver Components.

mode through the MMR and MMT control bits.

8.1 Receiver Mono Mode

8.2 Transmitter Mono Mode

data stream with a 48-kHz word rate. Figure 7. Software Mode Audio Data Flow Switching Options

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01 CHANNEL

Figure 8. CS8427 Clock Routing

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VLRCK is a virtual word clock, which may not exist, but is used to illustrate the U timing. VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate. If the serial audio output port is in master mode, VLRCK = OLRCK. If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required. Figure 13. AES3 Receiver Timing for U pin output data VLRCK is a virtual word clock, which may not exist, is used to illustrate the CUV timing. In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate. Figure 14. AES3 Transmitter Timing for C, U and V pin input data

Figure 15. Serial Audio Input Example Formats

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Figure 16. Serial Audio Output Example Formats

1. CONTROL PORT DESCRIPTION AND TIMING The control port is used to access the registers, al- lowing the CS8427 to be configured for the desired operational modes and formats. In addition, Chan- nel Status and User data may be read and written through the control port. The operation of the con- trol port may be completely asynchronous with re- spect to the audio sample rates. However, to avoid potential interference problems, the control port pins should remain static if no operation is re- quired. The control port has two modes: SPI and I²C, with the CS8427 acting as a slave device. SPI mode is selected if there is a high to low transition on the AD0/CS pin after the RST pin has been brought high. I²C mode is selected by connecting the AD0/CS pin to VL+ or DGND, thereby permanently selecting the desired AD0 bit address state.

9.1 SPI TM Mode

In SPI mode, CS is the CS8427 chip select signal; CCLK is the control port bit clock (input into the CS8427 from the microcontroller); CDIN is the in- put data line from the microcontroller; CDOUT is the output data line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. Figure 17 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be 0010000b. The eighth bit is a read/write indicator (R/W ), which should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated. The next eight bits are the data which will be placed into the register designat- ed by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 kΩ resistor, if desired. There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a ze- ro, the MAP will stay constant for successive read or writes. If INCR is set to a 1, then the MAP will au- toincrement after each byte is read or written, al- lowing block reads or writes of successive registers. To read a register, the MAP has to be set to the correct address by execut ing a partial write cycle which finishes (CS high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin a read, bring CS low, send out the chip address, and set the read/write bit (R/W) high. The next falling edge of CCLK will clock out the MSB of the addressed register (CDOUT will leave the high impedance state). If the MAP auto increment bit is set to 1, the data for successive registers will appear consecu- tively.

9.2 I²C Mode

In I²C mode, SDA is a bidirectional data line. Data is clocked into and out of the part by SCL, with the clock to data relationship as shown in Figure 18. There is no CS pin. Each individual CS8427 is giv- en a unique address. Pins AD0 and AD1 form the two least significant bits of the chip address and should be connected to VL+ or DGND as desired. The EMPH pin is used to set the AD2 bit, by con- necting a resistor from the EMPH pin to VL+ or to DGND. The state of the pin is sensed while the CS8427 is being reset. The upper four bits of the seven bit address field are fixed at 0010b. To com- municate with a CS8427, the chip address field, which is the first byte sent to the CS8427, should be 0010b followed by the settings of the EMPH AD1, and AD0. The eighth bit of the address is the R/W bit. If the operation is a write, the next byte is the Memory Address Pointer (MAP) which selects the register to be read or written. If the operation is a read, the contents of the register pointed to by the MAP will be output. Setting the auto increment bit in MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit, ACK, which is output from the CS8427 after each input byte is read. The ACK bit is input to the CS8427 from the microcontroller af- ter each transmitted byte. I²C mode is supported only with VL+ = 5.0 V.

9.3 Interrupts

The CS8427 has a comprehensive interrupt capa- bility. The INT output pin is intended to drive the in- terrupt input pin on the host microcontroller. The INT pin may be set to be active low, active high, or active low with no active pull-up transistor. This last

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controller interrupt input pin. Figure 17. Control Port Timing in SPI Mode

0010 AD2-0 R/W

Figure 18. Control Port Timing in I²C Mode

1. CONTROL PORT REGISTER SUMMARY

10.1 Memory Address Pointer (MAP)

modes, which can completely alter the normal operation of the CS8427.

00 Reserved

01 Control 1 SWCLK VSET MUTESAO MUTEAES 0 INT1 INT0 TCBLD

02 Control 2 0 HOLD1 HOLD0 RMCKF MMR MMT MMTCS MMTLR

03 Data Flow Control 0 TXOFF AESBP TXD1 TXD0 SPD1 SPD0 0

04 Clock Source Control 0 RUN CLK1 CLK0 OUTC INC RXD1 RXD0

05 Serial Input Format SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

06 Serial Output Format SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL

07 Interrupt 1 Status TSLIP OSLIP 0 0 0 DETC EFTC RERR

08 Interrupt 2 Status 00 0 0 E F T U Q C H0

09 Interrupt 1 Mask TSLIPM OSLIPM 0 0 0 DETCM EFTCM RERRM

10 Receiver Errors 0 QCRC CCRC UNLOCK V CONF BIP PAR

11 Receiver Error Mask 0 QCRCM CCRCM UNLOCKM VM CONFM BIPM PARM

12 CS Data Buffer Control 0 0 BSEL CBMR DETCI EFTCI CAM CHS

13 U Data Buffer Control 0 0 0 UD UBM1 UBM0 DETUI EFTUI

Table 1. Control Register Map Summary

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1. CONTROL PORT REGISTER BIT DEFINITIONS

11.1 Control 1 (01h)

SWCLK - Controls output of OMCK on RMCK when PLL loses lock Default = ‘0’ 0 - RMCK default function 1 - OMCK output on RMCK pin VSET - Transmitted Validity bit level Default = ‘0’ 0 - Indicates data is valid, linear PCM audio data 1 - Indicates data is invalid or not linear PCM audio data MUTESAO - Mute control for the serial audio output port Default = ‘0’ 0 - Not Muted 1 - Muted MUTEAES - Mute control for the AES transmitter output Default = ‘0’ 0 - Not Muted 1 - Muted INT1:INT0 - Interrupt output pin (INT) control Default = ‘00’ 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull up resistor on the INT pin. 11 - Reserved TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier Default = ‘0’ 0 - TCBL is an input 1 - TCBL is an output

11.2 Control 2 (02h)

HOLD1:HOLD0 - Determine how received audio sample is affected when a receiver error occurs Default = ‘00’ 00 - Hold the last valid audio sample 01 - Replace the current audio sample with 00 (mute) 10 - Do not change the received audio sample 11 - Reserved RMCKF - Select recovered master clock output pin frequency. Default = ‘0’ 0 - RMCK is equal to 256 * Fsi 1 - RMCK is equal to 128 * Fsi 7 6 543210 SWCLK VSET MUTESAO MUTEAES 0 INT1 INT0 TCBLD 7 6 543210

0 HOLD1 HOLD0 RMCKF MMR MMT MMTCS MMTLR

MMR - Select AES3 receiver mono or stereo operation Default = ‘0’ 0 - Normal stereo operation 1 - A and B subframes treated as consecutive samples of one channel of data. Data is duplicated to both left and right parallel outputs of the AES receiver block. The input sample rate (Fsi) is doubled compared to MMR=0 MMT - Select AES3 transmitter mono or stereo operation Default = ‘0’ 0 - Normal stereo operation 1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit) MMTCS - Select A or B channel status data to transmit in mono mode Default = ‘0’ 0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data. MMTLR - Channel Selection for AES Transmitter mono mode Default = ‘0’ 0 - Use left channel input data for consecutive subframe outputs 1- Use right channel input data for consecutive subframe outputs

11.3 Data Flow Control (03h)

The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, and AES3 transmitter. In conjunction with the Clock Source Control regis- ter, multiple Receiver/Transmitter/Transceiver modes may be selected. The output data should be muted prior to changing bits in this register to avoid transients. TXOFF - AES3 Transmitter Output Driver Control Default = ‘0 0 - AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive to 0 V. AESBP - AES3 bypass mode selection Default = ‘0’ 0 - Normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL threshold digital input. The transmitter clock (selecting using the OUTC bit in the Clock Source Control) must be present for the bypass mode to work. TXD1:TXD0 - AES3 Transmitter Data Source Default = ‘01’ 00 - Reserved 01 - Serial audio input port 10 - AES3 receiver 11 - Reserved 7 6 543210

0 TXOFF AESBP TXD1 TXD0 SPD1 SPD0 0

30 DS477F4

SPD1:SPD0 - Serial Audio Output Port Data Source Default = ‘10’ 00 - Reserved 01 - Serial Audio Input Port 10 - AES3 receiver 11 - Reserved

11.4 Clock Source Control (04h)

This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var- ious Receiver/Transmitter/Transceiver modes may be selected. RUN - Controls the internal clocks, allowing the CS8427 to be placed in a “powered down”, low current consumption, state. Default = ‘0’ 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational, allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Power consumption is low. 1 - Normal part operation. This bit must be written to the 1 state to allow the CS8427 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. CLK1:0 - Output side master clock input (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits are changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start the CS8427 (RUN = 1). Default = ‘00’ 00 - OMCK frequency is 256 * Fso 01 - OMCK frequency is 384 * Fso 10 - OMCK frequency is 512 * Fso 11 - Reserved OUTC - Output Time Base Default = ‘0’ 0 - OMCK input pin, modified by the selected divide ratio bits CLK1:0. 1 - Recovered Input Clock INC - Input Time Base Clock Source Default = ‘0’ 0 - Recovered Input Clock 1 - OMCK input pin, modified by the selected divide ratio bits CLK1:0. RXD1:0 - Recovered Input Clock Source Default = ‘00’ 00 - 256 * Fsi, where Fsi is derived from the ILRCK pin (only possible when the serial audio input port is in slave mode) 01 - 256 * Fsi, where Fsi is derived from the AES3 input frame rate 10 - Bypass the PLL and apply an external 256 * Fsi clock through the RMCK pin. The AES3 receiver is held in synchronous reset. This setting is useful to prevent UNLOCK interrupts when using an external RMCK and inputting data through the serial audio input port. 11 - Reserved. 7 6 543210

0 RUN CLK1 CLK0 OUTC INC RXD1 RXD0

11.5 Serial Audio Input Port Data Format (05h)

SIMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio input port is in slave mode 1 - Serial audio input port is in master mode SISF - ISCLK frequency (for master mode) Default = ‘0’ 0 - 64 * Fsi 1 - 128 * Fsi SIRES1:0 - Resolution of the input data, for right-justified formats Default = ‘00’ 00 - 24 bit resolution 01 - 20 bit resolution 10 - 16 bit resolution 11 - Reserved SIJUST - Justification of SDIN data relative to ILRCK Default = ‘0’ 0 - Left-justified 1 - Right-justified SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats Default = ‘0’ 0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge 1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge SISPOL - ISCLK clock polarity Default = ‘0’ 0 - SDIN sampled on rising edges of ISCLK 1 - SDIN sampled on falling edges of ISCLK SILRPOL - ILRCK clock polarity Default = ‘0’ 0 - SDIN data is for the left channel when ILRCK is high 1 - SDIN data is for the right channel when ILRCK is high

11.6 Serial Audio Output Port Data Format (06h)

SOMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio output port is in slave mode 1 - Serial audio output port is in master mode SOSF - OSCLK frequency (for master mode) Default = ‘0’ 0 - 64 * Fso 1 - 128 * Fso 7 6 543210 SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL 7 6 543210 SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL

32 DS477F4

SORES1:0 - Resolution of the output data on SDOUT and on the AES3 output Default = ‘00’ 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and V bits, the time slot normally occupied by the P bit is used to indicate the location of the block start, SDOUT pin only, serial audio output port clock must be derived from the AES3 receiver recovered clock) SOJUST - Justification of SDOUT data relative to OLRCK Default = ‘0’ 0 - Left-justified 1 - Right-justified (master mode only) SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats Default = ‘0’ 0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge 1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge SOSPOL - OSCLK clock polarity Default = ‘0’ 0 - SDOUT transitions occur on falling edges of OSCLK 1 - SDOUT transitions occur on rising edges of OSCLK SOLRPOL - OLRCK clock polarity Default = ‘0’ 0 - SDOUT data is for the left channel when OLRCK is high 1 - SDOUT data is for the right channel when OLRCK is high

11.7 Interrupt 1 Status (07h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00h. TSLIP - AES3 transmitter source data slip interrupt. In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high on receipt of a new TCBL signal. OSLIP - Serial audio output port data slip interrupt. When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sample is dropped or repeated. DETC - D to E C-buffer transfer interrupt. Indicates the completion of a D to E C-buffer transfer. See “Channel Status and User Data Buffer Man- agement” on page 51 for more information. EFTC - E to F C-buffer transfer interrupt. Indicates the completion of a E to F C-buffer transfer. See “Channel Status and User Data Buffer Man- agement” on page 51 for more information. RERR - A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt. 7 6 543210 TSLIP OSLIP 0 0 0 DETC EFTC RERR

11.8 Interrupt 2 Status (08h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00h. DETU - D to E U-buffer transfer interrupt. (Block Mode only) Indicates the completion of a D to E U-buffer transfer. See “Channel Status and User Data Buffer Man- agement” on page 51 for more information. EFTU - E to F U-buffer transfer interrupt. (Block Mode only) Indicates the completion of a E to F U-buffer transfer. See “Channel Status and User Data Buffer Man- agement” on page 51 for more information. QCH - A new block of Q-subcode data is available for reading. The data must be completely read within 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block.

11.9 Interrupt 1 Mask (09h)

The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in the Interrupt 1 register. This register defaults to 00h.

11.10 Interrupt 1 Mode MSB (0Ah) & Interrupt 1 Mode LSB (0Bh)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be- comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in- terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg- isters default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved 7 6 543210 000 0 D E T U E F T U Q C H 0 7 6 543210 TSLIPM OSLIPM 0 0 0 DETCM EFTCM RERRM 7 6 543210 TSLIP1 OSLIP1 0 0 0 DETC1 EFTC1 RERR1 TSLIP0 OSLIP0 0 0 0 DETC0 EFTC0 RERR0

34 DS477F4

11.11 Interrupt 2 Mask (0Ch)

The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in the Interrupt 2 register. This register defaults to 00h.

11.12 Interrupt 2 Mode MSB (0Dh) & Interrupt 2 Mode LSB (0Eh)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be- comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in- terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg- isters default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

11.13 Receiver Channel Status (0Fh) (Read Only)

The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Register. AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, decoded according to IEC60958 and AES3. 0000 - Auxiliary data is not present 0001 - Auxiliary data is 1 bit long 0010 - Auxiliary data is 2 bits long 0011 - Auxiliary data is 3 bits long 0100 - Auxiliary data is 4 bits long 0101 - Auxiliary data is 5 bits long 0110 - Auxiliary data is 6 bits long 0111 - Auxiliary data is 7 bits long 1000 - Auxiliary data is 8 bits long 1001 - 1111 Reserved PRO - Channel status block format indicator 0 - Received channel status block is in consumer format 1 - Received channel status block is in professional format 7 6 543210 0 0 0 0 DETUM EFTUM QCHM 0 7 6 543210 0 0 0 0 DETU1 EFTU1 QCH1 0 0 0 0 0 DETU0 EFTU0 QCH0 0 7 6 543210 AUX3 AUX2 AUX1 AUX0 PRO AUDIO COPY ORIG

0 - Received data is linearly coded PCM audio 1 - Received data is not linearly coded PCM audio COPY - SCMS copyright indicator 0 - Copyright asserted 1 - Copyright not asserted If the category code is set to General in the incoming AES3 stream, copyright will always be indicated by COPY, even when the stream indicates no copyright. ORIG - SCMS generation indicator, decoded from the category code and the L bit. 0 - Received data is 1st generation or higher 1 - Received data is original Note: COPY and ORIG will both be set to 1 if the incoming data is flagged as professional, or if the receiver is not in use.

11.14 Receiver Error (10h) (Read Only)

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries 0 - No error 1 - Error CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid in Pro mode. 0 - No error 1 - Error UNLOCK - PLL lock status bit. Updated on CS block boundaries. 0 - PLL locked 1 - PLL out of lock V - Received AES3 Validity bit status. Updated on sub-frame boundaries. 0 - Data is valid and is normally linear coded PCM audio 1 - Data is invalid, or may be valid compressed audio CONF - Confidence bit. Updated on sub-frame boundaries. 0 - No error 1 - Confidence error. This is the logical OR of BIP and UNLOCK. BIP - Bi-phase error bit. Updated on sub-frame boundaries. 0 - No error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries. 0 - No error 1 - Parity error 7 6 543210

0 QCRC CCRC UNLOCK V CONF BIP PAR

36 DS477F4

11.15 Receiver Error Mask (11h)

The bits in this register serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when unmasked. This register defaults to 00h.

11.16 Channel Status Data Buffer Control (12h)

BSEL - Selects the data buffer register addresses to contain User data or Channel Status data Default = ‘0’ 0 - Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data CBMR - Control for the first 5 bytes of channel status “E” buffer Default = ‘0’ 0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data 1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data DETCI - D to E C-data buffer transfer inhibit bit. Default = ‘0’ 0 - Allow C-data D to E buffer transfers 1 - Inhibit C-data D to E buffer transfers EFTCI - E to F C-data buffer transfer inhibit bit. Default = ‘0’ 0 - Allow C-data E to F buffer transfers 1 - Inhibit C-data E to F buffer transfers CAM - C-data buffer control port access mode bit Default = ‘0’ 0 - One byte mode 1 - Two byte mode CHS - Channel select bit Default = ‘0’ 0 - Channel A information is displayed at the EMPH pin and in the receiver channel status register. Channel A information is output during control port reads when CAM is set to 0 (One Byte Mode) 1 - Channel B information is displayed at EMPH pin and in the receiver channel status register. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode) 7 6 543210

0 QCRCM CCRCM UNLOCKM VM CONFM BIPM PARM

0 0 BSEL CBMR DETCI EFTCI CAM CHS

11.17 User Data Buffer Control (13h)

UD - User data pin (U) direction specifier If this bit is changed during normal operation, then always stop the CS8427 first (RUN = 0), write the new value, then start the CS8427 (RUN = 1). Default = ‘0’ 0 - The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK. This setting also chooses the U pin as the source for transmitted U data. 1 - The U pin is an output. The received U data is clocked out on both rising and falling edges of ILRCK. This setting also chooses the U data buffer as the source of transmitted U data. UBM1:0 - Sets the operating mode of the AES3 U bit manager Default = ‘00’ 00 - Transmit all zeros mode 01 - Block mode 10 - Reserved 11 - Reserved DETUI - D to E U-data buffer transfer inhibit bit (valid in block mode only). Default = ‘0’ 0 - Allow U-data D to E buffer transfers 1 - Inhibit U-data D to E buffer transfers EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only). Default = ‘0’ 0 - Allow U-data E to F buffer transfers 1 - Inhibit U-data E to F buffer transfer

11.18 Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only)

The following 10 registers contain the decoded Q-channel subcode data Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0] while bit 0 of address 14h is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79]. 7 6 543210 0 0 0 UD UBM1 UBM0 DETUI EFTUI 7 6 543210 CONTROL CONTROL CONTROL CONTROL ADDRESS ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK INDEX INDEX INDEX INDEX INDEX INDEX INDEX INDEX MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ABS MINUTE ABS MINUTE ABS MINUT E ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS SECOND ABS SECOND ABS SECOND ABS SECON D ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME

38 DS477F4

11.19 OMCK/RMCK Ratio (1Eh) (Read Only)

This register allows the calculation of the incoming sample rate by the host microcontroller from the equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256 Fso. ORR is represented as an unsigned 2-bit integer and a 6-bit fractional part. The value is mean- ingful only after the PLL has reached lock. For example, if the OMCK is 12.288 MHz, Fso would be 48 kHz (48 kHz = 12.288 MHz/256). Then if the input sample rate is also 48 KHz, you would get 1.0 from the ORR register.(The value from the ORR register is hexadecimal, so the actual value you will get is 40h). If F SO/FSI > 3 63/64, ORR will saturate at the value FFh. Also, there is no hysteresis on ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate. ORR7:6 - Integer part of the ratio (Integer value=Integer(SRR[7:6])) ORR5:0 - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64)

11.20 C-bit or U-bit Data Buffer (20h - 37h)

Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is accessible using these register addresses. 11.21 CS8427 I.D. and Version Register (7Fh) (Read Only) ID3:0 - ID code for the CS8427. Permanently set to 0111 VER3:0 - CS8427 revision level. Revision A is coded as 0001 7 6 543210 ORR7 ORR6 ORR5 ORR4 ORR3 ORR2 ORR1 ORR0 7 6 543210 ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0

1. PIN DESCRIPTION - SOFTWARE MODE SDA/CDOUT AD0/CS EMPH RXP RXN VA+ AGND FILT RST RMCK RERR ILRCK ISCLK SDIN *26 *25 *24 *23 *22 *18 *17 *16 *15 10* 11* 12* 13* 14* SCL/CCLK AD1/CDIN TXP TXN H/S DGND OMCK U INT SDOUT OLRCK OSCLK TCBL * Pins which remain the same function in all modes. + Pins which require a pull up or pull down resistor to select the desired startup option. L SDA/CDOUT 1 Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C mode, SDA is the con- trol I/O data line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the output data from the control port interface on the CS8427 AD0/CS 2 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8427 into SPI control port mode. With no falling edge, the CS8427 defaults to I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8427 EMPH 3 Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 ms pre-emphasis. EMPH is high when the Channel Status data indicates no pre- emphasis or indicates pre-emphasis other than 50/15 ms. This is also a start-up option pin, and requires a 47 kΩ resistor to either VL+ or DGND, which determines the AD2 address bit for the control port in I²C mode RXP RXN Differential Line Receiver (Input) - Receives differential AES3 data. VA+ 6 Positive Analog Power (Input) - Positive supply for the chip’s analog section. Nominally +5.0 V. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock AGND 7 Analog Ground (Input) - Ground for the analog section. AGND should be connected to the same ground as DGND FILT 8 PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See “Appendix C: PLL Filter” on page 55 for recommended schematic and compo- nent values. RST

9 Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal

states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8427 devices where synchronization between devices is important RMCK 10 Input Section Recovered Master Clock (Input/Output) - Input section recovered master clock output when PLL is used. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x. When the PLL is bypassed by the RXD[1:0] bits in the Clock Source Control reg- ister, an external clock of 256 Fs may be applied to this pin

40 DS477F4

RERR 11 Receiver Error (Output) - When high, indicates an error condition from the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity, parity error, bi-phase coding error, confidence, as well as loss of lock by the PLL. Each condition may be optionally masked from affecting the RERR pin using the Receiver Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately when all unmasked errors go away. ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin. TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. OSCLK 16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin OLRCK 17 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs) SDOUT 18 Serial Audio Output Data (Output) - Audio data serial output pin INT 19 Interrupt (Output) - Indicates errors and key events during the operation of the CS8427. All bits affecting INT may be unmasked through bits in the control registers. The condition(s) that initiated interrupt are readable through a control register. The polarity of the INT output, as well as selection of a standard or open drain output, is set through a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero U 20 User Data (Input/Output) - May optionally be used to input User bit data for transmission by the AES3 transmitter, see Figure 13 on page 22 for timing information. Alternatively, the U pin may be set to output User data from the AES3 receiver, see Figure 13 on page 22 for tim- ing information. If not driven, a 47 kΩ pull-down resistor is recommended for the U pin, since the default state of the UD direction bit sets the U pin as an input. The pull-down resistor ensures that the transmitted user data will be zero. If the U pin is always set to be an output, thereby causing the U bit manager to be the source of the U data, then the resistor is not necessary. The U pin should not be tied directly to ground, in case it is programmed to be an output, and subsequently tries to output a logic high. This situation may affect the long term reliability of the device. If the U pin is driven by a logic level output, then a 100Ω series resis- tor is recommended. OMCK 21 System Clock (Input) - When the OMCK System Clock Mode is enabled by the SWCLK bit in the Control 1 register, the clock signal input on this pin is output through RMCK. OMCK serves as reference signal for OMCK/RMCK ratio expressed in register 1Eh. DGND 22 Digital Ground (Input) - Ground for the digital section. DGND should be connected to the same ground as AGND VL+ 23 Positive Digital Power (Input) - Typically +3.3 V or +5.0 V. H/S

24 Hardware/Software Mode Control (Input) - Determines the method of controlling the oper-

ation of the CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontrol- ler. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be permanently tied to VL+ or DGND

Differential Line Driver (Output) - Drivers transmit AES3 data and are pulled low while the CS8427 is in the reset state. AD1/CDIN 27 Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface SCL/CCLK 28 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8427. In I²C mode, SCL requires an external pull-up resistor to VL+

42 DS477F4

1. HARDWARE MODE DESCRIPTION

Figure 19. Audio data is input through the AES3 re- ceiver, and routed to the serial audio output port. through the AES3 transmitter. and the transmitted U and V bits are 0. put, and reflect the received channel status data. shows the timing requirements. modified to the serial audio output port. source of the transmitted C, U and V data.

13.1 Serial Audio Port Formats

native serial audio port formats are available. page 23 and Figure 16 on page 24. are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 19. Hardware Mode

Table 2. Hardware Mode Start-up Options Table 3. Serial Audio Output Formats Available in Hardware Mode Table 4. Serial Audio Input Formats Available in Hardware Mode

44 DS477F4

1. PIN DESCRIPTION - HARDWARE MODE * Pins which remain the same function in all modes. + Pins which require a pull up or pull down resistor to select the desired startup option. COPY DGND2 EMPH/U RXP RXN VA+ AGND FILT RST RMCK RERR ILRCK ISCLK SDIN +28 *26 *25 *24 *23 *22 +*18 *17 *16 *15 10*+ 11*+ 12* 13* 14* ORIG V2 + TXP TXN H/S DGND APMS PRO/C AUDIO/V SDOUT OLRCK OSCLK TCBL L L COPY 1 COPY Channel Status Bit (Output) - Reflects the state of the Copyright Channel Status bit in the incoming AES3 data stream. If the category code is set to General, copyright will be indi- cated whatever the state of the Copyright bit. This is also a start-up option pin, and requires a pull-up or pull-down resistor. DGND2 DGND Digital Ground (Input) - Ground for the digital section. DGND should be connected to the same ground as AGND. EMPH/U 3 Pre-Emphasis Indicator / U-bit (Input/Output) - The EMPH/U pin either reflects the state of the EMPH channel status bit in the incoming AES3 data stream, or is the serial U-bit input for the AES3 transmitted data, clocked by OLRCK. If indicating emphasis: EMPH/U is low when the incoming Channel Status data indicates 50/15 ms pre-emphasis. EMPH/U is high when the Channel Status data indicates no pre-emphasis or indicates pre-emphasis other than 50/15 ms. RXP RXN Differential Line Receiver (Input) - Receives differential AES3 data. VA+ 6 Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5.0 V. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock AGND 7 Analog Ground (Input) - Ground for the analog section. AGND should be connected to the same ground as DGND FILT 8 PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. See “Appendix C: PLL Filter” on page 55 for recommended schematic and component values. RST

9 Reset (Input) - When RST is low, the CS8427 enters a low power mode and all internal states

are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8427 devices where synchronization between devices is important RMCK 10 Input Section Recovered Master Clock (Output) - Input section recovered master clock out- put when PLL is used. Frequency is 256x the sample rate (Fs). RERR 11 Receiver Error (Output) - When high, indicates an error in the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: parity error, bi-phase coding error, confidence, as well as loss of lock by the PLL.

ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin. TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. OSCLK 16 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin OLRCK 17 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs) SDOUT 18 Serial Audio Output Data (Output) - Audio data serial output pin AUDIO/V 19 Audio Channel Status Bit / V-Bit (Input/Output) - Reflects either the state of the audio/non- audio Channel Status bit in the incoming AES3 data stream or is the Validity bit data input for the AES3 transmitted data stream, clocked by OLRCK. PRO/C 20 PRO Channel Status Bit / C-Bit (Input/Output) - Reflects either the state of the Profes- sional/Consumer Channel Status bit in the incoming AES3 data stream or is the serial C-bit input for the AES3 transmitted data, clocked by OLRCK. APMS 21 Serial Audio Input Port Master/Slave Select (Input) - APMS should be connected to VL+ to set serial audio input port as a master, or connected to DGND to set the port as a slave. VL+ VL2+ Positive Digital Power (Input) - Typically +3.3 V or +5.0 V. H/S

24 Hardware/Software Mode Control (Input) - Determines the method of controlling the opera-

tion of the CS8427, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation and access to the CS and U data through dedicated pins. This pin should be permanently tied to VL+ or DGND TXP TXN Differential Line Driver (Output) - Drivers transmit AES3 data and are pulled low while the CS8427 is in the reset state. ORIG 28 ORIG Channel Status Bit (Output) - SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the source of the audio data stream is a copy. A high indicates that the source of the audio data stream is an original recording. This is also a start-up option pin, and requires a pull-up or pull-down resistor.

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1. APPLICATIONS

15.1 Reset, Power Down and Start-up

When RST is low, the CS8427 enters a low power mode and all internal states are reset, including the control port and registers, and the outputs are mut- ed. When RST is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state and begin operation. After the PLL has settled, the AES3 and serial audio outputs will be enabled. Some options within the CS8427 are controlled by a start-up mechanism. During the reset state, some of the output pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the level of these pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8427 by connecting a 47 kΩ resis- tor to between the pin and either VL+ (HI) or DGND (LO). For each mode, every start-up option select pin MUST have an external pull-up or pull-down re- sistor. In software mode, the only start-up option pin is EMPH , which is used to set a chip address bit for the control port in I²C mode. Hardware modes use many start-up options, which are de- tailed in the hardware definition section at the end of this data sheet.

15.2 ID Code and Revision Code

The CS8427 has a register that contains a four bit code to indicate that the addressed device is a CS8427. This is useful when other CS84XX family members are resident in the same system, allow- ing common software modules. The CS8427 four bit revi sion code is also avail- able. This allows the software driver for the CS8427 to identify which revision of the device is in a particular system, and modify its behavior ac- cordingly. To allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known.

15.3 Power Supply, Grounding, and PCB

For most applications, the CS8427 can be operat- ed from a single +5.0 V supply, following normal supply decoupling practices, see Figure 5 on page 11. Note that the I²C protocol is supported only in VL+ = 5.0 V mode. For applications where the re- covered input clock, output on the RMCK pin, is re- quired to be low jitter, then use a separate, quiet, analog +5.0 V supply for VA+, decoupled to AGND. In addition, a separate region of analog ground plane around the FILT, AGND, VA+, RXP, and RXN pins is recommended. The VL+ supply should be well decoupled with a 0.1 μF capacitor to DGND to minimize AES3 trans- mitter induced transients. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount de- coupling capacitors are recommended. Decou- pling capacitors should be mounted on the same side of the board as the CS8427 to minimize induc- tance effects, and all decoupling capacitors should be as close to the CS8427 as possible.

15.4 Synchronization of Multiple

The serial audio output ports of multiple CS8427s can be synchronized if all devices share the same master clock, OSCLK, OLRCK, and RST line and leave the reset state on the same master clock fall- ing edge. Either all the ports need to be in slave mode, or one can be set as a master. Multiple AES3 transmitters can be synchronized if all devices share the same master clock, TCBL, and RST signals and leave the reset state on the same master clock falling edge. The TCBL pin is used to synchronize multiple CS8427 AES3 trans- mitters at the channel status block boundaries. One CS8427 must have its TCBL set to master; the others must be set to slave TCBL. Alternative- ly, TCBL can be derived from external logic, in which case all the CS8427 devices should be set to slave TCBL.

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-013 Controlling Dimension is Millimeters 28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE e

48 DS477F4

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

1. ORDERING INFORMATION Product Description Package Pb-Free Grade Temp Range Container Order # CS8427 96 kHz Digital Audio Interface Transceiver 28-pin SOIC YES Commercial -10 to +70°C Rail CS8427-CSZ Tape & Reel CS8427-CSZR 28-pin TSSOP Rail CS8427-CZZ Tape & Reel CS8427-CZZR Automotive -40 to +85°C Rail CS8427-DZZ Tape & Reel CS8427-DZZR CDB8427 CS8427 Evaluation Board - - - - CDB8427

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ceiver to cables and fiber-optic components.

18.1 AES3 Transmitter External

vides a 5 V peak-to-peak signal into a 110 Ω load. shell, and with pin 1 of the connector grounded. +3.3 V, use resistor values of 243 Ω and 107 Ω. they usually have TTL or CMOS compatible inputs.

18.2 Isolating Transformer Requirements

sources on transformer selection. Figure 20. Professional Output Circuit Figure 21. Consumer Output Circuit Figure 22. TTL/CMOS Output Circuit

18.3 AES3 Receiver External

both the professional and consumer interfaces. however, strongly recommended. with different ground potentials are connected. depended upon to make that electrical connection. the consumer interface is an RCA phono socket.

18.4 Isolating Transformer Requirements

Figure 23. Professional Input Circuit Figure 24. Transformerless Professional Input Circuit Figure 25. Consumer Input Circuit Figure 26. TTL/CMOS Input Circuit

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1. APPENDIX B: CHANNEL STATUS AND

19.1 AES3 Channel Status(C) Bit

as the source of C data for the AES3 transmitter.

19.1.1 Manually accessing the E buffer

ister space of the CS8427, through the control port. Also provided are “D to E” and “E to F” inhibit bits. ior of the buffers with the selected audio data flow. transmit C data with invalid data. having to inhibit the next transfer. Figure 27. Channel Status Data Buffer Structure

19.1.2 Reserving the firs t 5 bytes in the E

19.1.3 Serial Copy Management System

Category Code, Copy bit and L bit appropriately.

19.1.4 Channel Status Data E Buffer

the LS Byte is the B channel data (see Figure 27). identical nature of A and B channel status data. Figure 28. Flowchart for Reading the E Buffer Figure 29. Flowchart for Writing the E Buffer

54 DS477F4

When reading data in one byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. If a write is be- ing done, the CS8427 expects a single byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. One byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. If the control port's autoincrement addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently. Two Byte mode There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8427 to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be in- put to the CS8427's control port. The A channel status data is first, B channel status data second.

19.2 AES3 User (U) Bit Management

The CS8427 U bit manager has two operating modes: transmit all zeros and block mode.

19.2.1 Mode 1: Transmit All Zeros

Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents or U data embedded in an input AES3 data stream. This mode is intended for the user who does not want to transceive U data, and simply wants the output U channel to contain no data.

19.2.2 Mode 2: Block Mode

Mode 2 is very similar to the scheme used to con- trol the C bits. Entire blocks of U data are buffered from input to output, using a cascade of 3 block- sized RAMs to perform the buffering. The user has access to the second of these 3 buffers, denoted the E buffer, through the control port. Block mode is designed for use in AES3 in, AES3 out situations in which input U data is decoded using a microcon- troller through the control port. It is also the only mode in which the user can merge his own U data into the transmitted AES3 data stream. The U buffer access only operates in two byte mode, since there is no concept of A and B blocks for user data. The arrangement of the data is as fol- lows:Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A 0]Bit0[B0]. The arrangement of the data in the each byte is that the MSB is the first received bit and is the first transmitted bit. The first byte read is the first byte received, and the first byte sent is the first byte transmitted. If you read two bytes from the E buffer, you will get the following arrangement:

20.1 General

cover the clock from the incoming data stream. bles do not vary with the data. Figure 30. PLL Block Diagram

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20.2 External Filter Components

20.2.1 General

worst case for an Fsi transition of 96 kHz.

20.2.2 Capacitor Selection

have a significant effect on receiver performance. traces add undesirable inductance to the circuit.

20.2.3 Circuit Board Layout

other and determine the performance of the PLL. Figure 31. Recommended Layout Example

20.3 Component Value Selection

ceiver jitter tolerance (see Table 7).

20.3.1 Identifying the Part Revision

which indicates what revision the part is.

20.3.2 Locking to th e RXP/RXN Receiver

Table 7. Values listed for the 32 to 96 kHz Fs and offer the best output jitter performance. Table 5. Second Line Part Marking Table 6. Locking to RXP/RXN - Fs = 8 to 96 kHz Table 7. Locking to RXP/RXN - Fs = 32 to 96 kHz the circuit and layout recommendations outlined previously.

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20.3.3 Locking to the ILRCK Input

and offer the best output jitter performance.

20.3.4 Jitter Tolerance

Table 7) have been tested to pass this template. Table 8. Locking to the ILRCK Input Figure 32. Jitter Tolerance Template

20.3.5 Jitter Attenuation

imum of 2 dB jitter gain or peaking. Figure 33. Revision A Figure 34. Revision A1 **Figure 35. Revision A2 using A1 values Figure 36. Revision A2 using A2* values**

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F3 January 2005 -Changed format of Figures 15 and 16 on page 23 and page 24. AES3 Direct format on page 15. Register Bit Definitions” on page 32 and page 33. Table 9. Revision History For all product questions and inquiries contact a Cirrus Logic Sales Representative. does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. or service marks of their respective owners. SPI is a trademark of Motorola Inc. AC-3 is a registered trademark of Dolby Laboratories Liscencing, Inc.