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Features
175 dB Dynamic Range –140 dB THD+N No Programming Required No External Master Clock Required Supports Sample Rates up to 211 kHz Input/Output Sample Rate Ratios of 7.5:1 to 1:8 Master Clock Support for 128 x Fs, 256 x Fs, 384 x Fs, and 512 x Fs (Master Mode) 16-, 20-, 24-, or 32-bit Data I/O 32-bit Internal Signal Processing Dither Automatically Applied and Scaled to Output Resolution Flexible 3-wire Serial Digital Audio Input and Output Ports Master and Slave Modes for Both Input and Output Bypass Mode Time Division Multiplexing (TDM) Mode Attenuates Clock Jitter Multiple Device Outputs are Phase Matched Linear Phase FIR Filter Automatic Soft Mute/Unmute +2.5 V Digital Supply (VD) +3.3 V or 5.0 V Digital Interface (VL) Space-saving 20-pin TSSOP and QFN Packages The CS8421 supports sample rates up to 211 kHz and is available in 20-pin TSSOP and QFN packages in both Commercial (-10° to +70°C) and Automotive (-40° to +85°C) grades. The CDB8421 Customer Demonstra- tion board is also available for device evaluation and implementation suggestions. Please see “Ordering In- formation” on page 36 for complete details. Serial Audio Input Time Varying Digital Filters BYPASS Digital PLL Clock Generator ILRCK ISCLK SDIN Sync Info Data Serial Audio Output OLRCK OSCLK SDOUT XTI XTO SRC_UNLOCK
2.5 V (VD) GND
TDM_IN MS_SEL SAIF SAOF Serial Port Mode Decoder Level Translators Level Translators MCLK_OUT 3.3 V or 5.0 V (VL) APRIL ‘09 DS641F2 CS8421
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The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter. Digital audio inputs and outputs can be 32, 24, 20, or 16 bits. Input and output data can be completely asynchronous, synchronous to an external data clock, or the part can operate without any external clock by using an integrated oscillator. Audio data is input and output through configurable 3-wire input/output ports. The CS8421 does not require any soft- ware control via a control port. Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix- ing consoles, high-quality D/A, effects processors, computer audio systems, and automotive audio systems. The CS8421 is also suitable for use as an asynchronous dec imation or interpolation filter. See Cirrus Logic Appli- cation Note AN270, “Audio A/D Conversion with an Asynchronous Decimation Filter”, available at www.cirrus.com for more details.
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- PIN DESCRIPTIONS
1.1 TSSOP PIN DESCRIPTIONS
20 SRC_UNLOCKXTO
MS_SELBYPASS OLRCKILRCK OSCLKISCLK SDOUTSDIN TDM_INMCLK_OUT
Pin Name # Pin Description XTO 1 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 21. XTI 2 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock” on page 21. VD 3 Digital Power (Input) - Digital core power supply. Typically +2.5 V. GND 4 Ground (Input) - Ground for I/O and core logic. RST 5 Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are reset. On initial power-up, RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase. BYPASS 6 Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample rate converter will be bypassed, and any data input through the serial audio input port will be directly output on the serial audio output port. When BYPASS is low, the sample rate converter will operate normally. ILRCK 7 Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the SDIN pin. ISCLK 8 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin. SDIN 9 Serial Audio Input Data Port (Input) - Audio data serial input pin. MCLK_OUT 10 Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See “Master Clock” on page 21. TDM_IN 11 Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 22. SDOUT 12 Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be pulled low through a 47 kΩ resistor, but should not be pulled high. OSCLK 13 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDOUT pin. OLRCK 14 Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the SDOUT pin. MS_SEL 15 Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio ports at startup and reset. See Table 1 on page 19 for settings. GND 16 Ground (Input) - Ground for I/O and core logic. VL 17 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. SAOF 18 Serial Audio Output Format Select (Input) - Used to select the serial audio output format at star- tup and reset. See Table 3 on page 19 for format settings. SAIF 19 Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup and reset. See Table 2 on page 19 for format settings. SRC_UNLOCK 20 SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and Varispeed” on page 20.
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1.2 QFN PIN DESCRIPTIONS
SRC_UNLOC SAIF SAOF ISCLK SDIN MCLK_OUT TDM_IN SDOUT VD GND RST BYPASS ILRCK VL GND MS_SEL OLRCK OSCLK
Pin Name # Pin Description VD 1 Digital Power (Input) - Digital core power supply. Typically +2.5 V. GND 2 Ground (Input) - Ground for I/O and core logic. RST 3 Reset (Input) - When RST is low, the CS8421 enters a low-power mode and all internal states are reset. On initial power-up, RST must be held low until the power supply is stable and all input clocks are stable in frequency and phase. BYPASS 4 Sample Rate Converter Bypass (Input) - When BYPASS is high, the sample-rate converter will be bypassed, and any data input through the serial audio input port will be directly output on the serial audio output port. When BYPASS is low, the sample rate converter will operate normally. ILRCK 5 Serial Audio Input Left/Right Clock (Input/Output) - Word-rate clock for the audio data on the SDIN pin. ISCLK 6 Serial Audio Bit Clock (Input/Output) - Serial-bit clock for audio data on the SDIN pin. SDIN 7 Serial Audio Input Data Port (Input) - Audio data serial input pin. MCLK_OUT 8 Master Clock Output (Output) - Buffered and level-shifted output for Master clock. If MCLK_OUT is not required, this pin should be pulled high through a 47 kΩ resistor to turn the output off. See “Master Clock” on page 21. TDM_IN 9 Serial Audio TDM Input (Input) - Time Division Multiplexing serial audio data input. Grounded when not used. See “Time Division Multiplexing (TDM) Mode” on page 22. SDOUT 10 Serial Audio Output Data Port (Output) - Audio data serial output pin. Optionally this pin may be pulled low through a 47 kΩ resistor, but should not be pulled high. OSCLK 11 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin. OLRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. MS_SEL 13 Master/Slave Select (Input) - Used to select Master or Slave for the input and output serial audio ports at startup and reset. See Table 1 on page 19 for settings. GND 14 Ground (Input) - Ground for I/O and core logic. VL 15 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. SAOF 16 Serial Audio Output Format Select (Input) - Used to select the serial audio output format at star- tup and reset. See Table 3 on page 19 for format settings. SAIF 17 Serial Audio Input Format Select (Input) - Used to select the serial audio input format at startup and reset. See Table 2 on page 19 for format settings. SRC_UNLOCK 18 SRC Unlock Indicator (Output) - Indicates when the SRC is unlocked. See “SRC Locking and Varispeed” on page 20. XTO 19 Crystal Out (Output) - Crystal output for Master clock. See “Master Clock” on page 21. XTI 20 Crystal/Oscillator In (Input) - Crystal or digital clock input for Master clock. See “Master Clock” on page 21. Thermal Pad - Thermal Pad - Thermal relief pad for optimized heat dissipation. This pad must be electrically con- nected to GND. See “Power Supply, Grounding, and PCB Layout” on page 24 for more information.
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- CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Notes: 1. Transient currents of up to 10 0 mA will not cause SCR latch-up. 2. Numbers separated by a colon indicate input and outp ut sample rates. For example, 48 kHz:96 kHz in- dicates that Fsi = 48 khz and Fso = 96 kHz. Parameter Symbol Min Nominal Max Units Power Supply Voltage VD VL 2.38 3.14 2.5 3.3 or 5.0 2.62 5.25 V V Ambient Operating Temperature: ‘-CZ’ ‘-CNZ’ ‘-DZ’ TA -10 -10 -40 +70 +70 +85 Parameter Symbol Min Max Units Power Supply Voltage VD VL -0.3 -0.3 3.5 6.0 V V Input Current, Any Pin Except Supplies (Note 1) Iin -± 1 0 m A Input Voltage V in -0.3 VL+0.4 V Ambient Operating Temperature (power applied) T A -55 +125 °C Storage Temperature T stg -65 +150 °C
PERFORMANCE SPECIFICATIONS (XTI/XTO = 27 MHz; Input signal = 1.000 kHz, 0 dBFS, Measurement Bandwidth = 20 to Fso/2 Hz, and Word Width = 32-Bits, unless otherwise stated.) Parameter Min Typ Max Units Resolution 16 - 32 bits Sample Rate with XTI = 27.000 MHz Slave Master 7.2 207 211 kHz kHz Sample Rate with other XTI clocks Slave Master XTI/3750 XTI/512 XTI/130 XTI/128 kHz kHz Sample Rate with ring oscillator (XTI to GND or VL, XTO floating) 12 - 96 kHz Sample Rate Ratio - Upsampling - - 1:8 Sample Rate Ratio - Downsampling - - 7.5:1 Interchannel Gain Mismatch - 0.0 - dB Interchannel Phase Deviation - 0.0 - Degrees Peak Idle Channel Noise Component (32-bit operation) - - -192 dBFS Dynamic Range (20 Hz to Fso/2, 1 kHz, -60 dBFS Input) 44.1 kHz:48 kHz A-Weighted Unweighted 180 177 dB dB 44.1 kHz:192 kHz A-Weighted Unweighted 175 172 dB dB 48 kHz:44.1 kHz A-Weighted Unweighted 180 177 dB dB 48 kHz:96 kHz A-Weighted Unweighted 179 176 dB dB 96 kHz:48 kHz A-Weighted Unweighted 176 173 dB dB 1 9 2k H z : 3 2k H z A - W e i g h t e d Unweighted 175 172 dB dB Total Harmonic Distortion + Noise (20 Hz to Fso/2, 1 kHz, 0 dBFS Input) 32 kHz:48 kHz -- 1 6 1 - d B 44.1 kHz:48 kHz -- 1 7 1 - d B 44.1 kHz:192 kHz - -130 - dB 48 kHz:44.1 kHz -- 1 6 0 - d B 48 kHz:96 kHz -- 1 4 8 - d B 96 kHz:48 kHz -- 1 6 8 - d B 1 9 2k H z : 3 2k H z -- 1 7 3 - d B
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DIGITAL FILTER CHARACTERISTICS 3. The equation for the group delay through the sample-rate converter is (56.581 / Fsi) + (55.658 / Fso). For example, if the input sample rate is 192 kHz and the output sample rate is 96 kHz, the group delay through the sample-rate converter is (56.581/192,000) + (55.658/96,000) =.875 milliseconds. DC ELECTRICAL CHARACTERISTICS (GND = 0 V; all voltages with respect to 0 V.) 4. Power Down Mode is defined as RST = LOW with all clocks and data lines held static, except when a crystal is attached across XTI-XTO, in which case the crystal will begin oscillating. 5. Normal operation is defined as RST = HI. Parameter Min Typ Max Units Passband (Upsampling or Downsampling) - - 0.4535*Fso Hz Passband Ripple - - ±0.007 dB Stopband 0.5465*Fso - - Hz Stopband Attenuation 125 - - dB Group Delay (Note 3) msParameters Symbol Min Typ Max Units Power-Down Mode (Note 4) Supply Current in power-down VD (Oscillator attached to XTI-XTO) VL = 3.3 V VL = 5.0 V 100 200 μA μA μA Supply Current in power-down VD (Crystal attached to XTI-XTO) VL = 3.3 V VL = 5.0 V 100 1.5 μA mA mA Normal Operation (Note 5) Supply Current at 48 kHz Fsi and Fso VD (Oscillator attached to XTI-XTO) VL = 3.3 V VL = 5.0 V 2.5 mA mA mA Supply Current at 192 kHz Fsi and Fso VD (Oscillator attached to XTI-XTO) VL = 3.3 V VL = 5.0 V mA mA mA Supply Current at 48 kHz Fsi and Fso VD (Crystal attached to XTI-XTO) VL = 3.3 V VL = 5.0 V mA mA mA Supply Current at 192 kHz Fsi and Fso VD (Crystal attached to XTI-XTO) VL = 3.3 V VL = 5.0 V 6.5 mA mA mA
DIGITAL INPUT CHARACTERISTICS DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.) SWITCHING SPECIFICATIONS (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameters Symbol Min Typ Max Units Input Leakage Current I in -- ± 1 0 μA Input Capacitance I in -8- p F Input Hysteresis -2 5 0- m V Parameters Symbol Min Max Units High-Level Output Voltage, except MCLK_OUT and SDOUT (IOH=-4 mA) V OH 0.77xVL - V Low-Level Output Voltage, except MCLK_OUT and SDOUT (IOL=4 mA) V OL -. 6 V High-Level Output Voltage, MCLK_OUT (I OH=-6 mA) V OH 0.77xVL - V Low-Level Output Voltage, MCLK_OUT (I OL=6 mA) V OL -. 6 V High-Level Output Voltage, SDOUT (I OH=-8 mA) V OH 0.77xVL - V Low-Level Output Voltage, SDOUT (I OL=8 mA) V OL -. 6 5 V High-Level Input Voltage V IH 0.6xVL VL+0.3 V Low-Level Input Voltage V IL -0.3 0.8 V Parameters Symbol Min Max Units RST pin Low Pulse Width (Note 6) 1- m s XTI Frequency (Note 7) Crystal Digital Clock Source 16.384 1.024 27.000 27.000 MHz MHz XTI Pulse Width High/Low 14.8 - ns MCLK_OUT Duty Cycle 45 55 % Slave Mode I/OSCLK Frequency - 24.576 MHz OLRCK High Time (Note 8) tlrckh 326 - ns I/OSCLK High Time t sckh 9- n s I/OSCLK Low Time t sckl 9- n s I/OLRCK Edge to I/OSCLK Rising t lcks 6- n s OLRCK Rising Edge to OSCLK Rising Edge (TDM) t fss 5- n s I/OSCLK Rising Edge to I/OLRCK Edge t lckd 5- n s OSCLK Rising Edge to OLRCK Falling Edge (TDM) t fsh 5- n s OSCLK Falling Edge/OLRCK Edge to SDOUT Output Valid t dpd -1 8 n s SDIN/TDM_IN Setup Time Before I/OSCLK Rising Edge t ds 3.5 - ns SDIN/TDM_IN Hold Time After I/OSCLK Rising Edge t dh 5- n s
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- After powering up the CS8421, RST should be held low until the power supplies and clocks are settled.
- The maximum possible sample rate is XTI/128.
- OLRCK must remain high for at least 8 OSCLK periods in TDM Mode.
- Only the input or the output serial port can be set as master at a given time.
Figure 1. Non-TDM Slave Mode Timing Figure 2. TDM Slave Mode Timing Figure 3. Non-TDM Master Mode Timing Figure 4. TDM Master Mode Timing
- TYPICAL CONNEC TION DIAGRAMS
Figure 5. Typical Connection Diagram, No External Master Clock and output serial ports as described in Table 2 on page 19 and Table 3 on page 19.
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Figure 6. Typical Connection Diagram, Master and Slave Modes “Serial Audio Output Port Start-Up Options (SAOF),” on page 19. ** MCLK_OUT pin should be pulled high through a 47 kΩ resistor if an MCLK output is not needed.
- APPLICATIONS The CS8421 is a 32-bit, high-performance, monolithic CMOS stereo asynchronous sample-rate converter. The digital audio data is input and output through configurable 3-wire serial ports. The digital audio input/output ports offer Left-Justified, Right-Justified, and I²S serial audio formats. The CS8421 also supports a TDM Mode which al- lows multiple channels of digital audio data on one serial line. A Bypass Mode allows the data to be passed directly to the output port without sample rate conversion. The CS8421 does not require a control port interface, helping to speed design time by not requiring the user to de- velop software to configure the part. Pins that are sensed after reset allow the part to be configured. See “Reset, Power-Down, and Start-Up” on page 23. Target applications include digital recording systems (DVD-R/RW, CD-R/RW, PVR, DAT, MD, and VTR), digital mix- ing consoles, high quality D/A, effects processors and computer audio systems. Figure 5 and 6 show the supply and external connections to the CS8421.
4.1 Three-wire Serial input/Output Audio Port
A 3-wire serial audio input/output port is provided. The interface format should be chosen to suit the attached device through the MS_SEL, SAIF, and SAOF pins. Tables 1, 2, and 3 show the pin functions and their corresponding set- tings. The following parameters are adjustable:
- Master or Slave
- Master clock (MCLK) frequencies of 128*Fsi/o, 2 56*Fsi/o, 384*Fsi/o, and 512*Fsi/o (Master Mode)
- Audio data resolution of 16-, 20-, 24-, or 32-bits
- Left- or Right-Justification of the data relati ve to left/right clock (LRCK) as well as I²S Figures 7, 8, and 9 show the input/output formats available. In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the XTI input pin master clock. In Slave Mode, the left/right clock and the serial bit cloc k are inputs and may be asyn chronous to the XTI master clock. The left/right clock should be continuous, but the duty cycle can be less than 50% if enough serial clocks are present in each phase to clock all of the data bits. ISCLK is always set to 64*Fsi when the input is set to master. In normal operation, OSCLK is set to 64*Fso. In TDM Slave Mode, OSCLK must operate at N*64*Fso, where N is the number of CS8421’s connected together. In TDM Master Mode, OSCLK is set to 256*Fso For more information about serial audio formats, refer to the Cirrus Logic applications note AN282, “The 2-Channel Serial Audio Interface: A Tutorial”, available at www.cirrus.com
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4.2 Mode Selection
The CS8421 uses the resistors attached to the MS_SEL, SAIF, and SAOF pins to determine the modes of operation. direct connection to VL or GND as appropriate. imize noise. Tables 1, 2, and 3 show the pin functions and their corresponding settings. Figure 7. Serial Audio Interface Format - I²S Figure 8. Serial Audio Interface Format - Left-Justified Figure 9. Serial Audio Interface Format - Right-Justified
Table 1. Serial Audio Port Master/Slave and Clock Ratio Select Start-Up Options (MS_SEL) Table 2. Serial Audio Input Port Start-Up Options (SAIF) Table 3. Serial Audio Output Port Start-Up Options (SAOF)
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4.3 Sample Rate Converter (SRC)
Multirate digital signal processing techniques are used to conceptually upsample the incoming data to a very high rate and then downsample to the outgoing rate. The internal data path is 32-bits wide even if a lower bit depth is selected at the output. The filtering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates are greater than or equal to 44.1 kHz. When the out- put sample rate becomes less than the input sample rate, the input is automatically band-limited to avoid aliasing products in the output. Ca reful design ensures minimum ripple and distortion products are added to the incoming signal. The SRC also determines the ratio between the incoming and outgoing sample rates and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little impact on the dynamic performance of the rate converter and has no influence on the output clock.
4.3.1 Data Resolution and Dither
When using the serial audio input port in Left-Justified and I²S Modes, all input data is treated as 32-bits wide. Any truncation that has been done prior to the CS8421 to less than 32-bits should have been done using an appropriate dithering process. If the serial audio input port is in Right-Justified Mode, the input data will be truncated to the bit depth set by SAIF pin setting. If the SAIF bit depth is set to 16-, 20-, or 24- bits, and the input data is 32-bits wide, truncation distortion will occur. Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (i.e. 16 clocks instead of 20 clocks), the input words will be truncated, caus ing truncation distortion at low levels. In summar y, there is no dithering mechanism on the input side of the CS8421, and care must be taken to ensure that no truncation occurs. Dithering is used internally where appropriate inside the SRC block. The output side of the SRC can be set to 16-, 20-, 24-, or 32-bits. Dithering is applied and is automatically scaled to the selected output word length. This dither is not correlated between left and right channels.
4.3.2 SRC Locking and Varispeed
The SRC calculates the ratio between the input sample rate and the output sample rate and uses this in- formation to set up various parameters inside the SRC block. The SRC takes some time to make this cal- culation, approximately 4200/Fso (8.75 ms at Fso of 48 kHz). If Fsi is changing, as in a varispeed application, the SRC will track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the incoming sample rate is stable, the SRC will return to normal levels of audio quality. The data buffer in the SRC can overflow if the input samp le rate changes at greater than 10%/sec. There is no provision for varispeed applications where Fso is changing. The SRC_UNLOCK pin is used to indicate when the SRC is not locked. When RST is asserted, or if there is a change in Fsi or Fso, SRC_UNLOCK will be set high. The SRC_UNLOCK pin will continue to be high until the SRC has reacquired lock and settled, at wh ich point it will transition low. When the SRC_UNLOCK pin is set low, SDOUT is outputting valid audio data. This can be used to signal a DAC to unmute its output.
4.3.3 Bypass Mode
When the BYPASS pin is set high, the input data bypasses the sample rate converter and is sent directly to the serial audio output port. No dithering is performed on the output data. This mode is ideal for passing non-audio data through without a sample-rate conversion. ILRCK and OLRCK should be the same sam- ple rate and synchronous in this mode.
4.3.4 Muting
The SDOUT pin is set to all zero output (full mute) immediately after the RST pin is set high. When the output from the SRC becomes valid, though the SRC may not have reached full performance, SDOUT is unmuted over a period of approximately 4096 OLRCK cycles (soft unmuted). When the output becomes invalid, depending on the condition, SDOUT is either immediately set to all zero output (hard muted) or SDOUT is muted over a period of approximately 4096 OLRCK cycles until it reaches full mute (soft mut- ed). The SRC will soft mute SDOUT if there is an illegal ratio between ILRCK and the XTI master clock. Conditions that will cause the SRC to hard mute SDOUT include removing OLRCK, the RST pin being set low, or illegal ratios between OLRCK and the XTI master clock. Af ter all invalid st ates have been cleared, the SRC will soft unmute SDOUT.
4.3.5 Group Delay and Phase Matching Between Multiple CS8421 Parts
The equation for the group delay through the sample rate converter is shown in “Digital Filter Character- istics” on page 12. This phase delay is equal across multiple parts. Therefore, when multiple parts operate at the same Fsi and Fso and use a common XTI/XTO clock, their output data is phase matched.
4.3.6 Master Clock
The CS8421 uses the clock signal supplied through XTI as its master clock (MCLK). MCLK can be sup- plied from a digital clock source, a crystal oscillator, or a fundamental mode crystal. Figure 10 shows the typical connection diagram for using a fundamental mode crystal. Please refer to the crystal manufactur- er’s specifications for the external capacitor recommendations. If XTO is not used, such as with a digital clock source or crystal oscillator, XTO should be left unconnected or pulled low through a 47 kΩ resistor to GND. If either serial audio port is set as master, MCLK will be used to supply the sub-clocks to the master SCLK and LRCK. In this case, MCLK will be synchronous to the master serial audio port. If both serial audio ports are set as slave, MCLK can be asynchronous to either or both ports. If the user needs to change the clock source to XTI while the CS8421 is still powered on and running, a RESET must be issued once the XTI clock source is present and valid to ensure proper operation. When both serial ports are configured as slave an d operating at sample rate s less than 96 kHz, the CS8421 has the ability to operate wi thout a master clock input through XTI. This benefits the design by not requiring extra external clock components (lowering production cost) and not requiring a master clock to be routed to the CS8421, resulting in lowered noise contribution in the system. In this mode, an internal oscillator provides the clock to run all of the internal logic. To enable the internal oscillator, simply tie XTI to GND or VL. In this mode, XTO should be left unconnected. The CS8421 can also provide a buffered MCLK output through the MCLK_OUT pin. This pin can be used to supply MCLK to other system components that operate synchronously to MCLK. If MCLK_OUT is not needed, the output of the pin can be disabled by pu lling the pin high through a 47 k Ω resistor to VL. MCLK_OUT is also disabled when using the internal oscillator mode. The MCLK_OUT pin will be set low when disabled by using the internal oscillator mode.
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4.3.7 Clocking
- If the input is set to master, Fsi ≤ XTI/128 and Fso ≤ XTI/130.
- If the output is set to master, Fso ≤ XTI/128 and Fsi ≤ XTI/130.
- If both input and output are set to slave, XTI ≥ 130*[maximum(Fsi,Fso)], XTI/Fsi < 3750, and XTI/Fso < 3750.
4.4 Time Division Mult iplexing (TDM) Mode
data to be multiplexed onto one line for input into a DSP or other TDM-capable multichannel device. the remaining CS8421’s output ports set to slave, as shown in Figure 14. on the first OSCLK falling edge after an OLRCK transition and is valid on the rising edge of OSCLK. 48 kHz, N = 8 (16 channels of serial audio data). with the valid data sample left-justifi ed within the time-slot. Valid data lengths are 16-, 20-, 24- or 32-bits. Figures 11 and 12 show the interface format for Master and Slave TDM Modes with a 32-bit word-length. Figure 10. Typical Connection Diagram for Crystal Circuit Figure 11. TDM Slave Mode Timing Diagram
4.5 Reset, Power-Down, and Start-Up
proximately 4 μs), the part is set to normal operation and all outputs are functional.
256 OSCLKs
Figure 12. TDM Master Mode Timing Diagram Figure 13. TDM Mode Configuration (All CS8421 Outputs are Slave) Figure 14. TDM Mode Configuration (First CS8421 Output is Master, All Others are Slave)
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4.6 Power Supply, Gr ounding, and PCB Layout
The CS8421 operates from a VD = +2.5 V and VL = +3.3 V or +5.0 V supply. These supplies may be set independently. Follow normal supply decoupling practices; see Figure 6. Extensive use of power an d ground planes, grou nd-plane fill in unu sed areas, and surface-mount decou- pling capacitors are recommended. Decoupling capacit ors should be mounted on the same side of the board as the CS8421 to minimize inductance effects, a nd all decoupling capacitors should be as close to the CS8421 as possible. The pin of the configuration resistors not connected to MS_SEL, SAIF, and SAOF should be connected as close as possible to VL or GND. The CS8421 is available in the compact QFN package. The underside of the QFN package reveals a metal pad that serves as a thermal relief to provide for optimal heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers.
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Figure 21. Wideband FFT Plot (16k Points) 0 dBFS 1 kHz Figure 22. Wideband FFT Plot (16k Points) -60 dBFS Figure 23. Wideband FFT Plot (16k Points) -60 dBFS Figure 24. Wideband FFT Plot (16k Points) -60 dBFS Figure 25. Wideband FFT Plot (16k Points) -60 dBFS Figure 26. Wideband FFT Plot (16k Points) -60 dBFS
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Figure 33. Wideband FFT Plot (16k Points) 0 dBFS 80 kHz Figure 34. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Figure 35. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Figure 36. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Figure 37. Wideband FFT Plot (16k Points) 0 dBFS 20 kHz Figure 38. THD+N vs. Output Sample Rate, 0 dBFS 1 kHz
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Figure 45. Dynamic Range vs. Output Sample Rate, - Figure 46. Dynamic Range vs. Output Sample Rate, - Figure 47. Frequency Response with 0 dBFS Input Figure 48. Passband Ripple, 192 kHz:48 kHz Figure 49. Dynamic Range vs. Output Sample Rate, - Figure 50. Linearity Error, 0 to -140 dBFS Input, 200 Hz
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Figure 57. THD+N vs. Input Amplitude, 1 kHz Tone, Figure 58. THD+N vs. Input Amplitude, 1 kHz Tone, Figure 59. THD+N vs. Input Amplitude, 1 kHz Tone, Figure 60. THD+N vs. Input Amplitude, 1 kHz Tone, Figure 61. THD+N vs. Input Amplitude, 1 kHz Tone, Figure 62. THD+N vs. Input Amplitude, 1 kHz Tone,
34 DS641F2
- PACKAGE DIMENSIONS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusi on/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re- duce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. TSSOP THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 2 Layer Board
4 Layer Board θJA
°C/Watt °C/Watt 20L TSSOP (4.4 MM BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW
- Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated terminal and is measured between 0.23mm and 0.33mm from the terminal tip. QFN THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A1 0.0000 -- 0.0020 0.00 -- 0.05 1 D 0.1969 BSC 5.00 BSC 1 E 0.1969 BSC 5.00 BSC 1 e 0.0256 BSC 0.65 BSC 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 2 Layer Board
°C/Watt °C/Watt Side View A A1 D2L b e Pin #1 Corner Bottom ViewTop View Pin #1 Corner D E E2 20-PIN QFN (5 × 5 MM BODY) PACKAGE DRAWING
36 DS641F2
- ORDERING INFORMATION 8. REVISION HISTORY Release Changes A1 Initial Advance Release PP1 -Updated “Features” on page 1. -Updated “Sample Rate with other XTI clocks” on page 11. -Updated “DC Electrical Characteristics” on page 12. -Updated “Digital Input Characteristics” on page 13. -Updated “Digital Interface Specifications” on page 13 -Updated Figure 6. “Typical Connection Diagram, Master and Slave Modes” on page 16. -Added Figure 5. “Typical Connection Diagram, No External Master Clock” on page 15. -Corrected reference to Bypass Mode to output only data on page 17. -Added Section 4.3.7 “Clocking” on page 22. -Updated “Master Clock” on page 21. -Updated “Time Division Multiplexing (TDM) Mode” on page 22. -Added Thermal Pad label “Pin Descriptions” on page 6. -Added Thermal Pad pin description to “QFN Pin Descriptions” on page 8. -Updated “Performance Plots” on page 25. PP2 -Updated “Characteristics and Specifications” on page 10. -Corrected Section 4.3.7 “Clocking” on page 22. -Corrected “QFN Thermal Characteristics” on page 35. PP3 -Updated “Digital Interface Specifications” on page 13. -Updated “Switching Specifications” on page 13. F1 Final Release F2 -Updated Thermal Pad pin description in “QFN Pin Descriptions” on page 8. -Updated “Power Supply, Grounding, and PCB Layout” on page 24.
ORDERING INFORMATION
Product Description Package Pb-Free Temp Range Container Order# CS8421 32-bit Asynchronous Sample Rate Converter 20-TSSOP YES -10° to +70°C Rail CS8421-CZZ Tape and Reel CS8421-CZZR 20-QFN Rail CS8421-CNZ Tape and Reel CS8421-CNZR 20-TSSOP -40° to +85°C Rail CS8421-DZZ Tape and Reel CS8421-DZZR CDB8421 Evaluation Board for CS8421 - - - CDB8421
Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIR- RUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOM- ER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING AT- TORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.