CS8420-CSR

CS8420_07 CIRRUS | Alldatasheet

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Technical content

Features

 Complete IEC60958, AES3, S/PDIF, EIAJ CP1201-compatible Transceiver with Asynchronous Sample Rate Converter  Flexible 3-wire Serial Digital I/O Ports  8-kHz to 108-kHz Sample Rate Range  1:3 and 3:1 Maximum Input to Output Sample Rate Ratio  128 dB Dynamic Range  -117 dB THD+N at 1 kHz  Excellent Performance at Almost a 1:1 Ratio  Excellent Clock Jitter Rejection  24-bit I/O Words  Pin and Microcontroller Read/Write Access to Channel Status and User Data  Microcontroller and Stand-Alone Modes General Description The CS8420 is a stereo digital audio sample rate con- verter (SRC) with AES3-type and serial digital audio inputs, AES3-type and serial digital audio outputs, and includes comprehensive control ability via a 4-wire mi- crocontroller port. Channel status and user data can be assembled in block-sized buffers, making read/modify/write cycles easy. Digital audio inputs and outputs may be 24, 20, or 16 bits. The input data can be completely asynchronous to the output data, with the output data being synchronous to an external system clock. The CS8420 is available in a 28-pin SOIC package in both Commercial (-10º to +70º C) and Automotive grades (-40º to +85º C). The CDB8420 Customer Dem- onstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 93 for or- dering information. Target applications include CD-R, DAT, MD, DVD and VTR equipment, mixing consoles, digital audio trans- mission equipment, high-quality D/A and A/D converters, effects processors, and computer audio systems. Serial Audio Input Clock & Data Recovery Misc. Control AES3 S/PDIF Encoder Serial Audio Output Receiver AES3 S/PDIF Decoder Sample Rate Converter C&Ub i t Data Buffer Control Port & Registers Output Clock Generator RXN RXP ILRCK ISCLK SDIN OLRCK OSCLK SDOUT TXP TXN RST OMCK EMPH U TCBL SDA/ CDOUT SCL/ CCLK AD1/ CDIN AD0/ CS INT VA+ AGND FILT RERR VD+ DGND H/S RMCK Driver APRIL '07 DS245F4 CS8420

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1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. SPECIFIED OPERATING CONDITIONS AGND, DGND = 0 V, all voltages with respect to 0 V. ABSOLUTE MAXIMUM RATINGS AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent dam- age to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up. Parameter Symbol Min Typ Max Units Power Supply Voltage VD+, VA+ 4.75 5.0 5.25 V Ambient Operating Temperature: Commercial Grade Automotive Grade TA -10 -40 +70 +85 Parameter Symbol Min Max Units Power Supply Voltage VD+, VA+ - 6.0 V Input Current, Any Pin Except Supplies, RXP/RXN (Note 1) I in -± 1 0 m A Input Voltage V in -0.3 (VD+) + 0.3 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C

PERFORMANCE SPECIFICATIONS DIGITAL FILTER CHARACTERISTICS 2. See “AES3 Transmitter and Receiver” on page 28. DC ELECTRICAL SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. 3. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 4. Normal operation is defined as RST = HI. Parameter* Symbol Min Typ Max Units Dynamic Range 120 128 - dB Input Sample Rate (serial input port) Fsi 8 - 108 kHz Output Sample Rate Fso 8 - 108 kHz Output to Input Sample Rate Ratio 0.33 - 3 Total Harmonic Distortion + Noise 1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7 1 kHz, -1 dBFS, 0.33 < Fso/Fsi < 3 10 kHz, -1 dBFS, 0.33 < Fso/Fsi < 1.7 10 kHz, -1 dBFS, 0.33 < Fso/Fsi < 3 THD+N -117 -112 -110 -107 dB dB dB dB Peak idle channel noise component - - -140 dBFS Resolution 16 - 24 bits Gain Error -0.12 - 0 dB Parameter* Symbol Min Typ Max Units Passband Upsampling Downsampling 0.4535*Fsi 0.4535*Fso Hz Hz Passband Ripple - - ±0.007 dB Stopband (Downsampling) 0.5465*Fso - Fsi/2 Hz Stopband Attenuation 110 - - dB Group Delay (Note 2) t gd - - 1.75 ms Group Delay Variation vs. Frequency Δtgd -- 0 . 0 μs Interchannel Phase Deviation - - 0.0 ° Parameters Symbol Min Typ Max Units Power Down Mode (Note 3) Supply Current in power down VA+ VD+ μA μA Normal Operation (Note 4) Supply Current at 48 kHz Fso and Fsi VA+ VD+ 3.7 mA mA Supply Current at 96 kHz Fso and Fsi VA+ VD+ 7.0 125 mA mA

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DIGITAL INPUT CHARACTERISTICS DIGITAL INTERFACE SPECIFICATIONS AGND = DGND = 0 V; all voltages with respect to 0 V. TRANSMITTER CHARACTERISTICS SWITCHING CHARACTERISTICS Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF. 5. Cycle-to-cycle jitter using 32-96 kHz external PLL components. 6. PLL is bypassed (RXD1:0 bits in the Clock Source Cont rol register set to 10b), clock is input to the RMCK pin. Parameters Symbol Min Typ Max Units Input Leakage Current I in -± 1 0 ± 1 5 μA Differential Input Voltage, RXP to RXN V TH 200 - - mVpp Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN V OH (VD+) - 1.0 - V Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN V OL -0 . 4 V High-Level Output Voltage (IOH = -21 mA), TXP, TXN (VD+) - 0.7 - V Low-Level Output Voltage (IOH = 21 mA), TXP, TXN - 0.7 V High-Level Input Voltage, except RXP, RXN V IH 2.0 (VD+) + 0.3 V Low-Level Input Voltage, except RXP, RXN V IL -0.3 0.8 V Parameters Symbol Typ Units TXP Output Resistance R TXP 25 Ω TXN Output Resistance R TXN 25 Ω Parameter Symbol Min Typ Max Units RST pin Low Pulse Width 200 - - μs OMCK Frequency for OMCK = 512 * Fso 4.096 - 55.3 MHz OMCK Low and High Width for OMCK = 512 * Fso 8.2 - - ns OMCK Frequency for OMCK = 384 * Fso 3.072 - 41.5 MHz OMCK Low and High Width for OMCK = 384 * Fso 12.3 - - ns OMCK Frequency for OMCK = 256 * Fso 2.048 - 27.7 MHz OMCK Low and High Width for OMCK = 256 * Fso 16.4 - - ns PLL Clock Recovery Sample Rate Range 8.0 - 108.0 kHz RMCK output jitter (Note 5) -2 0 0- p s R M S RMCK output duty cycle 40 50 60 % RMCK Input Frequency (Note 6) 2.048 - 27.7 MHz RMCK Input Low and High Width (Note 6) 16.4 - - ns AES3 Transmitter Output Jitter - - 1 ns

Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.

1. The active edges of ISCLK and OSCLK are programmable.
2. When OSCLK, OLRCK, ISCLK, and IL RCK are derived from OMCK they are clocked from its rising edge.

When these signals are derived from RMCK, they are clocked from its falling edge.

1. The polarity of ILRCK and OLRCK is programmable.
2. No more than 128 SCLK per frame.
3. This delay is to prevent the previous I/OSCLK edge from being interpreted as the first one after I/OLRCK
4. This setup time ensures that this I/OSCLK edge is interpreted as the first one after I/OLRCK has changed.

Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing

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Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.

1. If Fso or Fsi is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fso and

should be safe for all possible conditions.

1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 3. SPI Mode Timing

Inputs: Logic 0 = 0 V, Logic 1 = VD+; CL = 20 pF.

1. Data must be held for suffi cient time to bridge the 25 ns transition time of SCL.

Figure 4. I²C Mode Timing

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1. TYPICAL CONNECTION DIAGRAM

Figure 5. Recommended Connection Diagram for Software Mode

1. GENERAL DESCRIPTION The CS8420 is a fully asynchronous sample rate converter plus AES3 transceiver intended to be used in digital au- dio systems. Such systems include digital mixing consoles, effects processors, tape recorders, and computer mul- timedia systems. The CS8420 is intended for 16-, 20-, an d 24-bit applications where the input sample rate is unknown, or is known to be asynchronous to the system sample rate. On the input side of the CS8420, AES3 or 3-wire serial format can be chosen. The output side produces both AES3 and 3-wire serial format. An I²C/SPI-compatible microcontroller interface allows full block processing of channel sta- tus and user data via block reads from the incoming AES3 data stream and block writes to the outgoing AES3 data stream. The user can also access information decoded fr om the input AES3 data stream, such as the presence of non-audio data and pre-emphasis, as well as control the va rious modes of the device. For users who prefer not to use a micro-controller, six hardware modes have been provided and documented towards the end of this data sheet. In these modes, flexibility is limited, with pins providing some programmability. When used for AES3-input/AES3-output applications, the CS8420 can automatically transceive user data that con- forms to the IEC60958-recommended format. The CS8420 also allows access to the relevant bits in the AES3 data stream to comply with the serial copy management system (SCMS). The diagram on the cover of this data sheet s hows the main functional blocks of the CS8420. Figure 5 shows the supply and external connections to the device. Familiarity with the AES3 and IEC60958 specifications are assumed throughout this document. Application Note 22: Overview of Digital Audio Interface Data Structures, contains a tutorial on digital audio specifications. The paper An Understanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission, by Clif Sanchez, is an excellent tutorial on SCMS. It may be obtained from Cirrus Logic, Inc., or from the AES. To guarantee system compliance, the proper standards documents should be obtained. The latest AES3 standard should be obtained from the Audio Engineering Society (ANSI), the latest IEC60958 standard from the International Electrotechnical Commission and the latest EIAJ CP-1201 standard from the Japanese Electronics Bureau.

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1. DATA I/O FLOW AND CLOCKING OPTIONS

Figure 6. Software Mode Audio Data Flow Switching Options

01 CHANNEL

Figure 7. CS8420 Clock Routing routed back through the RXD1 multiplexer; RMCK is not bi-directional in this mode.

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Figure 8. Serial Audio Input, using PLL, SRC Enabled Figure 9. Serial Audio Input, No PLL, SRC Enabled Figure 10. AES3 Input, SRC Enabled Figure 11. Serial Audio Input, AES3 Input Clock Source, Figure 12. Serial Audio Input, SRC Output Clocked by Figure 13. AES3 Input, SRC to Serial Audio Output, Serial

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1. SAMPLE RATE CONVERTER (SRC) Multirate digital signal processing techniques are used to conceptually upsample the incoming data to very high rate and then downsample to the outgoing rate, resulting in a 24-bit output, regardless of the width of the input. The fil- tering is designed so that a full input audio bandwidth of 20 kHz is preserved if the input sample and output sample rates are greater than 44.1 kHz. When the output sample rate becomes less than the input sample rate, the input is automatically band limited to avoid aliasing products in the output. Careful design ensures minimum ripple and dis- tortion products are added to the incoming signal. The SRC also determines the ratio between the incoming and outgoing sample rates, and sets the filter corner frequencies appropriately. Any jitter in the incoming signal has little impact on the dynamic performance of the rate converter and has no influence on the output clock.

5.1 Dither

When using the AES3 input, and when using the serial audio input port in Left-Justified and I²S modes, all input data is treated as 24 bits wide. Any truncation that has been done prior to the CS8420 to less than 24 bits should have been done using an appropriate dither process. If the serial audio input port is used to feed the SRC, and the port is in Right-Justified mode, then the input data will be truncated to the SIRES bit setting value. If SIRES bits are set to 16 or 20 bits, and the input data is 24 bits wide, truncation distortion will occur. Similarly, in any serial audio input port mode, if an inadequate number of bit clocks are entered (say 16 in- stead of 20), the input words will be truncated, causing truncation distortion at low levels. In summary, there is no dithering mechanism on the input side of the CS8420, and care must be taken to ensure that no trun- cation occurs. Dithering is used internally where appropriate inside the SRC block. The output side of the SRC can be set to 16, 20, or 24 bits. Optional dithering can be applied, and is auto- matically scaled to the selected output word length. This dither is not correlated between left and right chan- nels. It is recommended that the dither control bit be left in its default ON state.

5.2 SRC Locking, Varispeed and th e Sample Rate Ratio Register

The SRC calculates the ratio between the input sample rate and the output sample rate and uses this infor- mation to set up various parameters inside the SRC block. The SRC takes some time to make this calcula- tion. For a worst case 3:1 to 1:3 in put sample rate transition, the SRC will take 9400/Fso to settle (195 ms at Fso of 48 kHz). For a po wer-up situation, the S RC will start from 1:1; the worst case time becomes 8300/Fso (172 ms at Fso of 48 kHz). If the PLL is in use (either AES3 or serial input port), the worst case locking time for the PLL and the SRC is the sum of each locking time. If Fsi is changing, for example in a varispeed application, the REUNLOCK interrupt will occur, and the SRC will track the incoming sample rate. During this tracking mode, the SRC will still rate convert the audio data, but at increased distortion levels. Once the incoming sample rate is stable, th e REUNLOCK interrupt will become false, and the SRC will return to normal levels of audio quality. The VFIFO interrupt occurs if the data buffer in the SRC overflows, which can occur if the input sample rate changes at >10%/second. Varispeed at Fsi slew rates approaching 10%/sec is on ly supported when the input is via the serial audio input port. When using the AES3 input, high frame rate slew rates will cause the PLL to lose lock. The sample rate ratio is also made available as a register, accessible via the control port. The upper 2 bits of this register form the integer part of the ratio, while the lower 6 bits form the fractional part. Since, in many instances Fso is known, this allows the calculation of the incoming sample rate by the host microcontroller.

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Figure 17. Serial Audio Input Example Formats

Figure 18. Serial Audio Output Example Formats

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1. AES3 TRANSMITTER AND RECEIVER The CS8420 includes an AES3-type digi tal audio receiver and an AES3-type di gital audio transmitter. A compre- hensive buffering scheme provides read/write access to the channel status and user data. This buffering scheme is described in “Channel Status and User Data Buffer Management” on page 81.

7.1 AES3 Receiver

The AES3 receiver accepts and decodes audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. The receiver consists of a differential input stage, accessed via pins RXP and RXN, a PLL based clock recovery circuit, and a decoder which separates the audio data from the channel status and user data. External components are used to terminate and isolate the incoming data cables from the CS8420. These components are detailed in “External AES3/SPDIF/IEC60958 Transmitter and Rece iver Components” on page 78.

7.1.1 PLL, Jitter Attenuation, and Varispeed

Please see “PLL Filter” on page 87 for general description of the PLL, selection of recommended PLL filter components, and layout considerations. Figure 5 shows the recommended configuration of the two ca- pacitors and one resistor that comprise the PLL filter.

7.1.2 OMCK Out On RMCK

A special mode is available that allows the clock that is being input through the OMCK pin to be output through the RMCK pin. This feature is controlled by the SWCLK bit in register 4 of the control registers. When the PLL loses lock, the frequency of the VCO drops to 300 kHz. The SWCLK function allows the clock from RMCK to be used as a clock in the system without any disruption when input is removed from the Receiver.

7.1.3 Error Reporting and Hold Function

While decoding the incoming AES3 data stream, the CS8420 can identify several kinds of error, indicated in the Receiver Error register. The UNLOCK bit indicates whether the PLL is locked to the incoming AES3 data. The V bit reflects the current validity bit status. The CONF (confidence) bit indicates the amplitude of the eye pattern opening, indicating a link that is close to generating errors. The BIP (bi-phase) error bit indicates an error in incoming bi-phase coding. The PAR (parity) bit indicates a received parity error. The error bits are “sticky” - they are set on the first occurrence of the associated error and will remain set until the user reads the register via the control port. This enables the register to log all unmasked errors that occurred since the last time the register was read. The Receiver Error Mask register allo ws masking of individual errors. The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is con- sidered unmasked, meaning th at its occurrence will be reported in the receiver error register, will affect the RERR pin, will invoke the occurrence of a RERR interrupt, and will affect the current audio sample according to the status of the HOLD bits. The HOLD bits allow a choice of holding the previous sample, replacing the current sample with zero (mute), or do not change the current audio sample. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not be reported in the receiver error register, will not induce a pulse on RERR or generate a RERR interrupt, and will not affect the current audio sample. The QCRC and CCRC errors do not affect the current audio sample, even if unmasked.

7.1.4 Channel Status Data Handling

status decodes are from the A channel (CHS = 0) or B channel (CHS = 1). Non-Audio Auto Detection section below. If 50/15 µs pre-emphasis is detected, then this is reflected in the state of the EMPH pin. The encoded sample word length channel status bits are decoded according to AES3-1992 or IEC 60958. by the word length settings; all 24 bits are passed on as received.

7.1.5 User Data Handling

scribes the overall handling of CS and U data. the data flow and clocking options selected, there may not be a clock available to qualify the U data output. Figure 19 illustrates the timing. Q-channel block, which may be read via the control port. RCBL and C output are only available in hardware mode 5. RCBL goes high 2 frames after receipt of a Z pre-amble, and is high for 16 frames. VLRCK is a virtual word clock, which may not exist, but is used to illustrate the CU timing. VLRCK duty cycle is 50%. VLRCK frequency is always equal to the incoming frame rate. If no SRC is used, and the serial audio output port is in master mode, VLRCK = OLRCK. If the serial audio output port is in slave mode, then VLRCK needs to be externally created, if required. Figure 19. AES3 Receiver Timing for C & U Pin Output Data

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7.1.6 Non-Audio Au to Detection

Since it is possible to convey non-audio data in an AES3 data stream, it is important to know whether the incoming AES3 data stream is digital audio or other data. This information is typically conveyed in channel status bit 1 (AUDIO), which is extracted automatically by the CS8420. However, certain non-audio sourc- es, such as AC-3® or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8420 AES3 re ceiver can detect such no n-audio data. This is acco mplished by looking for a 96-bit sync code, consisting of 0x0000, 0x0000, 0x0000, 0x0000, 0xF872, and 0x4E1F. When the sync code is detected, an internal AUTODETECT signal will be as serted. If no additional sync codes are de- tected within the next 4096 frames, AUTODETECT will be de-asserted until another sync code is detect- ed. The AUDIO bit in the Receiver Channel Status register is the logica l OR of AUTODETECT and the received channel status bit 1. If non-audio data is detected, the data is still processed exactly as if it were normal audio. It is up to the user to mute the outputs as required.

7.2 AES3 Transmitter

The AES3 transmitter encode s and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase mark-encoded. The resulting bit stream is t hen driven directly, or through a transformer, to an output connector. The transmitter is usually clocked from the output side clock domain of the sample rate converter. This clock may be derived from the clock input pin OMCK, or from the incoming data. In data flows with no SRC, and where OMCK is asynchronous to the data source, an interrupt bit is provided that will go high every time a data sample is dropped or repeated. The channel status (C) and user channel (U) bits in the transmitted data stream are taken from storage areas within the CS8420. The user can manipulate t he contents of the internal storage with a microcon- troller. The CS8420 will also run in one of several automatic modes. “Channel Status and User Data Buffer Management” on page 81 provides detailed descriptions of each automatic mode, and describes methods for accessing the storage areas. The transmitted user data can optionally be input via the U pin, under the control of a control port register bit. Figure 20 shows the timing requirements for inputting U data via the U pin.

7.2.1 Transmitted Frame and Ch annel Status Boundary Timing

The TCBL pin may be an input or an output, and is used to control or indicate the start of transmitted chan- nel status block boundaries. In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame boundaries. This may be achieved in 3 ways: 1) With TCBL configured as an input, and TCBL transitions high for >3 OMCK clocks, it will cause a frame start, and a new channel status block start. 2) If the AES3 output comes from the AES3 input, while there is no SRC, setting TCBL as output will cause AES3 output frame boundaries to align with AES3 input frame boundaries. 3) If the AES3 output comes from the serial audio input port while the port is in Slave mode, and TCBL is set to output, then the start of the A channel sub-frame will be aligned with the leading edge of ILRCK.

7.2.2 TXN and TXP Drivers

The line drivers are low-skew, low-impedance, differential outputs capable of driving cables directly. Both drivers are set to ground during reset (RST = low), when no AES3 transmit clock is provided, and option- ally under the control of a regist er bit. The CS8420 also allows imme diate mute of the AES3 transmitter audio data via a control register bit. External components are used to terminate and isolate the external cable from the CS8420. These com- ponents are detailed in “External AES3/SPDIF/IEC60958 Transmitter and Receiver Components” on page 78.

7.3 Mono Mode Operation

Currently, the AES3 st andard is being upda ted to include options for 96-k Hz sample rate operation. One method is to double the frame rate of the current format. This results in a 96-kHz sample rate, stereo signal carried over a single twisted pair cable. An alternate method is where the 2 sub-frames in a 48-kHz frame rate AES3 signal are used to carry consecutive samples of a mono signal, resulting in a 96-kHz sample rate stream. This allows older equipmen t, whose AES3 tran smitters and re- ceivers are not rated for 96-kHz frame rate operation, to handle 96-kHz sample rate information. In this “mono mode”, 2 AES3 cables are needed for stereo data transfer. Th e CS8420 offers mono mode opera- tion, both for the AES3 receiver and for the AES3 transmitter. Figure 21 shows the operation of mono mode in comparison with normal stereo mode. The receiver and transmitter sections may be independently set to mono mode via the MMR and MMT control bits. The receiver mono mode effectively doubles Fsi compared to the input frame rate. The clock output on the RMCK pin tracks Fsi, and so is doubled in frequency compared to stereo mode. In mono mode, A and B sub-frames are routed to the SRC inputs as consecutive samples. When the transmitter is in mono mo de, either A or B SRC consecutive outputs are routed alternately to A and B sub-frames in the AES3 output stream. Which channel status block is transmitted is also selectable. For the AES3 input to serial audio po rt output data flow, in receiver mono mode, then the receiver will run at a frame rate of Fsi/2, and the serial audio output port will run at Fsi. Identical data will appear in both left and right data fields on the SDOUT pin. For the serial audio input port to AES3 transmitter data flow, in transmitter mono mode, then the input port will run at Fso audio sample rate, while the AES3 transmitter frame rate will be at Fso/2. The data from either consecutive left, or right, positions will be selected for transmitting in A and B sub-frames.

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Figure 20. AES3 Transmitter Timing for C, U and V Pin Input Data In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate. VLRCK is a virtual word clock, which may not exist, and is used to illustrate CUV timing. VLRCK= ILRCK if SILRPOL = 1. VLRCK= ILRCK if SILRPOL = 1.

Figure 21. Mono Mode Operation Compared to Normal Stereo Operation

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1. AES3 TRANSMITTER AND RECEIVER

8.1 Sample Rate Converter

variation in signal delay through the parts is ±1.5 μs. the AES transmitter on all of the parts. Table 1. Minimizing Group Delay Through Multiple CS8420s When Locking to RXP/RXN Table 2. Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK

8.2 Non-SRC Delay

1. All inputs are slaves and all outputs are ma sters, both with respect to the outside world.
2. The inputs and outputs are synchronous to one another.

Table 3. Non-SRC Delay

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1. CONTROL PORT DESC RIPTION AND TIMING

avoid potential interference problems, the control port pins should remain static if no operation is required. by connecting the AD0/CS pin to VD+ or DGND, thereby permanently selecting the desired AD0 bit address state.

9.1 SPI Mode

to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. high or low with a 47 kΩ resistor, if desired. increment after each byte is read or written, allowing block reads or writes of successive registers. as desired. To begin a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. Figure 22. Control Port Timing in SPI Mode

9.2 I²C Mode

troller after each transmitted byte.

9.3 Interrupts

erals connected to the microcontroller interrupt input pin. many different set-ups are possible, depending on the needs of the equipment designer.

0010 AD2-0 R/W

Figure 23. Control Port Timing in I²C Mode

1. AD2 is derived from a resistor attached to the EMPH pin

AD1, and AD0 are determined by the state of the corresponding pins.

1. If operation is a write, this byte co ntains the Memory Address Pointer, MAP.
2. If operation is a read, the last bi t of the read should be NACK (high).

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1. CONTROL PORT REGISTER BIT DEFINITIONS

10.1 Memory Address Pointer (MAP)

This register defaults to 01 INCR Auto-Increment Address Control Bit 0 - Auto-increment address off 1 - Auto-increment address on MAP6-MAP0 Register address and function list 0 - Reserved 1 - Misc. Control 1 2 - Misc. Control 2 3 - Data Flow Control 4 - Clock Source Control 5 - Serial Audio Input Port Data Format 6 - Serial Audio Output Port Data Format 7 - Interrupt Register 1 Status 8 - Interrupt Register 2 Status 9 - Interrupt Register 1 Mask 10 - Interrupt Register1 Mode (MSB) 11 - Interrupt Register 1 Mode (LSB) 12 - Interrupt Register 2 Mask 13 - Interrupt Register 2 Mode (MSB) 14 - Interrupt Register 2 Mode (LSB) 15 - Receiver Channel Status Bits 16 - Receiver Error Status 17 - Receiver Error Mask 18 - Channel Status Da ta Buffer Control 19 - User Data Buffer Control 20 to 29 - Q-channel Subcode Bytes 0 to 9 30 - Sample Rate Ratio 31 - Reserved 32 to 55 - C-bit or U-bit Data Buffer 56 to 126 - Reserved 127 - Chip ID and version register Reserved registers must not be written to during no rmal operation. Some reserved registers are used for test modes, which can completely alter the normal operation of the CS8420. 7 6 543210 INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0

01 Control 1 SWCLK VSET MUTESAO MUTEAES DITH INT1 INT0 TCBLD

02 Control 2 TRUNC HOLD1 HOLD0 RMCKF MMR MMT MMTCS MMTLR

03 Data Flow Control AMLL TXOFF AESBP TXD1 TXD0 SPD1 SPD0 SRCD

04 Clock Source Control 0 RUN CLK1 CLK0 OUTC INC RXD1 RXD0

05 Serial Input Format SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

06 Serial Output Format SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL

07 Interrupt 1 Status TSLIP OSLIP SRE OVRGL OVRGR DETC EFTC RERR

08 Interrupt 2 Status 0 0 VFIFO REUNLOCK DETU EFTU QCH UOVW

09 Interrupt 1 Mask TSLIPM OSLIPM SREM OVRGLM OVRGRM DETCM EFTCM RERRM

10 Receiver Errors 0 QCRC CCRC UNLOCK V CONF BIP PAR

11 Receiver Error Mask 0 QCRCM CCRCM UNLOCKM VM CONFM BIPM PARM

12 CS Data Buffer Control 0 0 BSEL CBMR DETCI EFTCI CAM CHS

13 U Data Buffer Control 0 0 0 UD UBM1 UBM0 DETUI EFTUI

Table 4. Summary of all Bits in the Control Register Map

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10.2 Miscellaneous Control 1 (01h)

SWCLK Causes OMCK to be output through the RMCK pin when the PLL is unlocked 0 - RMCK is driven by the PLL VCO (default) 1 - OMCK is switched to output through the RMCK pin when the PLL is unlocked. Circuitry driv- en by the PLL is driven by OMCK. VSET Transmitted V bit level 0 - Transmit a 0 for the V bit, indicating that the data is valid, and is normally linear PCM audio (default) 1 - Transmit a 1 for the V bit, indicating that the data is invalid or is not linear PCM audio data MUTESAO Mute control for the serial audio output port 0 - Normal output (default) 1 - Mute the serial audio output port MUTEAES Mute control for th e AES3 transmitter output 0 - Normal output (default) 1 - Mute the AES3 transmitter output DITH Dither Control 0 - Triangular PDF dither applied to output data. The level of the dither is automatically adjusted to be appropriate for the output word length selected by the SORES bits (default) 1 - No dither applied to output data. INT[1:0] Interrupt (INT) output pin control 00 - Active high, high output indicates an interrupt condition has occurred (default) 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. This setting requires an external pull up resistor on the INT pin. 11 - Reserved TCBLD Transmit Channel Status Bloc k pin (TCBL) direction specifier 0 - TCBL is an input (default) 1 - TCBL is an output 7 6 543210 SWCLK VSET MUTESAO MUTEAES DITH INT1 INT0 TCBLD

10.3 Miscellaneous Control 2 (02h)

TRUNC Determines whether the word length is set according to the incoming Channel Status data 0 - Data to the SRC is not truncated (default) 1 - Data to the SRC is set according to the AUX field in the incoming data stream HOLD[1:0] The HOLD bits determine how the receiv ed audio sample is affected when a receiver error occurs. 00 - Hold the last valid audio sample (default) 01 - Replace the current audio sample with 00 (mute) 10 - Do not change the received audio sample 11 - Reserved RMCKF Select recovered master clock output pin frequency. 0 - RMCK is equal to 256 * Fsi (default) 1 - RMCK is equal to 128 * Fsi MMR Select AES3 receiver mo no or stereo operation 0 - Interpret A and B subframes as two independent channels (normal stereo operation, default) 1 - Interpret A and B subframes as consecutive samples of one channel of data.This data is duplicated to both left and right parallel outputs of the AES receiver block. The input sample rate (Fsi) is doubled compared to MMR=0 MMT Select AES3 transmitter mono or stereo operation 0 - Outputs left channel input into A subframe and right channel input into B subframe (normal stereo operation, default). 1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit) MMTCS Select A or B channel status data to transmit in mono mode 0 - Use channel A CS data for the A sub-frame slot and use channel B CS data for the B sub- frame slot (default) 1 - Use the same CS data for both the A and B sub-frame output slots. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data. MMTLR Channel Selection fo r AES Transmitter mono mode 0 - Use left channel input data for consecutive sub-frame outputs (default) 1 - Use right channel input data for consecutive sub-frame outputs 7 6 543210 TRUNC HOLD1 HOLD0 RMCKF MMR MMT MMTCS MMTLR

36 DS245F4

10.4 Data Flow Control (03h)

The Data Flow Control register configures the flow of audio data to/from the following blocks: Serial Audio Input Port, Serial Audio Output Port, AES3 receiver, AES3 transmitter, and Sample Rate Converter. In conjunction with the Clock Source Control register, multiple Receiver/Trans- mitter/Transceiver modes may be selected. The output data should be muted prior to changing bits in this register to avoid transients. AMLL Auto Mutes the SRC data sink when Receiver lock is lost, zero data is transmitted. The SRC data sink may be either, or both, the Transmitter and the Serial Audio Output Port. 0 - Disables Auto Mute on loss of lock (default) 1 - Enables Auto Mute on loss of lock TXOFF AES3 Transmitter Output Driver Control 0 - AES3 transmitter output pin drivers normal operation (default) 1 - AES3 transmitter output pin drivers drive to 0 V. AESBP AES3 bypass mode selection 0 - normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which become a normal TTL threshold digital input. TXD[1:0] AES3 Transmitter Data Source 00 - SRC output (default) 01 - Serial audio input port 10 - AES3 receiver 11 - Reserved SPD[1:0] Serial Audio Outp ut Port Data Source 00 - SRC output (default) 01 - Serial Audio Input Port 10 - AES3 receiver 11 - Reserved SRCD Input Data Source for SRC 0 - Serial Audio Input Port (default) 1 - AES3 Receiver 7 6 543210 AMLL TXOFF AESBP TXD1 TXD0 SPD1 SPD0 SRCD

10.5 Clock Source Control (04h)

This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, various Receiver/Transmitter/Transceiver modes may be selected. RUN The RUN bit controls the internal clocks, allowing the CS8420 to be placed in a “powered down”, low current consumption, state. 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port is operational, allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Power consumption is low (default). 1 - Normal part operation. This bit must be written to the 1 state to allow the CS8420 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. CLK[1:0] Output side master clock in put (OMCK) frequency to output sample rate (Fso) ratio selector. If these bits are changed during normal operation, then always stop the CS8420 first (RUN = 0), then write the new value, then start the CS8420 (RUN = 1). 00 - OMCK frequency is 256*Fso(default) 01 - OMCK frequency is 384*Fso 10 - OMCK frequency is 512*Fso 11 - reserved OUTC Output Time Base 0 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0, (default) 1 - Recovered Input Clock INC Input Time Base Clock Source 0 - Recovered Input Clock (default) 1 - OMCK input pin (modified by the selected divide ratio bits CLK1 & CLK0) RXD[1:0] Recovered Input Clock Source 00 - 256*Fsi, where Fsi is derived from the ILRCK pin (only possible when the serial audio input port is in Slave mode, default) 01 - 256*Fsi, where Fsi is derived from the AES3 input frame rate 10 - Bypass the PLL and apply an external 256*Fsi clock via the RMCK pin. The AES3 receiver is held in synchronous reset. This setting is useful to prevent UNLOCK interrupts when using an external RMCK and inputting data via the serial audio input port. 11 - Reserved 7 6 543210

0 RUN CLK1 CLK0 OUTC INC RXD1 RXD0

38 DS245F4

10.6 Serial Audio Input Po rt Data Format (05h)

SIMS Master/Slave Mode Selector 0 - Serial audio input port is in Slave mode (default) 1 - Serial audio input port is in Master mode SISF ISCLK frequency (for Master mode) 0 - 64*Fsi (default) 1 - 128*Fsi SIRES[1:0] Resolution of the input data, for right-justified formats 00 - 24 bit resolution (default) 01 - 20 bit resolution 10 - 16 bit resolution 11 - Reserved SIJUST Justification of SDIN data relative to ILRCK 0 - Left-Justified (default) 1 - Right-Justified SIDEL Delay of SDIN data relative to ILRCK, for left-justified data formats 0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (default) 1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge SISPOL ISCLK clock polarity 0 - SDIN sampled on rising edges of ISCLK (default) 1 - SDIN sampled on falling edges of ISCLK SILRPOL ILRCK clock polarity 0 - SDIN data is for the left channel when ILRCK is high (default) 1 - SDIN data is for the right channel when ILRCK is high 7 6 543210 SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

10.7 Serial Audio Output Po rt Data Format (06h)

SOMS Master/Slave Mode Selector 0 - Serial audio output port is in Slave mode (default) 1 - Serial audio output port is in Master mode SOSF OSCLK frequency (for Master mode) 0 - 64*Fso (default) 1 - 128*Fso SORES[1:0] Resolution of th e output data on SDOUT and AES3 output when the sample rate converter is set as the source 00 - 24 bit resolution (default) 01 - 20 bit resolution 10 - 16 bit resolution 11 - Direct copy of the received NRZ data from the AES3 receiver (including C, U, and V bits, the time slot normally occupied by the P bit is used to indicate the location of the block start, SDOUT pin only, serial audio output port clock must be derived from the AES3 receiver recovered clock) SOJUST Justification of SDOU T data relative to OLRCK 0 - Left-Justified (default) 1 - Right-Justified (Master mode only) SODEL Delay of SDOUT data relative to OLRCK, for left-justified data formats 0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge (default) 1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge SOSPOL OSCLK clock polarity 0 - SDOUT transitions occur on falling edges of OSCLK (default) 1 - SDOUT transitions occur on rising edges of OSCLK SOLRPOL OLRCK clock polarity 0 - SDOUT data is for the left channel when OLRCK is high (default) 1 - SDOUT data is for the right channel when OLRCK is high 7 6 543210 SOMS SOSF SORES1 SORES0 SO JUST SODEL SOSPOL SOLRPOL

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10.8 Interrupt 1 Register Status (07h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00. TSLIP AES3 transmitter source data slip interrupt. In data flows with no SRC, and where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. Also, when TCBL is an input, and when the SRC is not in use, this bit will go high on receipt of a new TCBL signal. OSLIP Serial audio output port data s lip interrupt. When the serial audio output port is in Slave mode, and OLRCK is asynchronous to the port data source, this bit will go high every time a data sam- ple is dropped or repeated. Also, when the SRC is used, and the SRC output goes to the output serial port configured in Slave mode, this bit will indicate if the ratio of OMCK frequency to OL- RCK frequency does not match what is set in the CLK1 and CLK0 bits. SRE Sample rate range exceeded indicator. Occurs if Fsi/Fso or Fso/Fsi exceeds 3. OVRGL Over-range indicator for left (A) channel SRC output. Occurs on internal over-range for left channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale. OVRGR Over-range indicator for right (B) channel SR C output. Occurs on internal over-range for right channel data. Note that the CS8420 automatically clips over-ranges to plus or minus full scale DETC D to E C-buffer transfer interrupt. The source for this bit is true during the D to E buffer transfer in the C bit buffer management process. EFTC E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in the C bit buffer management process. RERR A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt. 7 6 543210 TSLIP OSLIP SRE OVRGL OVRGR DETC EFTC RERR

10.9 Interrupt Register 2 Status (08h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00. VFIFO Varispeed FIFO overflow indica tor. Occurs if the data buffer in the SRC overflows. This will oc- cur if the input sample rate slows too fast. REUNLOCK Sample rate converter unlock indicator. This interrupt occurs if the SRC is still tracking a chang- ing input or output sample rate. DETU D to E U-buffer transfer interrupt. The source of this bit is true during the D to E buffer transfer in the U bit buffer management process (block mode only). EFTU E to F U-buffer transfer interrupt. The source of this bit is true during the E to F buffer transfer in the U bit buffer management process (block mode only). QCH A new block of Q-subcode data is available fo r reading. The data must be completely read with- in 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block. UOVW U-bit FIFO Overwrite. Th is interrupt occurs on an overwrite in the U-bit FIFO.

10.10 Interrupt 1 Re gister Mask (09h)

The bits of this register serve as a mask for the Interrupt 1 Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions ali gn with the corresponding bits in Inte rrupt Register 1. This register de- faults to 00.

10.11 Interrupt Register 1 Mode Registers MSB & LSB (0Ah,0Bh)

The two Interrupt Mode registers form a 2-bit code for ea ch Interrupt Register 1 function. This code deter- mines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or on the continuing occurrence of the interrupt condition. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved 7 6 543210 0 0 VFIFO REUNLOCK DETU EFTU QCH UOVW 7 6 543210 TSLIPM OSLIPM SREM OVRGLM OVRGRM DETCM EFTCM RERRM 7 6 543210 TSLIP1 OSLIP1 SRE1 OVRGL1 OVRGR1 DETC1 EFTC1 RERR1 TSLIP0 OSLIP0 SRE0 OVRGL0 OVRGR0 DETC0 EFTC0 RERR0

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10.12 Interrupt 2 Register Mask (0Ch)

The bits of this register serve as a mask for the Interrupt 2 Register. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions alig n with the corresponding bits in Inte rrupt Register 2. This register de- faults to 00.

10.13 Interrupt Register 2 Mode Registers MSB & LSB (0Dh,0Eh)

The two Interrupt mode registers form a 2-bit code for each Interrupt 2 register function. This code deter- mines whether the INT pin is set active on the arrival of the interrupt condition, on the removal of the interrupt condition, or on the continuing occurrence of the interrupt condition. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved 76543210 0 0 VFIFOM REUNLOCKM DETUM EFTUM QCHM UOVWM 76543210 0 0 VFIFO1 REUNLOCK1 DE TU1 EFTU1 QCH1 UOVW1 0 0 VFIFO0 REUNLOCK0 DE TU0 EFTU0 QCH0 UOVW0

10.14 Receiver Channel Stat us (0Fh) (Read Only)

The bits in this register can be associated with either channel A or B of the received data. The desired channel is selected with the CHS bit of the Channel Status Data Buffer Control Regis- ter. AUX[3:0] The AUX3-0 bits indicate th e width of the incoming auxiliary data field, as indicated by the in- coming channel status bits, decoded according to IEC60958 and AES3. 0000 - Auxiliary data is not present 0001 - Auxiliary data is 1 bit long 0010 - Auxiliary data is 2 bits long 0011 - Auxiliary data is 3 bits long 0100 - Auxiliary data is 4 bits long 0101 - Auxiliary data is 5 bits long 0110 - Auxiliary data is 6 bits long 0111 - Auxiliary data is 7 bits long 1000 - Auxiliary data is 8 bits long 1001 - 1111 Reserved PRO Channel status block format indicator 0 - Received channel status block is in consumer format 1 - Received channel status block is in professional format AUDIO Audio indicator 0 - Received data is linearly coded PCM audio 1 - Received data is not linearly coded PCM audio COPY SCMS copyright indicator 0 - Copyright asserted 1 - Copyright not asserted ORIG SCMS generation indicator. This is decoded from the category code and the L bit. 0 - Received data is 1st generation or higher 1 - Received data is original Note: COPY and ORIG will both be set to 1 if the incoming data is flagged as professional or if the receiver is not in use. 76543210 AUX3 AUX2 AUX1 AUX0 PRO AUDIO COPY ORIG

44 DS245F4

10.15 Receiver Error (10h) (Read Only)

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. This register defaults to 00. QCRC Q-subcode data CRC error has occurred. Updated on Q-subcode block boundaries. 0 - No error 1 - Error CCRC Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries. This bit is valid in Professional mode only. 0 - No error 1 - Error UNLOCK PLL lock status bit. Updated on CS block boundaries. 0 - PLL locked 1 - PLL out of lock V Received AES3 Validity bit status. Updated on sub-frame boundaries. 0 - Data is valid and is normally linear coded PCM audio 1 - Data is invalid, or may be valid compressed audio CONF Confidence bit. Updated on sub-frame boundaries. 0 - No error 1 - Confidence error. This indicates that the received data eye opening is less than half a bit period, indicating a poor link that is not meeting specifications. BIP Bi-phase error bit. Updated on sub-frame boundaries. 0 - No error 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR Parity bit. Updated on sub-frame boundaries. 0 - No error 1 - Parity error 76543210

0 QCRC CCRC UNLOCK V CONF BIP PAR

10.16 Receiver Error Mask (11h)

The bits in this register serve as masks for the corresponding bits of the Receiver Error Regis- ter. If a mask bit is set to 1, the error is considered unmasked, meaning that its occurrence will appear in the receiver error register, will affect the RERR pin, will affect the RERR interrupt, and will affect the current audio sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is considered masked, meaning that its occurrence will not appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when unmasked. This register defaults to 00.

10.17 Channel Status Data Buffer Control (12h)

BSEL Selects the data buffer regist er addresses to contain User data or Channel Status data 0 - Data buffer address space contains Channel Status data (default) 1 - Data buffer address space contains User data CBMR Control for the first 5 byte s of channel status “E” buffer 0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data (default) 1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data DETCI D to E C-data buffer transfer inhibit bit. 0 - Allow C-data D to E buffer transfers (default) 1 - Inhibit C-data D to E buffer transfers EFTCI E to F C-data buffer transfer inhibit bit. 0 - Allow C-data E to F buffer transfers (default) 1 - Inhibit C-data E to F buffer transfers CAM C-data buffer control port access mode bit 0 - One byte mode 1 - Two byte mode CHS Channel select bit 0 - Channel A information is displayed at the EMPH pin and in the receiver channel status register. Channel A information is output during control port reads when CAM is set to 0 (One Byte Mode) 1 - Channel B information is displayed at the EMPH pin and in the receiver channel status register. Channel B information is output during control port reads when CAM is set to 0 (One Byte Mode) 76543210

0 QCRCM CCRCM UNLOCKM VM CONFM BIPM PARM

0 0 BSEL CBMR DETCI EFTCI CAM CHS

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10.18 User Data Buffer Control (13h)

UD User data pin (U) direction specifier 0 - The U pin is an input. The U data is latched in on both rising and falling edges of OLRCK. This setting also chooses the U pin as the source for transmitted U data (default). 1 - The U pin is an output. The received U data is clocked out on both rising and falling edges of ILRCK. This setting also chooses the U data buffer as the source of transmitted U data. UBM[1:0] Sets th e operating mode of the AES3 U bit manager 00 - Transmit all zeros mode (default) 01 - Block mode 10 - Reserved 11 - IEC consumer mode B DETUI D to E U-data buffer transfer inhibit bit (valid in block mode only). 0 - Allow U-data D to E buffer transfers (default) 1 - Inhibit U-data D to E buffer transfers EFTUI E to F U-data buffer transfer inhibit bit (valid in block mode only). 0 - Allow U-data E to F buffer transfers (default) 1 - Inhibit U-data E to F buffer transfer Q-Channel Subcode Bytes 0 to 9 (14h - 1Dh) (Read Only) The following 10 registers contain the decoded Q-channel subcode data Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus bit 7 of address 14h is Q[0] while bit 0 of address 14h is Q[7]. Similarly bit 0 of address 1Dh corresponds to Q[79]. 76543210 0 0 0 UD UBM1 UBM0 DETUI EFTUI 76543210 CONTROL CONTROL CONTROL CONTR OL ADDRESS ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK INDEX INDEX INDEX INDEX INDEX INDEX INDEX INDEX MINUTE MINUTE MINUTE MINUTE M INUTE MINUTE MINUTE MINUTE SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE AB S MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME

10.19 Sample Rate Ratio (1Eh) (Read Only)

The Sample Rate Ratio is Fso divided by Fsi. This value is represented as an integer and a fractional part. The value is meaningful only after the both the PLL and SRC have reached lock, and the SRC output is being used SRR[7:6 The integer part of the sample rate ratio SRR[5:0] The fractional part of the sample rate ratio

10.20 C-Bit or U- Bit Data Buffer (20h - 37h)

Either channel status data buffer E or user data buffer E (provided UBM bits are set to block mode) is ac- cessible via these register addresses. 10.21 CS8420 I.D. and Version Register (7Fh) (Read Only) ID[3:0] ID code for the CS8420. Permanently set to 0001 VER[3:0] CS8420 Revision Level: Revision B is coded as 0001 Revision C is coded as 0011 Revision D is coded as 0100 76543210 SRR7 SRR6 SRR5 SRR4 SRR3 SRR2 SRR1 SRR0

7654321 I D 3

ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0

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1. SYSTEM AND APPLICATIONS ISSUES

11.1 Reset, Power Down and Start-up Options

When RST is low, the CS8420 enters a low-power mode. All internal states are reset, including the control port and registers, and the outputs are muted. When RST is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writ ing a 1 to the RUN bit will then cause the part to leave the low-power state and begin operation. After the PLL and the SRC have settled, the AES3 and serial audio outputs will be enabled. Some options within the CS8420 are controlled by a st art-up mechanism. During the reset state, some of the output pins are reconfigured internally to be inpu ts. Immediately upon exiting the reset state, the level of these pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8420 by connecting a 47 kΩ resistor between the pin and either VD+ (High) or DGND (Low). For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor. In software mode, the only start-up option pin is EMPH , which is used to set a chip ad- dress bit for the control port in I²C mode. Hardware modes use many start-up options, which are detailed in the hardware definition section at the end of this data sheet.

11.2 Transmitter Startup

When the CS8420 is taken out of power-down and the AES3 receiver is configured to be in-circuit, the part uses the clock recovered from the AES3 input stream to advance its internal state machine to run. This can be a problem if no valid AES3 stream is present at the RXP/RXN pins and data input through the serial audio port needs to be output through the AES3 transmitter. To complete initialization and begin operation when the AES3 receiver is in-circuit and no valid AES3 input stream is presented to the RXP/RXN pins, the user must execute the following sequence: 1. Place the CS8420 in power-down (RUN = 0). 2. Set the serial audio input and output ports to Slave mode (SIMS = 0, SOMS = 0). 3. Set the input and output time base to the OMCK input pin (OUTC = 0, INC = 1). 4. Configure the SRC to receiv e its input from the serial audio input port (SRCD = 0). 5. Configure the serial audio output port to receive its input from the serial audio input port (SPD[1:0] = 01). 6. Configure the AES3 transm itter to receive its input from the serial audio input port (TXD[1:0] = 01). 7. Set the RUN bit (RUN = 1). After completing steps 1-7, the tran smitter will function properl y, and the data flow can be altered for the application without powering down.

11.3 SRC Invalid State

Occasionally the CS8420 SRC will enter an invalid state. This can happ en after the RUN bit has been set when an AES3 stream is first plugged into the part or when a source device interrupts the SRC input stream. When this happens, two symptoms may be noticeable: notches occurring in the frequency response and spurious tones being generated in response to some input frequencies. To avoid this problem in Software mode, use the microcontroller to monitor the UNLOCK bit in control reg- ister 10h. When the part achieves lock, clear the RUN bit in register 4 and then set it again. This will reset all internal state machines. Alternately, the user may use the following sequence: 1. Power on CS8420. 2. Write the following register sequence: 3. Wait for PLL to lock. 4. Wait 250ms for SRC to lock. 5. Write the following register sequence: 6. If PLL goes out of lock, start at step 2 and repeat. When synchronizing multiple CS8420s, wait for all PLLs to lock before continuing to the next step. These actions clear the invalid state if it has occurred. In Hardware mode, monitor the RERR pin for receiver lock status. When the part achieves lock, set the RST pin low for at least 200 μs and then set it high again. This action clears the invalid state if it has occurred. When polling the RERR pin again, the user must account for the fact that the RERR pin will be high during reset and remain high until the PLL has reachieved lock. In either Software or Hardware mode, when clearing the invalid state, it is ad visable to mute any devices connected to the output of the CS8420.

11.4 C/U Buffer Data Corruption

Occasionally the C/U buffer data may be corrupted. This can happen after the RUN bit has been set and data has been written to the C/U buffer (20h-37h). If no further data is written to the C buffer after the initial write and the receiver input is interrupted multiple times, the contents of the buffer may be reset to all zeros. The buffer will not be corrupted if the buffer data is being updated, only when the data is static and the re- ceiver input has been interrupted multiple times. To avoid this problem in Software mode when the C/U buffer contents should remain static, use the micro- controller to monitor the UNLOCK bit in control register 10h or the RERR pin. If the part indicates the PLL has lost lock, rewrite the C/U buffer data. Repeat this action every time the PLL goes out of lock. In Hardware mode, this limitation does not exist as the serial C/U data is being fed directly to the transmitter. Register Value 04h 09h 03h 95h 04h 49h Register Value 03h 81h 04h 41h

50 DS245F4

11.5 Block-Mode U-Data D- to-E Buffer Transfers

When Fsi ≠ Fso, Block-Mode U-data transfers from the D buffer to the E buffer are not synchronous to the input clock domain. D-to-E buffer transfers can always be detected by the activation of the DETU bit (bit 3 in register 08h) when Fsi ≠ Fso or Fsi = Fso. IEC Consumer B mode, serial U-data output, and the Q- channel subcode bytes (registers 14h - 1Dh) are unaffected by the input/output sample rate relationship.

11.6 ID Code and Revision Code

The CS8420 has a register that cont ains a 4-bit code to indicate that the addressed device is a CS8420. This is useful when other CS84xx family members are resident in the same system, allowing common soft- ware modules. The CS8420 4-bit revision code is also available. This allows the software driver for the CS8420 to identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcon- troller, and used wherever appropriate as revision details become known.

11.7 Power Supply, Gr ounding, and PCB layout

For most applications, the CS8420 can be operated from a single +5V supply, following normal supply de- coupling practice (see Figure 5. “Recommended Connection Diagram for Software Mode” on page 12). For applications where the recovered input clock, output on the RMCK pin, is required to be low-jitter, then use a separate, quiet, analog +5V supply for VA+, decoupled to AGND. In addition, a separate region of analog ground plane around the FILT, AGND, VA+, RXP and RXN pins is recommended. The VD+ supply should be well-decoupled with a 0.1 μF capacitor to DGND to minimize AES3 transmitter induced transients. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Make sure decoupling capacitors are mounted on the same side of the board as the CS8420, to minimize via inductance effects. All decoupling capacitors should be as close to the CS8420 as possible.

11.8 Synchronization of Multiple CS8420s

The serial audio output ports of multiple CS8420s can be synchronized by sharing the same master clock, OSCLK, OLRCK, and RST line and ensuring that all devices leave the reset state on the same master clock falling edge. Either all the ports need to be in Slave mode, or one can be set as a master. The AES3 transmitters may be synch ronized by sharing the same master clock, TCBL, and RST signals, and ensuring all devices leave the reset state on the same master clock falling edge. The TCBL pin is used to synchronize multiple CS8420 AES3 transmitters at the channel st atus block boundar ies. One CS8420 must have its TCBL set to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived from some external logic, in which case all the CS8420 devices should be set to slave TCBL.

11.9 Extended Range Sample Rate Conversion

For handling sampling rate conversion ratios greater than 3:1 or less than 1:3, the user can use a cascade of two devices. The product of the conversion ratio of the two devices should eq ual the target conversion ratio.

1. SOFTWARE MODE - PIN DESCRIPTION The above diagram and the following pi n descriptions apply to Software mode. In Hardware mode, some pins change their function as described in subsequent sections of this data sheet. Fixed function pins are marked with a *, and will be described once in this se ction. Pins marked with a + are used upon reset to select various start-up options, and require a pull-up or pull-down resistor. Power Supply Connections: VD+ - Positive Digital Power * Positive supply for the digital section. Nominally +5.0 V. VA+ - Positive Analog Power * Positive supply for the analog section. Nominally +5.0 V. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock. DGND - Digital Ground * Ground for the digital section. DGND should be connected to the same ground as AGND. AGND - Analog Ground * Ground for the analog section. AGND should be connected to the same ground as DGND. Clock-Related Pins: OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate (Fso). RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 128x or 256x the input sample rate (Fsi).

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FILT - PLL Loop Filter * An RC network should be connected between this pi n and ground. Recommended schematic and component val- ues are given in “PLL Filter” on page 87. Overall Device Control: H/S - Hardware or Software Control Mode Select * The H/S pin determines the method of controlling the operat ion of the CS84 20, and the method of accessing CS and U data. In Software mode, device control and CS and U data access is primarily via the control port, using a microcontroller. In Hardware mode, alternate modes and ac cess to CS and U data is provided by pins. This pin should be permanently tied to VD+ or DGND. RST - Reset Input * When RST is low, the CS8420 enters a low-power mode and all internal states are reset. On initial power-up, RST must be held low until the power supply is stable, and a ll input clocks are stable in frequency and phase. This is particularly true in Hardware mode with multiple CS8420 devices, where synchronization between devices is impor- tant. INT - Interrupt Output The INT output pin indicates errors and key events during the operation of the CS8420 . All bits affecting INT are maskable via control registers. The condition(s) that initiated interrupt are readable via a control register. The polarity of the INT output, as well as selection of a standard or open-drain output, is set via a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read, and the interrupt status bits have re- turned to zero. Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi) AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3-type data. RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that can cause RERR to go high are: validity, parity error, bi-phase coding error, confidence, QCRC and CCRC errors, as well as loss of lock in the PLL. Optionally, each condition may be masked from affecting the RERR pin using the Receiver Error Mask Register. The RERR pin tracks the status of the unmasked errors: the pin goes high as soon as an unmasked error occurs and goes low immediately when all unmasked errors go away.

EMPH - Pre-Emphasis Indicator Output EMPH is low when the incoming AES3 data indicates the presence of 50/15 μs pre-emphasis. When the AES3 data indicates the absence of pre-emphasis or the presence of other than 50/15 μs pre-emphasis EMPH is high. This is also a start-up option pin, and requires a 47 kΩ resistor to either VD+ or DGND, which determines the AD2 address bit for the control port in I²C mode. Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso) AES3/SPDIF Transmitter Interface: TCBL - Transmit Channel Status Block Start This pin can be configured as an input or output. When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK (or RMCK, depending on which clock is operating the AES3 encoder block) clocks will cause the next transmitted sub-frame to be the start of a channel status block. TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. Control Port Signals: SCL/CCLK - Control Port Clock SCL/CCLK is the serial control interface clock, and is used to clock control data bits into and out of the CS8420. AD0/CS - Address Bit 0 (I²C) / Control Port Chip Select (SPI) A falling edge on this pin puts the CS8420 into SPI Control Port mode. With no falling edge, the CS8420 defaults to I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8420. AD1/CDIN - Address Bit 1 (I²C) / Serial Control Data In (SPI) In I²C mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface SDA/CDOUT - Serial Control Data I/O (I²C) / Data Out (SPI) In I²C mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VD+. In SPI mode, CDOUT is the output data from the control port interface on the CS8420.

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Miscellaneous Pins: U - User Data The U pin may optionally be used to input User data fo r transmission by th e AES3 transmitter (see Figure 20 for timing information). Alternatively, the U pin may be set to output User data from the AES3 receiver (see Figure 19 for timing information). If not driven, a 47 kΩ pull-down resistor is recommended for the U pin since the default state of the UD direction bit sets the U pin as an input. The pull-down resistor ensures that the transmitted user data will be zero. If the U pin is always set to be an output, thereby causing the U bit manager to be the source of the U data, the resistor is not necessary. The U pin should not be tied directly to ground in case it is programmed to be an output and subsequently tries to output a logic high. This situation may affect the long-term reliability of the device. If the U pin is driven by a logic level output, a 100 Ω series resistor is recommended.

13.1 Overall Description

Hardware mode. Various pins change function in Hardware mode, and various data paths are also possible. the data flows and pin definitions for each Hardware mode.

13.1.1 Hardware Mode Definitions

which modes depends on which Hardware mode is being used.

13.1.2 Serial Audio Port Formats

format. Timing diagrams are shown in Figures 17 and 18. scriptions list and a definition of the available start-up options. Table 5. Hardware Mode Definitions Table 6. Serial Audio Output Formats Available in Hardware Mode Table 7. Serial Audio Input Formats Available in Hardware Mode

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13.2 Hardware Mode 1 Description (DEFAULT Data Flow, AES3 Input)

the received channel status data, and the transmitted U and V bits are 0. AUDIO/V pins. Figure 20 shows the timing requirements. pages contain the detailed pin descriptions for Hardware mode 1. If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held. received PRO, EMPH, AUDIO are visible. Table 8. Hardware Mode 1 Start-Up Options are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 24. Hardware Mode 1 - Default Data Flow, AES3 Input

13.2.1 Pin Description - Hardware Mode 1

Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, as shown in Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to ground in Hardware mode 1 in order to select the AES3 input. MUTE - Mute Output Data Input If MUTE is low, audio data is passed normally. If MUTE is high, both the AES3 transmitted audio data and the serial audio output port data is set to digital zero. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso). AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is also a start-up option pin and requires a pull-up or pull-down resistor.

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RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor. EMPH/U - Pre-Emphasis Indicator Output or U-Bit Data Input The EMPH/U pin reflects either the state of the EMPH channel status bits in the incoming AES3 type data stream, or is the serial U-bit input for the AES3 type transm itted data, clocked by OLRCK. When indicating emphasis, EMPH/U is low if the incoming data indicates 50/15 μs pre-emphasis and high otherwise. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This is also a start-up option pin, and requires a pull-up or pull-down resistor. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. PRO/C - Professional Channel Status Bit Output or C-Bit Data Input The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK. AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK. Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso) AES3/SPDIF Transmitter Interface: TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When o perated as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. TCBLD - Transmit Channel Status Block Direction Input Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state.

13.3 Hardware Mode 2 Description

The C, U, and V bits in the AES3 output stream may be set in two methods, selected by the CUVEN pin. TCBL. Figure 20 shows the timing requirements. Audio serial port data formats are selected as shown in Tables 6, 7 and 10. and whether TCBL is an input or an output. The serial audio input port is always a slave. a r eo m i t t e df r o mt h i sd i agram. Please refer to the Typical Connection Diagram for hook-up details. Figure 25. Hardware Mode 2 - Default Data Flow, Serial Audio Input

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00 PRO=0, COPY=0, L=0

01 PRO=0, COPY=0, L=1

10 PRO=0, COPY=1, L=0

11 PRO=1

Table 9. HW Mode 2A COPY/C and ORIG/U Pin Function

00 Serial Input & Output Format IF1&OF1

01 Serial Input & Output Format IF2&OF2

10 Serial Input & Output Format IF3&OF3

11 Serial Input & Output Format IF4&OF3

Table 10. HW Mode 2 Serial Audio Port Format Selection Table 11. Hardware Mode 2 Start-Up Options

13.3.1 Pin Description - Hardware Mode 2

Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to VD+ in Hardware mode 2, in order to select the serial audio input. SFMT0, SFMT1 - Serial Audio Port Data Format Select Inputs SFMT0 and SFMT1 select the serial audio input and output ports’ format. See Table 10. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso). Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi)

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RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). LOCK - PLL Lock Indicator Output LOCK low indicates that the PLL is locked. This is also a start-up option pin, and requires a pull-up or pull-down resistor. Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When o perated as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. CUVEN - C, U and V bit Input Enable Mode Input The CUVEN pin determines how the channel status data, user data and validity bit is input. When CUVEN is low, Hardware mode 2A is selected, where the EMPH /V, COPY/C and ORIG/U pins are used to enter selected channel status data. When CUVEN is high, hardware 2B is selected, where the EMPH /V, COPY/C and ORIG/U pins are used to enter serial C, U and V data. EMPH/V - Pre-Emphasis Indicator Input or V Bit Input In mode 2A, EMPH /V low sets the 3 EMPH channel status bits to indicate 50/15 μs pre-emphasis. EMPH /V high sets the 3 EMPH bits to 000 indicating no pre-emphasis. In mode 2B, EMPH /V low sets the V bit to indicate valid audio. EMPH/V high sets the V-bit to indicate non-valid audio. COPY/C - COPY Channel Status Bit Input or C Bit Input In mode 2A, the COPY/C pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream (See Table 9). In mode 2B, COPY/C becomes the direct C bit input data pin. ORIG/U - ORIG Channel Status Bit Input or U Bit Input In mode 2A, the ORIG/U pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream. (See Table 9). In mode 2B, ORIG/U becomes the direct U bit input data pin.

13.4 Hardware Mode 3 Description

synchronous to OMCK, may be input into the serial audio input port, and output via the AES3 transmitter. received channel status data, and the transmitted U and V bits are zero. AUDIO/V pins. Figure 20 shows the timing requirements. The serial audio input port is always a slave. If a validity, parity, bi-phase, or lock receiver error occurs, the current audio sample will be held. U, and V data. The following pages contain the detailed pin descriptions for Hardware mode 3. are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 26. Hardware Mode 3 - Transceive Data Flow, with SRC

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Table 12. Hardware Mode 3 Start-Up Options

13.4.1 Pin Description - Hardware Mode 3

Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso). Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. This data will be transmitted out the AES3 port. ISCLK - Serial Audio Input Port Bit Clock Input Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input Word rate clock for the audio data on the SDIN pin. The frequency will be at the output sample rate (Fso) Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin.

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OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the output sample rate (Fso). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When o perated as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is also a start-up option pin, and requires a pull-up or pull-down resistor. RERR - Receiver Error Indicator Output When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor. EMPH/U - Pre-emphasis Indicator Output or U-Bit Data Input The EMPH/U pin either reflects the state of the EMPH channel status bits in the incoming AES3 type data stream, or is the serial U-bit input for th e AES3 type transmitted data , clocked by OLRCK. If indicating emphasis EMPH/U is low when the incoming data indicates 50/15 μs pre-emphasis and high otherwise. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This is also a start-up option pin, and requires a pull-up or pull-down resistor. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This is also a start-up option pin, and requires a pull-up or pull-down resistor. PRO/C - Professional Channel Status Bit Output or C-Bit Data Input The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK. AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.

13.5 Hardware Mode 4 Description

input port, and output via the AES3 transmitter. from the received channel status data, and the transmitted U and V bits are 0. AUDIO/V pins. Figure 20 shows the timing requirements. The APMS pin allows the serial audio input port to be set to master or slave. to the serial audio output port. The following pages contain the detailed pin descriptions for Hardware mode 4. are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 27. Hardware Mode 4 - Transceive Data Flow, Without SRC

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Table 13. Hardware Mode 4 Start-Up Options

13.5.1 Pin Description - Hardware Mode 4

Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. This data will be transmitted out the AES3 port. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. The frequency will be at the input sample rate (Fsi) APMS - Serial Audio Input Port Master or Slave APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave. Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor.

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OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi). AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operat ed as input, driving TCBL high for at leas t three RMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). This is also a start-up option pin, and requires a pull-up or pull-down resistor. RERR - Receiver Error Indicator Output When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin, and requires a pull-up or pull-down resistor. EMPH/U - Pre-emphasis Indicator Output or U-Bit Data Input The EMPH/U pin either reflects the state of the EMPH channel status bit in the incoming AES3 type data stream, or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. If indicating emphasis EMPH /U is high when the incoming data indicates 50/15 μs pre-emphasis and low otherwise. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. This is also a start-up option pin, and requires a pull-up or pull-down resistor. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This is also a start-up option pin, and requires a pull-up or pull-down resistor. PRO/C - Professional Channel Status Bit Output or C-Bit Data Input The PRO/C pin either reflects the state of the Professional/Consumer Channel Status bit in the incoming AES3 type data stream, or is the serial C-bit input for the AES3 type transmitted data, clocked by OLRCK. AUDIO/V - Audio Channel Status Bit Output or V-Bit Data Input The AUDIO/V pin either reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream, or is the V-bit data input for the AES3 type transmitted data stream, clocked by OLRCK.

13.6 Hardware Mode 5 Description

to the serial audio output port. Table 14. Hardware Mode 5 Start-Up Options are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 28. Hardware Mode 5 - AES3 Receiver Only

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13.6.1 Pin Description - Hardware Mode 5

Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to DGND in Hardware mode 5, in order to select the AES3 input. OMCK - Output Section Master Clock Input Output section master clock input. This pin is not used in this mode and should be connected to DGND. Audio Output Interface: SDOUT - Serial Audio Output Port Data Output Audio data serial output pin. This is also a start-up option pin, and requires a pull-up or pull-down resistor. OSCLK - Serial Audio Output Port Bit Clock Input or Output Serial bit clock for audio data on the SDOUT pin. OLRCK - Serial Audio Output Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDOUT pin. The frequency will be at the input sample rate (Fsi).

AES3/SPDIF Receiver Interface: RXP, RXN - Differential Line Receiver Inputs Differential line receiver inputs, carrying AES3 type data. RMCK - Input Section Recovered Master Clock Output Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi). RERR - Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: validity, parity error, and bi-phase coding error, as well as loss of lock in the PLL. NVERR - No Validity Receiver Error Indicator When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is updated once per frame of incoming AES3 data. Conditions that cause NVERR to go high are: parity error, and bi-phase coding error, as well as loss of lock in the PLL. EMPH - Pre-emphasis Indicator Output EMPH is low when the incoming AES3 data indicates the presence of 50/15 μs pre-emphasis. When the AES3 data indicates the absence of pre-emphasis or the presence of non 50/15 μs pre-emphasis EMPH is high. This is also a start-up option pin, and requires a pull-up or pull-down resistor. COPY - Copy Channel Status Bit Output The COPY pin reflects the state of the COPY Channel Status bit in the incoming AES3 type data stream. ORIG - Original Channel Status Output SCMS generation indicator. This is decoded from the incoming category code and the L bit. A low output indicates that the audio data stream is 1st generation or higher. A high indicates that the audio data stream is original. This is also a start-up option pin, and requires a pull-up or pull-down resistor. PRO - Professional Channel Status Bit Output The PRO pin reflects the state of th e Professional/Consumer Channel Status bit in the incoming AES3 type data stream. AUDIO - Audio Channel Status Bit Output The AUDIO pin reflects the state of the audio/non audio Channel Status bit in the incoming AES3 type data stream. RCBL - Receiver Channel Status Block Output RCBL indicates the beginning of a received channel status block. RCBL goes high 2 frames after the reception of a Z preamble, remains high for 16 frames while COPY, ORIG, AUDIO, EMPH and PRO are updated, and returns low for the remainder of the block. RCBL changes on rising edges of RMCK. CHS - Channel Select Input Selects which sub-frame’s channel status data is output on the EMPH, COPY, ORIG, PRO and AUDIO pins. Chan- nel A is selected when CHS is low, channel B is selected when CHS is high. U - User Data Output The U pin outputs user data from the AES3 receiver, clocked by rising and falling edges of OLRCK. C - Channel Status Data Output The C pin outputs channel status data from the AES3 receiver, clocked by rising and falling edges of OLRCK.

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13.7 Hardware Mode 6 Description

routed to the AES3 transmitter. Sample Rate Converter (0101100b). is in Master mode). Figure 20 shows the timing requirements. slave by the state of the APMS input pin. The following pages contain detailed pin descriptions for Hardware mode 6. are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 29. Hardware Mode 6 - AES3 Transmitter Only

Table 16. HW 6 Serial Port Format Selection Table 15. HW 6 COPY/C and ORIG Pin Function

00 Serial Input Format IF1

01 Serial Input Format IF2

10 Serial Input Format IF3

11 Serial Input Format IF4

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13.7.1 Pin Description - Hardware Mode 6

Overall Device Control: DFC0, DFC1 - Data Flow Control Inputs DFC0 and DFC1 inputs determine the major data flow options available in Hardware mode, according to Table 5. S/AES - Serial Audio or AES3 Input Select S/AES is connected to VD+ in Hardware mode 6, in order to select the serial audio input. SFMT0, SFMT1 - Serial Audio Input Port Data Format Select Inputs SFMT0 and SFMT1 select the serial audio input port format. See Table 15. OMCK - Output Section Master Clock Input Output section master clock input. The frequency must be 256x the output sample rate (Fso). Audio Input Interface: SDIN - Serial Audio Input Port Data Input Audio data serial input pin. ISCLK - Serial Audio Input Port Bit Clock Input or Output Serial bit clock for audio data on the SDIN pin. *P i n sw h i c hremain the same function in all modes. COPY/C DFC0 EMPH SFMT0 SFMT1 VA+ AGND FILT RST APMS TCBLD ILRCK ISCLK SDIN *24 *23 *22 ORIG DFC1 TXP TXN H/S VD+ DGND OMCK S/AES AUDIO U V CEN TCBL

ILRCK - Serial Audio Input Port Left/Right Clock Input or Output Word rate clock for the audio data on the SDIN pin. APMS - Serial Audio Input Port Master or Slave. APMS should be connected to VD+ to set serial audio input port as a master, or connected to DGND to set the port as a slave. AES3/SPDIF Transmitter Interface: TXN, TXP - Differential Line Driver Outputs Differential line driver outputs, transmitting AES3 type data. Drivers are pulled to low while the CS8420 is in the reset state. TCBL - Transmit Channel Status Block Start When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When opera ted as input, driving TCBL high for at least three OMCK clocks will cause the current transmitted sub-frame to be the start of a channel status block. TCBLD - Transmit Channel Status Block Direction Input Connect TCBLD to VD+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. EMPH - Pre-Emphasis Indicator Input In mode 6B, EMPH pin low sets the 3 EMPH channel status bits to indicate 50/15 μs pre-emphasis. If EMPH is high the 3 EMPH channel status bits are set to 000 indicating no pre-emphasis. COPY/C - COPY Channel Status Bit Input or C Bit Input In mode 6B, the COPY/C pin determines the state of t he COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream (See Table 15). In mode 6A, the COPY/C pin becomes the direct C bit input data pin. ORIG - ORIG Channel Status Bit Input In mode 6B, the ORIG pin determines the state of the COPY, PRO and L Channel Status bits in the outgoing AES3 type data stream. See Table 15. AUDIO - Audio Channel Status Bit Input In mode 6B, the AUDIO pin determines the st ate of the audio/non audio Channe l Status bit in the outgoing AES3 type data stream. V - Validity Bit Input In modes 6A and 6B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. U - User Data Bit Input In modes 6A and 6B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. CEN - C Bit Input Enable Mode Input The CEN pin determines how the channel status data bits are input. When CE N is low, Hardware mode 6A is se- lected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When CEN is high, Hardware mode 6B is selected, where the COPY/C pin is used to enter serial channel status data.

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1. EXTERNAL AES3/SPDIF/IEC609 58 TRANSMITTER AND RECEIVER

14.1 AES3 Transmitter External Components

and with pin 1 of the connector grounded. RCA phono socket. This circuit is also short circuit protected. Figure 30. Professional Output Circuit Figure 31. Consumer Output Circuit

also useful when driving multiple digital audio outputs since RS422 line drivers have TTL compatible inputs.

14.2 AES3 Receiver Ex ternal Components

they are, however, strongly recommended. frequency energy could be coupled into the receiver, causing degradation in analog performance. Figures 33 and 34 show an optional DC blocking capacitor (0.1μF to 0.47 μF) in series with the cable input. flow, if a DC voltage is present on the cable. Figure 32. TTL/CMOS Output Circuit Figure 33. Professional Input Circuit Figure 34. Transformerless Professional Input Circuit

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for the consumer interface is shown in Figure 35. TTL/CMOS logic outputs drive the CS8420 receiver section.

14.3 Isolating Transformer Requirements

ufacturers and their part numbers. Figure 35. Consumer Input Circuit Figure 36. TTL/CMOS Input Circuit

1. CHANNEL STATUS AND USER DATA BUFFER MANAGEMENT

the user to completely manage the C and U data via the control port.

15.1 AES3 Channel Status(C) Bit Management

bits), and also 384 bits of U information. The user may read from or write to these RAMs via the control port. bit for channel status block A. block transfers from the E buffer. cation, then they will need to be updated via the control port by the microcontroller for every outgoing block. Figure 37. Channel Status Data Buffer Structure

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15.1.1 Manually Accessing the E Buffer

would overwrite the desired transmit C data with invalid data. to the E buffer actually gets transmitted and not overwritten by a D-to-E transfer. Figure 38. Channel Status Block Handling When Fso is Not Equal to Fsi Figure 39. Flowchart for Reading the E Buffer

15.1.2 Reserving the First 5 Bytes in the E Buffer

users who want to transmit certain channel status settings which are different from the incoming settings. In this case, the user would have to superimpose his settings on the E buffer after every D-to-E overwrite. until the next user change. This mode is enabled via the Channel Status Data Buffer Control register.

15.1.3 Serial Copy Mana gement System (SCMS)

Code, Copy bit and L bit appropriately.

15.1.4 Channel Status Data E Buffer Access

LS Byte is the B channel data (see Figure 37). sired mode is selected via a control register bit. Figure 40. Flowchart for Writing the E Buffer

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15.1.5 One-Byte Mode

In many applications, the channel status blocks for the A and B channels will be identical. In this situation, if the user reads a byte from one of the channel's blocks, the corresponding byte for the other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. One-Byte mode take s advantage of the often id entical nature of A and B channel status data. When reading data in one-byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. If a write is being done, the CS8420 expects a single byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. One-Byte mode saves the user subs tantial control port access time, as it effectively accesses 2 bytes’ worth of information in 1 byte's worth of access ti me. If the control port's auto-increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently.

15.1.6 Two-Byte Mode

There are those applicat ions in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, Two-Byte mode should be used to access the E buffer. In this mode, a read will cause the CS8420 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8420's control port. The A channel status data is first, B channel status data second.

15.2 AES3 User (U) Bit Management

The CS8420 U bit manager has four operating modes: Mode 1. Transmit all zeros Mode 2. Block mode Mode 3. Reserved Mode 4. IEC Consumer B

15.2.1 Mode 1: Transmit All Zeros

Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents or U data embedded in an input AES3 data stream. This mode is intended for the user who does not want to trans- ceive U data, and simply wants the output U channel to contain no data.

15.2.2 Mode 2: Block Mode

Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered from input to output, using a cascade of three block-sized RAMs to perform the buffering. The user has access to the second of these three buffers, denoted the E bu ffer, via the control port. Block mode is designed for use in AES3 in, AES3 out situatio ns in which input U data is decod ed using a microcontroller via the control port. It is also the only mode in which the user can merge his/her own U data into the transmitted AES3 data stream. The U buffer access only operates in Two-Byte mode, since there is no concept of A and B blocks for user data. The arrangement of the data in the each byte is that the MSB is the first received bit and is the first

transmitted bit. The first byte read is the first byte received, and the firs t byte sent is the first byte trans- mitted.

15.2.3 IEC60958 Recommended U Data Fo rmat for Consumer Applications

Modes (3) and (4) are intended for use in AES3 in, AES3 out situatio ns, in which the input U data is for- matted as recommended in the “IEC60958 Digital Audio Interface, part 3: Consumer applications” docu- ment. In this format, “messages” are formed in the U data from Information Units or IUs. An IU is 8 bits long, and the MSB is always 1, and is called the start bit, or 'P' bit. The remaining 7-bits are called Q, R, S, T, U, V, & W, and carry the desired data. A “message” consists of 3 to 129 IUs. Multiple IUs are considered to be in the same message if they are separated by 0 to 8 zeros, denoted here as filler. A filler sequence of nine or more zeros indicates an inter- message gap. The desired information is normally carr ied in the sequence of corresponding bits in the IUs. For example, the sequential Q bits from each IU make up the Q sub-code data that is used to indicate Compact Disk track information. This data is automatically extracted from the received IEC60958 stream, and is presented in the control port register map space. Where incoming U data is coded in the above format, and needs to be re-trans mitted, the data transfer cannot be done using shift registers, because of the different Fsi and Fso sampling clocks. Instead, input data must be buffered in a FIFO structure, and then read out by the AES3 transmitter at appropriate times. Each bit of each IU must be transceived; unlike the audio samples, there can be no sample rate conver- sion of the U data. Therefore, there are two potential problems: (1) Message Partitioning When Fso > Fsi, more data is tr ansmitted than received per unit ti me. The FIFO will fr equently be com- pletely emptied. Sensible behavior must occur when the FIFO is empty, otherwise, a single incoming mes- sage may be erroneously partitioned into multiple, smaller, messages. (2) Overwriting When Fso < Fsi, more data is received than transmitted per unit time. There is a danger of the FIFO be- coming completely full, allowing incoming data to overwrite data that has not yet been output through the AES3 transmitter.

15.2.4 Mode (3): Reserved

This mode has been removed. Use IEC Consumer mode B.

15.2.5 Mode (4): IEC Consumer B

In this mode, the partitioning problem is solved by buffering an entire message before starting to transmit it. In this scheme, zero-segments between messages will be expanded when Fso > Fsi, but the integrity of individual messages is preserved. The overwriting problem (when Fso < Fs i) is solved by only storing a po rtion of the input U data in the FIFO. Specifically, only the IUs themselves are stored (and not the zeros that provide inter-IU and inter- message “filler”). An inter-IU filler segment of fixed length (OF) will be added back to the messages at the FIFO output, where the length of OF is equal to the shortest observed input filler segment (IF). Storing only IUs (and not filler) within the FIFO makes it possible for the slower AES3 transmitter to “catch up” to the faster AES3 receiver as data is read out of the FIFO. This is because nothing is written into the FIFO when long strings of zeros are input to the A ES-EBU receiver. During this time of no writing, the

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transmitter can read out data that had previously accumulated, allowing the FIFO to empty out. If the FIFO becomes completely empty, zeros are transmitted until a complete message is written into the FIFO. Mode 4 is not fail-safe; the FIFO can still get completely full if there isn't enough “zero-padding” between incoming messages. It is up to the user to provide proper padding, as defined below: Minimum padding = (Fsi/Fso - 1)*[8N + (N-1)*IF +9] + 9 where N is the number of IUs in the message, IF is the number of filler bits between each IU, and Fso ≤ Fsi. Example 1: Fsi/Fso = 2, N=4, IF=1: minimum proper padding is 53 bits. Example 2: Fsi/Fso = 1, N=4, IF=7: min proper padding is 9 bits. The CS8420 detects when an overwrite has occurred in the FIFO, and synchronously resets the entire FIFO structure to preven t corrupted U data from be ing merged into the tran smitted AES3 data stream. The CS8420 can be configured to generate an interrupt when this occurs. Mode 4 is recommended for properly formatted U data where mode 3 cannot provide acceptable perfor- mance, either because of a too-extreme Fsi/Fso ratio, or because it's unacceptable to change the lengths of filler segments. Mode 4 provides error-free performance over the complete range of Fsi/Fso ratios (pro- vided that the input messages are properly zero-padded for Fsi > Fso).

16.1 General

the PLL is locked to ILRCK, it is updated at FS so that the duty cycle of the input doesn’t affect jitter. dent jitter effects because the AES3 preambles do not vary with the data. The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. wide lock range mode and re-acquire a new nominal center sample rate.

16.2 External Filter Components

16.2.1 General

Figure 41. PLL Block Diagram

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16.2.2 Capacitor Selection

to shock and vibration. These include the Z5U and Y5V dielectrics.

16.2.3 Circuit Board Layout

42 contains a suggested layout for the PLL filter components and for bypassing the analog supply voltage. form factor. The traces are on the top surface of the board with the IC so that there is no via inductance. extend back to their origin and are shown only in truncated form in the drawing.

16.3 Component Value Selection

16.3.1 Identifying th e Part Revision

which indicates what revision the part is. Table 17. Second Line Part Marking Figure 42. Recommended Layout Example

16.3.2 Locking to the R XP/RXN Receiver Inputs

Table 18. Locking to RXP/RXN - Fs = 8 to 96 kHz Table 19. Locking to RXP/RXN - Fs = 32 to 96 kHz* tions do not have allowances for locking to sample rates less than 32 kHz or for locking to the ILRCK input. recommendations outlined previously.

16.3.3 Locking to the ILRCK Input

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16.3.4 Jitter Tolerance

Table 19) have been tested to pass this template.

16.3.5 Jitter Attenuation

ing to the ILRCK input. These specifications state a maximum of 2 dB jitter gain or peaking. Figure 43. Jitter Tolerance Template Figure 44. Revision D Jitter Attenuation Fig ure 45. Revision D1 Jitter Attenuation

1. PARAMETER DEFINITIONS Input Sample Rate (Fsi) The sample rate of the incoming digital audio. Input Frame Rate The frame rate of the received AES3 format data. Output Sample Rate (Fso) The sample rate of the outgoing digital audio. Output Frame Rate The frame rate of the transmitted AES3 format data. Dynamic Range The ratio of the maximum signal level to the noise floor. Total Harmonic Distortion and Noise The ratio of the noise and distortion to the test signal level. Normally referenced to 0 dBFS. Peak Idle Channel Noise Component With an all-zero input, what is the amplitude of th e largest frequency component visible with a 16K point FFT. The value is in dB ratio to full-scale. Input Jitter Tolerance The amplitude of jitter on the AES3 stream, or in the ILRCK clock, that will cause measurable artifacts in the SRC output. Test signal is full scale 9 kHz, Fsi is 48 kH z, Fso is different 48 kHz, jitter is 2 kHz sinusoidal, and audio band white noise. AES3 Transmitter Output Jitter With a jitter free OMCK clock, what is the jitter added by the AES3 transmitter. Gain Error The difference in amplitude between the output and the input signal level, within the passband of the digital filter in the SRC.

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1. PACKAGE DIMENSIONS THERMAL CHARACTERISTICS AND SPECIFICATIONS INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 ∝ 0° 8° 0° 8° Parameter Symbol Min Typ Max Units Junction to Ambient thermal impedance (28 pin SOIC) θJA - 65 - °C/W Allowable Junction Temperature T J -- 1 3 5 ° C 28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE e

1. ORDERING INFORMATION 20. REVISION HISTORY Product Description Package Pb-Free Grade Temp Range Container Order# CS8420 Digital Audio Sample Rate Converter 28-SOIC No Commercial -10º to +70ºC Rail CS8420-CS Tape and Reel CS8420-CSR Yes Commercial -10º to +70ºC Rail CS8420-CSZ Tape and Reel CS8420-CSZR Automotive -40º to +85ºC Rail CS8420-DSZ Tape and Reel CS8420-DSZR CDB8420 Evaluation Board for CS8420 - - - - - CDB8420 Release Changes PP1 1st Preliminary Release PP2 2nd Preliminary Release PP3 3rd Preliminary Release PP4 -Added IS package to front page. -Added IS package to “Ambient Operating Temperature:” on page 6. -Corrected “Minimizing Group Delay Through Multiple CS8420s When Locking to ILRCK” on page 28. -Revised “SRC Invalid State” on page 49. PP5 -Added DS package to front page. -Added DS package to “Ambient Operating Temperature:” on page 6. -Corrected “tdpd” on page 9. -Corrected “tlmd” on page 9. -Corrected “tsmd” on page 9. -Corrected “tdh” on page 10. -Added “C/U Buffer Data Corruption” on page 49 PP6 -Added lead-free ordering information. Final Release 1 -Changed format of Figure 17 on page 20 and Figure 18 on page 21. -Changed SORES description to refer to sample rate converter as data source in “Serial Audio Output Port Data Format (06h)” on page 39. -Added “Transmitter Startup” on page 48. -Integrated D1 Errata in Section 16.2 on page 87 . Final Release 2 -Updated Ordering Information. -Added “Block-Mode U-Data D-to-E Buffer Transfers” on page 50. F3 Final Release 3 -Updated Ordering Information. F4 Final Release 4 -Updated Leaded/Lead-Free information in “Ordering Information” on page 93.

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