CS8416-DSZ

CS8416_07 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

 Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF-Compatible Receiver  +3.3 V Analog Supply (VA)  +3.3 V Digital Supply (VD)  +3.3 V or +5.0 V Digital Interface Supply (VL)  8:2 S/PDIF Input MUX  AES/SPDIF Input Pins Selectable in Hardware Mode  Three General Purpose Outputs (GPO) Allow Signal Routing  Selectable Signal Routing to GPO Pins  S/PDIF-to-TX Inputs Selectable in Hardware Mode  Flexible 3-wire Serial Digital Output Port  32 kHz to 192 kHz Sample Frequency Range  Low-Jitter Clock Recovery  Pin and Microcontroller Read Access to Channel Status and User Data  SPI™ or I²C ® Control Port Software Mode and Stand-Alone Hardware Mode  Differential Cable Receiver  On-Chip Channel Status Data Buffer Memories  Auto-Detection of Compressed Audio Input Streams  Decodes CD Q Sub-Code  OMCK System Clock Mode See the General Description and Ordering Information on page 2. Clock & Data Recovery Misc. Control Serial Audio Output Receiver AES3 S/PDIF Decoder Control Port & Registers RXN RXP1 OLRCK OSCLK SDOUT RST SDA/ CDOUT SCL/ CCLK AD1/ CDIN AD0/ CS AGND FILT VL DGNDRMCK RXP2 RXP3 RXP4 RXP5 RXP6 RXP7 8:2 MUX OMCK GPO0 GPO1 AD2/GPO2 RXP0 n:3 MUX VDVA TX Passthrough Format Detect C & U bit Data Buffer De-emphasis Filter AUGUST '07 DS578F3 CS8416

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The CS8416 is a monolithic CMOS device that receives and decodes one of eight stereo pairs of digital audio data according to the IEC60958, S/PDIF, EIAJ CP1201, or AES3 interface standards. The CS8416 has a serial digital audio output port and comprehensive control ability through a selectable control port in Software Mode or through selectable pins in Hardware Mode. Channel status data are assembled in buffers, making read access easy. GPO pins may be assigned to route a variety of signals to output pins. A low-jitter clock recovery mechanism yields a very clean recovered clock from the incoming AES3 stream. Stand-alone operation allows systems with no microcontroller to operate the CS8416 with dedicated output pins for channel status data. The CS8416 is available in 28-pin TSSOP, SOIC, and QF N packages in Commercial grade (-10° to +70° C) and Automotive grade (-40° to +85° C). The CDB8416 Customer Demonstration board is also available for device eval- uation and implementation suggestions. Please refer to “Ordering Information” on page 59 for complete ordering information. Target applications include A/V receivers, CD-R, DVD receivers, multimedia speakers, digital mixing consoles, ef- fects processors, set-top boxes, and computer and automotive audio systems.

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1. CHARACTERISTICS AND SPECIFICATIONS All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C. SPECIFIED OPERATING CONDITIONS (AGND, DGND = 0 V, all voltages with respect to 0 V) ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent dam- age to the device. Normal operation is not guaranteed at these extremes.) Notes: 1. Transient currents of up to 10 0 mA will not cause SCR latch-up. Parameter Symbol Min Typ Max Units Power Supply Voltage VA VD VL 3.13 3.13 3.13 3.3 3.3 3.3 or 5.0 3.46 3.46 5.25 V V V Ambient Operating Temperature: Commercial Grade Automotive Grade T A -10 -40 +70 +85 °C Parameter Symbol Min Max Units Power Supply Voltage VA, VD,VL - 6.0 V Input Current, Any Pin Except Supplies (Note 1) Iin -± 1 0 m A Input Voltage V in -0.3 (VL) + 0.3 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C

DC ELECTRICAL CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.) Notes: 2. Power-Down Mode is defined as RST = LO with all clocks and data lines held static. 3. Normal operation is defined as RST = HI. 4. Assumes that no inputs are floating. It is recommended that all inputs be driven high or low at all times. DIGITAL INPUT CHARACTERISTICS (AGND = DGND = 0 V; all voltages with respect to 0 V.) DIGITAL INTERFACE SPECIFICATIONS (AGND = DGND = 0 V; all voltages with respect to 0 V.) Parameters Symbol Min Typ Max Units Power-Down Mode (Notes 2, 4) Supply Current in power-down VA VD VL = 3.3 V VL = 5.0 V IA ID IL IL μA μA μA μA Normal Operation (Notes 3, 4) Supply Current at 48 kHz frame rate VA VD VL = 3.3 V VL = 5.0 V IA ID IL IL 5.7 5.9 2.8 4.2 mA mA mA mA Supply Current at 192 kHz frame rate VA VD VL = 3.3 V VL = 5.0 V IA ID IL IL 9.4 7.8 11.8 mA mA mA mA Parameters Symbol Min Typ Max Units Input Leakage Current I IN -- ± 0 . 5 μA Differential Input Sensitivity, RXP[7:0] to RXN V TH - 150 200 mVpp Input Hysteresis V H 0.15 - 1.0 V Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA) V OH (VL) - 1.0 - V Low-Level Output Voltage (IOL = 3.2 mA) V OL -0 . 5 V High-Level Input Voltage, except RXP[7:0], RXN V IH 2.0 (VL) + 0.3 V Low-Level Input Voltage, except RXP[7:0], RXN V IL -0.3 0.8 V

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(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Notes: 5. Typical RMS cycle-to-cycle jitter. 6. Duty cycle when clock is recovered from biphase encoded input. 7. Duty cycle when OMCK is swit ched over for output on RMCK. Parameter Symbol Min Typ Max Units RST Pin Low Pulse Width 200 - - μS PLL Clock Recovery Sample Rate Range 30 - 200 kHz RMCK Output Jitter (Note 5) -2 0 0- p s R M S RMCK Output Duty-Cycle (Note 6) (Note 7) RMCK/OMCK Maximum Frequency - - 50 MHz

1. In Software Mode the active edges of OSCLK are programmable.
2. In Software Mode the polari ty of OLRCK is programmable.
3. This delay is to prevent the previous OSCLK edge from being interpreted as the first one after OLRCK
4. This setup time ensures that this OSCLK edge is interpreted as the first one after OLRCK has changed.

Figure 1. Audio Port Master Mode Timing Figure 2. Audio Po rt Slave Mode and Data Input

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1. If Fs is lower than 46.875 kHz, the maximum CCLK frequency should be less than 128 Fs. This is dic-

32 kHz, so choosing CCLK to be less than or equal to 4.1 MHz should be safe for all possible conditions.

1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 3. SPI Mode Timing

1. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Figure 4. I²C Mode Timing

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1. PIN DESCRIPTION - SOFTWARE MODE

2.1 TSSOP Pin Description

Pin # Pin Description VA 6 Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock VD 23 Digital Power (Input) – Digital core power supply. Nominally +3.3 V VL 21 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V AGND 7 Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con- nected to a common ground area under the chip. DGND 22 Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected to a common ground area under the chip. RST 9 Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. FILT 8 PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground. For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on page 53 for more information on the PLL and the external components. RXP0 RXP1 RXP2 RXP3 RXP4 RXP5 RXP6 RXP7 Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float- ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec- ommended input circuits. RXP3 OLRCK RXP2 OSCLK RXP1 SDOUT RXP0 OMCK RXN RMCK VA VD AGND DGND FILT VL RST GPO0 RXP4 GPO1 RXP5 AD2 / GPO2 RXP6 SDA / CDOUT RXP7 SCL / CCLK AD0 / CS AD1 / CDIN 82 1 12 17 14 15 Top-Down View 28-pin SOIC/TSSOP Package

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single- ended operation this should be AC coupled to ground through a capacitor. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits. OMCK 25 System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock. OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System Clock Mode” section on page 28 RMCK 24 Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency defaults to 256x the sample rate (Fs) and may be set to 128x through the RMCKF bit in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4 register (04h). OSCLK 27 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin OLRCK 28 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs) SDOUT 26 Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode. SDA / CDOUT 17 Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out- put data from the control port interface on the CS8416. See the “Control Port Description” section on page 33. SCL / CCLK 16 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the “Control Port Description” section on page 33. AD0 / CS 14 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416 into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8416. See the “Control Port Description” section on page 33. AD1 / CDIN 15 Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description” section on page 33. AD2 / GPO2 18 General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose Outputs” on page 29 for GPO functions. GPO1 19 General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions. GPO0 20 General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions. Pin Name Pin # Pin Description

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2.2 QFN Pin Description

Pin # Pin Description VA 3 Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock VD 20 Digital Power (Input) – Digital core power supply. Nominally +3.3 V VL 18 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V AGND 4 Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con- nected to a common ground area under the chip. DGND 19 Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be connected to a common ground area under the chip. RST 6 Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. FILT 5 PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground. For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on page 53 for more information on the PLL and the external components. 10 11 12 13 14 22232425262728 Top-Down View 28-pin QFN Package Thermal Pad RXP1 RXP2 RXP3 OLRCK OSCLK SDOUT OMCK RXP5 RXP6 RXP7 AD0 / CS AD1 / CDIN SCL / CCLK SDA / CDOUT RXP0 RXN VA AGND FILT RST RXP4 RMCK VD DGND VL GPO0 GPO1 AD2 / GPO2

Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF encoded digital data. The RXP[7:0] inputs comprise the 8:2 S/PDIF Input Multiplexer. The select line control is accessed using the Control 4 register (04h). Unused multiplexer inputs should be left float- ing or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for rec- ommended input circuits. RXN 2 Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[7:0] to form an AES3 differential input. In single- ended operation this should be AC coupled to ground through a capacitor. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits. OMCK 22 System Clock (Input) - When the OMCK System Clock Mode is enabled using the SWCLK bit in the Control 1 register, the clock signal input on this pin is automatically output through RMCK on PLL unlock. OMCK serves as the reference signal for OMCK/RMCK ratio expressed in register 18h. “OMCK System Clock Mode” section on page 28 RMCK 21 Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency defaults to 256x the sample rate (F s) and may be set to 128x through the RMCKF bit in the Control 1 register (01h). RMCK may also be set to high impedance by the RXD bit in the Control 4 register (04h). OSCLK 24 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin OLRCK 25 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs) SDOUT 23 Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled high to VL through a 47 kΩ resistor to place the part in Software Mode. SDA / CDOUT 14 Serial Control Data I/O (I²C) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the out- put data from the control port interface on the CS8416. See the “Control Port Description” section on page 33. SCL / CCLK 13 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8416. CCLK is an open drain output and requires an external pull-up resistor to VL. See the “Control Port Description” section on page 33. AD0 / CS 11 Address Bit 0 (I²C) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8416 into SPI Control Port Mode. With no falling edge, the CS8416 defaults to I²C Mode. In I²C Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8416. See the “Control Port Description” section on page 33. AD1 / CDIN 12 Address Bit 1 (I²C) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In SPI Mode, CDIN is the input data line for the control port interface. See the “Control Port Description” section on page 33. AD2 / GPO2 15 General Purpose Output 2 (Output) - If using the I²C control port, this pin must be pulled high or low through a 47 kΩ resistor. See the “Control Port Description” section on page 33 and “General Purpose Outputs” on page 29 for GPO functions. GPO1 16 General Purpose Output 1 (Output) - See “General Purpose Outputs” on page 29 for GPO functions. GPO0 17 General Purpose Output 0 (Output) - See “General Purpose Outputs” on page 29 for GPO functions. THERMAL PAD - Thermal Pad - Thermal relief pad for optimized heat dissipation. Pin Name Pin # Pin Description

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1. PIN DESCRIPTION - HARDWARE MODE

3.1 TSSOP Pin Description

Pin Name Pin # Pin Description VA 6 Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock VD 23 Digital Power (Input) – Digital core power supply. Nominally +3.3 V VL 21 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V AGND 7 Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip. DGND 22 Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con- nected to a common ground area under the chip. RST Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. FILT 8 PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground. For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on page 53 for more information on the PLL and the external components. RXP0 RXP1 RXP2 RXP3 Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits. RXN 5 Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single- ended operation this should be AC coupled to ground through a capacitor. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits. RXP3 OLRCK RXP2 OSCLK RXP1 SDOUT RXP0 OMCK RXN RMCK VA VD AGND DGND FILT VL RST TX RXSEL1 C RXSEL0 U TXSEL1 RCBL TXSEL0 96KHZ NV / RERR AUDIO 82 1 12 17 14 15 Top-Down View 28-pin SOIC/TSSOP Package

System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on OMCK after reset. When enabled, the clock signal input on this pin is automatically output through RMCK on PLL unlock. See “OMCK System Clock Mode” on page 28. RMCK 24 Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency is 256x the sample rate (Fs) when the U pin is pulled down by a 47 kΩ resistor to DGND. Frequency is 128x the sample rate (Fs) when the U pin is pulled up by a 47 kΩ resistor to VL. OSCLK 27 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin OLRCK 28 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs) SDOUT 26 Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to DGND through a 47 kΩ resistor to place the part in Hardware Mode. RXSEL1 RXSEL0 11 Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input. TXSEL1 TXSEL0 TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out- put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs. TX 20 S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs. NV/RERR 14 Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected by a 47 kΩ resistor to DGND. RERR is selected by a 47 kΩ resistor to VL. AUDIO 15 Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See “Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at reset. 96KHZ 16 96 kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the Emphasis Audio Match feature at reset. RCBL 17 Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set the serial audio port to master or slave at reset. C1 9 Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset. U1 8 User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the frequency of RMCK to either 256*Fs or 128*Fs at reset. Pin Name Pin # Pin Description

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3.2 QFN Pin Description

Pin Name Pin # Pin Description VA 3 Analog Power (Input) - Analog power supply. Nominally +3.3 V. This supply should have as little noise as possible since noise on this pin will directly affect the jitter performance of the recovered clock VD 20 Digital Power (Input) – Digital core power supply. Nominally +3.3 V VL 18 Logic Power (Input) – Input/Output power supply. Nominally +3.3 V or +5.0 V AGND 4 Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be connected to a common ground area under the chip. DGND 19 Digital & I/O Ground (Input) - Ground for the I/O and core logic. AGND and DGND should be con- nected to a common ground area under the chip. RST Reset (Input) - When RST is low, the CS8416 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. FILT 5 PLL Loop Filter (Output) - An RC network should be connected between this pin and analog ground. For minimum PLL jitter, return the ground end of the filter network directly to AGND. See “PLL Filter” on page 53 for more information on the PLL and the external components. RXP0 RXP1 RXP2 RXP3 Positive AES3/SPDIF Input (Input) - Single-ended or differential receiver inputs carrying AES3 or S/PDIF encoded digital data. The RXP[3:0] inputs comprise the 4:2 S/PDIF Input Multiplexer. The select line control is accessed using the RXPSEL[1:0] pins. Unused multiplexer inputs should be left floating or tied to AGND. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits. 10 11 12 13 14 22232425262728 Top-Down View 28-pin QFN Package Thermal Pad RXP1 RXP2 RXP3 OLRCK OSCLK SDOUT OMCK RXSEL0 TXSEL1 TXSEL0 NV / RERR AUDIO 96KHZ RCBL RXP0 RXN VA AGND FILT RST RXSEL1 RMCK VD DGND VL TX C U

Negative AES3/SPDIF Input (Input) - Single-ended or differential receiver input carrying AES3 or S/PDIF encoded digital data. Used along with RXP[3:0] to form an AES3 differential input. In single- ended operation this should be AC coupled to ground through a capacitor. See “External AES3/SPDIF/IEC60958 Receiver Components” on page 49 for recommended input circuits. OMCK 22 System Clock (Input) - OMCK System Clock Mode is enabled by a transition (rising edge active) on OMCK after reset. When enabled, the clock signal input on this pin is automatically output through RMCK on PLL unlock. See “OMCK System Clock Mode” on page 28. RMCK 21 Input Section Recovered Master Clock (Output) - Input section recovered master clock output from the PLL. Frequency is 256x the sample rate (Fs) when the U pin is pulled down by a 47 kΩ resistor to DGND. Frequency is 128x the sample rate (Fs) when the U pin is pulled up by a 47 kΩ resistor to VL. OSCLK 24 Serial Audio Output Bit Clock (Input/Output) - Serial bit clock for audio data on the SDOUT pin OLRCK 25 Serial Audio Output Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDOUT pin. Frequency will be the output sample rate (Fs) SDOUT 23 Serial Audio Output Data (Output) - Audio data serial output pin. This pin must be pulled low to DGND through a 47 kΩ resistor to place the part in Hardware Mode. RXSEL1 RXSEL0 8 Receiver MUX Selector (Input) - Used to select which pin, RXP[3:0], is used for the receiver input. TXSEL1 TXSEL0 TX Pin MUX SELECTION (Input) - Used to select which pin, RXP[3:0], is passed to the TX pin out- put. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs. TX 17 S/PDIF MUX Passthrough (Output) - Single-ended signal is resolved to full-rail, but is not de-jittered before it is output. Output is set by TXSEL[1:0]. This pin is also used to select the type of phase detector (PDUR) at reset. If TX passthrough is not used, the user should set it to output one of the unused receiver inputs. NV/RERR 11 Non-Validity Receiver Error/Receiver Error (Output) - Receiver error indicator. NVERR is selected by a 47 kΩ resistor to DGND. RERR is selected by a 47 kΩ resistor to VL. AUDIO 12 Audio Channel Status Bit (Output) – When low, a valid linear PCM audio stream is indicated. See “Non-Audio Detection” on page 31. This pin is also used to select the serial port format (SFSEL1) at reset. 96KHZ 13 96 kHz Sample Rate Detect (Output) - If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. Also used to set the Emphasis Audio Match feature at reset. RCBL 14 Receiver Channel Status Block (Output) -Indicates the beginning of a received channel status block. RCBL goes high two frames after the reception of a Z preamble, remains high for 16 frames and then returns low for the remainder of the block. RCBL changes on rising edges of RMCK. Also used to set the serial audio port to master or slave at reset. C1 6 Channel Status Data (Output) - Outputs channel status data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the serial port format (SFSEL0) at reset. U1 5 User Data (Output) - Outputs user data from the AES3 receiver, clocked by the rising and falling edges of OLRCK. Also used to select the frequency of RMCK to either 256*F s or 128*Fs at reset. THERMAL PAD - Thermal Pad - Thermal relief pad for optimized heat dissipation. Pin Name Pin # Pin Description

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1. TYPICAL CONNECTION DIAGRAMS

Figure 5. Typical Connection Diagram - Software Mode pling capacitors between VA and AGND. for typical input configurations and recommended input circuits.

Figure 6. Typical Connection Diagram - Hardware Mode

• These pins must be pulled high to VL or low to DGND through a 47 kΩ resistor.

pling capacitors between VA and AGND. for typical input configurations and recommended input circuits.

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1. APPLICATIONS

5.1 Reset, Power-Down and Start-Up

When RST is low, the CS8416 enters a low power mode and all internal states are reset, including the con- trol port and registers, and the output s are muted. In Software Mode, when RST is high, the control port becomes operational, and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state and begin operation. After the PLL has settled, the serial audio outputs will be enabled. Some options within the CS8416 are controlled by a st art-up mechanism. During the reset state, some of the pins are reconfigured internally to be inputs. Immediately upon exiting the reset state, the level of these pins is sensed. The pins are then switched to be outputs. This mechanism allows output pins to be used to set alternative modes in the CS8416 by connecting a 47 k Ω resistor to between the pin and either VL (HI) or DGND (LO). For each mode, every start-up option select pin MUST have an external pull-up or pull-down resistor as there are no internal pull-up or pull-down resistors for these startup conditions (except for TX, which has an internal pull-down). In Software Mode, the only start-up option pins are GPO2, which are used to set a chip address bit for the control port in I²C Mode, and SDOUT, which selects between Hardware and Software Modes. The Hardware Mode uses many start-up options, which are detailed in Section 15.2 “Hard- ware Mode Function Selection” on page 46.

5.2 ID Code and Revision Code

The CS8416 has a register that contains a 4-bit code to indicate that the addressed device is a CS8416. This is useful when other CS84XX family members are resident in the same system, allowing common soft- ware modules. The CS8416 4-bit revision code is also available. This allows the software driver for the CS8416 to identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future revisions, it is strongly recommend that the revision code is read into a variable area within the microcon- troller, and used wherever appropriate as revision details become known.

5.3 Power Supply, Gr ounding, and PCB Layout

For most applications, the CS8416 can be operated fr om a single +3.3 V supply, following normal supply decoupling practices (See Figures 5 and 6). For applications where the recovered input clock, output on the RMCK pin, is required to be low jitter, then use a se parate, quiet, analog +3.3 V supply for VA, decoupled to AGND. Make certain that no digital traces are routed near VA, AGND, or FILT as noise may couple and degrade performance. These pins should be well isolated from switching signals and other noise sources. VL sets the level for the digital inputs and outputs, as well as the AES/SPDIF receiver inputs. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as the CS8416 to minimize inductance effects, and all decoupling capacitors should be as close to the CS8416 as possible. See “PLL Filter” on page 53 for layout recommendations for the PLL.

1. GENERAL DESCRIPTION The CS8416 is a monolithic CMOS device that receives and decodes audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8416 provides an 8:2 multiplexer to select between eight inputs for decoding and to allow an input signal to be routed to an output of the CS8416. Input data can be ei ther differential or single-ended. A low jitter clock is re- covered from the incoming data using a PLL. The decoded audio data is output through a configurable, 3-wire serial audio output port. The channel status and Q-channel subc ode portion of the user data are assembled in registers and may be accessed through an SPI or I²C port. Three General Purpose Output (GPO) pins are provided to allow a variety of signals to be accessed under software control. In Hardware Mode, dedicated pins are used to select audio stream inputs for decoding and transmission to a dedicated TX pin. Hardware Mode also provides channel status and user data output pins. Figures 5 and 6 show the power supply and external connections to the CS8416 when configured for Software Mode and Hardware Mode. Please note that all I/O pins, including RXN and RXP[7:0], operate at the VL voltage.

6.1 AES3 and S/PDIF Standards Documents

This document assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3, IEC60958, and IEC61937 specifications on hand for easy reference. The latest AES3 standard is available from the Audio Engi neering Society or ANSI at www.aes.org or at www.ansi.org. Obtain a copy of the latest IEC60958/61937 st andard from ANSI or from the International Electrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from the Japanese Electronics Bureau. Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. The paper An Understanding and Implemen tation of the SCMS Serial C opy Management System for Digital Audio Transmission, by Clifton Sanchez, is an excellent tuto rial on SCMS. It is available from the AES as reprint 3518. 7. SERIAL AUDIO OUTPUT PORT A 3-wire serial audio output port is provided. The port can be adjusted to suit the attached device by setting the con- trol registers. The following parameters are adjustable: mast er or slave, serial clock frequency, audio data resolu- tion, left- or right-justification of the data relative to left/right clock, optional one-bit cell delay of the first data bit, the polarity of the bit clock, and the polarity of the left/right clock. By setting the appropriate control bits, many formats are possible. Figure 7 shows a selection of common output formats, along with the control bit settings. A special AES3 direct out- put format is included, which allows the serial output port access to the V, U, and C bits embedded in the serial audio data stream. When using the part in AES3 direct-output format, the de-emphasis filter must be off (see Section 14.4 on page 38). The P bit, which would normally be a parity bit, is replaced by a Z bit, which is used to indicate the start of each block. The received channel status block start signal is also available as the RCBL pin in Hardware Mode and through a GPO pin in Software Mode. In master mode, the left/right clock (OLRCK) and the serial bit clock (OSCLK) are outputs, derived from the recov- ered RMCK clock. In slave mode, OLRCK and OSCLK are inputs. OLRCK is normally synchronous to the appropri- ate master clock, but OSCLK can be asynchronous and discontinuous if required. By appropriate phasing of OLRCK and control of the serial clocks, multiple CS8416’s can share one serial port. OLRCK should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to

24 DS578F3

CS8416 allows immediate mute of the serial audio output port audio data by the MUTESAO bit of Control Register 1. Serial Audio Interface: A Tutorial”, available at www.cirrus.com. Figure 7. Serial Audio Output Example Formats

7.1 Slip/Repeat Behavior

dicate when repeated or dropped samples occur. Refer to Figure 8 for the AES3 data format diagram. input AES3 data (Z/X) preamble frequency, the data will be slipped or repeated at the output of the CS8416.

1. If during that time, the internal data buffer was not updated, a slip has occurred. Data from the previous

the register is read. It will then be reset until another slip/repeat condition occurs.

1. If during that time the internal data buffer did not update between two positive or negative edges (de-
2. If during that time, it did see a positive edge on OLRCK (or negative edge if the SOLRPOL is set to 1)

until either the register is read or a slip/repeat condition occurs. will be equal to the difference in frequency between the input AES data and the slave serial output LRCK. Figure 8. AES3 Data Format

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7.2 AES11 Behavior

audio data will be 3 frames. data through the part will be a multiple of 1/Fs plus the delay between OLRCK and the preambles. Both of these conditions are within the tolerance range set forth in the AES11 standard. Table 1. Typical Delays by Frequency Values

the input structure of the receiver.

8.1.1 General

ommended dielectrics for the AC coupling capacitors are C0G or X7R. below DGND may degrade performance or damage the part.

8.1.2 Software Mode

multiplexer defaults to RXP0. Figure 9. Receiver Input Structure If RXP[7:0] is selected by either the receiver MUX or the TX passthrough MUX, N=1. If RXP[7:0] is selected by both the receiver MUX and the TX passthrough MUX, N=2. If RXP[7:0] is not selected at all, N=0 (i.e. high impedance).

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ended signal is resolved to full-rail, but is not de-jittered before it is output.

8.1.3 Hardware Mode

In Hardware Mode the input to the decoder is selected by dedicated pins, RXSEL[1:0]. The pass through signal is selected by dedicated pins, TXSEL[1:0] for output on the dedicated TX pin. This single-ended signal is resolved to full-rail, but is not de-jittered before it is output. are selected by RXSEL[1:0] and TXSEL[1:0] respectively.

8.2 OMCK System Clock Mode

output on RMCK by using the FSWCLK bit in the Control0 register. cy. Table 2 shows an example of output clocks based on clock switching being enabled or disabled.

8.3 Clock Recover y and PLL Filter

capacitors and one resistor that comprise the PLL filter. OSLCK = 64*Fs, and FSWCLK (Software Mode only) = ‘0’. Table 2. Clock Switching Output Clock Rates

1. Frequency = 25 MHz Max, duty cycle not guaranteed, target duty cycle = 50% @ FS = 48 kHz.

EMPH 0001 State of EMPH bit in the incoming data stream. 96KHZ 1000 If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate. VLRCK 1010 Virtual LRCK. Can be used to frame the C and U output data. Table 3. GPO Pin Configurations

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10.ERROR AND STATUS REPORTING

10.1 General

While decoding the incoming bi-phase encoded data stream, the CS8416 has the ability to identify various error conditions.

10.1.1 Software Mode

Software Mode allows the most flex ibility in reading errors. When unma sked, bits in the Receiver Error register (0Ch) indicate the following errors: 1. QCRC – CRC error in Q subcode data. 2. CCRC – CRC error in channel status data. 3. UNLOCK – PLL is not locked to incoming data stream. 4. V – Data Validity bit is set. 5. CONF – The logical OR of UNLOCK and BIP. The input data stream may be near error condition due to jitter degradation. 6. BIP – Biphase encoding error. 7. PAR – Parity error in incoming data. The error bits are “sticky,” meaning that they are set on the first occu rrence of the associated error and will remain set until the user reads the register through the control port. This enables the register to log all unmasked errors that occurred since the last time the register was read. As a result of the bits “stickiness,” it is necessary to perform two reads on these registers to see if the error condition still exists. The Receiver Error Mask register (06h) allows masking of individual errors. The bits in this register default to 00h and serve as masks for the corresponding bits of the Receiver Error register. If a mask bit is set to 1, the error is unmasked, which implies the following: its occurrence will be reported in the receiver error register, induce a pulse on RERR, invoke the occurrence of a RERR interrupt, and affect the current audio sample according to the status of the HOLD bits. The exceptions are the QCRC and CCRC errors, which do not affect the current audio sample, even if unmasked. The HOLD bits allow a choice of:

• Holding the previous sample
• Replacing the current sample with zero (mute) OR
• Not changing the current audio sample

10.1.2 Hardware Mode

In Hardware Mode, the user may only choose between Non-Validity Receiver Error (NVERR) or Receiver Error (RERR) by pulling the NV/RERR pin low or high, respectively. The pull-up/pull-down condition will be sensed on start-up, and the appropriate error reporting will be set. RERR – The previous audio sample is held and passed to the serial audio output port if the validity bit is high, or a parity, bi-phase, confidence or PLL lock error occurs during the current sample. NVERR – The previous audio sample is held and passed to the serial audio output port if a parity, bi- phase, confidence or PLL lock error occurs during the current sample.

10.2 Non-Audio Detection

An AES3 data stream may be used to convey non-audio data, thus it is important to know whether the in- coming AES3 data stream is digital audio or not. This information is typically conveyed in channel status bit 1, which is extracted automatically by the CS8416. However, certain non-audio sources, such as AC-3™ or MPEG encoders, may not adhere to this convention, and the bit may not be properly set. The CS8416 AES3 receiver can detect such non-audio data through the use of an autodetect module. The autodetect module is similar to autodetect software used in Cirrus Logic DSPs. If the AES3 stream contains sync codes in the proper format for IEC61937 or DTS ® data transmission, an internal AUTODETECT signal will be asserted. If the sync codes no longer ap pear after a certain amount of time, autodetection will time-out and AUTODETECT will be de-asserted until another format is detected. The AUDIO signal is the logical OR of AUTODETECT an d the received channel status bit 1 (as decoded according to the CHS bit in the Control1 register). In Hardware Mode, AUDIO is output on pin 15. In Software Mode, AUDIO is available through the GPO pins. If non-audio data is detected, the data is still processed exactly as if it were normal audio. The exception is the use of de-emphasis auto-select feature which will bypass the de-emphasis filter if the input stream is detected to be non-audio. It is up to the user to mute the outputs as required.

10.2.1 Format Detection

In Software Mode, the CS8416 can automatically dete ct various serial audio input formats. The Format Detect Status regi ster (0Bh) is used to indica te a detected format . The register will indicate if uncom- pressed PCM data, IEC61937 data, DTS_LD data, DTS_CD data, or digital silence was detected. Addi- tionally, the IEC61937 Pc/Pd burst preambles are av ailable in registers 23h-26h. See the register descriptions for more information.

10.3 Interrupts

The CS8416 has a comprehe nsive interrupt capability. The INT sig nal, available in Software Mode, indi- cates when an interrupt condition has occurred and may be output on one of the GPOs. It can also be set through bits INT[1:0] in the Control1 register (01h) to be active low, active high or active low with no active pull-up transistor. This last mode is used for active low, wired-OR hook- ups, with multiple peripherals con- nected to the microcontroller interrupt input pin. Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. Each source may be masked off thro ugh mask register bits. In addition, each source ma y be set to risi ng edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensitive modes within the mi- crocontroller, many different configurations are possible, depending on the needs of the equipment design- er. Refer to the register descriptions for the Interrupt Mask (07h), Interrupt Mode MSB (08h), Interrupt Mode LSB (09h), and Interrupt 1 Status (0Dh) registers

32 DS578F3

“Channel Status Buffer Management” on page 51 describes Channel Status and User data control.

11.1 Software Mode

coded in the received AES3/SPDIF stream. status data. Registers 1Eh - 22h contain the B channel status data. GPO pins. Figure 10 illustrates timing of the C and U data and their related signals. bits can be stripped from the SDOUT signal by external control logic such as a DSP or microcontroller. decoding of a new Q-channel block, which may be read through the control port.

11.2 Hardware Mode

lustrates timing of the C and U data and their related signals. “Hardware Mode Equivalent Register Settings” on page 47 to configure these pins.. Figure 10. C/U Data Outputs – RCBL goes high 2 frames after receipt of a Z preamble and is high for 16 frames.

12.1 SPI Mode

to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. be placed into the register designated by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 kΩ resistor, if desired. cessive registers will appear consecutively. Figure 11. Control Port Timing in SPI Mode

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12.2 I²C Mode

from successive registers will appear consecutively. Each byte is separated by an acknowledge bit (ACK). microcontroller after each transmitted byte. Figure 12. Control Port Timing, I²C Slave Mode Write Figure 13. Control Port Timing, I²C Slave Mode Read

13.CONTROL PORT REGISTER QUICK REFERENCE Addr (HEX) R / W F u n c t i o n 76543210

00 R/W Control0 0 FSWCLK 0 0 PDUR TRUNC Reserved Reserved

01 R/W Control1 SWCLK MUTSAO INT1 INT0 HOLD1 HOLD0 RMCKF CHS

02 R/W Control2 DETCI EMPH_CN

EMPH_CN TL1 EMPH_CN TL0 GPO0SEL3 GPO0SEL2 GPO0SEL1 GPO0SEL0

03 R/W Control3 GPO1SEL3 GPO1SEL2 GPO1SEL1 GPO 1SEL0 GPO2SEL3 GPO2SEL2 GPO2SEL1 GPO2SEL0

04 R/W Control4 RUN RXD RXSEL2 RXSEL1 RXSEL0 TXSEL2 TXSEL1 TXSEL0

05 R/W Serial Audio Data

SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL

06 R/W Receiver Error

0 QCRCM CCRCM UNLOCKM VM CONFM BIPM PARM

07 R/W Interrupt Mask 0 PCCHM OSLIPM DETCM CCHM RERRM QCHM FCHM

08 R/W Interrupt Mode

0 PCCH1 OSLIP1 DETC1 CCH1 RERR1 QCH1 FCH1

09 R/W Interrupt Mode

0 PCCH0 OSLIP0 DETC0 CCH0 RERR0 QCH0 FCH0

AUX3 AUX2 AUX1 AUX0 PRO COPY ORIG EMPH 0B R Audio Format Detect

0 PCM IEC61937 DTS_LD DTS_CD Reserved DGTL_SIL 96KHZ

0C R Receiver Error 0 QCRC CCRC UNLOCK V CONF BIP PAR 0D R Interrupt Status 0 PCCH OSLIP DETC CCH RERR QCH FCH 0E R Q-Channel Subcode [0:7] CONTROL CONTROL CONTROL CONTROL ADDRESS ADDRESS ADDRESS ADDRESS 0F R Q-Channel Subcode [8:15] TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK

10 R Q-Channel

Subcode [16:23] INDEX INDEX INDEX INDEX INDEX INDEX INDEX INDEX

11 R Q-Channel

Subcode [24:31] MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE MINUTE

12 R Q-Channel

Subcode [32:39] SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND

13 R Q-Channel

Subcode [40:47] FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME

14 R Q-Channel

Subcode [48:55] ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO

15 R Q-Channel

Subcode [56:63] ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE

16 R [Q-Channel

Subcode 64:71] ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND

17 R Q-Channel

Subcode [72:79] ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME

18 R OMCK_RMCK

ORR7 ORR6 ORR5 ORR4 ORR3 ORR2 ORR1 ORR0

19 R Channel A Status AC0[7] AC0[6] AC0[5] AC0[4] AC0[3] AC0[2] AC0[1] AC0[0]

1A R Channel A Status AC1[7] AC1[6] AC1[5] AC1[4] AC1[3] AC1[2] AC1[1] AC1[0] 1B R Channel A Status AC2[7] AC2[6] AC2[5] AC2[4] AC2[3] AC2[2] AC2[1] AC2[0] 1C R Channel A Status AC3[7] AC3[6] AC3[5] AC3[4] AC3[3] AC3[2] AC3[1] AC3[0] 1D R Channel A Status AC4[7] AC4[6] AC4[5] AC4[4] AC4[3] AC4[2] AC4[1] AC4[0]

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1. CONTROL PORT REGISTER DESCRIPTIONS

14.1 Memory Address Pointer (MAP)

MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write. Default = ‘0000000’

14.2 Control0 (00h)

FSWCLK – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK (Control1 register bit 6) bit functionality or PLL lock. Default = ‘0’ 0 – Clock signal on OMCK is output on RMCK according to the SWCLK bit functionality. 1 – Forces the clock signal on OMCK to be output on RMCK regardless of the SWCLK bit functionality. PDUR – Changes the type of phase detector used to lock to the active RXP[7:0] input. This bit should only be set if the sample rate range is between 32 kHz and 108 kHz. If the sample rate is outside of this range and the PDUR bit is set, loss of lock may occur. Default = ‘0’ 0 – Normal Update Rate Phase Detector - Recovered master clock (RMCK) will have low wide-band jitter, but increased in-band jitter. 1E R Channel B Status BC0[7] BC0[6] BC0[5] BC0[4] BC0[3] BC0[2] BC0[1] BC0[0] 1F R Channel B Status BC1[7] BC1[6] BC1[5] BC1[4] BC1[3] BC1[2] BC1[1] BC1[0]

20 R Channel B Status BC2[7] BC2[6] BC2[5] BC2[4] BC2[3] BC2[2] BC2[1] BC2[0]

21 R Channel B Status BC3[7] BC3[6] BC3[5] BC3[4] BC3[3] BC3[2] BC3[1] BC3[0]

22 R Channel B Status BC4[7] BC4[6] BC4[5] BC4[4] BC4[3] BC4[2] BC4[1] BC4[0]

23 R Burst Preamble PC

PC0[7] PC0[6] PC0[5] PC0[4] PC0[3] PC0[2] PC0[1] PC0[0]

24 R Burst Preamble PC

PC1[7] PC1[6] PC1[5] PC1[4] PC1[3] PC1[2] PC1[1] PC1[0]

25 R Burst Preamble PD

PD0[7] PD0[6] PD0[5] PD0[4] PD0[3] PD0[2] PD0[1] PD0[0]

26 R Burst Preamble PD

PD1[7] PD1[6] PD1[5] PD1[4] PD1[3] PD1[2] PD1[1] PD1[0] 7F R ID & Version ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0 76543210

0 M A P 6M A P 5M A P 4M A P 3M A P 2M A P 1M A P 0

0 FSWCLK 0 0 PDUR TRUNC Reserved Reserved

(HEX) R / W F u n c t i o n 76543210

1 – Higher Update Rate Phase Detector - Recovered master clock (RMCK) will have low in-band jitter, but increased wide-band jitter. Use this setting for the best performance when the output is connected to a delta- sigma digital-to-analog converter (DAC). TRUNC – Determines if the audio word length is set according to the incoming channel status data as de- coded by the AUX[3:0] bits. The resulting word length in bits is 24 minus AUX[3:0]. Default = ‘0’ 0 – Incoming data is not truncated. 1 – Incoming data is truncated according to the length specified in the channel status data. Truncation occurs before the de-emphasis filter. TRUNC has no effect on output data if de-emphasis filter is not used. Reserved – These bits may change state depending on the input audio data.

14.3 Control1 (01h)

SWCLK - Lets OMCK determine RMCK, OSCLK, OLRCK when PLL loses lock Default = ‘0’ 0 - Disable automatic clock switching. RMCK runs at the VCO frequency (~750 kHz) on PLL Unlock. 1 - Enable automatic clock switching on PLL unlock. OMCK clock input is automatically output on RMCK on PLL Unlock. MUTESAO - Mute control for the serial audio output port Default = ‘0’ 0 - SDOUT not muted. 1 – SDOUT muted (set to all zeros). INT[1:0] - Interrupt output pin (INT) control Default = ‘00’ 00 - Active high; high output indicates interrupt condition has occurred. 01 - Active low, low output indicates an interrupt condition has occurred. 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. Thus it is not recommended to multiplex INT onto GPO2 in I²C Control Port Mode since an external resistor is required on GPO2 to spec- ify the AD2 bit of the chip address. 11 – Reserved. HOLD[1:0] – Determine how received audio sample is affected when a receive error occurs Default = ‘00’ 00 – hold last audio sample. 01 – replace the current audio sample with all zeros (mute). 10- do not change the received audio sample. 11 - reserved 76543210 SWCLK MUTESAO INT1 INT0 HOLD1 HOLD0 RMCKF CHS

38 DS578F3

RMCKF – Recovered Master Clock Frequency Default = ‘0’ 0 – RMCK output frequency is 256*FS. 1 – RMCK output frequency is 128*FS. CHS – Sets which channel's C data is decoded in the Receiver Channel Status register (0Ah). Default = ‘0’ 0 – A channel. 1 – B channel. If CHS = 0 and TRUNC = 1, both channels' audio data will be truncated by the AUX[3:0] bits indicated in the channel A Channel Status data. If CHS = 1 and TRUNC = 1, both channels' audio data will be truncated by the AUX[3:0] bits indicated in the channel B Channel Status data. This will occur even if the AUX[3:0] bits indicated in the channel A Channel Status data are not equal to the AUX[3:0] bits indicated in the channel B Channel Status data.

14.4 Control2 (02h)

DETCI – D to E status transfer inhibit Default = ‘0’ 0 – Allow update. 1 – Inhibit update. EMPH_CNTL[2:0] – De-emphasis filter control. See Figure 14 for De-emphasis filter response. Default = ‘000’ 000 – If the serial audio output port is using the AES3 direct-output format, the de-emphasis filter must re- main off. 001 – 32 kHz setting. 010 – 44.1 kHz setting. 011 – 48 kHz setting. 100 – 50 μs/15 μs de-emphasis filter auto-select on. Coefficients (32, 44.1 or 48 kHz or no de-emphasis fil- ter at all) match the pre-emphasis and sample frequency indicators in the channel status bits of Channel A. Thus it is impossible to have de-emphasis applied to one channel but not the other. The de-emphasis filter is turned off if the audio data is detected to be non-audio data. GPO0SEL[3:0] – GPO0 Source select. See “General Purpose Outputs” on page 29. Default = ‘0000’ 76543210 DETCI EMPH_CNTL2 EMPH_CNTL1 EMPH_CNTL0 GPO0SEL3 GPO0SEL2 G PO0SEL1 GPO0SEL0

14.5 Control3 (03h)

GPO1SEL[3:0] – GPO1 Source select. See “General Purpose Outputs” on page 29. GPO2SEL[3:0] – GPO2 Source select. See “General Purpose Outputs” on page 29.

14.6 Control4 (04h)

operational, allowing registers to be read or changed. Power consumption is low. input clocks should be stable in frequency and phase when RUN is set to 1. 0 -RMCK is an output, Clock is derived from input frame rate. 1 – RMCK becomes high impedance. The output of OSCLK, OLRCK, and SDOUT are indeterminate. Figure 14. De-Emphasis Filter Response

40 DS578F3

TX_SEL[2:0] – Selects RXP0 to RXP7 as the input for GPO TX source Default =’001’ 000 – RXP0 001 – RXP1, etc

14.7 Serial Audio Data Format (05h)

SOMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio output port is in slave mode. OSCLK and OLRCK are inputs. 1 - Serial audio output port is in master mode. OSCLK and OLRCK are outputs. SOSF - OSCLK frequency (for master mode) Default = ‘0’ 0 - OSCLK output frequency is 64*Fs. 1 - OSCLK output frequency is 128*Fs. SORES[1:0] - Resolution of the output data on SDOUT Default = ‘00’ 00 - 24-bit resolution. 01 - 20-bit resolution. 10 - 16-bit resolution. 11 - Direct copy of the received NRZ data from the AES3 receiver including C, U, and V bits. The time slot occupied by the Z bit is used to indicate the location of the block start. This setting forces the SOJUST bit to be “0”. When using this setting, the de-emphasis filter must be off. SOJUST - Justification of SDOUT data relative to OLRCK Default = ‘0’ 0 - Left-Justified. 1 - Right-Justified (master mode only and SORES ≠11). SODEL - Delay of SDOUT data relative to OLRCK, for Left-Justified data formats (This control is only valid in Left-Justified Mode) Default = ‘0’ 0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge. 1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge. SOSPOL - OSCLK clock polarity Default = ‘0’ 0 - SDOUT is sampled on rising edges of OSCLK. 1 - SDOUT is sampled on falling edges of OSCLK. 76543210 SOMS SOSF SORES1 SORES0 SOJUST SODEL SOSPOL SOLRPOL

SOLRPOL - OLRCK clock polarity Default = ‘0’ 0 - SDOUT data is valid for the left channel when OLRCK is high. 1 - SDOUT data is valid for the right channel when OLRCK is high.

14.8 Receiver Error Mask (06h)

The bits in this register serve as masks for the corresponding bits of the Receiver Error Register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will appear in the receiver error register, will affect RERR, will affect the RERR interrupt, and will affect the curr ent audio sample according to the status of the HOLD bit. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not appear in the receiver error register, will not affect the RERR pin, will not affect the RERR interrupt, and will not affect the current audio sample. The CCRC and QCRC bits behave differently from the other bits: they do not affect the current audio sample even when unmasked. This register defaults to 00h.

14.9 Interrupt Mask (07h)

The bits of this register serve as a mask for the Interrupt Status register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the internal INT signal or the status reg- ister. The bit positions align with the corresponding bits in Interrupt Status register. This register defaults to 00h. The INT signal may be selected to output on the GPO pins. See “General Purpose Outputs” on page 29.

14.10 Interrupt Mode MSB (08h) and Interrupt Mode LSB(09h)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Status regi ster function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These registers default to 00h. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved 76543210

0 PCCHM OSLIPM DETCM CCHM RERRM QCHM FCHM

42 DS578F3

14.11 Receiver Channel Status (0Ah)

The bits in this register can be associated with either channel A or B of the received data. The desired chan- nel is selected with the CHS bit of the Control1 register. AUX3:0 - Incoming auxiliary data field width, as indicated by the incoming channel status bits, decoded ac- cording to IEC60958 and AES3. 0000 - Auxiliary data is not present. 0001 - Auxiliary data is 1 bit long. 0010 - Auxiliary data is 2 bits long. 0011 - Auxiliary data is 3 bits long. 0100 - Auxiliary data is 4 bits long. 0101 - Auxiliary data is 5 bits long. 0110 - Auxiliary data is 6 bits long. 0111 - Auxiliary data is 7 bits long. 1000 - Auxiliary data is 8 bits long. 1001 - 1111 Reserved PRO - Channel status block format indicator 0 - Received channel status block is in the consumer format. 1 - Received channel status block is in the professional format. COPY - SCMS copyright indicator 0 - Copyright asserted. 1 - Copyright not asserted. If the category code is set to General in the incoming AES3 stream, copyright will always be indicated by COPY, even when the stream indicates no copyright. ORIG - SCMS generation indicator, decoded from the category code and the L bit. 0 - Received data is 1st generation or higher. 1 - Received data is original. Note: COPY and ORIG will both be set to 1 if incoming data is flagged as professional or if the receiver is not in use. EMPH – Indicates whether the input audio data has been pre-emphasized. Also indicates turning on of the de-emphasis filter during de-emphasis auto-select mode. 0 – 50 μs/15 μs pre-emphasis indicated. 1 – 50 μs/15 μs pre-emphasis not indicated.

14.12 Format Detect Status (0Bh)

Note: PCM, DTS_LD, DTS_CD and IEC61937 are mutually exclusive. A ‘1’ indicated the condition was detected. PCM – Uncompressed PCM data was detected. IEC61937 – IEC61937 data was detected. DTS_LD – DTS_LD data was detected. 76543210 AUX3 AUX2 AUX1 AUX0 PRO COPY ORIG EMPH 76543210

DTS_CD – DTS_CD data was detected. Reserved – This bit may change state depending on the input audio data. DGTL_SIL – Digital Silence was detected: at least 2047 consecutive constant samples of the same 24-bit audio data on both channels. 96KHZ – If the input sample rate is ≤ 48 kHz, outputs a “0”. Outputs a “1” if the sample rate is ≥ 88.1 kHz. Otherwise the output is indeterminate.

14.13 Receiver Error (0Ch)

This register contains the AES3 receiver and PLL status bits. Unmasked bits will go high on occurrence of the error, and will stay high until the register is read. Reading the register resets all bits to 0, unless the error source is still true. Bits that are masked off in the receiver error mask register will always be 0 in this register. QCRC - Q-subcode data CRC error indicator. Updated on Q-subcode block boundaries 0 - No error. 1 - Error. CCRC - Channel Status Block Cyclic Redundancy Check bit. Updated on CS block boundaries, valid in Pro mode 0 - No error. 1 - Error. UNLOCK - PLL lock status bit. Updated on CS block boundaries. 0 - PLL locked. 1 - PLL out of lock. V - Received AES3 Validity bit status. Updated on sub-frame boundaries. 0 - Data is valid and is normally linear coded PCM audio. 1 - Data is invalid, or may be valid compressed audio. CONF - Confidence bit. Updated on sub-frame boundaries. 0 - No error. 1 - Confidence error. The logical OR of UNLOCK and BIP. The input data stream may be near error condi- tion due to jitter degradation. BIP - Bi-phase error bit. Updated on sub-frame boundaries. 0 - No error. 1 - Bi-phase error. This indicates an error in the received bi-phase coding. PAR - Parity bit. Updated on sub-frame boundaries. 0 - No error. 1 - Parity error. 76543210

0 QCRC CCRC UNLOCK V CONF BIP PAR

44 DS578F3

14.14 Interrupt 1 Status (0Dh)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A “0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. PCCH – PC burst preamble change. Indicates that the PC byte has changed from its previ ous value. If the IEC61937 bit in the Format Detect Status register goes high, it will cause a PCCH interrupt even if the PC byte hasn’t changed since the last time the IEC61937 bit went high. OSLIP - Serial audio output port data slip interrupt When the serial audio output port is in slave mode , and OLRCK is asynchronous to the port data source, this bit will go high ever y time a data sample is dropped or r epeated. See “Slip/Repeat Behavior” on page 25 for more information. DETC - D to E C-buffer transfer interrupt. Indicates the completion of a D to E C-buffer transfer. See “Channel Status Buffer Management” on page 51. C_CHANGE -Indicates that the current 10 bytes of channel status is different from the previous 10 bytes. (5 bytes per channel) RERR - A receiver error has occurred. The Receiver Error register may be read to determine the nature of the error which caused the interrupt. QCH – A new block of Q-subcode is available for reading. The data must be read within 588 AES3 frames after the interrupt occurs to avoid corruption of the data by the next block. FCH – Format Change: Goes high when the PCM, IEC61937, DTS_LD, DTS_CD, or DGTL_SIL bits in the Format Detect Status register transition from 0 to 1. When these bits in the Format Detect Status register transition from 1 to 0, an interrupt will not be generated.

14.15 Q-Channel Subcode (0Eh - 17h)

Each byte is LSB first with respect to the 80 Q-subcode bits Q[79:0]. Thus, bit 7 of address 0Eh is Q[0] while bit 0 of address 0Eh is Q[7]. Similarly, bit 0 of address 17h corresponds to Q[79]. 76543210

0 PCCH OSLIP DETC CCH RERR QCH FCH

CONTROL CONTROL CONTROL CONTR OL ADDRESS ADDRESS ADDRESS ADDRESS TRACK TRACK TRACK TRACK TRACK TRACK TRACK TRACK INDEX INDEX INDEX INDEX INDEX INDEX INDEX INDEX MINUTE MINUTE MINUTE MINUTE M INUTE MINUTE MINUTE MINUTE SECOND SECOND SECOND SECOND SECOND SECOND SECOND SECOND FRAME FRAME FRAME FRAME FRAME FRAME FRAME FRAME ZERO ZERO ZERO ZERO ZERO ZERO ZERO ZERO ABS MINUTE ABS MINUTE ABS MINUTE ABS MINUTE AB S MINUTE ABS MINUTE ABS MINUTE ABS MINUTE ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS SECOND ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME ABS FRAME

14.16 OMCK/RMCK Ratio (18h)

This register allows the calculation of the incoming sample rate by the host microcontroller from the equation ORR=Fso/Fsi. The Fso is determined by OMCK, whose frequency is assumed to be 256*Fso. ORR is rep- resented as an unsigned 2-bit integer and a 6-bit fractional part. The value is meaningful only after the PLL has reached lock. For example, if the OMCK is 12.288 MHz, Fso would be 48 kHz (48 kHz = 12.288 MHz/256). Then, if the input sample rate is al so 48 kHz, you would get 1.0 from the ORR register (The value from the ORR regist er is hexadecimal, so the ac tual value you will get is 40h). If FSO/FSI > 3 63/64, ORR will saturate at the value FFh. Also, th ere is no hysteresis on ORR. Therefore a small amount of jitter on either clock can cause the LSB ORR[0] to oscillate. ORR[7:6] - Integer part of the ratio (Integer value=Integer(SRR[7:6])). ORR[5:0] - Fractional part of the ratio (Fraction value=Integer(SRR[5:0])/64).

14.17 Channel Status Re gisters (19h - 22h)

14.18 IEC61937 PC/PD Burst Preamble (23h - 26h)

14.19 CS8416 I.D. and Ve rsion Register (7Fh) ID[3:0] - ID code for the CS8416. Permanently set to 0010 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B) VER[3:0] = 0011 (revision C) VER[3:0] = 0111 (revision D) VER[3:0] = 1111 (revision E) 76543210 ORR7 ORR6 ORR5 ORR4 ORR3 ORR2 ORR1 ORR0 19h Channel A Status Byte 0 AC0[7] AC0[6] AC0[5] AC0[4] AC0[3] AC0[2] AC0[1] AC0[0] 1Ah Channel A Status Byte 1 AC1[7] AC1[6] AC1[5] AC1[4] AC1[3] AC1[2] AC1[1] AC1[0] 1Bh Channel A Status Byte 2 AC2[7] AC2[6] AC2[5] AC2[4] AC2[3] AC2[2] AC2[1] AC2[0] 1Ch Channel A Status Byte 3 AC3[7] AC3[6] AC3[5] AC3[4] AC3[3] AC3[2] AC3[1] AC3[0] 1Dh Channel A Status Byte 4 AC4[7] AC4[6] AC4[5] AC4[4] AC4[3] AC4[2] AC4[1] AC4[0] 1Eh Channel B Status Byte 0 BC0[7] BC0[6] BC0[5] BC0[4] BC0[3] BC0[2] BC0[1] BC0[0] 1Fh Channel B Status Byte 1 BC1[7] BC1[6] BC1[5] BC1[4] BC1[3] BC1[2] BC1[1] BC1[0] 20h Channel B Status Byte 2 BC2[7] BC2[6] BC2[5] BC2[4] BC2[3] BC2[2] BC2[1] BC2[0] 21h Channel B Status Byte 3 BC3[7] BC3[6] BC3[5] BC3[4] BC3[3] BC3[2] BC3[1] BC3[0] 22h Channel B Status Byte 4 BC4[7] BC4[6] BC4[5] BC4[4] BC4[3] BC4[2] BC4[1] BC4[0] 23h Burst Preamble PC Byte 0 PC0[7] PC0[6 ] PC0[5] PC0[4] PC0[3] PC0[2] PC0[1] PC0[0] 24h Burst Preamble PC Byte 1 PC1[7] PC1[6 ] PC1[5] PC0[4] PC1[3] PC1[2] PC1[1] PC1[0] 25h Burst Preamble PD Byte 0 PD0[7] PD0[6 ] PD0[5] PC0[4] PD0[3] PD0[2] PD0[1] PD0[0] 26h Burst Preamble PD Byte 1 PD1[7] PD1[6 ] PD1[5] PD1[4] PD1[3] PD1[2] PD1[1] PD1[0] 76543210 ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0

46 DS578F3

in Hardware Mode, described in Section 15.2 “Hardware Mode Function Selection” on page 46. cause the previous audio sample to be held.

15.1 Serial Audio Port Formats

fines the equivalent Software Mode bit settings for each format. the serial audio port format.

15.2 Hardware Mode Function Selection

are omitted from the diagram. Please refer to the Typical Connection Diagram for connection details. Figure 15. Hardware Mode Data Flow

conditions (set after reset).

15.3 Hardware Mode Equival ent Register Settings

Listed below are the equivalent values that the registers are set to in Hardware Mode. PDUR = Set by TX pin pull-up/down after reset. SWCLK = Set to 1 if there a transition on OMCK after reset. Otherwise set to 0. RMCKF = Set by U pin pull-up/down after reset. TX Normal Phase Detector update rate. Higher Phase Detector update rate. Table 4. Hardware Mode Start-Up Pin Conditions

48 DS578F3

RX_SEL[1:0] = RX_SEL[1:0] pins. TX_SEL[1:0] = TX_SEL[1:0] pins. SOMS = set by RCBL pull-up/down after reset. bits[6:0] = Set by pull-up/down on AUDIO & C after reset. See Table 5 for bit settings. VM = set by NV/RERR pull-up/down after reset. Registers 07h through 7Fh do not have Hardware Mode equivalent settings. Table 5. Hardware Mode Serial Audio Format Select

16.1 AES3 Receiver Ex ternal Components

110 Ω ± 20% impedance. The XLR connector on the receiver should have female pins with a male shell. quired by the AES specification, they are strongly recommended. frequency energy could be coupled into the receiver, causing degradation in analog performance. or any DC current flow, if a DC voltage is present on the cable. the consumer interface is shown in Figure 19. TTL/CMOS logic outputs drive the CS8416 receiver section.

16.2 Isolating Transformer Requirements

Figure 16. Professional Input Circuit Figure 17. Transformerless Professional Input Circuit

50 DS578F3

Figure 18. Consumer Input Circuit Fi gure 19. S/PDIF MUX Input Circuit Figure 20. TTL/CMOS Input Circuit

17.CHANNEL STATUS BUFFER MANAGEMENT

17.1 AES3 Channel Status (C) Bit Management

The CS8416 contains sufficient RAM to store the first 5 bytes of C data for both A and B channels (5 x 2 x 8 = 80 bits). The user may read from this buffer’s RAM through the control port. The buffering scheme involves two buffers, named D and E, as shown in Figure 21. The MSB of each byte represents the first bit in the serial C data stream. For example, the MSB of byte 0 (which is at control port address 19h) is the consumer/professional bit for channel status block A. The first buffer (D) accepts incoming C data from the AES receiver. The 2nd buffer (E) accepts entire blocks of data from the D buffer. The E buffer is also accessible from the control port, allowing reading of the first five bytes of C data. The complete C data may be obtained through the C pin in Hardware Mode and through one of the GPO pins in Software Mode. The C data is serially shifted out of the CS8416 clocked by the rising and falling edges of OLRCK.

17.2 Accessing the E Buffer

The user can monitor the incoming data by reading the E buffer, which is mapped into the register space of the CS8416, through the control port. The user can configure the interrupt enable register to cause interrupts to occur whenever D to E buffer transfers occur. This allows determination of the allowable time periods to interact with the E buffer. Also provided is a D to E inhibit bit in the Control2 register (02h). This may be used whenever “long” control port interactions are occurring or for debugging purposes. A flowchart for reading the E buffer is shown in Figure 22. Since a D to E interrupt occurs just after reading, there is a substantial time interval until the next D to E transfer (appro ximately 192 frames worth of time). This is usually enough time to access the E data without having to inhibit the next transfer.

17.2.1 Serial Copy Mana gement System (SCMS)

In Software Mode, the CS8416 allows read access to all the channel status bits. For consumer mode SCMS compliance, the host microcontroller needs to read and interpret the Category Code, Copy bit and L bit appropriately. In Hardware Mode, the SCMS protocol can be followed by either using the COPY and ORIG output pins, or by using the C bit serial output pin. These options are documented in Section 15. “Hardware Mode” on page 46.

52 DS578F3

Figure 21. Channel Status Data Buffer Structure Figure 22. Flowchart for Reading the E Buffer

18.1 General

ed at each preamble in the bi-phase encoded stream. This occurs at twice the sampling frequency, FS. dependent jitter affects because the preambles do not vary with the data. The PLL has the ability to lock onto a wide range of input sample rates with no external component changes. to its wide lock range mode and re-acquire a new nominal center sample rate.

18.2 External Filter Components

18.2.1 General

and offer good output jitter performance. Lock times are worst case for an Fsi transition of 192 kHz. the PLL filter be returned directly to the AGND pin independently of the ground plane. Figure 23. PLL Block Diagram

54 DS578F3

18.2.2 Capacitor Selection

tive to shock and vibration. These include the Z5U and Y5V dielectrics.

18.2.3 Circuit Board Layout

contains a suggested layout for the PLL filter components and for bypassing the analog supply voltage. VA and AGND traces extend back to their origin and are shown only in truncated form in the drawing.

18.2.4 Component Value Selection

The external PLL component values are listed in Table 6. Table 6. External PLL Component Values Figure 24. Recommended Layout Example

18.2.5 Jitter Attenuation

mum of 2 dB jitter gain or peaking. Figure 25. Jitter Attenuation Characteristics of PLL

56 DS578F3

19.PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-013 Controlling Dimension is Millimeters 28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE e

Notes: 1. “D” and “E1” are reference datums and do not includ e mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/ intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re- duce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. TSSOP THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 4 Layer Board θJA - 40 -° C / W a t t 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

58 DS578F3

28-PIN QFN (5 × 5 MM BODY) PACKAGE DRAWING Notes: 1. Dimensioning and tolerance per ASME Y 14.5M-1995. 2. Dimensioning lead width applies to the plated te rminal and is measured between 0.23mm and 0.28mm from the terminal tip. QFN THERMAL CHARACTERISTICS INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A1 0.0000 -- 0.0020 0.00 -- 0.05 1 D 0.1969 BSC 5.00 BSC 1 E 0.1969 BSC 5.00 BSC 1 e 0.0197 BSC 0.50 BSC 1 JEDEC #: MO-220 Controlling Dimension is Millimeters. Parameter Symbol Min Typ Max Units Junction to Ambient Thermal Impedance 2 Layer Board

4 Layer Board θJA

°C/Watt °C/Watt Side View A A1 D2L b e Pin #1 Corner Bottom ViewTop View Pin #1 Corner D E E2

20.ORDERING INFORMATION Product Description Pb-Free Grade Temp Range Package Container Order# CS8416 192 kHz Digital Audio Interface Receiver YES Commercial -10° to +70° C 28-SOIC Rail CS8416-CSZ Tape and Reel CS8416-CSZR 28-TSSOP Rail CS8416-CZZ Tape and Reel CS8416-CZZR 28-QFN Rail CS8416-CNZ Tape and Reel CS8416-CNZR Automotive -40° to +85° C 28-SOIC Rail CS8416-DSZ Tape and Reel CS8416-DSZR 28-TSSOP Rail CS8416-DZZ Tape and Reel CS8416-DZZR 28-QFN Rail CS8416-DNZ Tape and Reel CS8416-DNZR CDB8416 Evaluation Board for CS8416 - - - - - CDB8416

60 DS578F3

21.REVISION HISTORY Release Changes -Reformatted “Features” on page 1 -Added RMCK/OMCK maximum in“Switching Characteristics” on page 8. -Corrected AES3 Direct format in “Serial Audio Output Example Formats” on page 24. -Corrected Table 2 and page 28 text referencing VCO idle frequency. -Added timing note to Figure 10 on page 32. -Corrected “Control Port Description” on page 33 to reflect the Auto-Increment function of the MAP . -Added thermal relief pad label to QFN package in “Pin Description - Software Mode” on page 12 and “Pin Description - Hardware Mode” on page 16. -Added “TSSOP Thermal Characteristics” on page 57 and “QFN Thermal Characteristics” on page 58. F2 Clarified use of de-emphasis filt er in AES3 direct-output format. F3 Updated ordering information to include Automotive grade QFN option. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you, go to www.cirrus.com. IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRI TICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN S UCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. AC-3 is a registered trademark of Dolby Laboratories, Inc. DTS is a registered trademark of the Digital Theater Systems, Inc. I²C is a registered trademark of Philips Semiconductor. SPI is a trademark of Motorola Inc.