CS8406-IZ

CS8406 CIRRUS | Alldatasheet

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Features

Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF compatible transmitter +3.3 V or 5.0 V Digital Supply (VD) +3.3 V or 5.0 V Digital Interface (VL) On-chip Channel Status and User bit buffer memories allow block sized updates Flexible 3-wire serial digital audio input port Up to 192 kHz frame rate Microcontroller write access to Channel Status and User bit data On-chip differential line driver Generates CRC codes and parity bits Standalone mode allows use without a microcontroller 28-pin SOIC/TSSOP package General Description The CS8406 is a monolithic CMOS device which en- codes and transmits audio data according to the AES3, IEC60958, S/PDIF, or EIAJ CP1201. The CS8406 ac- cepts audio and digital data, which is then multiplexed, encoded and driven onto a cable. The audio data is input through a configurable, 3-wire input port. The channel status and user bit data are input through an SPI or I²C microcontroller port, and may be assembled in block sized buffers. For systems with no microcontroller, a stand alone mode allows direct ac- cess to channel status and user bit data pins. Target applications include A/V Receivers, CD-R, DVD receivers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems.

ORDERING INFORMATION

-10 to +70°C CS8406-CZ 28-pin TSSOP -10 to +70°C CS8406-IS 28-pin SOIC -40 to +85°C CS8406-IZ 28-pin TSSOP -40 to +85°C CS8406-DS 28-pin SOIC -40 to +85°C CS8406-DZ 28-pin TSSOP -40 to +85°C CDB8416 Evaluation Board I Serial Audio Input Misc. Control AES3 S/PDIF Encoder C & U bit Data Buffer Control Port & Registers Output Clock Generator RXP ILRCK ISCLK SDIN TXP TXN RST OMCK U SDA/ CDOUT SCL/ CCLK AD1/ CDIN AD0/ CS INT VL GND Driver AD2 H/S VD TCBL JUL ‘04 DS580F1

CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Notes: Transient currents of up to 100 mA will not cause SCR latch-up. Parameter Symbol Min Typ Max Units Power Supply Voltage VD VL 3.14 3.14 3.3 or 5.0 3.3 or 5.0 5.25 5.25 V V Ambient Operating Temperature: ‘-CS’ & ‘-CZ’ ‘-IS’, ‘-IZ’, ‘-DS’, & ‘-DZ’ TA TA -10 -40 +70 +85 Parameter Symbol Min Max Units Power Supply Voltage VD, VL 6.0 V Input Current, Any Pin Except Supplies (Note 1) Iin ±10 mA Input Voltage Vin -0.3 VL + 0.3 V Ambient Operating Temperature (power applied) TA -55 125 Storage Temperature Tstg -65 150

DC ELECTRICAL CHARACTERISTICS (GND = 0 V; all voltages with respect to 0 V.) Notes: Power Down Mode is defined as RST = LO with all clocks and data lines held static. Normal operation is defined as RST = HI. Assumes that no inputs are left floating. It is recommended that all digital inputs be driven high or low at all times. DIGITAL INPUT CHARACTERISTICS DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.) TRANSMITTER CHARACTERISTICS Parameters Symbol Min Typ Max Units Power-down Mode (Note 2) Supply Current in power down VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V ID ID IL IL µA µA µA µA Normal Operation (Note 3) Supply Current at 48 kHz frame rate (Note 4) VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V ID ID IL IL 1.9 3.5 6.5 10.6 mA mA mA mA Supply Current at 192 kHz frame rate (Note 4) VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V ID ID IL IL 7.6 12.7 7.2 mA mA mA mA Parameters Symbol Min Typ Max Units Input Leakage Current Iin ±0.5 µA Input Hysteresis (all inputs except OMCK) 0.25 V Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN VOH VL - 1.0 V Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN VOL 0.4 V High-Level Output Voltage, TXP, TXN (21 mA at VL = 5.0 V) (15 mA at VL = 3.3 V) VL - 0.7 VL - 0.7 VL VL V V Low-Level Output Voltage, TXP, TXN (21 mA at VL = 5.0 V) (16 mA at VL = 3.3 V) 0.7 0.7 V V High-Level Input Voltage VD = 5.0 V VD = 3.3 V VIH 2.75 2.0 VL + 0.3 VL + 0.3 V V Low-Level Input Voltage VD = 5.0 V VD = 3.3 V VIL -0.3 -0.3 0.8 0.8 V V Parameters Symbol Typ Units TXP Output Resistance VL = 5.0 V VL = 3.3 V RTXP 26.5 33.5 Ω Ω TXN Output Resistance VL = 5.0 V VL = 3.3 V RTXN 26.5 33.5 Ω Ω

(Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) SWITCHING CHARACTERISTICS - SERIAL AUDIO PORTS (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Notes: The active edge of ISCLK is programmable in Software mode. The polarity of ILRCK is programmable in Software mode. Prevents the previous ISCLK edge from being interpreted as the first one after ILRCK has changed. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed. Parameter Symbol Min Typ Max Units RST pin Low Pulse Width 200 µs OMCK Frequency for OMCK = 512*Fs 4.1 98.4 MHz OMCK Low and High Width for OMCK = 512*Fs 4.1 ns OMCK Frequency for OMCK = 384*Fs 3.1 73.8 MHz OMCK Low and High Width for OMCK = 384*Fs 6.1 ns OMCK Frequency for OMCK = 256*Fs 2.0 49.2 MHz OMCK Low and High Width for OMCK = 256*Fs 8.1 ns OMCK Frequency for OMCK = 128*Fs 1.0 24.6 MHz OMCK Low and High Width for OMCK = 128*Fs 18.3 ns Frame Rate 192 kHz AES3 Transmitter Output Jitter 200 ps Parameter Symbol Min Typ Max Units SDIN Setup Time Before ISCLK Active Edge (Note 5) tds ns SDIN Hold Time After ISCLK Active Edge (Note 5) tdh ns Master Mode OMCK to ISCLK active edge delay (Note 5) tsmd ns OMCK to ILRCK delay (Note 6) tlmd ns ISCLK and ILRCK Duty Cycle Slave Mode ISCLK Period tsckw ns ISCLK Input Low Width tsckl 14.4 ns ISCLK Input High Width tsckh 14.4 ns ISCLK Active Edge to ILRCK Edge (Note 7) tlrckd ns ILRCK Edge Setup Before ISCLK Active Edge (Note 8) tlrcks ns

memory. Access to the control register file can be carried out at the full 6 MHz rate. Tsch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns. Data must be held for sufficient time to bridge the transition time of CCLK. Figure 3. SPI Mode timing

Data must be held for sufficient time to bridge the 300 ns transition time of SCL. Figure 4. I²C Mode timing

Figure 5. Recommended Connection Diagram for Software Mode

Figure 6. Recommended Connection Diagram for Hardware Mode

1. GENERAL DESCRIPTION The CS8406 is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts au- dio, channel status and user data, which is then multiplexed, encoded, and driven onto a cable. The audio data is input through a configurable, 3-wire input port. The channel status bits and user bit data are input through an SPI or I²C Mode microcontroller port and may be assembled in sep- arate block sized buffers. For systems with no microcontroller, a stand alone mode allows direct access to channel status and user data input pins. Target applications include CD-R, DAT, DVD, MD and VTR equipment, mixing consoles, digital audio transmission equipment, high quality A/D converters, effects processors, set-top TV box- es, and computer audio systems. Figure 5 shows the supply and external connections to the CS8406 when configured for opera- tion with a microcontroller. Figure 6 shows the supply and external connections to the CS8406 when configured for operation without a microcontroller. 3.1 AES3 and S/PDIF Standards Documents This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3 and IEC60958 specifications on hand for easy ref- erence. The latest AES3 standard is available from the Audio Engineering Society or ANSI at national Electrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is avail- able from the Japanese Electronics Bureau. Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. The paper An Understanding and Implementation of the SCMS Serial Copy Management Sys- tem for Digital Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the AES as reprint 3518.

1. THREE-WIRE SERIAL INPUT AUDIO PORT A 3-wire serial audio input port is provided. The interface format can be adjusted to suit the at- tached device through the control registers. The following parameters are adjustable: Master or slave Serial clock frequency Audio data resolution Left or right justification of the data relative to left/right clock Optional one-bit cell delay of the first data bit Polarity of the bit clock Polarity of the left/right clock. (By setting the appropriate control bits, many formats are pos- sible). Figure 7 shows a selection of common input formats with the corresponding control bit settings. In master mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK input pin master clock. In slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the OMCK master clock, but the serial bit clock can be asynchronous and dis- continuous if required. The left/right clock should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to clock all the data bits.

Figure 7. Serial Audio Input Example Formats

1. AES3 TRANSMITTER The CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme pro- vides write access to the channel status and user data. This buffering scheme is described in Appendix B: Channel Status and User Data Buffer Management. The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multi- plexed together and bi-phase mark encoded. The resulting bit stream is driven to an output con- nector either directly or through a transformer. The transmitter is clocked from the clock input pin, OMCK. If OMCK is asynchronous to the data source, an interrupt bit (TSLIP) is provided that will go high every time a data sample is dropped or repeated. The channel status (C) and user (U) bits in the transmitted data stream are taken from storage areas within the CS8406. The user can manually access the internal storage or configure the CS8406 to run in one of several automatic modes. Appendix B: Channel Status and User Data Buffer Management provides detailed descriptions of each automatic mode and describes meth- ods of manually accessing the storage areas. The transmitted user bit data can optionally be in- put through the U pin, under the control of a control port register bit. Figure 8 shows the C/U/V timing requirements. 5.1 Transmitted Frame and Channel Status Boundary Timing The TCBL pin is used to control or indicate the start of transmitted channel status block bound- aries and may be an input or an output. In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame boundaries. This may be achieved in two ways: a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a new channel status block start. b) If the serial audio input port is in slave mode and TCBL is set to output, the start of the A chan- nel sub-frame will be aligned with the leading edge of ILRCK. 5.2 TXN and TXP Drivers The line drivers are low skew, low impedance, differential outputs capable of driving cables di- rectly. Both drivers are set to ground during reset (RST = LOW), when no AES3 transmit clock is provided, and optionally under the control of a register bit. The CS8406 also allows immediate muting of the AES3 transmitter audio data through a control register bit. External components are used to terminate and isolate the external cable from the CS8406. These components are detailed in “Appendix A: External AES3/SPDIF/IEC60958 Transmitter Components” on page 39.

5.3 Mono Mode Operation An alternate method for transmitting an AES3 192 kHz sample rate stream is mono mode. Mono mode is implemented by using the two sub-frames in a 96 kHz biphase encoded stream to carry consecutive samples of a single channel of a 192 kHz PCM stream (i.e. a mono signal). This al- lows older equipment, whose AES3 transmitters and receivers are not rated for 192 kHz frame rate operation, to handle 192 kHz sample rate information. In this mono mode, two AES3 cables and two CS8406's are needed for stereo data transfer. The CS8406 is set to mono mode by the MMT control bit. In mono mode, the input port will run at the audio sample rate (Fs), while the AES3 transmitter frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be se- lected for transmission on the A and B sub-frames, and the channel status block transmitted is also selectable. Using mono mode is only necessary if the incoming audio sample rate is already at 192 kHz and contains both left and right audio data words. The “mono mode” AES3 output stream may also be achieved by keeping the CS8406 in normal stereo mode, and placing consecutive audio sam- ples in the left and right positions in an incoming 96 kHz word rate data stream. Figure 8 shows the C/U/V timing requirements.

• VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing.
• VLRCK duty cycle is 50%.
• In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, VLRCK frequency = 2xAES3 frame rate.
• If the serial audio input port is on slave mode and TCBL is an output, then VLRCK = ILRCK if SILRPOL = 0 and VLRCK = ILRCK if SILRPOL =1.
• If the serial audio input port is in master mode and TCBL is an input, then VLRCK = ILRCK if SILRPOL = 0 and VLRCK = ILRCK if SILRPOL =1. Tth VCU[0] VCU[1] VCU[2] VCU[3] VCU[4] VLRCK V/C/U (Input) Data [4] Data [5] Data [6] Data [7] Data [8] SDIN (Input) Data [0] Data [1] Data [2] Data [3] Data [4] TXP(N) (Output) Z Y X Y X Tsetup Thold Tth Thold = 0 Tth > 3 OMCK clocks, if TCBL is Input Tsetup ≥ 7.5% AES3 frame time TCBL (In/Output) VLRCK U (Input) SDIN (Input) TXP(N) (Output) TCBL (In/Output) TXP(N) (Output) AES3 Transmitter in Mono mode Thold = 0 Tth > 3 OMCK clocks, if TCBL is Input Tsetup ≥ 15% AES3 frame time

Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data

Send start condition. Send 0010xxx0 (chip address & write operation). Receive acknowledge (ACK) bit. Send MAP byte, auto increment off. Receive ACK bit. Send stop condition, aborting write. Send start condition. Send 0010xxx(chip address & read operation). Receive ACK bit. Receive byte, contents of selected register. Send no acknowledge (NO ACK) bit. Send stop condition. Setting the auto increment bit in the MAP allows successive reads or writes of consecutive reg- isters. Each byte is separated by an acknowledge bit. 6.3. Memory Address Pointer (MAP) 6.3.1. Memory Address Pointer (MAP) Register Detail 6.3.2. INCR (Auto Map Increment Enable) Default = ‘0’ 0 - Disabled, the MAP will stay constant for successive writes 1 - Enabled, the MAP will auto increment after each byte is written, allowing block reads or writes of successive registers 6.3.3. MAP6-0 (Memory Address Pointer) Default = ‘0000000’ INCR MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0

for test modes, which can completely alter the normal operation of the CS8406. Table 1. Control Register Map Summary

CONTROL PORT REGISTER BIT DEFINITIONS 8.1 Control 1 (01h) VSET - Transmitted Validity bit level Default = ‘0’ 0 - Indicates data is valid, linear PCM audio data 1 - Indicates data is invalid or not linear PCM audio data MUTEAES - Mute control for the AES transmitter output Default = ‘0’ 0 - Not Muted 1 - Muted INT1:0 - Interrupt output pin (INT) control Default = ‘00’ 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier Default = ‘0’ 0 - TCBL is an input 1 - TCBL is an output VSET MUTEAES INT1 INT0 TCBLD

8.2 Control 2 (02h) MMT - Select AES3 transmitter mono or stereo operation Default = ‘0’ 0 - Normal stereo operation 1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit) MMTCS - Select A or B channel status data to transmit in mono mode Default = ‘0’ 0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data. MMTLR - Channel Selection for AES Transmitter mono mode Default = ‘0’ 0 - Use left channel input data for consecutive subframe outputs 1- Use right channel input data for consecutive subframe outputs 8.3 Data Flow Control (03h) The Data Flow Control register configures the flow of audio data. The output data should be muted prior to changing bits in this register to avoid transients. TXOFF - AES3 Transmitter Output Driver Control Default = ‘0 0 - AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive to 0 V. AESBP - AES3 bypass mode selection Default = ‘0’ 0 - Normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL threshold digital input. MMT MMTCS MMTLR TXOFF AESBP

8.4 Clock Source Control (04h) This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var- ious Receiver/Transmitter/Transceiver modes may be selected. RUN - Controls the internal clocks, allowing the CS8406 to be placed in a “powered down” low current consumption, state. Default = ‘0’ 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port registers are operational, allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Power consumption is low. 1 - Normal part operation. This bit must be set to 1 to allow the CS8406 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector. If these bits are changed during normal operation, then always stop the CS8406 first (RUN = 0), write the new value, then start the CS8406 (RUN = 1). Default = ‘00’ 00 - OMCK frequency is 256*Fs 01 - OMCK frequency is 384*Fs 10 - OMCK frequency is 512*Fs 11 - OMCK frequency is 128*Fs 8.5 Serial Audio Input Port Data Format (05h) SIMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio input port is in slave mode 1 - Serial audio input port is in master mode SISF - ISCLK frequency (for master mode) Default = ‘0’ 0 - 64*Fs 1 - 128*Fs SIRES1:0 - Resolution of the input data, for right-justified formats Default = ‘00’ 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - Reserved RUN CLK1 CLK0 SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

SIJUST - Justification of SDIN data relative to ILRCK Default = ‘0’ 0 - Left-justified 1 - Right-justified SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats Default = ‘0’ 0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (left justified mode) 1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (I²S mode) SISPOL - ISCLK clock polarity Default = ‘0’ 0 - SDIN sampled on rising edges of ISCLK 1 - SDIN sampled on falling edges of ISCLK SILRPOL - ILRCK clock polarity Default = ‘0’ 0 - SDIN data is for the left channel when ILRCK is high 1 - SDIN data is for the right channel when ILRCK is high 8.6 Interrupt 1 Status (07h) (Read Only) For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to ‘0’, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register defaults to 00h. TSLIP - AES3 transmitter source data slip interrupt In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high on receipt of a new TCBL signal. EFTC - E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in the C bit buffer management process. TSLIP EFTC

8.7 Interrupt 2 Status (08h) (Read Only) For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to ‘0’, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register defaults to 00h. EFTU - E to F U-buffer transfer interrupt. (Block Mode only) The source of this bit is true during the E to F buffer transfer in the U bit buffer management process. 8.8 Interrupt 1 Mask (09h) The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in Interrupt 1 register. This register defaults to 00h. 8.9 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh) The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be- comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in- terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg- isters default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved 8.10 Interrupt 2 Mask (0Ch) The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in Interrupt 2 register. This register defaults to 00h. EFTU TSLIPM EFTCM TSLIP1 EFTC1 TSLIP0 EFTC0 EFTUM

8.11 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh) The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be- comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in- terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg- isters default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved 8.12 Channel Status Data Buffer Control (12h) BSEL - Selects the data buffer register addresses to contain User data or Channel Status data Default = ‘0’ 0 - Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data Note: There are separate complete buffers for the Channel Status and User bits. This control bit determines which buffer appears in the address space. EFTCI - E to F C-data buffer transfer inhibit bit. Default = ‘0’ 0 - Allow C-data E to F buffer transfers 1 - Inhibit C-data E to F buffer transfers CAM - C-data buffer control port access mode bit Default = ‘0’ 0 - One byte mode 1 - Two byte mode EFTU1 EFTU0 BSEL EFTCI CAM

8.13 User Data Buffer Control (13h) UD - User bit data source specifier Default = ‘0’ 0 - U Pin is the source of transmitted U data 1 - U data buffer is the source of transmitted U data UBM1:0 - Sets the operating mode of the AES3 User bit manager Default = ‘00’ 00 - Transmit all zeros mode 01 - Block mode 10 - Reserved 11 - Reserved EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only). Default = ‘0’ 0 - Allow U-data E to F buffer transfers 1 - Inhibit U-data E to F buffer transfers 8.14 Channel Status bit or User bit Data Buffer (20h - 37h) Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block mode) is accessible through these register addresses. 8.15 CS8406 I.D. and Version Register (7Fh) (Read Only) ID[3:0] - ID code for the CS8406. Permanently set to 1110 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B) UD UBM1 UBM0 EFTUI ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0

1. PIN DESCRIPTION - SOFTWARE MODE VD Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. VL Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. GND Ground (Input) - Ground for I/O and core logic. RST Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8406 devices, where synchronization between devices is important. H/S Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation of the CS8406, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. To select Software mode, this pin should be permanently tied to GND. TXN TXP Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled low while the CS8406 is in the reset state. OMCK Master Clock (Input) - The frequency can be set through the control port registers. ISCLK Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. ILRCK Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. SDIN Serial Audio Data Port (Input) - Audio data serial input pin. SDA / CDOUT SCL / CCLK AD0 / CS AD1 / CDIN AD2 TXP RXP TXN TEST H/S VD VL TEST GND TEST OMCK RST U TEST INT TEST TEST ILRCK TEST ISCLK TEST SDIN TCBL

Serial Control Data I/O (I²C Mode) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI mode, CDOUT is the output data from the control port interface on the CS8406 SCL/CCLK Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8406. In I²C mode, SCL requires an external pull-up resistor to VL. AD0/CS Address Bit 0 (I²C Mode) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8406 into SPI control port mode. With no falling edge, the CS8406 defaults to I²C mode. In I²C mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8406 AD1/CDIN Address Bit 1 (I²C Mode) / Serial Control Data in (SPI) (Input) - In I²C mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface. AD2 Address Bit 2 (I²C Mode) (Input) - Determines the AD2 address bit for the control port in I²C mode, and should be connected to GND or VL. If SPI mode is used, the AD2 pin should be connected to either GND or VL. RXP Auxiliary AES3 Receiver Port (Input) - Input for an alternate, already AES3 coded, audio data source. INT Interrupt (Output) - Indicates key events during the operation of the CS8406. All bits affecting INT may be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt are readable in the control registers. The polarity of the INT output, as well as selection of a standard or open drain output, is set through a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero. TCBL Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. U User Data (Input) - May optionally be used to input User data for transmission by the AES3 transmitter, see Figure 4 for timing information. If not driven, a 47 kΩ pull-down resistor is recommended for the U pin. If the U pin is driven by a logic level output, then a 100 Ω series resistor is recommended. TEST Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how- ever current consumption from VL will increase by 25 µA per TEST pin that is left floating.

The CS8406 has a hardware mode that allows the use of the device without a microcontroller. mode pin description section. input port and routed to the AES3 transmitter. channel status data is derived from the state of the COPY/C, ORIG, EMPH, and AUDIO pins. the transmitted category code is set to General (00h). pins at both edges of ILRCK. Figure 8 shows the timing requirements. Power supply pins are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 12. Hardware Mode Data Flow

Table 4. Table 5 describes the equivalent software mode, bit settings for each of the available for- mats. Timing diagrams are shown in Figure 7. Table 2. Hardware Mode COPY/C and ORIG pin functions Table 3. Hardware Mode Serial Audio Port Format Selection Table 4. Hardware Mode OMCK Clock Ratio Selection Table 5. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode

11.PIN DESCRIPTION - HARDWARE MODE VD Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. VL Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. GND Ground (Input) - Ground for I/O and core logic. RST Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8406 devices, where synchronization between devices is important. H/S Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation of the CS8406, and the method of accessing CS and U data. Hardware mode provides an alternate mode of operation, and access to CS and U data is provided by dedicated pins. To select Hardware mode, this pin should be permanently tied to VL. TXN TXP Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled low while the CS8406 is in the reset state. OMCK Master Clock (Input) - The frequency can be set through the HWCK[1:0] pins. ISCLK Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. ILRCK Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. SDIN Serial Audio Data Port (Input) - Audio data serial input pin. SFMT0 SFMT1 Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on page 33. COPY / C ORIG TEST HWCK1 EMPH TXP SFMT0 TXN SFMT1 H/S VD VL TEST GND TEST OMCK RST HWCK0 APMS AUDIO TCBLD U ILRCK V ISCLK CEN SDIN TCBL

Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL to set serial audio input port as a master or connected to GND to set the port as a slave. HWCK0 HWCK1 OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 33. TCBLD Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL to set TCBL as an output. Connect TCBLD to GND to set TCBL as an input. TCBL Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. CEN C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, hard- ware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When CEN is high, hardware mode B is selected, where the COPY/C pin is used to enter serial channel status data. V Validity Bit (Input) - In hardware modes A and B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. U User Data Bit (Input) - In hardware modes A and B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. COPY/C COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2 on page 33. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin, which is sampled on both edges of LRCK. EMPH Pre-Emphasis Indicator (Input) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3 empha- sis channel status bits to indicate 50/15 µs pre-emphasis of the transmitted audio data. If EMPH is high, then the three EMPH channel status bits are set to 000, indicating no pre-emphasis. AUDIO Audio Channel Status Bit (Input) - In hardware mode A (CEN = 0), the AUDIO pin determines the state of the audio/non audio Channel Status bit in the outgoing AES3 data stream. ORIG ORIG Channel Status Bit Control (Input) - In hardware mode A (CEN = 0), the ORIG and COPY/C pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2 on page 33. TEST Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how- ever current consumption from VL will increase by 25 µA per TEST pin that is left floating.

low power state and begin operation. systems, allowing common software modules. Figure 6. The VD and VL supplies should be decoupled with a 0.1 µF capacitor to GND to mini- mize AES3 transmitter induced transients. itors should be as close to the CS8406 as possible. nal logic, whereby all CS8406 devices should be set to slave TCBL.

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A 0.093 0.098 0.104 2.35 2.50 2.65 0.004 0.008 0.012 0.10 0.20 0.30 b 0.013 0.017 0.020 0.33 0.42 0.51 C 0.009 0.011 0.013 0.23 0.28 0.32 D 0.697 0.705 0.713 17.70 17.90 18.10 E 0.291 0.295 0.299 7.40 7.50 7.60 e 0.040 0.050 0.060 1.02 1.27 1.52 H 0.394 0.407 0.419 10.00 10.34 10.65 L 0.016 0.026 0.050 0.40 0.65 1.27 JEDEC #: MS-013 Controlling Dimension is Millimeters 28L SOIC (300 MIL BODY) PACKAGE DRAWING D H E b A c L SEATING PLANE e

Notes: 1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX A 0.47 1.20 0.002 0.004 0.006 0.05 0.10 0.15 0.03150 0.035 0.04 0.80 0.90 1.00 b 0.00748 0.0096 0.012 0.19 0.245 0.30 2,3 D

0.378 BSC

0.382 BSC

0.386 BSC

9.60 BSC

9.70 BSC

9.80 BSC

E 0.248 0.2519 0.256 6.30 6.40 6.50 0.169 0.1732 0.177 4.30 4.40 4.50 e

0.026 BSC

0.65 BSC

L 0.020 0.024 0.029 0.50 0.60 0.75 JEDEC #: MO-153 Controlling Dimension is Millimeters. 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 2 3 e A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

allows the user to manage the C and U data through the control port. RAM buffers through the control port. sumer/professional bit for channel status block A.

15.1.1 Accessing the E buffer

transmitted by writing to the E buffer. sets this bit. This may be used whenever “long” control port interactions are occurring. starts after a E to F transfer, which is based on the output timebase. Figure 16. Channel Status Data Buffer Structure

COPY/C pin when the part is in hardware mode.

15.1.2 Serial Copy Management System (SCMS)

Code, Copy bit and L bit appropriately.

15.1.3 Channel Status Data E Buffer Access

and the LS Byte is the B channel data (see Figure 16). There are two methods of accessing this memory, known as one byte mode and two byte mode. The desired mode is selected through a control register bit.

15.1.3.1 One Byte mode

often identical nature of A and B channel status data. Figure 17. Flowchart for Writing the E Buffer

byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. One byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. If the control port's auto increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently.

15.1.3.2 Two Byte mode

There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8406 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8406's control port. The A channel status data is first, B channel status data second. 15.2 AES3 User (U) Bit Management The CS8406 U bit manager has two operating modes: Mode 1. Transmit all zeros. Mode 2. Block mode.

15.2.1 Mode 1: Transmit All Zeros

Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents. This mode is intended for the user who wants the output U channel to contain no data.

15.2.2 Mode 2: Block Mode

Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered using 2 block-sized RAMs to perform the buffering. The user has access to the first buffer, denoted the E buffer, through the control port. It is the only mode in which the user can merge his own U data into the transmitted AES3 data stream. The U buffer access only operates in two byte mode, since there is no concept of A and B blocks for user data. The arrangement of the data is as followings: Bit15[A7] Bit14[B7] Bit13[A6] Bit12 [B6]...Bit1 [A0] Bit0[B0]. The arrangement of the data in the each byte is that the MSB is the first transmitted bit. The bit for the A subframe is followed by the bit for the B subframe.

-Corrected “OMCK Low and High Width for OMCK = 384*Fs” on page 7. -Corrected “Rise Time of Both SDA and SCL Lines” on page 10. -Corrected “Fall Time of Both SDA and SCL Lines” on page 10. -Corrected “SDIN Setup Time Before ISCLK Active Edge” on page 7. -Corrected Note 5 on page 7. -Corrected Note 6 on page 7. -Corrected H/S pin description on page 34. Table 6. Revision History For all product questions and inquiries contact a Cirrus Logic Sales Representative. consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. or service marks of their respective owners. a license under the Philips I²C Patent Rights to use those components in a standard I²C system.