CS8406-CSZR

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Features

 Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF-compatible Transmitter  +3.3 V or 5.0 V Digital Supply (VD)  +3.3 V or 5.0 V Digital Interface (VL)  On-Chip Channel Status and User Bit Buffer Memories Allow Block-Sized Updates  Flexible 3-Wire Serial Digital Audio Input Port  Up to 192-kHz Frame Rate  Microcontroller Write Access to Channel Status and User Bit Data  On-Chip Differential Line Driver  Generates CRC Codes and Parity Bits  Stand-Alone Mode Allows Use Without a Microcontroller General Description The CS8406 is a monolithic CMOS device which en- codes and transmits audio data according to the AES3, IEC60958, S/PDIF, or EIAJ CP1201 standards. The CS8406 accepts audio and digital data, which is then multiplexed, encoded, and driven onto a cable. The audio data is input through a configurable, 3-wire input port. The channel status and user bit data are in- put through an SPI™ or I²C TM microcontroller port, and may be assembled in block- sized buffers. For systems with no microcontroller, a Stand-Alone Mode allows di- rect access to channel status and user bit data pins. The CS8406 is available in 28-pin TSSOP, SOIC, and QFN packages in both Commercial (-10º to +70ºC) and Automotive grades (-40º to +85ºC). The CDB8416 Demonstration board is also available for device evaluation and implementation suggestions. Please refer to “Ordering Information” on page 37 for complete details. Target applications include A/V Receivers, CD-R, DVD receivers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems. RXP ILRCK ISCLK SDIN TXP TXN RST OMCKUS D A / CDOUT SCL/ CCLK AD1/ CDIN AD0/ CS INT VL GND AD2H/S VD TCBL Misc. Control Serial Audio Input C or U Data Buffer Control Port & Registers AES3 S/PDIF Encoder Output Clock Generator Driver OCT '09 DS580F5 CS8406

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1. CHARACTERISTICS AND SPECIFICATIONS (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical performance characteristics and specifications are derived from measurements taken at nominal supply voltages and TA = 25°C.) SPECIFIED OPERATING CONDITIONS (GND = 0 V, all voltages with respect to 0 V) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages with respect to 0 V. Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.) Notes: 1. Transient currents of up to 10 0 mA will not cause SCR latch-up. DC ELECTRICAL CHARACTERISTICS (GND = 0 V; all voltages with respect to 0 V.) 2. Power Down Mode is defined as RST = LO with all clocks and data lines held static. 3. Normal operation is defined as RST = HI. 4. Assumes that no inputs are left floating. It is reco mmended that all digital inputs be driven high or low at all times. Parameter Symbol Min Typ Max Units Power Supply Voltage VD VL 3.14 3.14 3.3 or 5.0 3.3 or 5.0 5.25 5.25 V V Ambient Operating Temperature: Commercial Grade Automotive Grade TA TA -10 -40 +70 +85 Parameter Symbol Min Max Units Power Supply Voltage VD, VL - 6.0 V Input Current, Any Pin Except Supplies (Note 1) Iin -± 1 0 m A Input Voltage V in -0.3 VL + 0.3 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units Power-Down Mode (Note 2) Supply Current in power down VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V ID ID IL IL μA μA μA μA Normal Operation (Note 3) Supply Current at 48 kHz frame rate (Note 4) VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V ID ID IL IL 1.9 3.5 6.5 10.6 mA mA mA mA Supply Current at 192 kHz frame rate (Note 4) VD = 3.3 V VD = 5.0 V VL = 3.3 V VL = 5.0 V ID ID IL IL 7.6 12.7 7.2 mA mA mA mA

DIGITAL INPUT CHARACTERISTICS DIGITAL INTERFACE SPECIFICATIONS (GND = 0 V; all voltages with respect to 0 V.) TRANSMITTER CHARACTERISTICS SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0 V, Logic 1 = VL; CL = 20 pF) Parameters Symbol Min Typ Max Units Input Leakage Current I in -- ± 0 . 5 μA Input Hysteresis (all inputs except OMCK) - 0.25 - V Parameters Symbol Min Max Units High-Level Output Voltage (IOH = -3.2 mA), except TXP/TXN V OH VL - 1.0 - V Low-Level Output Voltage (IOH = 3.2 mA), except TXP/TXN V OL -0 . 4 V High-Level Output Voltage, TXP, TXN (21 mA at VL = 5.0 V) (15 mA at VL = 3.3 V) VL - 0.7 VL - 0.7 VL VL V V Low-Level Output Voltage, TXP, TXN (21 mA at VL = 5.0 V) (16 mA at VL = 3.3 V) 0.7 0.7 V V High-Level Input Voltage VD = 5.0 V VD = 3.3 V VIH 2.75 2.0 VL + 0.3 VL + 0.3 V V Low-Level Input Voltage VD = 5.0 V VD = 3.3 V VIL -0.3 -0.3 0.8 0.8 V V Parameters Symbol Typ Units TXP Output Resistance VL = 5.0 V VL = 3.3 V RTXP 26.5 33.5 Ω Ω TXN Output Resistance VL = 5.0 V VL = 3.3 V RTXN 26.5 33.5 Ω Ω Parameter Symbol Min Typ Max Units RST pin Low Pulse Width 200 - - μs OMCK Frequency for OMCK = 512*Fs 4.1 - 98.4 MHz OMCK Low and High Width for OMCK = 512*Fs 4.1 - - ns OMCK Frequency for OMCK = 384*Fs 3.1 - 73.8 MHz OMCK Low and High Width for OMCK = 384*Fs 6.1 - - ns OMCK Frequency for OMCK = 256*Fs 2.0 - 49.2 MHz OMCK Low and High Width for OMCK = 256*Fs 8.1 - - ns OMCK Frequency for OMCK = 128*Fs 1.0 - 24.6 MHz OMCK Low and High Width for OMCK = 128*Fs 18.3 - - ns Frame Rate 8- 1 9 2 k H z AES3 Transmitter Output Jitter - 200 - ps RMS

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1. The active edge of ISCLK is programmable in Software Mode.
2. The polarity of ILRCK is programmable in Software Mode.
3. Prevents the previous ISCLK edge from being inte rpreted as the first one after ILRCK has changed.
4. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.

Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing

1. If Fs is lower than 51.850 kHz, the maximum CCLK frequency should be less than 115 Fs. This is dic-

tated by the timing requirements necessary to access the Channel Status and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate.

1. T sch must be greater than the larger of the two values, either 1/256FS + 8 ns, or 66 ns.
2. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 3. SPI Mode Timing

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1. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Figure 4. I²C Mode Timing

1. TYPICAL CONNEC TION DIAGRAMS

Figure 5. Recommended Connection Diagram for Software Mode

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Figure 6. Recommended Connection Diagram for Hardware Mode

1. GENERAL DESCRIPTION The CS8406 is a monolithic CMOS device which encodes a nd transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 interface standards. The CS8406 accepts audio, channel status and user da- ta, which is then multiplexed, encoded, and driven onto a cable. The audio data is input through a configurable, 3-wire input port. The channel status bits and user bit data are input through an SPI or I²C Mode microcontroller port and may be assembled in separate block sized buffers. For systems with no microcontroller, a Stand-Alone Mode allows direct access to channel status and user data input pins. Target applications include CD-R, DAT, DVD, MD and VTR equipment, mixing consoles, digital audio transmission equipment, high quality A/D converters, effects processors, set-top TV boxes, and computer audio systems. Figure 5 shows the supply and external connections to the CS8406 when configured for operation with a microcon- troller. Figure 6 shows the supply and external connections to the CS8406 when configured for operation without a microcontroller.

3.1 AES3 and S/PDIF Standards Documents

This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advisable to have current copies of the AES3 and IEC60958 specifications on hand for easy reference. The latest AES3 standard is available from the Audio Engi neering Society or ANSI at www.aes.org or www.ansi.org. Obtain the latest IE C60958 standard from ANSI or from the International Electrotechnical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from the Japanese Electronics Bureau. Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. The paper An Understanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission, by Clifton Sanchez, is an ex cellent tutorial on SCMS. It is available from the AES as reprint 3518.

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1. THREE-WIRE SERIAL INPUT AUDIO PORT

• Master or slave
• Serial clock frequency
• Audio data resolution
• Left or right justification of the data relative to left/right clock
• Optional one-bit cell delay of the first data bit
• Polarity of the bit clock
• Polarity of the left/right clock (by setting the app ropriate control bits, many formats are possible.) Figure 7 shows a selection of common input formats with the corresponding control bit settings. In Master Mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK input pin master clock. In Slave Mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be synchronous to the OMCK master clock, but the serial bit clock can be asynchronous and discontinuous if required. The left/right clock should be continuous, but the duty cycle can be less than the specified typical value of 50% if enough serial clocks are present in each phase to clock all the data bits. ILRCK ISCLK SDIN Left Justified (In) MSB LSB Left Right MSB I S (In) Right Justified (In) MSB LSB MSB LSB MSB Left Right MSB LSB MSB LSB Left Right LSB MSB LSB ILRCK ISCLK SDIN ILRCK ISCLK SDIN

Figure 7. Serial Audio Input Example Formats

1. AES3 TRANSMITTER The CS8406 includes an AES3 digital audio transmitter. A comprehensive buffering scheme provides write access to the channel status and user data. Th is buffering scheme is described in “Appendix B: Channel Status and User Data Buffer Management” on page 39. The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase mark encoded. The resulting bit stream is driven to an output connector ei ther directly or through a transformer. The transmitter is clocked from the clock input pin, OMCK. If OMCK is asyn chronous to the data source , an interrupt bit (TSLIP) is provided that will go high every time a data sample is dropped or repeated. The channel status (C) and user (U) bi ts in the transmitted data stream are taken from storage areas within the CS8406. The user can access the internal storage or configure the CS8406 to run in one of several automatic modes. “Appendix B: Channel Status and User Data Buffer Management” on page 39 provides detailed descriptions of each automatic mode and describes methods of accessing the storage areas. The transmitted user bit data can optionally be input through the U pin, under the control of a control port register bit. Figures 8 and 9 show the C/U/V timing requirements.

5.1 TXN and TXP Drivers

The AES3 transmitter line driv ers are low skew, low impedance, differential outputs capable of driving ca- bles directly. Both drivers are set to ground during reset (RST = LOW), when no AES3 transmit clock is pro- vided, and optionally under the control of a register bit. The CS8406 also allows immediate muting of the AES3 transmitter audio data through a control register bit. External components are used to terminate and isolate the external cable from the CS8406. These compo- nents are detailed in “Appendix A: External AES3/SPDIF/IEC60958 Transmitter Components” on page 38.

5.2 Mono Mode Operation

An alternate method for tr ansmitting an AES3 192 kHz sample rate stream is Mono M ode. Mono Mode is implemented by using the two sub-frames in a 96 kH z biphase encoded stream to carry consecutive sam- ples of a single channel of a 192 kHz PCM stream (i.e. a mono signal). This allows older equipment, whose AES3 transmitters and receivers are not rated for 192 kHz frame rate operation, to handle 192 kHz sample rate information. In this Mono Mode, two AES3 cables and two CS8406's are needed for stereo data trans- fer. The CS8406 is set to Mono Mode by the MMT control bit. In Mono Mode, the input port will run at the audio sample rate (Fs), while the AES3 transmitter frame rate will be at Fs/2. Consecutive left or right channel serial audio data samples may be selected for transmission on the A and B sub-frames, and the channel status block transmitted is also selectable. Using Mono Mode is only necessary if the incoming a udio sample rate is already at 192 kHz and contains both left and right audio data words. The “Mono Mode” AES3 output stream may also be achieved by keep- ing the CS8406 in normal stereo mode, and placing consecutive audio samples in the left and right positions in an incoming 96 kHz word rate data stream. Figure 9 shows the C/U/V timing requirements.

5.3 Transmitted Frame and Ch annel Status Boundary Timing

The TCBL pin is used to indicate the start of trans mitted channel status block boundaries and may be an input or an output. In some applications, it may be necessary to contro l the precise timing of the transmitted AES3 frame boundaries. This may be achieved in two ways:

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frame will be aligned with the leading edge of ILRCK. VLRCK = ILRCK when SILRPOL = 0 and VLRCK = ILRCK when SILRPOL = 1. Figure 8. AES3 Transmitter Timing for C, U, and V Pin Input Data, Stereo Mode

1. T setup ≥ 15% AES3 frame rate
2. T th > 3 OMCKS if TCBL is an input

Figure 9. AES3 Transmitter Timing for C, U, and V Pin Input Data, Mono Mode

1. T setup ≥ 15% AES3 frame rate
2. T th > 3 OMCKS if TCBL is an input

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6.1 SPI Mode

line to the microcontroller. Data is clocked in on the rising edge of CCLK and out on the falling edge. externally pulled high or low with a 47 kΩ resistor, if desired. cessive registers will appear consecutively. Figure 10. Control Port Timing in SPI Mode

6.2 I²C Mode

be connected to VL or GND as desired. the microcontroller after each transmitted byte. in Figure 12, the write operation is aborted after the acknowledge for the MAP by sending a stop condition. Figure 11. Control Port Timing, I²C Slave Mode Write Figure 12. Control Port Timing, I²C Slave Mode Read

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1. CONTROL PORT REGISTER SUMMARY

test modes, which can completely alter the normal operation of the CS8406.

00 Reserved 0 0 0 0 0 0 0 0

01 Control 1 0 VSET 0 MUTEAES 0 INT1 INT0 TCBLD

02 Control 2 0 0 0 0 0 MMT MMCST MMTLR

03 Data Flow Control 0 TXOFF AESBP 0 0 0 0 0

04 Clock Source Control 0 RUN CLK1 CLK0 0 0 0 0

05 Serial Input Format SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

06 Reserved 0 0 0 0 0 0 0 0

07 Interrupt 1 Status TSLIP 0 0 0 0 0 EFTC 0

08 Interrupt 2 Status 0 0 0 0 0 EFTU 0 0

09 Interrupt 1 Mask TSLIPM 0 0 0 0 0 EFTCM 0

12 CS Data Buffer Control 0 0 BSEL 0 0 EFTCI CAM 0

13 U Data Buffer Control 0 0 0 UD UBM1 UBM0 0 EFTUI

Table 1. Control Register Map Summary

1. CONTROL PORT REGIST ER BIT DEFINITIONS

8.1 Memory Address Pointer (MAP)

MAP[6:0] - Memory Address Pointer. Will automatically increment after each read or write.

8.2 Default = ‘000000’Control 1 (01h)

VSET - Transmitted Validity bit level Default = ‘0’ 0 - Indicates data is valid, linear PCM audio data 1 - Indicates data is invalid or not linear PCM audio data MUTEAES - Mute control for the AES transmitter output Default = ‘0’ 0 - Not Muted 1 - Muted INT1:0 - Interrupt output pin (INT) control Default = ‘00’ 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier Default = ‘0’ 0 - TCBL is an input 1 - TCBL is an output

8.3 Control 2 (02h)

MMT - Select AES3 transmitter mono or stereo operation Default = ‘0’ 0 - Normal stereo operation 1 - Output either left or right channel inputs into co nsecutive subframe outputs (Mono Mode, left or right is determined by MMTLR bit) 76543210

0 MAP6 MAP5 MAP4 MAP3 MAP2 MAP1 MAP0

0 VSET 0 MUTEAES 0 INT1 INT0 TCBLD

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MMTCS - Select A or B channel status data to transmit in Mono Mode Default = ‘0’ 0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subf rame outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data. MMTLR - Channel Selection for AES Transmitter Mono Mode Default = ‘0’ 0 - Use left channel input data for consecutive subframe outputs 1- Use right channel input data for consecutive subframe outputs

8.4 Data Flow Control (03h)

The Data Flow Control register configures the flow of audio data. The output data should be muted prior to changing bits in this register to avoid transients. TXOFF - AES3 Transmitter Output Driver Control Default = ‘0 0 - AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive to 0 V. AESBP - AES3 bypass mode selection Default = ‘0’ 0 - Normal operation 1 - Connect the AES3 transmitter driver input di rectly to the RXP pin, which becomes a normal TTL threshold digital input.

8.5 Clock Source Control (04h)

This register configures the clock sources of various blocks. In conjunction with the Data Flow Control reg- ister, various Receiver/Transmitter/Transceiver modes may be selected. RUN - Controls the internal clocks, allowing the CS8406 to be placed in a “powered down” low current con- sumption, state. Default = ‘0’ 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port registers are operational, allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Power consumption is low. 1 - Normal part operation. This bit must be set to 1 to allow the CS8406 to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector. If these bits are changed during normal operation, always stop the CS8406 first (RUN = 0), write the new value, then start the CS8406 (RUN = 1). 7 6 54321 0

0 TXOFF AESBP 0 0 0 0 0

0 RUN CLK1 CLK0 0 0 0 0

Default = ‘00’ 00 - OMCK frequency is 256*Fs 01 - OMCK frequency is 384*Fs 10 - OMCK frequency is 512*Fs 11 - OMCK frequency is 128*Fs

8.6 Serial Audio Input Port Data Format (05h)

SIMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio input port is in Slave Mode 1 - Serial audio input port is in Master Mode SISF - ISCLK frequency (for Master Mode) Default = ‘0’ 0 - 64*Fs 1 - 128*Fs SIRES1:0 - Resolution of the input data, for right-justified formats Default = ‘00’ 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - Reserved SIJUST - Justification of SDIN data relative to ILRCK Default = ‘0’ 0 - Left-justified 1 - Right-justified SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats Default = ‘0’ 0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (Left-Justified Mode) 1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (I²S Mode) SISPOL - ISCLK clock polarity Default = ‘0’ 0 - SDIN sampled on rising edges of ISCLK 1 - SDIN sampled on falling edges of ISCLK SILRPOL - ILRCK clock polarity Default = ‘0’ 0 - SDIN data is for the left channel when ILRCK is high 1 - SDIN data is for the right channel when ILRCK is high 765 4 3 2 1 0 SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

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8.7 Interrupt 1 Status (07h) (Read Only)

For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register defaults to 00h. TSLIP - AES3 transmitter source data slip interrupt In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a da ta sample is dropped or repeated. When TCBL is an input, this bit will go high on receipt of a new TCBL signal. EFTC - E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in the C bit buffer management process.

8.8 Interrupt 2 Status (08h) (Read Only)

For all bits in this register, a ‘1’ means the associated interrupt condition has occurred at least once since the register was last read. A ‘0’ means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to ‘0’, unless the Interrupt Mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be ‘0’ in this register. This register defaults to 00h. EFTU - E to F U-buffer transfer interrupt. (Block Mode on ly) The source of this bit is true during the E to F buffer transfer in the U bit buffer management process.

8.9 Interrupt 1 Mask (09h)

The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is un- masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meanin g that its occurrence will not affect the INT pin or the status register. The bit positions align with the corresponding bits in Interrupt 1 register. This register defaults to 00h. 7 6 54321 0 TSLIP 0 0 0 0 0 EFTC 0 7 6 54321 0 000 0 0 E F T U 0 0 7 6 54321 0 TSLIPM 0 0 0 0 0 EFTCM 0

8.10 Interrupt 1 Mode MSB (0Ah) and Interrupt 1 Mode LSB (0Bh)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with th e interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be- comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

8.11 Interrupt 2 Mask (0Ch)

The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is un- masked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status regi ster. The bit positions align with the corresponding bits in Interrupt 2 register. This register defaults to 00h.

8.12 Interrupt 2 Mode MSB (0Dh) and Interrupt Mode 2 LSB (0Eh)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with th e interrupt condition. In the Rising edge active mode, the INT pin becomes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin be- comes active during the interrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These registers default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

8.13 Channel Status Data Buffer Control (12h)

BSEL - Selects the data buffer register addresses to contain User data or Channel Status data Default = ‘0’ 0 - Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data 765 4 3 2 1 0 TSLIP1 0 0 0 0 0 EFTC1 0 TSLIP0 0 0 0 0 0 EFTC0 0 765 4 3 2 1 0 000 0 0 E F T U M 0 0 765 4 3 2 1 0 000 0 0 E F T U 1 0 0 000 0 0 E F T U 0 0 0 765 4 3 2 1 0 0 0 BSEL 0 0 EFTCI CAM 0

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Note: There are separate complete buffers for the Channel Status and User bits. This control bit deter- mines which buffer appears in the address space. EFTCI - E to F C-data buffer transfer inhibit bit. Default = ‘0’ 0 - Allow C-data E to F buffer transfers 1 - Inhibit C-data E to F buffer transfers CAM - C-data buffer control port access mode bit Default = ‘0’ 0 - One-Byte Mode 1 - Two-Byte Mode

8.14 User Data Buffer Control (13h)

UD - User bit data source specifier Default = ‘0’ 0 - U Pin is the source of transmitted U data 1 - U data buffer is the source of transmitted U data UBM1:0 - Sets the operating mode of the AES3 User bit manager Default = ‘00’ 00 - Transmit all zeros mode 01 - Block Mode 10 - Reserved 11 - Reserved EFTUI - E to F U-data buffer transfer inhibit bit (valid in Block Mode only). Default = ‘0’ 0 - Allow U-data E to F buffer transfers 1 - Inhibit U-data E to F buffer transfers

8.15 Channel Status Bit or User Bit Data Buffer (20h - 37h)

Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to Block Mode) is accessible through these register addresses. 8.16 CS8406 I.D. and Version Re gister (7Fh) (Read Only) ID[3:0] - ID code for the CS8406. Permanently set to 1110 VER[3:0] = 0001 (revision A) VER[3:0] = 0010 (revision B) 7 6 54321 0 0 0 0 UD UBM1 UBM0 0 EFTUI 7 6 543210 ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0

1. PIN DESCRIPTION - SOFTWARE MODE SDA / CDOUT SCL / CCLK AD0 / CS AD1 / CDIN AD2 TXP RXP TXN TSTN H/S VD VL TEST GND TEST OMCK RST U TEST INT TEST TEST ILRCK TEST ISCLK TEST SDIN TCBL 82 1 12 17 14 15 Top-Down (Through Package) View 28-Pin QFN Package 8 9 10 11 12 14 222324252628 SCL / CCLK AD1 / CDIN TXP TXN H/S VL TEST RST TEST TEST ILRCK SDA / CDOUT AD0 / CS AD2 RXP TSTN OMCK U INT TEST TEST Thermal Pad VD ISCLK TEST GND TEST SDIN TCBL

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VD 6 Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. VL 23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. GND 22 Ground (Input) - Ground for I/O and core logic. RST 9 Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are sta- ble in frequency and phase. This is particularly true in Hardware Mode with multiple CS8406 devices, where synchronization between devices is important. H/S 24 Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation of the CS8406, and the method of accessing CS and U data. In Software Mode, device control and CS and U data access is primarily through the control port, using a microcontroller. To select Software Mode, this pin should be permanently tied to GND. TXN TXP Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled low while the CS8406 is in the reset state. OMCK 21 Master Clock (Input) - The frequency can be set through the control port registers. ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin. SDA/CDOUT 1 Serial Control Data I/O (I²C Mode) / Data Out (SPI) (Input/Output) - In I²C Mode, SDA is the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL. In SPI Mode, CDOUT is the output data from the control port interface on the CS8406 SCL/CCLK 28 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8406. In I²C Mode, SCL requires an external pull-up resistor to VL. AD0/CS 2 Address Bit 0 (I²C Mode) / Control Port Chip Select (SPI) (Input) - A falling edge on this pin puts the CS8406 into SPI Control Port Mode. With no falling edge, the CS8406 defaults to I²C Mode. In I²C Mode, AD0 is a chip address pin. In SPI Mode, CS is used to enable the control port interface on the CS8406 AD1/CDIN 27 Address Bit 1 (I²C Mode) / Serial Control Data in (SPI) (Input) - In I²C Mode, AD1 is a chip address pin. In SPI Mode, CDIN is the input data line for the control port interface. AD2 3 Address Bit 2 (I²C Mode) (Input) - Determines the AD2 address bit for the control port in I²C Mode, and should be connected to GND or VL. If SPI Mode is used, the AD2 pin should be connected to either GND or VL. RXP 4 Auxiliary AES3 Receiver Port (Input) - Input for an alternate, already AES3 coded, audio data source. INT 19 Interrupt (Output) - Indicates key events during the operation of the CS8406. All bits affecting INT may be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt are readable in the control registers. The polarity of the INT output, as well as selection of a standard or open drain output, is set through a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero. TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. U 20 User Data (Input) - May optionally be used to input User data for transmission by the AES3 transmitter, see Figure 4 for timing information. If not driven, a 47 kΩ pull-down resistor is recommended for the U pin. If the U pin is driven by a logic level output, a 100 Ω series resistor is recommended. TSTN 5 Test In (Input) - This pin is an input used for test purposes. It must be tied to ground for normal operation.

Test Pins - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left floating, how- ever current consumption from VL will increase by 25 μA per TEST pin that is left floating. Thermal Pad - Thermal Pad (QFN package only) - Thermal relief pad for optimized heat dissipation. This pad must be electrically connected to GND. See“Power Supply, Grounding, and PCB layout” on page 33 for more information.

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selected by connecting the H/S pin to VL. The flexibility of the CS8406 is necessarily limited in Hardware Mode. Various pins change function as described in the Hardware Mode pin description section.

10.1 Channel Status, User and Validity Data

pins map to channel status bits. In Consumer Mode, the transmitted category code is set to General (00h). ILRCK. Figure 9 shows the timing requirements. Power supply pins are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 13. Hardware Mode Data Flow

10.2 Serial Audio Port

11 P R O = 1

Table 2. Hardware Mode COPY/C and ORIG Pin Functions Table 3. Hardware Mode Serial Audio Port Format Selection Table 4. Hardware Mode OMCK Clock Ratio Selection Table 5. Equivalent Register Settings of Serial Audio Input Formats in Hardware Mode

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11.PIN DESCRIPTION - HARDWARE MODE COPY / C ORIG TEST HWCK1 EMPH TXP SFMT0 TXN SFMT1 H/S VD VL TEST GND TEST OMCK RST HWCK0 APMS AUDIO TCBLD U ILRCK V ISCLK CEN SDIN TCBL 82 1 12 17 14 15 Top-Down (Through Package) View 28-Pin QFN Package 8 9 10 11 12 14 222324252628 ORIG HWCK1 TXP TXN H/S VL TEST RST APMS TCBLD ILRCK COPY / C TEST EMPH SFMT0 SFMT1 OMCK HWCK0 AUDIO V CEN Thermal Pad VD ISCLK U GND TEST SDIN TCBL

VD 6 Digital Power (Input) - Digital core power supply. Typically +3.3 V or +5.0 V. VL 23 Logic Power (Input) - Input/Output power supply. Typically +3.3 V or +5.0 V. GND 22 Ground (Input) - Ground for I/O and core logic. RST 9 Reset (Input) - When RST is low, the CS8406 enters a low power mode and all internal states are reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in Hardware Mode with multiple CS8406 devices, where synchronization between devices is important. H/S 24 Hardware/Software Control Mode Select (Input) - Determines the method of controlling the operation of the CS8406, and the method of accessing CS and U data. Hardware Mode provides an alternate mode of operation, and access to CS and U data is provided by dedicated pins. To select Hardware Mode, this pin should be permanently tied to VL. TXN TXP Differential Line Drivers (Output) - These pins transmit biphase encoded data. The drivers are pulled low while the CS8406 is in the reset state. OMCK 21 Master Clock (Input) - The frequency can be set through the HWCK[1:0] pins. ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin. SFMT0 SFMT1 Serial Audio Data Format Select (Input) - Selects the serial audio input port format. See Table 3 on page 29. APMS 10 Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL to set serial audio input port as a master or connected to GND to set the port as a slave. HWCK0 HWCK1 OMCK Clock Ratio Select (Input) - Selects the ratio of OMCK to the input sample rate (Fs). A pull-up to VL or pull-down to GND is required to set the appropriate mode. See Table 4 on page 29. TCBLD 11 Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL to set TCBL as an output. Connect TCBLD to GND to set TCBL as an input. TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block. CEN 16 C Bit Enable (Input) - Determines how the channel status data bits are input. When CEN is low, Hard- ware Mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When CEN is high, Hardware Mode B is selected, where the COPY/C pin is used to enter serial channel status data. V 17 Validity Bit (Input) - In Hardware Modes A and B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. U 18 User Data Bit (Input) - In Hardware Modes A and B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. COPY/C 1 COPY Channel Status Bit/C Bit (Input) - In Hardware Mode A (CEN = 0), the COPY/C and ORIG pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2 on page 29. In Hardware Mode B, the COPY/C pin becomes the direct C bit input data pin, which is sampled on both edges of LRCK. EMPH 3 Pre-Emphasis Indicator (Input) - In Hardware Mode A (CEN = 0), the EMPH pin low sets the 3 empha- sis channel status bits to indicate 50/15μs pre-emphasis of the transmitted audio data. If EMPH is high, then the three EMPH channel status bits are set to 000, indicating no pre-emphasis. AUDIO 19 Audio Channel Status Bit (Input) - In Hardware Mode A (CEN = 0), the AUDIO pin determines the state of the audio/non audio Channel Status bit in the outgoing AES3 data stream. ORIG 28 ORIG Channel Status Bit Control (Input) - In Hardware Mode A (CEN = 0), the ORIG and COPY/C pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2 on page 29.

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Test Pins (Input) - These pins are unused inputs. It is recommended that these pins be tied to a supply (VL or GND) to minimize leakage current. The CS8406 will operate correctly if these pins are left float- ing, however current consumption from VL will increase by 25 μA per TEST pin that is left floating. Thermal Pad - Thermal Pad (QFN package only) - Thermal relief pad for optimized heat dissipation. This pad must be electrically connected to GND. See“Power Supply, Grounding, and PCB layout” on page 33 for more information.

12.APPLICATIONS

12.1 Reset, Power Down and Start-Up

When RST is low, the CS8406 enters a low power mode and all internal states are reset, including the con- trol port and registers, and the outputs ar e disabled. In Software Mode when RST is high, the control port becomes operational and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state and begin operation. In Hardware Mode when RST is high, the part will automatically leave the low power state and begin operation.

12.2 ID Code and Revision Code

The CS8406 has a register that contains a four-bit code to indicate that the addressed device is a CS8406. This is useful when other CS84XX family members ar e resident in the same or similar systems, allowing common software modules. The CS8406 four-bit revision level code is also available. This allows the software driver for the CS8406 to identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future revisions, it is strongly recommended that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known.

12.3 Power Supply, Ground ing, and PCB layout

be set independently. Follow normal supply decoupling practices, see Figures 5 and 6. The VD and VL sup- plies should be decoupled with a 0.1μF capacitor to GND to minimize AES3 transmitter induced transients. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decoupling capacitors are recommended. Decoupling capacitors should be mounted on the same side of the board as the CS8406 to minimize inductance effects, and all decoupling capacitors should be as close to the CS8406 as possible. The CS8406 is available in the compact QFN package. The underside of the QFN package reveals a metal pad; this pad must mate with an equally dimensioned copper pad on the PCB and must be electrically con- nected to ground. A series of vias should be used to connect this copper pad to one or more ground planes on other PCB layers.

12.4 Synchronization of Multiple CS8406s

The AES3 transmitters of multiple CS8406s can be synchronized if all devices share the same master clock, TCBL, and RST signals. The TCBL pin is used to synchron ize multiple CS8406 AES3 transmitters at the channel status block boundaries. One CS8406 must have its TCBL set to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived from external logic, whereby all CS8406 devices should be set to slave TCBL.

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13.PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-013 Controlling Dimension is Millimeters 28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE e

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/ intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not re- duce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

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Note: 1. Dimensioning lead width applie s to the metallized terminal and is measured betw een 0.15 mm and 0.25 mm from the terminal tip. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-220 Controlling Dimension is Millimeters. PIN #1 CORNER LA eb D

1.00 REF

PIN #1 IDENTIFIER LASER MARKING E TOP VIEW SIDE VIEW BOTTOM VIEW 28L QFN (4.00 mm BODY) PACKAGE DRAWING

14.ORDERING INFORMATION Product Description Pb-Free Package Grade Temp Range Container Order# CS8406 192 kHz Digital Audio Transmitter YES SOIC Commercial -10º to +70ºC Rail CS8406-CSZ Tape and Reel CS8406-CSZR Automotive -40º to +85ºC Rail CS8406-DSZ Tape and Reel CS8406-DSZR TSSOP Commercial -10º to +70ºC Rail CS8406-CZZ Tape and Reel CS8406-CZZR Automotive -40º to +85ºC Rail CS8406-DZZ Tape and Reel CS8406-DZZR QFN Commercial -10º to +70ºC Rail CS8406-CNZ Tape and Reel CS8406-CNZR Automotive -40º to +85ºC Rail CS8406-DNZ Tape and Reel CS8406-DNZR CDB8416 CS8406 & CS8416 Evaluation Board - - - - CDB8416

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15.1 AES3 Transmitter External Components

protected, has the proper source impedance, and provides a 5 V peak-to-peak signal into a 110 Ω load. with pin 1 of the connector grounded. and change 90.9 Ω to 107 Ω. The connector for a consumer app lication would be an RCA phono socket. This circuit is also short circuit protected. also useful when driving multiple digital audio outputs since RS422 line drivers have TTL compatible inputs.

15.2 Isolating Transformer Requirements

Figure 14. Professional Output Circuit Figure 15. Consumer Output Circuit (VL = 5.0 V) Figure 16. TTL/CMOS Output Circuit

manage the C and U data through the control port.

16.1 AES3 Channel Status(C) Bit Management

nel status information are buffered at the input, synchronized to the output timebase, and then transmitted. The buffering scheme involves a cascade of 2 block-sized buffers, named E and F, as shown in Figure 17. (which is at control port address 20h) is the consumer/professional bit for channel status block A. as the source of C data for the AES3 transmitter. The F buffer accepts block transfers from the E buffer.

16.1.1 Accessing the E buffer

transfers occur. This allows determination of the allowable time periods to interact with the E buffer. bit. This may be used whenever “long” control port interactions are occurring. after a E to F transfer, which is based on the output timebase. Figure 17. Channel Status Data Buffer Structure

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16.1.2 Serial Copy Mana gement System (SCMS)

bit and L bit appropriately.

16.1.3 Channel Status Data E Buffer Access

LS Byte is the B channel data (see Figure 17). desired mode is selected through a control register bit.

16.1.3.1 One-Byte Mode

to its control port. This byte will be written to both the A and B locations in the addressed word. Figure 18. Flowchart for Writing the E Buffer

16.1.3.2 Two-Byte Mode

There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, Two-Byte Mode should be used to access the E buffer. In this mode, a read will cause the CS 8406 to output two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8406's control port. The A channel status data is first; B channel status data second.

16.2 AES3 User (U) Bit Management

The CS8406 U bit manager has two operating modes: Mode 1. Transmit all zeros. Mode 2. Block mode.

16.2.1 Mode 1: Transmit All Zeros

Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents. This mode is intended for the user who wants the output U channel to contain no data.

16.2.2 Mode 2: Block Mode

Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered using 2 block-sized RAMs to perform the buffering. The user has access to the first buffer, denoted the E buffer, through the control port. It is the only mode in which the user can merge his own U data into the transmit- ted AES3 data stream. The U buffer access only operates in Two-Byte Mode, since there is no concept of A and B blocks for user data. The arrangement of the data is as followings: Bit15[A7] Bit14[B7] Bit13[A6] Bit12 [B6]...Bit1 [A0] Bit0[B0]. The arrangement of the data in the each byte is that the MSB is the first transmitted bit. The bit for the A subframe is followed by the bit for the B subframe.

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17.REVISION HISTORY Release Date Changes F3 July 2005 - Updated Packaging Information to include Lead Free devices and updated “Table of Contents” on page 2. F4 April 2006 - Removed references to “Autoincrement” feature in “Control Port Description” on page 16. Indicated that the MAP will always increment. - Corrected definition of pin 5 in “Pin Description - Software Mode” on page 25. F5 October 2009 - Added QFN package option to “General Description” on page 1, “Package Dimen- sions” on page 34, and “Ordering Information” on page 37. - Added QFN pin-out drawing and thermal pad description to “Pin Description - Software Mode” on page 25 and “Pin Description - Hardware Mode” on page 30. - Added QFN thermal pad guidelines to “Power Supply, Grounding, and PCB layout” on page 33. Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest to you, go to www.cirrus.com IIMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER’S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD- ING ATTORNEYS’ FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I²C is a trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc.