CS8405

CS8405A CIRRUS | Alldatasheet

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Features

/circle6 Complete EIAJ CP1201, IEC-60958, AES3, S/PDIF compatible transmitter /circle6 +5 V Digital Supply(VD) /circle6 +3 V to 5 V Digital Interface (VL) /circle6 On-chip Channel Status and User bit buffer memories allow block sized updates /circle6 Flexible 3-wire serial digital audio input port /circle6 Up to 96 kHz frame rate /circle6 Microcontroller write access to Channel Status and User bit data /circle6 On-chip differential line driver /circle6 Generates CRC codes and parity bits /circle6 Standalone mode allows use without a microcontroller General Description The CS8405A is a monolithic CMOS device which en- codes and transmits audio data according to the AES3, IEC60958, S/PDIF, or EIAJ CP1201. The CS8405A ac- cepts audio and digital data, which is then multiplexed, encoded and driven onto a cable. The audio data is input through a configurable, 3-wire in- put port. The channel status and user bit data are input through an SPI or Two-Wire microcontroller port, and may be assembled in block sized buffers. For systems with no microcontroller, a stand alone mode allows di- rect access to channel status and user bit data pins. Target applications include A/V Receivers, CD-R, DVD receivers, digital mixing consoles, effects processors, set-top boxes, and computer and automotive audio systems.

ORDERING INFORMATION

CS8405A-CS 28-pin SOIC -10 to +70°C CS8405A-CZ 28-pin TSSOP -10 to +70°C CS8405A-IS 28-pin SOIC -40 to +85°C CS8405A-IZ 28-pin TSSOP -40 to +85°C CDB8415A Evaluation Board I Serial Audio Input Misc. Control AES3 S/PDIF Encoder C&Ub i t Data Buffer Control Port & Registers Output Clock Generator RXP ILRCK ISCLK SDIN TXP TXN RST OMCKUT C B L S D A / CDOUT SCL/ CCLK AD1/ CDIN AD0/ CS INT VL+ DGND Driver AD2H/S VD+ JUN ‘02 DS469PP4

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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. "Advance" product infor- mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the infor- mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, tradesecrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in thism a - terial and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. An export license and/or quota needs tobe obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT- ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners.

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1. CHARACTERISTICS AND SPECIFICATIONS POWER AND THERMAL CHARACTERISTICS (DGND = 0 V, all voltages with respect to ground) Notes: 1. -CS’ and ‘-CZ’ parts are specified to operate over -10 ° C to 70° C but are tested at 25° C only. 2. ‘- IS’ and ‘-IZ’ parts are tested over the full -40°C to 85°C temperature range. ABSOLUTE MAXIMUM RATINGS (DGND = 0V, all voltages with respect to ground) Notes: 3. Transient currents of up to 100 mA will not cause SCR latch-up. Parameter Symbol Min Typ Max Units Power Supply Voltage VD+ VL+ 4.5 2.85 5.0 5.5 5.5 V V Supply Current at 48 kHz frame rate VD+ VL+ = 3V VL+ = 5V 6.3 30.1 46.5 mA mA mA Supply Current at 96 kHz frame rate VD+ VL+ = 3V VL+ = 5V 6.6 44.8 76.6 mA mA mA Supply Current in power down Reset high, VD+ Reset high, VL+ = 3V Reset high, VL+ = 5V µA µA µA Ambient Operating Temperature:CS8405-CS & -CZ (Note 1) CS8405-IS & -IZ (Note 2) T A -10 -40 25 70 Parameter Symbol Min Max Units Power Supply Voltage VD/VL+ - 6.0 V Input Current, Any Pin Except Supply (Note 3) I in -± 1 0 m A Input Voltage V in -0.3 (VL+) + 0.3 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C

(TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%) Notes: 4. At 5V mode, V IL = 0.8V (Max), at 3V mode, V IL =0.4V (Max). SWITCHING CHARACTERISTICS (TA = 25 °C for suffixes ‘CS’ &’CZ’, TA = -40 to 85°C for ‘IS’ & ‘IZ’ ; VD+ = 5V±10%, VL+ = 3/5V ±5/10%, Inputs: Logic 0 = 0 V, Logic 1 = VL+; C L =2 0p F ) Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 2.0 - (VL+) + 0.3 V Low-Level Input Voltage (Note 4) V IL -0.3 - 0.4/0.8 V Low-Level Output Voltage, (Io=-3.2 mA), except TXP, TXN V OL -- 0 . 4 V High-Level Output Voltage, (Io=3.2 mA), except TXP , TXN V OH (VL+) - 1 - - V Input Leakage Current I in -± 1 ± 1 0 µA Output High Voltage, TXP , TXN (IOH = 14 mA) (VL+) - 0.7 (VL+) - 0.4 - V Output Low Voltage, TXP, TXN (I OL =1 4m A ) - 0 . 4 0 . 7 V Parameter Symbol Min Typ Max Units RST pin Low Pulse Width 200 - - µs OMCK Frequency for OMCK = 512*Fs 4.1 - 55.3 MHz OMCK Low and High Width for OMCK = 512*Fs 7.2 - - ns OMCK Frequency for OMCK = 384*Fs 3.1 - 41.5 MHz OMCK Low and High Width for OMCK = 384*Fs 9.6 - - ns OMCK Frequency for OMCK = 256*Fs 2.0 - 27.7 MHz OMCK Low and High Width for OMCK = 256*Fs 14.4 - - ns Frame Rate 8.0 - 108.0 kHz AES3 Transmitter Output Jitter - - 1 ns

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Notes: 5. The active edge of ISCLK is programmable.

1. The polarity of ILRCK is programmable.
2. No more than 128 SCLK per frame.
3. This delay is to prevent the previous ISCLK edge from being interpreted as the first one after ILRCK has
4. This setup time ensures that this ISCLK edge is interpreted as the first one after ILRCK has changed.

Figure 1. Audio Port Master Mode Timing Figure 2. Audio Port Slave Mode and Data Input Timing

be safe for all possible conditions.

1. Data must be held for sufficient time to bridge the transition time of CCLK.

Figure 3. SPI Mode timing

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Notes: 13. Two-Wire Mode is compatible with the I 2C® protocol and is supported only at 5V mode.

1. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.

Figure 4. Two-Wire Mode timing

1. TYPICAL CONNECTION DIAGRAM

Figure 5. Recommended Connection Diagram for Software Mode

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1. GENERAL DESCRIPTION The CS8405A is a monolithic CMOS device which encodes and transmits audio data according to the AES3, IEC60958, S/PDIF, and EIAJ CP1201 inter- face standards. The CS8405A accepts audio, chan- nel status and user data, which is then multiplexed, encoded, and driven onto a cable. The audio data is input through a configurable, 3- wire input port. The channel status bits and user bit data are input through an SPI or Two-Wire Mode microcontroller port and may be assembled in sep- arate block sized buffers. For systems with no microcontroller, a stand alone mode allows direct access to channel status and user data input pins. Target applications include CD-R, DAT, DVD, MD and VTR equipment, mixing consoles, digital audio transmission equipment, high quality A/D converters, effects processors, set-top TV boxes, and computer audio systems. Figure 5 shows the supply and external connec- tions to the CS8405A when configured for opera- tion with a microcontroller.

3.1 AES3 and S/PDIF Standards

This data sheet assumes that the user is familiar with the AES3 and S/PDIF data formats. It is advis- able to have current copies of the AES3 and IEC60958 specifications on hand for easy refer- ence. The latest AES3 standard is available from the Au- dio Engineering Society or ANSI at www.aes.org or www.ansi.org. Obtain the latest IEC60958 stan- dard from ANSI or from the International Electro- technical Commission at www.iec.ch. The latest EIAJ CP-1201 standard is available from the Japa- nese Electronics Bureau. Crystal Application Note 22: Overview of Digital Audio Interface Data Structures contains a useful tutorial on digital audio specifications, but it should not be considered a substitute for the standards. The paper An Understanding and Implementation of the SCMS Serial Copy Management System for Digital Audio Transmission, by Clifton Sanchez, is an excellent tutorial on SCMS. It is available from the AES as preprint 3518. 4. THREE-WIRE SERIAL INPUT AUDIO PORT A 3-wire serial audio input port is provided. The in- terface format can be adjusted to suit the attached device through the control registers. The following parameters are adjustable:

• M a s t e ro rs l a v e  Serial clock frequency  Audio data resolution  Left or right justification of the data relative to left/right clock  Optional one-bit cell delay of the first data bit  Polarity of the bit clock  Polarity of the left/right clock. (By setting the appropriate control bits, many formats are pos- sible). Figure 6 shows a selection of common input for- mats with the corresponding control bit settings. In master mode, the left/right clock and the serial bit clock are outputs, derived from the OMCK in- put pin master clock. In slave mode, the left/right clock and the serial bit clock are inputs. The left/right clock must be syn- chronous to the OMCK master clock, but the serial bit clock can be asynchronous and discontinuous if required. The left/right clock should be continuous, but the duty cycle can be less than the specified typ- ical value of 50% if enough serial clocks are present in each phase to clock all the data bits.

Figure 6. Serial Audio Input Example Formats

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1. AES3 TRANSMITTER The CS8405A includes an AES3 digital audio transmitter. A comprehensive buffering scheme provides write access to the channel status and user data. This buffering scheme is described in “Ap- pendix B: Channel Status and User Data Buffer Management” on page 34. The AES3 transmitter encodes and transmits audio and digital data according to the AES3, IEC60958 (S/PDIF), and EIAJ CP-1201 interface standards. Audio and control data are multiplexed together and bi-phase mark encoded. The resulting bit stream is driven to an output connector either di- rectly or through a transformer. The transmitter is clocked from the clock input pin, OMCK. If OMCK is asynchronous to the data source, an in- terrupt bit(TSLIP) is provided that will go high ev- ery time a data sample is dropped or repeated. Be aware that the pattern of slips does not have hyster- esis and so the occurrence of the interrupt condition is not deterministic. The channel status (C) and user (U) bits in the transmitted data stream are taken from storage ar- eas within the CS8405A. The user can manually access the internal storage or configure the CS8405A to run in one of several automatic modes. “Appendix B: Channel Status and User Data Buffer Management” on page 34 provides detailed de- scriptions of each automatic mode and describes methods of manually accessing the storage areas. The transmitted user bit data can optionally be in- put through the U pin, under the control of a control port register bit. Figure 7 shows the timing require- ments for inputting U data through the U pin.

5.1 Transmitted Frame and Channel

The TCBL pin is used to control or indicate the start of transmitted channel status block boundaries and may be an input or an output. In some applications, it may be necessary to control the precise timing of the transmitted AES3 frame boundaries. This may be achieved in two ways: a) With TCBL set to input, driving TCBL high for >3 OMCK clocks will cause a frame start, as well as a new channel status block start. b) If the serial audio input port is in slave mode and TCBL is set to output, the start of the A channel sub-frame will be aligned with the leading edge of ILRCK.

5.2 TXN and TXP Drivers

The line drivers are low skew, low impedance, dif- ferential outputs capable of driving cables directly. Both drivers are set to ground during reset (RST low), when no AES3 transmit clock is provided, and optionally under the control of a register bit. The CS8405A also allows immediate muting of the AES3 transmitter audio data through a control reg- ister bit. External components are used to terminate and iso- late the external cable from the CS8405A. These components are detailed in “Appendix A: External AES3/SPDIF/IEC60958 Transmitter Compo- nents” on page 33.

5.3 Mono Mode Operation

An AES3 stream may be used in more than one way to transmit 96 kHz sample rate data. One method is to double the frame rate of the current format. This results in a stereo signal with a sample rate of 96 kHz, carried over a single twisted pair ca- ble. An alternate method is implemented using the two sub-frames in a 48 kHz frame rate AES3 signal to carry consecutive samples of a mono signal, re- sulting in a 96 kHz sample rate stream. This allows older equipment, whose AES3 transmitters and re- ceivers are not rated for 96 kHz frame rate opera- tion, to handle 96 kHz sample rate information. In this “mono mode”, two AES3 cables are needed for stereo data transfer. The CS8405A offers mono

mode by the MMT control bit. channel status block transmitted is also selectable. VLRCK is a virtual word clock, which may not exist, and is used to illustrate the CUV timing. In stereo mode, VLRCK frequency = AES3 frame rate. In mono mode, ALRCK frequency = 2xAES3 frame rate. Figure 7. AES3 Transmitter Timing for C, U, and V Pin Input Data

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respect to the audio sample rate. Wire, with the CS8405A acting as a slave device.

6.1 SPI Mode

OUT is the output data line to the microcontroller. or low with a 47 kΩ resistor, if desired. Figure 8. Control Port Timing in SPI Mode

6.2 Two-Wire Mode

bits of the seven-bit address field are fixed at 0010. from the CS8405A after each input byte is read. Wire Mode is compatible with the I2C protocol.

6.3 Interrupts

crocontroller interrupt input pin.

0010 AD2-0 R/W

Figure 9. Control Port Timing in Two-Wire Mode

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1. CONTROL PORT REGISTER SUMMARY

7.1 MEMORY ADDRESS POINTER (MAP)

test modes, which can completely alter the normal operation of the CS8405A.

0 Reserved 0 0 0 0 0 0 0 0

1 Control 1 0 VSET 0 MUTEAES 0 INT1 INT0 TCBLD

2 Control 2 0 0 0 0 0 MMT MMCST MMTLR

3 Data Flow Control 0 TXOFF AESBP 0 0 0 0 0

4 Clock Source Control 0 RUN CLK1 CLK0 0 0 0 0

5 Serial Input Format SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

6 Reserved 0 0 0 0 0 0 0 0

7 Interrupt 1 Status TSLIP 0 0 0 0 0 EFTC 0

8 Interrupt 2 Status 0 0 0 0 0 EFTU 0 0

9 Interrupt 1 Mask TSLIPM 0 0 0 0 0 EFTCM 0

12 CS Data Buffer Control 0 0 BSEL 0 0 EFTCI CAM 0

13 U Data Buffer Control 0 0 0 UD UBM1 UBM0 0 EFTUI

Table 1. Control Register Map Summary

1. CONTROL PORT REGISTER BIT DEFINITIONS

8.1 Control 1 (1h)

VSET - Transmitted Validity bit level Default = ‘0’ 0 - Indicates data is valid, linear PCM audio data 1 - Indicates data is invalid or not linear PCM audio data MUTEAES - Mute control for the AES transmitter output Default = ‘0’ 0 - Not Muted 1-M u t e d INT1:INT0 - Interrupt output pin (INT) control Default = ‘00’ 00 - Active high; high output indicates interrupt condition has occurred 01 - Active low, low output indicates an interrupt condition has occurred 10 - Open drain, active low. Requires an external pull-up resistor on the INT pin. 11 - Reserved TCBLD - Transmit Channel Status Block pin (TCBL) direction specifier Default = ‘0’ 0-T C B Li sa ni n p u t 1 - TCBL is an output 7 6 543210

0 VSET 0 MUTEAES 0 INT1 INT0 TCBLD

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8.2 Control 2 (2h)

MMT - Select AES3 transmitter mono or stereo operation Default = ‘0’ 0 - Normal stereo operation 1 - Output either left or right channel inputs into consecutive subframe outputs (mono mode, left or right is determined by MMTLR bit) MMTCS - Select A or B channel status data to transmit in mono mode Default = ‘0’ 0 - Use channel A CS data for the A subframe and use channel B CS data for the B subframe 1 - Use the same CS data for both the A and B subframe outputs. If MMTLR = 0, use the left channel CS data. If MMTLR = 1, use the right channel CS data. MMTLR - Channel Selection for AES Transmitter mono mode Default = ‘0’ 0 - Use left channel input data for consecutive subframe outputs 1- Use right channel input data for consecutive subframe outputs

8.3 Data Flow Control (3h)

The Data Flow Control register configures the flow of audio data. The output data should be muted prior to changing bits in this register to avoid transients. TXOFF - AES3 Transmitter Output Driver Control Default = ‘0 0 - AES3 transmitter output pin drivers normal operation 1 - AES3 transmitter output pin drivers drive to 0 V. AESBP - AES3 bypass mode selection Default = ‘0’ 0 - Normal operation 1 - Connect the AES3 transmitter driver input directly to the RXP pin, which becomes a normal TTL threshold digital input. 7 6 543210 0 0 0 0 0 MMT MMTCS MMTLR 7 6 543210

0 T X O F F A E S B P 00000

8.4 Clock Source Control (4h)

This register configures the clock sources of various blocks. In conjunction with the Data Flow Control register, var- ious Receiver/Transmitter/Transceiver modes may be selected. RUN - Controls the internal clocks, allowing the CS8405A to be placed in a “powered down” low current consumption, state. Default = ‘0’ 0 - Internal clocks are stopped. Internal state machines are reset. The fully static control port registers are operational, allowing registers to be read or changed. Reading and writing the U and C data buffers is not possible. Power consumption is low. 1 - Normal part operation. This bit must be set to 1 to allow the CS8405A to begin operation. All input clocks should be stable in frequency and phase when RUN is set to 1. CLK1:0 - Output master clock (OMCK) input frequency to output sample rate (Fs) ratio selector. If these bits are changed during normal operation, then always stop the CS8405A first (RUN = 0), write the new value, then start the CS8405A (RUN = 1). Default = ‘00’ 00 - OMCK frequency is 256*Fs 01 - OMCK frequency is 384*Fs 10 - OMCK frequency is 512*Fs 11 - Reserved

8.5 Serial Audio Input Port Data Format (5h)

SIMS - Master/Slave Mode Selector Default = ‘0’ 0 - Serial audio input port is in slave mode 1 - Serial audio input port is in master mode SISF - ISCLK frequency (for master mode) Default = ‘0’ 0-6 4 * F s 1 - 128*Fs SIRES1:0 - Resolution of the input data, for right-justified formats Default = ‘00’ 00 - 24-bit resolution 01 - 20-bit resolution 10 - 16-bit resolution 11 - Reserved 7 6 543210

0 R U N C L K 1 C L K 0 0000

SIMS SISF SIRES1 SIRES0 SIJUST SIDEL SISPOL SILRPOL

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SIJUST - Justification of SDIN data relative to ILRCK Default = ‘0’ 0 - Left-justified 1 - Right-justified SIDEL - Delay of SDIN data relative to ILRCK, for left-justified data formats Default = ‘0’ 0 - MSB of SDIN data occurs in the first ISCLK period after the ILRCK edge (left justified mode) 1 - MSB of SDIN data occurs in the second ISCLK period after the ILRCK edge (I 2S mode) SISPOL - ISCLK clock polarity Default = ‘0’ 0 - SDIN sampled on rising edges of ISCLK 1 - SDIN sampled on falling edges of ISCLK SILRPOL - ILRCK clock polarity Default = ‘0’ 0 - SDIN data is for the left channel when ILRCK is high 1 - SDIN data is for the right channel when ILRCK is high

8.6 Interrupt 1 Status (7h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00h. TSLIP - AES3 transmitter source data slip interrupt In data flows where OMCK, which clocks the AES3 transmitter, is asynchronous to the data source, this bit will go high every time a data sample is dropped or repeated. When TCBL is an input, this bit will go high on receipt of a new TCBL signal. EFTC - E to F C-buffer transfer interrupt. The source for this bit is true during the E to F buffer transfer in the C bit buffer management process. 7 6 543210 T S L I P 0 0000 E F T C 0

8.7 Interrupt 2 Status (8h) (Read Only)

For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register. Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true. Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults to 00h. EFTU - E to F U-buffer transfer interrupt. (Block Mode only) The source of this bit is true during the E to F buffer transfer in the U bit buffer management process.

8.8 Interrupt 1 Mask (9h)

The bits of this register serve as a mask for the Interrupt 1 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in Interrupt 1 register. This register defaults to 00h.

8.9 Interrupt 1 Mode MSB (Ah) and Interrupt 1 Mode LSB(Bh)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be- comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in- terrupt condition. Be aware that the active level(Actice High or Low) only depends on the INT[1:0] bits. These regis- ters default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

8.10 Interrupt 2 Mask (Ch)

The bits of this register serve as a mask for the Interrupt 2 register. If a mask bit is set to 1, the error is unmasked, meaning that its occurrence will affect the INT pin and the status register. If a mask bit is set to 0, the error is masked, meaning that its occurrence will not affect the INT pin or the status register. The bit positions align with the corre- sponding bits in Interrupt 2 register. This register defaults to 00h. 7 6 543210 000 0 0 E F T U 0 0 7 6 543210 T S L I P M 0 0000 E F T C M 0 7 6 543210 TSLIP1 0 0 0 0 0 EFTC1 0 TSLIP0 0 0 0 0 0 EFTC0 0 7 6 543210 000 0 0 E F T U M 0 0

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8.11 Interrupt 2 Mode MSB (Dh) and Interrupt Mode 2 LSB(Eh)

The two Interrupt Mode registers form a 2-bit code for each Interrupt Register 1 function. There are three ways to set the INT pin active in accordance with the interrupt condition. In the Rising edge active mode, the INT pin be- comes active on the arrival of the interrupt condition. In the Falling edge active mode, the INT pin becomes active on the removal of the interrupt condition. In Level active mode, the INT interrupt pin becomes active during the in- terrupt condition. Be aware that the active level (Active High or Low) only depends on the INT[1:0] bits. These reg- isters default to 00. 00 - Rising edge active 01 - Falling edge active 10 - Level active 11 - Reserved

8.12 Channel Status Data Buffer Control (12h)

BSEL - Selects the data buffer register addresses to contain User data or Channel Status data Default = ‘0’ 0 - Data buffer address space contains Channel Status data 1 - Data buffer address space contains User data Note: There are separate complete buffers for the Channel Status and User bits. This control bit determines which buffer appears in the address space. EFTCI - E to F C-data buffer transfer inhibit bit. Default = ‘0’ 0 - Allow C-data E to F buffer transfers 1 - Inhibit C-data E to F buffer transfers CAM - C-data buffer control port access mode bit Default = ‘0’ 0-O n eb y t em o d e 1-T w ob y t em o d e 7 6 543210 0 0 0 0 0 EFTU1 0 0 0 0 0 0 0 EFTU0 0 0 7 6 543210 0 0 BSEL 0 0 EFTCI CAM 0

8.13 User Data Buffer Control (13h)

UD - User bit data pin (U) direction specifier Default = ‘0’ 0 - The U pin is an input. The User bit data is latched in on both rising and falling edges of OLRCK. This setting also chooses the U pin as the source for transmitted U data. 1 - The U pin is an output. The received U data is clocked out on both rising and falling edges of ILRCK. This setting also chooses the U data buffer as the source of transmitted U data. UBM1:0 - Sets the operating mode of the AES3 User bit manager Default = ‘00’ 00 - Transmit all zeros mode 01 - Block mode 10 - Reserved 11 - Reserved EFTUI - E to F U-data buffer transfer inhibit bit (valid in block mode only). Default = ‘0’ 0 - Allow U-data E to F buffer transfers 1 - Inhibit U-data E to F buffer transfer

8.14 Channel Status bit or User bit Data Buffer (20h - 37h)

Either the channel status data buffer E or the separate user bit data buffer E (provided UBM bits are set to block mode) is accessible through these register addresses. 8.15 CS8405A I.D. and Version Register (7Fh) (Read Only) ID3:0 - ID code for the CS8405A. Permanently set to 0110 VER3:0 - CS8405A revision level. Revision A is coded as 0001 7 6 543210 0 0 0 UD UBM1 UBM0 0 EFTUI 7 6 543210 ID3 ID2 ID1 ID0 VER3 VER2 VER1 VER0

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1. PIN DESCRIPTION - SOFTWARE MODE SDA/CDOUT 1 Serial Control Data I/O (Two-Wire Mode) / Data Out (SPI) (Input/Output)-I nT w o - W i r eM o d e ,S D Ai s the control I/O data line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode, CDOUT is the output data from the control port interface on the CS8405A AD0/CS

2 Address Bit 0 (Two-Wire Mode) / Control Port Chip Select (SPI) (Input/Output) - A falling edge on

this pin puts the CS8405A into SPI control port mode. With no falling edge, the CS8405A defaults to Two-Wire mode. In Two-Wire mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port interface on the CS8405A AD2 3 Address Bit 2 (Two-Wire Mode) (Input) - Determines the AD2 address bit for the control port in Two- Wire mode, and should be connected to DGND or VL+. If SPI mode is used, the AD2 pin should be con- nected to DGND. RXP 4 Auxiliary AES3 Receiver Port (Input) - Input for an alternate, already AES3 coded, audio data source. DGND2 DGND4 DGND3 DGND Digital Ground (Input) - Ground for the digital section. VD+ VL+ Positive Digital Power (Input) - Typically +5 V. VD+ must be +5 V while VL+ may be operated at 3.3 V RST

9 Reset (Input)-W h e nR S Tis low, the CS8405A enters a low power mode and all internal states are

reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A devices, where synchronization between devices is important. NC1 NC2 NC3 NC4 NC5 No Connect - These pins should not be connected to any signals or PCB trace. They may be driven high and/or low by the CS8405A. ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin. TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block.

INT 19 Interrupt (Output) - Indicates key events during the operation of the CS8405A. All bits affecting INT may be unmasked through bits in the control registers. Indication of the condition(s) that initiated an interrupt are readable in the control registers. The polarity of the INT output, as well as selection of a standard or open drain output, is set through a control register. Once set true, the INT pin goes false only after the interrupt status registers have been read and the interrupt status bits have returned to zero. U 20 User Data (Input/Output) - May optionally be used to input User data for transmission by the AES3 transmitter, see Figure 7 for timing information. Alternatively, the U pin may be set to output, which also selects the internal buffer as the source of transmitted U data. If not driven, a 47 kΩ pull-down resistor is recommended for the U pin, because the default state of the UD direction bit sets the U pin as an input. The pull-down resistor ensures that the transmitted user data will be zero. If the U pin is always set to be an output, thereby causing the U bit manager to be the source of the U data, then the resistor is not nec- essary. The U pin should not be tied directly to ground, in case it is programmed to be an output, and subsequently tries to output a logic high. This situation may affect the long term reliability of the device. If the U pin is driven by a logic level output, then a 100 Ω series resistor is recommended. OMCK 21 Master Clock (Input) - The frequency must be 256x, 384x, or 512x the sample rate. H/S

24 Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation

of the CS8405A, and the method of accessing Channel Status and User bit data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode provides an alternate mode of operation, and access to CS and U data is provided by dedicated pins. This pin should be permanently tied to VL+ or DGND. TXN 25 Differential Line Drivers (Output) - Transmitting AES3 data. Drivers are pulled low while the CS8405A is in the reset state.TXP AD1/CDIN 27 Address Bit 1 (Two-Wire Mode) / Serial Control Data in (SPI) (Input) - In Two-Wire mode, AD1 is a chip address pin. In SPI mode, CDIN is the input data line for the control port interface. SCL/CCLK 28 Control Port Clock (Input) - Serial control interface clock and is used to clock control data bits into and out of the CS8405A. In Two-Wire mode, SCL requires an external pull-up resistor to VL+.

26 DS469PP4

Figure 10. Audio data is input through the serial au- dio input port and routed to the AES3 transmitter.

10.1 Channel Status, User and Validity

10.2 Serial Audio Port Formats

a r es h o w ni nF i g u r e6 . Power supply pins and the reset pin are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details. Figure 10. Hardware Mode

00 PRO=0, COPY=0, L=0 copyright

01 PRO=0, COPY=0, L=1 copyright,

10 PRO=0, COPY=1, L=0

11 PRO=1

Table 2. Hardware Mode COPY/C and ORIG pin

00 Serial Input Format IF1 - Left Justified

01 Serial Input Format IF2 - I2S

10 Serial Input Format IF3 - Right Justified, 24-

11 Serial Input Format IF4 - Right Justified, 16-

Table 3. Hardware Mode Serial Audio Port Format Selection Table 4. Equivalent Register Settings of Serial Audio Input Formats Available in Hardware Mode

28 DS469PP4

1. PIN DESCRIPTION - HARDWARE MODE COPY/C 1 COPY Channel Status Bit/C Bit (Input) - In hardware mode A (CEN = 0), the COPY/C and ORIG pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see Table 2. In hardware mode B, the COPY/C pin becomes the direct C bit input data pin. VL2+ VD+ VL3+ VL+ VL4+ Positive Digital Power (Input) - Typically +5 V. VD+ must be +5 V, the other VL+ pins may be operated at (CEN = 0)+3.3 V EMPH

3 Pre-Emphasis Indicator (Input) - In hardware mode A (CEN = 0), the EMPH pin low sets the 3 empha-

sis channel status bits to indicate 50/15 µs pre-emphasis of the transmitted audio data. If EMPH is high, then the three EMPH channel status bits are set to 000, indicating no pre-emphasis. SFMT0 SFMT1 Serial Audio Data Format Select (Input) - select the serial audio input port format. See T able 3. DGND6 DGND3 DGND Digital Ground (Input) - Ground for the digital section. RST reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are stable in frequency and phase. This is particularly true in hardware mode with multiple CS8405A devices, where synchronization between devices is important. APMS 10 Serial Audio Data Port Master/Slave Select (Input) - APMS should be connected to VL+ to set serial audio input port as a master or connected to DGND to set the port as a slave. TCBLD 11 Transmit Channel Status Block Direction (Input) - Connect TCBLD to VL+ to set TCBL as an output. Connect TCBLD to DGND to set TCBL as an input. ILRCK 12 Serial Audio Input Left/Right Clock (Input/Output) - Word rate clock for the audio data on the SDIN pin. ISCLK 13 Serial Audio Bit Clock (Input/Output) - Serial bit clock for audio data on the SDIN pin. SDIN 14 Serial Audio Data Port (Input) - Audio data serial input pin. TCBL 15 Transmit Channel Status Block Start (Input/Output) - When operated as output, TCBL is high during the first sub-frame of a transmitted channel status block, and low at all other times. When operated as input, driving TCBL high for at least three OMCK clocks will cause the next transmitted sub-frame to be the start of a channel status block.

CEN 16 CB i tE n a b l e(Input) - Determines how the channel status data bits are input. When CEN is low, hard- ware mode A is selected, where the COPY/C, ORIG, EMPH and AUDIO pins are used to enter selected channel status data. When CEN is high, hardware mode B is selected, where the COPY/C pin is used to enter serial channel status data. V 17 Validity Bit (Input) - In hardware modes A and B, the V pin input determines the state of the validity bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. U 18 User Data Bit (Input) - In hardware modes A and B, the U pin input determines the state of the user data bit in the outgoing AES3 transmitted data. This pin is sampled on both edges of the ILRCK. AUDIO 19 Audio Channel Status Bit (Input)-I nh a r d w a r em o d eA( C E N=0 ) ,t h eA U D I Opin determines the state of the audio/non audio Channel Status bit in the outgoing AES3 data stream. OMCK 21 Master Clock (Input) - The frequency must be only 256x the sample rate. H/S 24 Hardware/Software Control Mode Select (Input) -Determines the method of controlling the operation of the CS8405A, and the method of accessing CS and U data. In software mode, device control and CS and U data access is primarily through the control port, using a microcontroller. Hardware mode pro- vides an alternate mode of operation, and access to CS and U data is provided by dedicated pins. This pin should be permanently tied to VL+ or DGND. TXN TXP Differential Line Drivers (Output) - Transmitting AES3 data. The drivers are pulled low while the CS8405A is in the reset state. ORIG 28 ORIG Channel Status Bit Control (Input) - In hardware mode A (CEN = 0), the ORIG and COPY/C pins determine the state of the Copyright, Pro, and L Channel Status bits in the outgoing AES3 data stream, see T able 2.

30 DS469PP4

1. APPLICATIONS

12.1 Reset, Power Down and Start-up

When RST is low, the CS8405A enters a low pow- er mode and all internal states are reset, including the control port and registers, and the outputs are disabled. When RST is high, the control port be- comes operational and the desired settings should be loaded into the control registers. Writing a 1 to the RUN bit will then cause the part to leave the low power state and begin operation.

12.2 ID Code and Revision Code

The CS8405A has a register that contains a four-bit code to indicate that the addressed device is a CS8405A. This is useful when other CS84XX fam- ily members are resident in the same or similar sys- tems, allowing common software modules. The CS8405A four-bit revision level code is also available. This allows the software driver for the CS8405A to identify which revision of the device is in a particular system, and modify its behavior accordingly. To allow for future revisions, it is strongly recommended that the revision code is read into a variable area within the microcontroller, and used wherever appropriate as revision details become known.

12.3 Power Supply, Grounding, and PCB

The CS8405A operates from a +5V supply. It may also be operated with VD+ at +5V and the other VL+ pins at +3.3 V. Follow normal supply decou- pling practices, see Figure 5. The VL+ supplies should be decoupled with a 0.1 µF capacitor to DGND to minimize AES3 transmitter induced transients. Extensive use of power and ground planes, ground plane fill in unused areas and surface mount decou- pling capacitors are recommended. Decoupling ca- pacitors should be mounted on the same side of the board as the CS8405A to minimize inductance ef- fects, and all decoupling capacitors should be as close to the CS8405A as possible.

12.4 Synchronization of Multiple

The AES3 transmitters of multiple CS8405As can be synchronized if all devices share the same mas- ter clock, TCBL, and RST signals and all exit the reset state on the same master clock falling edge. The TCBL pin is used to synchronize multiple CS8405A AES3 transmitters at the channel status block boundaries. One CS8405A must have its TCBL set to master; the others must be set to slave TCBL. Alternatively, TCBL can be derived from external logic, whereby all CS8405A devices should be set to slave TCBL.

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX JEDEC #: MS-013 Controlling Dimension is Millimeters 28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L SEATING PLANE e

32 DS469PP4

Notes: 1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2.Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3.These dimensions apply to the flat section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN NOM MAX MIN NOM MAX JEDEC #: MO-153 Controlling Dimension is Millimeters. 28L TSSOP (4.4 mm BODY) PACKAGE DRAWING E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

14.1 AES3 Transmitter External

also short circuit protected.

14.2 Isolating Transformer Requirements

sources on transformer selection. Figure 11. Professional Output Circuit Figure 12. Consumer Output Circuit Figure 13. TTL/CMOS Output Circuit

34 DS469PP4

1. APPENDIX B: CHANNEL STATUS

15.1 AES3 Channel Status(C) Bit

buffers through the control port.

15.1.1 Accessing the E buffer

allowable time periods to interact with the E buffer. port interactions are occurring. when the part is in hardware mode. Figure 14. Channel Status Data Buffer Structure Figure 15. Flowchart for Writing the E Buffer

15.1.2 Serial Copy Management System

(SCMS) In software mode, the CS8405A allows read/modi- fy/write access to all the channel status bits. For consumer mode SCMS compliance, the host mi- crocontroller needs to manipulate the Category Code, Copy bit and L bit appropriately. In hardware mode, the SCMS protocol can be fol- lowed by either using the COPY and ORIG input pins, or by using the C bit serial input pin. These options are documented in the hardware mode sec- tion of this data sheet.

15.1.3 Channel Status Data E Buffer Access

The E buffer is organized as 24 x 16-bit words. For each word the MS Byte is the A channel data, and the LS Byte is the B channel data (see Figure 14). There are two methods of accessing this memory, known as one byte mode and two byte mode. The de- sired mode is selected through a control register bit.

15.1.3.1 One Byte mode

In many applications, the channel status blocks for the A and B channels will be identical. In this situ- ation, if the user reads a byte from one of the chan- nel's blocks, the corresponding byte for the other channel will be the same. Similarly, if the user wrote a byte to one channel's block, it would be necessary to write the same byte to the other block. One byte mode takes advantage of the often identi- cal nature of A and B channel status data. When reading data in one byte mode, a single byte is returned, which can be from channel A or B data, depending on a register control bit. If a write is be- ing done, the CS8405A expects a single byte to be input to its control port. This byte will be written to both the A and B locations in the addressed word. One byte mode saves the user substantial control port access time, as it effectively accesses 2 bytes worth of information in 1 byte's worth of access time. If the control port's auto increment addressing is used in combination with this mode, multi-byte accesses such as full-block reads or writes can be done especially efficiently.

15.1.3.2 Two Byte mode

There are those applications in which the A and B channel status blocks will not be the same, and the user is interested in accessing both blocks. In these situations, two byte mode should be used to access the E buffer. In this mode, a read will cause the CS8405A to out- put two bytes from its control port. The first byte out will represent the A channel status data, and the 2nd byte will represent the B channel status data. Writing is similar, in that two bytes must now be input to the CS8405A's control port. The A channel status data is first, B channel status data second.

15.2 AES3 User (U) Bit Management

The CS8405A U bit manager has two operating modes: Mode 1. Transmit all zeros. Mode 2. Block mode.

15.2.1 Mode 1: Transmit All Zeros

Mode 1 causes only zeros to be transmitted in the output U data, regardless of E buffer contents. This mode is intended for the user who wants the output U channel to contain no data.

15.2.2 Mode 2: Block Mode

Mode 2 is very similar to the scheme used to control the C bits. Entire blocks of U data are buffered using 2 block-sized RAMs to perform the buffering. The user has access to the first buffer, denoted the E buff- er, through the control port. It is the only mode in which the user can merge his own U data into the transmitted AES3 data stream. The U buffer access only operates in two byte mode, since there is no con- cept of A and B blocks for user data. The arrangement o ft h ed a t ai sa sf o l l o w i n g s : Bit15[A7]Bit14[B7]Bit13[A6]Bit12[B6]...Bit1[A0] Bit0[B0]. The arrangement of the data in the each byte is that the MSB is the first transmitted bit. The bit for the A subframe is followed by the bit for the B sub- frame.