CS7615

CS7615 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

/c108 10-Bit A/D Converter /c108 Multi-Sync CCD Timing Generator, handles imagers up to 1000 pixels wide /c108 Integrated Correlated Double Sampler /c108 38 dB Automatic Analog Gain Control /c108 Up to 90 dB Total Gain Adjust Range /c108 Closed-Loop “Fuzzy” AGC/Exposure /c108 Code 16 Black Level Clamp /c108 I2C Control Bus /c108 4-Phase Vertical CCD Timing Signals /c108 No CCD Buffer Amplifier Required /c108 Master Clock or Crystal Controlled

Description

The CS7615 is a low-power Analog front-end processor for standard four-color interline transfer CCD imagers. The architecture includes a correlated double sampler, AGC amplifier, black-level clamp, 10-Bit A/D converter, and a complete multi-sync CCD timing generator. The analog CCD imager output can be directly connected to the CS7615 input, which does not require an external buffer amplifier. The pixel data is double sampled for im- proved noise performance, and gain adjusted prior to being digitized by the A/D converter. Feedback from the A/D converter holds the image black level at code-16 (assumes 8-bit data path), addressing ITU-601 compli- ance issues. The multi-sync CCD timing generator is programmed via the I 2C bus, and can be used with a wide range of interline transfer CCD imagers up to 1000 pixels wide. The CS7615 supports full ITU-601 compli- ance for images up to 720 pixels wide, and is compatible with both NTSC and PAL timing. The CS7615 is de- signed to be used along with either the CS7665 or CS7666 Digital Color-Space Processor for CCD Camer- as, which generates a 4:2:2 component digital video output.

ORDERING INFORMATION

CS7615-KQ 0 ° to +70° C 44-pin TQFP (10 mm × 10 mm × 1.6 mm) CCD Output Master Clock CDS/AGC Data Out PLL Output Register I2C Block Formatter A/D Converter Black Level Timing Generator AGC Controller CCD Timing Signals I2C Bus Clocks Out JUL ‘98 DS231PP6

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ANALOG CHARACTERISTICS: (TA=25°C; VAA =V DD =5V; Output Load=30pF ) DIGITAL CHARACTERISTICS: (TA=25°C; VAA =V DD =5V; Output Load=30pF ) POWER CONSUMPTION: (TA=25°C; VAA =V DD =5V; Output Load=30pF ) Parameter Symbol Min Typ Max Units Dynamic Performance Integral Non-Linearity INL - 1 - LSB Differential Non-Linearity DNL - 0.75 - LSB Analog Input Analog Input Capacitance C IN -1 0- p F Automatic Gain Control Maximum Gain G MAX -2 0- d B Minimum Gain G MIN -0- d B Gain Increment ΔG - 78.4 117.6 mdB Parameter Symbol Min Typ Max Units Logic Inputs High-Level Input Voltage V IH VDD -0.8 - - V Low-Level Input Voltage V IL -- 0 . 8 V Input Leakage Current I IN -- 1 0 m A Logic Outputs High-Level Output Source Current @ VOH = VDD -0.4V I OH --1 m A Low-Level Output Sink Current @ VOL = 0.4V I OL --1 m A 3-State Leakage Current I OZ -- 1 0 µA Parameter Symbol Min Typ Max Units Power Dissipation P D -6 5 0- m W Analog Power Supply Current Normal Mode Low-Power Mode IAN IALP mA mA DIgital Power Supply Current Normal Mode Low-Power Mode IDN IDLP mA mA

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Figure 1. I2C Timing Diagram

Specifications are subject to change without notice. Figure 2. Analog Input

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trates the system interconnect. and the CS7666 data sheet for more details. Figure 3. Typical 4-Chip Digital CCD Camera Figure 4. CS7615/CS7665 Interface

32 XTALIN

55 CLKIN

Figure 5. CS7615/CS7666 Interface

connected directly to the CS7665.

3 Binary

P3P2P1P0 = error protection bits (as per ITU-656). At reset or power down, 040h. Figure 6. CS7615 Output Data Format

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allows for compatibility with a variety of CCDs. ters that may be set to control these signals. high during the active video portion of the line. VH1X, VH3X - CCD charge read out pulse. HSYNC - Horizontal sync signal. signal sets the electronic shutter speed. VRST - Vertical field reset signal. during the active video lines. *Internal signal on the CS7615 - not a chip output. taining a fixed 63.5 µs horizontal line time. Figure 7. CS7615 Output Data and Clocks

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54 dB as it deems necessary. programmable to meet the needs of the user. frame is used for the AGC algorithm. data are used in the histogramming. Figure 9. Timing Diagram for Href, HSYNC, Clamp, and Henb

Target Value: Adjusts the brightness threshold. tion voltage is less than 1.6V. applied prior to amplification by the VGA. Figure 10. Vertical Shift Register Signal Timings

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Figure 11. Vertical Shift Register Signal Timings for Charge Read Out Phase

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Table 2. Horizontal timing specifications

Analog to Digital Converter After the pixel data is double sampled and the ap- propriate gain has been applied, it is digitized by the internal 10-bit A/D converter. These resulting mosaic data are input to the formatter which for- mats the data before sending it to the chip output. The output of the A/D converter is also used by the internal AGC loop in determining the proper gain setting, and by the black level adjust when reading the black pixels. Black Level Adjust to Code 16 (10-bit Code 64) The output data are adjusted to hold the image black level at the 8-bit code of 16, in compliance to the ITU-601 recommendation. During the blanking periods, the black level adjustment is updated when over black pixels. The number of black pixels used is programmable by the user through the I 2C inter- face. Formatter The formatter adds the necessary EAV/SAV timing codes to the output data in accordance with the ITU-656 recommendation.

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and read the contents of these device registers. non-existent registers within the selected device. erations will return a value of 00h. The WRITE format consists of a three-byte packet. Table 3. WRITE Format Packet Table 4. ADDRESS SET Format Packet Operation The READ operation consist of two or more bytes. Table 5. READ Format Packet.

Software Reset Register (00h) SR4 Setting bit SR4 to logic high will initiate a CS7615 software reset. Software reset resets all the digital blocks except for I2C and the ADC calibration logic. The clocks remain running. This reset bit automatically clears. Low Power Register (20h) PD4 Setting bit PD4 to logic high will place the CS7615 chip in a low power mode. The I2C interface and clock generation circuitry will remain powered up. Operational control #1 Register (24h) PAL Logic high indicates a PAL standard camera system, logic low indicates NTSC. Default = 0. AGCW Used to window the portion of the frame to use for AGC. Default = 00. 00 = use entire frame 01 = use center 1/4 area of frame 10 = use center 1/16 area of frame 11 = reserved AGCDI Logic high disables CS7615’s automatic gain control circuitry. User may manually control gain through the gain register 25h/26h. Default = 0. AGCALG Controls data used in CS7615’s AGC loop. Logic high indicates mosaic data, logic low indicates luma data. Default = 0. CCDTYP Logic high signifies that a Type B CCD is being used, logic low signifies a Type A CCD. Default = 0. FLCKLS Logic high restricts shutter to flickerless settings. Default = 0. PALENV Logic high when the camera system is being used in a PAL environment, logic low in an NTSC environment. Default = 0. R/W Read/Write R Read WW r i t e RES Reserved 76543210 res res res SR4 res res res res rrr w rrrr 76543210 res res res PD4 res res res res rrr r / w rrrr 76543210 PAL AGCW1 AGCW2 AGCDIS AGCCALG CCDTYP FLCKLS PALENV r/w r/w r/w r/w r/w r/w r/w r/w

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Gain Registers (25-26h) 25h: 26h: AGC(10:0) Gain control word for the automatic gain control. This 11 bit word is a 2’s compliment number which has a minimum value of -784 (decimal) (Reg 26h = 04h; Reg 25h = 5F0h) for PAL or - 765d for NTSC (Reg 26h = 05h; Reg 25h = 03) and a maximum value of 484d (Reg 26h = 01h; Reg 25h = E4h). The gain range is -54 dB to 38 dB in steps of 0.078 dB ideal, 0.12 dB max step is guaranteed only for chip GAIN. Default is 000h. AGC Error Statistic Register (27h): AGCER The 8 MSBs of the gain error statistic calculated as part of the AGC loop. AGC Count Statistic Register (28h) AGCCT The output of the 1-of-7 block which denotes the bin where the AGC target was met. AGC Target Value Register (29h) AGCTG The target value used in the AGC loop. It denotes the number of pixels that must be exceeded for an intensity bin to give an output of ‘1’. Default is 0h. 000=64 100=1024 001=128 101=2048 010=256 110=4096 011=512 111=8192 76543210 AGC10 AGC9 AGC8 AGC7 AGC6 AGC5 AGC4 AGC3 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res AGC2 AGC1 AGC0 rrrrr r / w r / w r / w 76543210 agcer7 agcer6 agcer5 agcer4 agcer3 agcer2 agcer1 agcer0 rrrrrrrr 76543210 res agcct6 agcct5 agcct4 agcct3 agcct2 agct1 agcct0 rrrrrrrr 76543210 res res res res res agctg2 agctg1 agctg0 rrrrr r / w r / w r / w

AGC Maximum Gain Register (2Ah) MGN Sets the maximum gain allowable if the user chooses to limit the chip gain beyond a certain value. The range is 0-242, with the actual max gain word being twice this value. Default is F2h. AGC Slew and Speed Register (2Bh) SLEW Sets the rate of decay of gain when the gain target is exceeded in the maximum intensity bin. Default is 0h. 00 = -8 10 = -32 01 = -16 11 = -64 SPD Varies the AGC loop gain. The error signal used for correction is multiplied by the speed num- ber before being added to the accumulator. Default is 0h. 00 = 1x 10 = 4x 01 = 2x 11 = 8x AGC Minimum Gain Register (2Ch) MNGN Sets the minimum gain allowable if the user chooses to limit the chip gain from a certain value. Default is 00h. CCD Signal Alignment Register (2Dh) These signals adjust the edges of H1 or FR with respect to the internal sampling clock. HR Adjusts the location of the rising edge of H1. HF Adjusts the location of the falling edge of H1. FRR Adjusts the location of the rising edge of FR. FRF Adjusts the location of the falling edge of FR. 76543210 mgn7 mgn6 mgn5 mgn4 mgn3 mgn2 mgn1 mgn0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res slew1 slew0 spd1 spd0 rrrr r / w r / w r / w r / w 76543210 mng7 mng6 mng5 mng4 mng3 mng2 mng1 mng0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 HR1 HR0 HF1 HF0 FRR1 FRR0 FRF1 FRF0 r/w r/w r/w r/w r/w r/w r/w r/w

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VRST Registers (2Eh, 2Fh) 2Eh: 2Fh: These parameters are needed only when the VRST input is used. VRSTN The line number gets reset to this value on a negative edge of VRST. Default is 004h. VRSTDY Logic high denotes VRST will be delayed with respect to the line position. Default = 0 (no delay). VRSTFLD Logic high denotes the field is reset to even on a negative edge of VRST, logic low denotes the field is reset to odd. Default = 0. Maximum Shutter Exposure Register (30h) MXSH If the user chooses to limit the exposure time, the max shutter gain is set to this value. 00h=full exposure, BFh=min exposure for NTSC, C4h= min exposure for PAL. Operational Control #2 Register (31h) BLKDIS Logic high disables the black level loop. Black level remains at the current value. Default =0. ADCAL1 Analog-to-digital converter option. When written to a logic high, calibration is immediately en- tered. This bit goes back low when calibration is complete. ADCAL2 Analog-to-digital converter option. Logic high results in calibration being done after every frame, logic low results in calibration only on power up. Default = 0. CNVFST Logic high sets the frequency of HCLK to 16×the line frequency, logic low sets HCLK to 1×the line frequency. Default = 0. 76543210 VRSTN8 VRSTN7 VRSTN6 VRSTN5 VRSTN4 VRSTN3 VRSTN2 VRSTN1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res VRSTDY VRSTFLD VRSTN0 rrrrr r / w r / w r / w 76543210 MSXH7 MSXH6 MSXH5 MSXH4 MSXH3 MSXH2 MSXH1 MSXH0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res BLKDIS ADCAL1 ADCAL2 CNVFST rrrr r / w r / w r / w r / w

Timing Control- Line Number Registers (33h-39h) 33h: 34h: 35h: 36h: 37h: 38h: 39h: VLO The number of lines in an odd field. Default is 106h. VLE The number of lines in an even field. Default is 107h. VBE Line number for end of VREF for even field. Default is 013h. VBO Line number for end of VREF for odd field. Default is 012h. XSE Line number for charge transfer for even field. Default is 011h. XSO Line number for charge transfer for odd field. Default is 010h. 76543210 VLO8 VLO7 VLO6 VLO5 VLO4 VLO3 VLO2 VLO1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 VLE8 VLE7 VLE6 VLE5 VLE4 VLE3 VLE2 VLE1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 VBE8 VBE7 VBE6 VBE5 VBE4 VBE3 VBE2 VBE1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 VBO8 VBO7 VBO6 VBO5 VBO4 VBO3 VBO2 VBO1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 XSE8 XSE7 XSE6 XSE5 XSE4 XSE3 XSE2 XSE1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 XSO8 XSO7 XSO6 XSO5 XSO4 XSO3 XSO2 XSO1 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res VLO0 VLE0 VBE0 VBO0 XSE0 XSO0 r r r/w r/w r/w r/w r/w r/w

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Timing Control-Horizontal Blank Pd Register (40h) HBPD Number of pixel clocks in the horizontal blank period. Default is 70h. Timing Control- Line Length Register (41h-42h) 41h: 42h: HLEN Total number of pixels in line length. Default is 270h. Timing Control- HSYNC Registers (43h-44h) 43h: 44h: HSYNR Number of pixels from HREF to leading edge of HSYNC. Default is 14h. HSYNF Number of pixels from HREF to trailing edge of HSYNC. Default is 44h. Timing Control - Black Clamp Register (45h) BC Number of pixels from HREF to leading edge of black clamp. Default is 08h. Black clamp falls on leading edge of HENB. 76543210 HBPD7 HBPD6 HBPD5 HBPD4 HBPD3 HBPD2 HBPD1 HBPD0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 HLEN9 HLEN8 HLEN7 HLEN6 HLEN5 HLEN4 HLEN3 HLEN2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res HLEN1 HLEN0 rrrrrr r / w r / w 76543210 HSYNR7 HSYNR6 HSYNR5 HSYNR4 HSYNR3 HSYNR2 HSYNR1 HSYNR0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 HSYNF7 HSYNF6 HSYNF5 HSYNF4 HSYNF3 HSYNF2 HSYNF1 HSYNF0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 r/w r/w r/w r/w r/w r/w r/w r/w

Timing Control - HENB Registers (46h-47h) 46h: 47h: HEND Number of pixels from HREF to leading edge of HENB. Default is 1Ch. HSTART Number of pixels from HREF to trailing edge of HENB. Default is 68h. Timing Control - V1X Registers (48h-49h) 48h: 49h: V1X is a vertical register shift clock. V1R Number of pixels from HREF to leading edge of V1X. Default is 22h. V1F Number of pixels from HREF to trailing edge of V1X. Default is 36h. 76543210 HEND7 HEND6 HEND5 HEND4 HEND3 HEND2 HEND1 HEND0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 HSTART7 HSTART6 HSTART5 HSTART4 HSTART3 HSTART2 HSTART1 HSTART0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V1R7 V1R6 V1R5 V1R4 V1R3 V1R2 V1R1 V1R0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V1F7 V1F6 V1F5 V1F4 V1F3 V1F2 V1F1 V1F0 r/w r/w r/w r/w r/w r/w r/w r/w

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Timing Control - V2X Registers (4Ah-4Bh) 4Ah: 4Bh: V2X is a vertical register shift clock. V2R Number of pixels from HREF to leading edge of V2X. Default is 2Ch. V2F Number of pixels from HREF to trailing edge of V2X. Default is 40h. Timing Control - V3X Registers (4Ch-4Dh) 4Ch: 4Dh: V3X is a vertical register shift clock. V3F Number of pixels from HREF to leading edge of V3X. Default is 1Dh. V3R Number of pixels from HREF to trailing edge of V3X. Default is 3Bh. 76543210 V2R7 V2R6 V2R5 V2R4 V2R3 V2R2 V2R1 V2R0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V2F7 V2F6 V2F5 V2F4 V2F3 V2F2 V2F1 V2F0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V3F7 V3F6 V3F5 V3F4 V3F3 V3F2 V3F1 V3F0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V3R7 V3R6 V3R5 V3R4 V3R3 V3R2 V3R1 V3R0 r/w r/w r/w r/w r/w r/w r/w r/w

Timing Control - V4X Registers (4Eh-4Fh): 4Eh: 4Fh: V4X is a vertical register shift clock. V4F Number of pixels from HREF to leading edge of V4X. Default is 29h. V4R Number of pixels from HREF to trailing edge of V4X. Default is 45h. Timing Control - Charge Read Out in Odd Field V2X Registers (50h-52h) 50h: 51h: 52h: Charge readout timing for V2X in an odd field in number of pixels. V2OR From HREF to leading edge of V2X. Default is 185h. V2OF From HREF to trailing edge of V2X. Default is 1E9h. 76543210 V4F7 V4F6 V4F5 V4F4 V4F3 V4F2 V4F1 V4F0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V4R7 V4R6 V4R5 V4R4 V4R3 V4R2 V4R1 V4R0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V2OR9 V2OR8 V2OR7 V2OR6 V2OR5 V2OR4 V2OR3 V2OR2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V2OF9 V2OF8 V2OF7 V2OF6 V2OF5 V2OF4 V2OF3 V2OF2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res V2OF1 V2OF0 V2OR1 V2OR0 rrrr r / w r / w r / w r / w

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Timing Control - Charge Read Out in Odd Field V3X Registers (53h-55h) 53h: 54h: 55h: Charge readout timing for V3X in an odd field in number of pixels. V3OF From HREF to leading edge of V3X. Default is 188h. V3OR From HREF to trailing edge of V3X. Default is 3Bh. Timing control - Charge Read Out in Even Field V2X Registers (56h-58h) 56h: 57h: 58h: Charge readout timing for V2X in an even field in number of pixels. V2ER From HREF to leading edge of V2X. Default is 185h. V2EF From HREF to trailing edge of V2X. Default is 40h. 76543210 V3OF9 V3OF8 V3OF7 V3OF6 V3OF5 V3OF4 V3OF3 V3OF2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V3OR7 V3OR6 V3OR5 V3OR4 V3OR3 V3OR2 V3OR1 V3OR0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res V3OF1 V3OF0 rrrrrr r / w r / w 76543210 V2ER9 V2ER8 V2ER7 V2ER6 V2ER5 V2ER4 V2ER3 V2ER2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V2EF7 V2EF6 V2EF5 V2EF4 V2EF3 V2EF2 V2EF1 V2EF0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res V2ER1 V2ER0 rrrrrr r / w r / w

Timing Control - Charge Read Out in Even Field V3X Registers (59h-5Bh) 59h: 5Ah: 5Bh: Charge readout timing for V3X in an even field in number of pixels. V3EF From HREF to leading edge of V3X. Default is 188h. V3ER From HREF to trailing edge of V3X. Default is 3Bh. Timing Control - Charge Read Out in Even Field V4X Registers (5Ch-5Eh) 5Ch: 5Dh: 5Eh: Charge readout timing for V4X in an even field in number of pixels. V4EF From HREF to leading edge of V4X. Default is 1E9h. V4ER From HREF to trailing edge of V4X. Default is 45h. 76543210 V3EF9 V3EF8 V3EF7 V3EF6 V3EF5 V3EF4 V3EF3 V3EF2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V3ER7 V3ER6 V3ER5 V3ER4 V3ER3 V3ER2 V3ER1 V3ER0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res V3EF1 V3EF0 rrrrrr r / w r / w 76543210 V4EF9 V4EF8 V4EF7 V4EF6 V4EF5 V4EF4 V4EF3 V4EF2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 V4ER7 V4ER6 V4ER5 V4ER4 V4ER3 V4ER2 V4ER1 V4ER0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res res res V4EF1 V4EF0 rrrrrr r / w r / w

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Timing Control - H1X Registers (5Fh-61h) 5Fh: 60h: 61h: Charge read out timing for VH1X in number of pixels. VH1F From HREF to leading edge of VH1X. Default is 18Fh. VH1R From HREF to trailing edge of VH1X. Default is 1ADh. Timing Control - VH1X Registers (62h-64h) 62h: 63h: 64h: Charge read out timing for VH3X in number of pixels. VH3F From HREF to leading edge of VH3X. Default is 1B7h. VH3R From HREF to trailing edge of VH3X. Default is 1D5h. 76543210 VH1F9 VH1F8 VH1F7 VH1F6 VH1F5 VH1F4 VH1F3 VH1F2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 VH1R9 VH1R8 VH1R7 VH1R6 VH1R5 VH1R4 VH1R3 VH1R2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res VH1R1 VH1R0 VH1F1 VH1F0 rrrr r / w r / w r / w r / w 76543210 VH3F9 VH3F8 VH3F7 VH3F6 VH3F5 VH3F4 VH3F3 VH3F2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 VH3R9 VH3R8 VH3R7 VH3R6 VH3R5 VH3R4 VH3R3 VH3R2 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 res res res res VH3R1 VH3R0 VH3F1 VH3F0 rrrr r / w r / w r / w r / w

Black Level Adjust Register (68h) BLK Offset added to input of ADC so that the output of ADC during black pixels is code 64. 00h-FFh represents a voltage range of 0-186mV. Default is 8Fh. This register is automatically updated when black level adjust is enabled. Version (Minor) Register (69h) The minor version register in the CS7615 rev A is assigned the value 00h. The Rev B device is assigned the value 01h. With each minor version the value is increased by 1. Version (Major) Register (6Ah) The major version register in the CS7615 rev A is assigned the value FFh. With each major version the value is decreased by 1. Station Address Register (FEh) STA CS7615’s Station address, 7 MSBs (LSB of complete 8-bit station address determined by read/write bit). 76543210 BLK7 BLK6 BLK5 BLK4 BLK3 BLK2 BLK1 BLK0 r/w r/w r/w r/w r/w r/w r/w r/w 76543210 76543210 rrrrrrrr 76543210 76543210 rrrrrrrr 76543210 r e s S T A 6S T A 5S T A 4S T A 3S T A 2S T A 1S T A 0 r r/w r/w r/w r/w r/w r/w r/w

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V AA - Analog power supply, PIN 19, 21. Nominally +5 volts. VDD - Digital power supply, PIN 5, 41. Nominally +5 volts. 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 CS7615-KQ 44-pin TQFP Top View GNDD VDD VH1X CLKO DO9(MSB) DO8 DO7 DO6 DO5 DO4 VDD GNDD CLK2XO GNDA GNDA RESET FCLKIN GNDA INTERP VRST SCL SDA HSYNC V1X V2X OFDX XTALIN XTALOUT HCLK DO0(LSB) DO1 DO2 DO3 AIN GNDA VAA FR VAA GNDA V4X VH3X V3X

GNDA - Analog Ground, PIN 12, 15, 16, 18, 22. Analog ground reference. GNDD - Digital Ground, PIN 6, 40. Digital ground reference. Analog Input AIN - Video Input, PIN 17. CCD output signal. Digital Inputs VRST - Vertical sync reset, PIN 10. Used to reset vertical line counter in genlock mode. VRST is falling edge triggered. INTERP - Digital Video Horizontal Data Rate Scaler Enable, PIN 11. Active high logic input sets CLKO output rate to 1× non-interpolated data rate, and the CLK2XO output rate to 2× interpolated data rate (5/2× CLKO rate). Logic low causes the CLKO output rate to be the pixel rate, while CLKX2O is set to twice the pixel rate. FCLKIN - Frequency of crystal input, PIN 13. Logic input identifying the external crystal as a 1× rate or a 2× rate crystal. This pin should be set high for a 1× crystal or clock source; logic low for a 2× crystal or clock source. RESET - Master reset, PIN 14. May be connected to external power-on-reset-circuit. Clears registers to default values. Active logic high. XTALIN - Crystal input, PIN 32. May be 1× or 2× the data rate. XTALOUT - Oscillator output to crystal, PIN 33. If the on-chip oscillator is used, this output connects to the crystal. Timing Generator Outputs HSYNC - Horizontal sync signal, PIN 7. To be used in genlock mode. HSYNC is a rising pulse.

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FR- Reset gate clock pulse for CCD, PIN 20. Connect directly to CCD. FR is a rising pulse. H1- Horizontal shift register clock #1, PIN 23. Connect directly to CCD. H2- Horizontal shift register clock #2, PIN 24. Connect directly to CCD. V4X- Vertical shift register clock, PIN 25. Connects to vertical driver. VH3X- Charge read out pulse, PIN 26. Connect to vertical driver. V3X- Vertical shift register clock, PIN 27. Connects to vertical driver. VH1X- Charge read out pulse, PIN 28. Connect to vertical driver. V1X- Vertical shift register clock, PIN 29. Connects to vertical driver. V2X- Vertical shift register clock, PIN 30. Connects to vertical driver. OFDX- Charge sweep out pulse for shutter control, PIN 31. Connect to vertical driver. OFDX is a falling pulse. HCLK- Horizontal line frequency clock, PIN 34. Connect to DC-DC converter. HCLK is a falling pulse when it is in “HREF” output mode. Mosaic Data and clock Outputs D O[0..9] - Digital Mosaic Outputs. CMOS level Mosaic coded CCD output data.

CLKO - Mosaic Output Data Clock, PIN 4. CLK2XO - Mosaic Output Data Interpolation Clock, PIN 39. horizontal data rate scaler is used in the color processor. SDA - Primary I2C Data Bus, PIN 8. Primary I2C data bus. Used with SCL to read and write the internal register set. SCL - Primary I2C Clock, PIN 9. Primary I2C Clock. Used with SDA to read and write the internal register set. Table 6. Digital Mosaic Outputs.

34 DS231PP6

A 0.000 0.065 0.00 1.60 A1 0.002 0.006 0.05 0.15 B 0.012 0.018 0.30 0.45 D 0.478 0.502 11.70 12.30 D1 0.404 0.412 9.90 10.10 E 0.478 0.502 11.70 12.30 E1 0.404 0.412 9.90 10.10 e 0.029 0.037 0.70 0.90 L 0.018 0.030 0.45 0.75 ∝ 0.000 7.000 0.00 7.00 JEDEC # : MS-026 44L TQFP PACKAGE DRAWING E D1D e L B A

• Notes •