CS7410 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
lSuper on-chip Integration for low cost and low count bill of materials l32-Bit RISC Processor performs audio decode and system management functions l16-bit DSP for audio special effects l80 Kbytes internal SRAM, and 256 Kbytes internal ROM lInterfaces to external SDRAM or EDO DRAM (for shock protection), and to external ROM/FLASH (for custom program storage) lCD serial interface with advanced pattern matching and software error handling lIntegrated DAC functionality lSimultaneous 4 channels PCM audio output and IEC-958 output. lLarge number of GPIO pins for servo control, key scan, LCD control, etc. lThree serial control/status ports lSophisticated clock management and low power consumption lSupports ISO9660 and multi-session write methods lLow power 0.18 micron technology l100-pin MQFP package l100-pin LQFP package
Description
The CS7410 is a true system-on-a-chip for the CD- based digital audio market. With a powerful RISC pro- cessor, one DSP, integrated audio ΔΣ modulator, large internal SRAM and program ROM, and glueless inter- face to popular CD chip sets, the CS7410 is a complete single chip low-power programmable audio decoder. This powerful architecture is easily capable of MP3, WMA, and other future audio formats. The CS7410’s flexible architecture and low power consumption make it an ideal low-cost solution for a wide range of player ap- plications. For portable audio systems, the memory interface can be used to add DRAM or SRAM for Elec- tronic Shock Protection (ESP). A flexible set of interfaces are available for end-user I/O such as a keypad and LCD control for use in mass market CD players, boom boxes, and shelf-top systems.
ORDERING INFORMATION
CS7410-CM 0° to 70° C 100-pin MQFP CS7410-CQ 0° to 70° C 100-pin LQFP Audio Interface ΔΣ Modulator PCM Out IEC-958 X,Y Data memory CPU / MAC Instruction Cache 80 KB Internal SRAM 256 KB Internal ROMDRAM Control Mini DMA ROM/SRAM Control Flash Control Memory Controller Register Bank System Miscellaneous Clock Control Timers Get Bits Data Cache Instruction Cache CPU MAC CD Interface PLLControl FIFO External Interface 2-Wire Debug Interface 3/4 Wire Serial Programmable I/O PWM Out RISC-32 DSP-16 JUL ‘02 DS553PP1
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Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/sales.cfm IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. “Advance” product infor- mation describes products that are in development and subject to development changes. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the infor- mation contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights of the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other parts of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma- terial and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANT- ED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners.
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- CHARACTERISTICS AND SPECIFICATIONS
1.1 AC AND DC PARAMETRIC SPECIFICATIONS
(AGND, DGND=0V, all voltages with respect to 0V)
1.1.1 Absolute Maximum Rating
CAUTION: Operating beyond these Minimum and Maximum limits can result in permanent damage to the device. Cirrus Logic recommends that CS7410 devices operate at the settings described in the next ta- ble.
1.1.2 RECOMMENDED OPERATING CONDITIONS
1.1.3 Electrical Specifications
(TA = 0 to 70 oC) Symbol Description Min. Max. Unit VDDIO Power Supply Voltage on I/O ring -0.5 4.6 Volts VDDCORE Power Supply Voltage on core logic and PLL -0.5 2.5 Volts VI Digital Input Applied Voltage (power applied) -0.5 5.5 Volts II Digital Input Forced Current -10 10 mA IO Digital Output Forced Current -50 50 mA TSOL Lead Soldering Temperature 260 oC TVSOL Vapor Phase Soldering Temperature 235 oC TSTOR Storage Temperature (no power applied) -40 125 oC TAMB Ambient Temperature (power applied) 0 70 oC PTOT Power consumption 1 W Parameter Symbol Min Typ Max Units Supply Voltage, IO VDD 3.0 3.3 3.6 Volts Supply Voltage, core and PLL VDD 1.62 1.8V 1.98 Volts Ambient Temperature (power applied) TAMB 0 25 70 oC Parameter Symbol Conditions Min Typ Max Units Power Supply Supply Current, IO IDD Normal Operating 13 mA Supply Current, core and PLL IDD Normal Operating 70 mA
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Input Voltage, High VIH 2.0 Volts Input Voltage, Low VIL 0.8 Volts Input Current IIN VIN = VDD or VSS -1 +1 µA Input Pull up/down resistor RI 75 KΩ Output Voltage, High VOH @ buffer rating 2.4 Volts Output Voltage, Low VOL @ buffer rating 0.4 Volts High-Z-state Leakage IOZ VOUT = VSS or VDD -1 +1 µA Parameter Symbol Conditions Min Typ Max Units
1.1.4 DC CHARACTERISTICS
1.1.4.1 SDRAM Interface
Table 1. SDRAM Characterization Data Figure 1. SDRAM Timing
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Figure 2. SDRAM Load Mode
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Figure 5. SDRAM Refresh
1.1.4.2 Serial Interface
Table 2. Serial Interface Characterization Data Figure 6. Serial Interface Timing Diagram
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1.1.4.3 EDO DRAM interface
Note:Values shown are for minimum internal clock period (11ns) and all programmed wait states enabled. Table 3. EDO DRAM Characterization Data
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Figure 9. EDO Refresh Timing Diagram
1.1.4.4 FLASH / ROM Interface
Note:Values shown are for minimum internal clock period (11ns) and no programmed wait states. Table 4. FLASH/ROM Read Characterization Data 1.Value shown for 3 programmed wait states. Figure 10. FLASH/ROM Read
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Figure 11. FLASH/ROM Write
1.1.4.5 Audio Output Interface
Table 5. Audio Output Interface Symbols and Characterization Data
- Active clock edge is programmable. Timing is referenced from the active edge.
Figure 12. Audio Output Timing
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1.1.4.6 CD Interface
Figure 13. CD Interface Timing
Figure 14. CD Interface Timing Diagrams
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1.1.4.7 Miscellaneous Timings
Figure 15. Miscellaneous Timings
2.1 CS7410 Typical Application
Figure16 shows an example of a complete audio player using the CS7410.
2.2 CS7410 Block Summaries
2.2.1 RISC-32
- Powerful 32-bit RISC processor
- Comprehensive development tool support
- Big or little endian data formats supported
- 32x32 (64-bit result) MAC, 2 cycles / multiply with C support
- 4 Kbyte instruction cache, 2 Kbyte data cache
- Single cycle instructions, runs up to 90 MHz
2.2.2 DSP-16
- Powerful 16-bit DSP processor
- 16-bit fixed point logic, with 36 bit accumula- tor.
- Single-cycle throughput, 2-cycle latency multi- ply accumulate, 16-bit simple integer logic
- 512 byte instruction cache, 8 Kbyte program visible local memory
- Single cycle instructions, runs up to 90 MHz
- DSP MAC is pipelined, 1 cycle / multiply
2.2.3 System Controls
- Includes 32 hardware lockable semaphore reg- isters
- Two general-purpose registers for inter-proces- Servo DSP/Rd Channel Speakers/Headphones (2 or 4 channel) PCM DACs OP-AMPs 4 Chan. Debug Optical Driver 2 Chan. IEC-958 ROM/FLASH (optional) 0-2 MB For new code DRAM EDO/SDRAM (optional) 0-8 MB For shock protection Serial EEPROM (optional) Keypad Matrix LCD Controller/ Display IR receiver GPIO Memory Interface Serial Interface Digital Audio Out DAC Out CD Interface CS7410
Figure 16. CS7410 Application
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- Three 32-bit timers for I/O and other uses, with programmable interval rates
- “Getbits” module accelerates peripheral stream parsing
- Both hardware and software interrupts on data or debug
2.2.4 Memory System
- Large internal SRAM (80 Kbyte) and internal program ROM (256 Kbyte)
- Supports both Synchronous and EDO DRAM (256 KBytes to 8 MBytes) for ESP
- Supports one bank of FLASH and ROM (up to
2 MBytes) for nonvolatile storage
- 4-, 8-, or16-bit data bus for DRAM, 8-bit data bus for ROM
2.2.5 CD Interface
- Glueless interfaces to CD servo chip set, sup- porting all standard CD formats
- Includes pattern matching hardware to support fast ESP recovery
2.2.6 Audio Interface
- Supports 4 channels PCM, I 2S connectivity at up to 24 bits
- Flexible audio clocking scheme using internal PLL and dividers, or external pins
- Simultaneous IEC-958 output with program- mable channel status and user data
- Integrated sigma-delta (ΔΣ ) stereo audio mod- ulator
2.2.7 External Interface
- 2-wire serial slave port, used for debug
- 3- or 4-wire synchronous serial master/slave port for external controller or slave peripheral
- Separate synchronous serial master port opti- mized for receiving CD sub-codes
- Up to 29 programmable bi-directional I/O (GPIO) and up to 9 output only (GPO) pins (some multiplexed with other peripherals)
- All pins defined as GPIOs can be used to re- ceive edge or level detection interrupts.
- Pulse-width modulated (PWM) output pin can be used to create simple ADC using low-cost comparator (i.e., for battery voltage monitor)
2.2.8 System Functions
- Internal oscillator uses external crystal, or re- ceives clock (i.e. 16.9 MHz) from CD servo
- Internal PLL generates any system clock fre- quency, chip can run up to 90 MHz
- Includes clock divider and clock shutoff cir- cuits for low power/sleep modes
- Advanced 0.18 micron CMOS technology, runs off 1.8 V and 3.3 V
- All I/O pins are 3.3 V, with 5 V tolerance
- 100-pin MQFP package
- 100-pin LQFP package
- FUNCTIONAL DESCRIPTION
3.1 RISC-32 Processor
The CS7410 includes a powerful, proprietary 32- bit RISC processor backed by powerful software development tools. The RISC-32 has a MAC en- gine which performs multiply/accumulate in 2 cy- cles with C support, effectively achieving single cycle throughput. There are other instructions that are designed to help with performing audio decoding. The RISC processor coordinates on-chip multi-threaded tasks, as well as supervises system activities such as keypad and front panel display control.
3.2 DSP-16 Processor
The CS7410 contains a proprietary digital signal processor (DSP) called DSP-16, which is opti- mized for audio and sound applications. In the CS7410, the DSP-16 assists with audio decoding and provides added functions such as surround sound and equalization. The DSP performs 16-bit simple integer operations, and has a 16-bit fixed point logic unit with a 32-bit accumulator. There are 24 general-purpose registers, and eight independent address generation registers, featur- ing: post-increment ALU, linear and circular buffer operations, bit reverse ALU operations, and dual operand read from memory. The multiply-accumu- lator has single-cycle throughput, with two cycle latency. The DSP is optimized for bit packing and unpacking operations. The interface to main mem- ory is designed for bursting flexible block sizes and skip counts.
3.3 Memory Control
The Memory Controller performs the arbitration functions for all the other modules in the CS7410, allowing access to internal ROM and SRAM, and to external ROM and DRAM. The Memory Con- troller services and arbitrates a number of clients and stores their code and/or data within the local memory. This arbitration and scheduling guaran- tees the allocation of sufficient bandwidth to the various clients. An optimal application will use only internal ROM and SRAM for code and data storage, which results in the best timing and lowest power consumption. External DRAM may be used for runtime code storage or for ESP RAM. In both of these applica- tions, the data throughput requirement is low, and the Memory Controller acts as a DMA engine to move data between external and internal memory with minimal power consumption. The internal ROM contains most of the code required for audio decoding and system functions. Additional code can be stored in external ROM (managed by the Memory Controller) or a small se- rial ROM (controlled by GPIOs). The CS7410 also supports code storage in external FLASH with in- system write capability for customer code updates. Future firmware releases will provide a complete solution requiring no external ROM.
3.4 CD Interface
The CD Interface receives compressed or uncom- pressed (direct audio) data from the CD servo/read channel chip, performs descrambling and CRC checking, and writes the data to an internal FIFO. Additional C3 error decoding is done in software. The CD interface is compatible with all commonly used CD formats. The CS7410 contains a hardware pattern matching circuit to scan the incoming CD data for a pattern of up to 64 bytes. This circuit is used to assist the Electronic Shock Protection function by quickly lo- cating and matching the incoming data with data stored in the ESP RAM.
3.5 System Control Functions
The system control functions are used to coordinate the activities of the multiple processors, and to pro- vide the supporting system operations. Two 32-bit communication registers are available for inter-
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processor communication, and 32 semaphore reg- isters are used for resource locking. Three timers are available for general-purpose functions, as well as more specialized functions, such as watchdog timers and performance monitoring. The large number of general purpose I/Os offers flexibility in system configurations. Three separate synchronous serial interfaces, conforming to indus- try-standard protocols, are available for a variety of system interface functions. Four general purpose software interrupts and twelve hardware interrupts help reduce peripheral overhead and improve UI responsiveness. Power-down control of the internal clocks is also possible. An internal PLL is used to generate the internal system and memory clocks as well as audio clocks for all supported sample rates.
3.6 Audio Output
Decoded audio data is written into an output FIFO in 16-, 18-, 20- or 24-bit PCM format. A flexible audio output stage can simultaneously output 4 channels of PCM data to external audio DACs, plus an independent IEC-958 encoded output. The IEC- 958 output has fully programmable channel status (commercial), and provides a flexible solution to support all IEC-958 modes for user data. The audio output circuit contains an auto-mute detect circuit, which can generate internal or external mute con- trols PCM FIFO data up to 18 bits can also be output by the on-board sigma-delta stereo modulator. The sigma-delta modulator yields a typical 85 dB sig- nal-to-noise ratio with few external components re- quired, resulting in a low-cost, low parts count analog front end. The modulator has a 32x upsam- pling filter, followed by a 32x interpolator, and fi- nally a 5 th-order Sigma-Delta modulator. The auto-mute circuit also works on the modulator out- put, and there are separate programmable attenua- tors for the modulator output and both PCM outputs.
4.1 Pin Identification
Figure17 shows the CS7410 pins grouped by function, also showing the number of pins in each group. Table6 lists the conventions used to identify the pin type and direction.pin assignments. Table 6. Pin Type and Direction Legend Figure 17. CS7410 Pin Identification
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some signal pins, a secondary function and direction are also shown. Table 6. Pin Type and Direction Legend (Continued)
1 PLL_GND Gnd PLL Ground
2 PLL_1V8 Pwr PLL Power
3 M_D_15 B4 I DRAM Data[15] B NVMem
4 M_D_14 B4 I DRAM Data[14] B NVMem
5 M_D_13 B4 I DRAM Data[13] B NVMem
6 M_D_12 B4 I DRAM Data[12] B NVMem
7 M_D_11 B4 I DRAM Data[11] B NVMem
8 M_D_10 B4 I DRAM Data[10] B NVMem
9 M_D_9 B4 I DRAM Data[9] B NVMem
10 M_D_8 B4 I DRAM Data[8] B NVMem
11 M_D_7 B4 I DRAM Data[7] B NVMem Data[7] B
12 CORE_1V8 Pwr Core Power
13 M_D_6 B4 I DRAM Data[6] B NVMem Data[6] B
14 CORE_GND Gnd Core Ground
15 M_D_5 B4 I DRAM Data[5] B NVMem Data[5] B
16 IO_3V3 Pwr I/O Power
17 XTLCLK_O O O Oscillator Out O
Table 7. Pin Assignments
18 XTLCLK_I I I Oscillator In I
19 IO_GND Gnd I/O Ground
20 M_D_4 B4 I DRAM Data[4] B NVMem Data[4] B
21 M_D_3 B4 I DRAM Data[3] B NVMem Data[3] B
22 M_D_2 B4 I DRAM Data[2] B NVMem Data[2] B
23 M_D_1 B4 I DRAM Data[1] B NVMem Data[1] B
24 M_D_0 B4 I DRAM Data[0] B NVMem Data[0] B
25 M_A_11 B4 I DRAM Address[11] O NVMem
26 M_A_10 B4 I DRAM Address[10] O NVMem
27 M_A_9 B4 I DRAM Address[19] O NVMem
28 M_A_8 B4 I DRAM Address[8] O NVMem
29 M_A_7 B4 I DRAM Address[7] O NVMem
30 M_A_6 B4 I DRAM Address[6] O NVMem
31 M_A_5 B4 I DRAM Address[5] O NVMem
32 M_A_4 B4 I DRAM Address[4] O NVMem
33 M_A_3 B4 I DRAM Address[3] O NVMem
34 M_A_2 T4 I DRAM Address[2] O NVMem
35 M_A_1 T4 I DRAM Address[1] O NVMem
36 M_A_0 T4 I DRAM Address[0] O NVMem
37 DR_RAS_L T4 I DRAM RAS_L O
38 CORE_1V8 Pwr Core Power
39 DR_CAS_L T4 I DRAM CAS_L O
Table 7. Pin Assignments (Continued)
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40 CORE_GND Gnd Core Ground
41 M_WE_L T4 I DRAM WE_L O NVM_WE_L
42 IO_GND Gnd I/O Ground
43 DR_CKO T4 I SDRAM CKO O
44 IO_3V3 Pwr I/O Power
45 DR_CKE T4 I SDRAM CKE O
46 DR_BS_L B4 I SDRAM BS_L O NVMem
47 M_AP_OE B4 I SDRAM AP, EDO DRAM
48 NVM_CE_L T4 I NVM_CE_L O
49 KP_IN_0 B4U I GPIO[19] B
50 KP_IN_1 B4U I GPIO[20] B
51 KP_IN_2 B4U I GPIO[21] B
52 KP_IN_3 B4U I GPIO[22] B
53 KP_IN_4 B4U I GPIO[23] B
54 KP_OUT_0 B4 I GPIO[24] B
55 KP_OUT_1 B4 I GPIO[25] B
56 KP_OUT_2 B4 I GPIO[26] B
57 KP_OUT_3 B4 I GPIO[27] B
58 KP_OUT_4 B4 I GPIO[28] B
59 IR_IN B4S I GPIO[4] B
60 SER1_CLK D4S I Debug Port Clock B
61 SER1_DAT D4S I Debug Port Data B
62 SER4_CLK B4S I GPIO[5] B
63 SER4_DAT B4S I GPIO[6] B
64 IO_GND Gnd I/O Ground
65 SER2_CLK B4 I Serial2 Clock B GPIO[7] B
66 SER2_DI B4 I Serial2 Data In B GPIO[8] B
67 SER2_DO B4 I Serial2 Data Out B GPIO[9] B
68 SER2_CS B4 I Serial2 Chip Select B GPIO[10] B
69 SER3_CLK B4 I Serial3 Clock O GPIO[11] B
70 SER3_DO B4 I Serial3 Data Out O GPIO[12] B
71 CORE_1V8 Pwr Core Power
72 SER3_DI B4 I Serial3 Data In I GPIO[13] B
73 CORE_GND Gnd Core Ground
74 SER3_SS0 B4 I Serial3 Chip Select0 O GPIO[14] B
75 IO_3V3 Pwr I/O Power
76 SER3_SS1 B4 I Serial3 Chip Select1 O GPIO[15] B
77 SERVOCK B4 I Servo Clock In I GPIO[17] B
78 PCM_XCK B4 I PCM_XCK B
79 PCM_MUTE B4 I PCM_MUTE O GPO[4] O 1
80 CD_C2P0 B4 I CD_C2P0 I GPIO[16] B
81 CD_BCLK IS I CD_BCLK I
82 CD_LRCK I I CD_LRCK I
83 CD_DATA I I CD_DATA I
84 DAC_LP O4 O ΔΣ DAC Left Positive Out O GPO[5] O
85 DAC_LN O4 O ΔΣ DAC Left Negative Out O GPO[6] O
86 IO_GND Gnd I/O Ground
87 DAC_RP O4 O ΔΣ DAC Right Positive Out O GPO[7] O
88 DAC_3V3 Pwr ΔΣ DAC I/O Power
89 DAC_RP O4 O ΔΣ DAC Right Negative Out O GPO[8] O
90 RST_N IS I Reset_L I
91 TEST I I Manufacturing Test I
92 PCM_BCK B4 O PCM_BCK O GPO[0] O 1
93 PCM_LRCK B4 O PCM_LRCK O GPO[1] O 1
94 PCM_DO_0 B4 O PCM_Dout[0] O GPO[2] O 2
95 PCM_DO_1 B4 O PCM_Dout[1] O GPO[3] O 1
96 IEC958_O B4 I IEC-958 Out O GPIO[18] B
97 GPIO_0 B4 I GPIO[0] B
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- Optional pull up or pull down resistor may be connected to configure internal ROM program
- Required external resistor required to select processor boot from internal ROM (pull down) or external
- Drives for a short time after reset, then reverts to high impedance
4.2 Miscellaneous Pins
CS7410 can accommodate a variety of input frequencies, such as 44.1 KHz x 256, x 384, or x 512.
4.3 Serial Interface Pins
and can also be used a general-purpose serial port.
98 GPIO_1 B4 I GPIO[1] B PWM_Out O
99 GPIO_2 B4 I GPIO[2] B
100 GPIO_3 B4 I GPIO[3] B
17 XTLCLK_O O Crystal output
18 XTLCLK_I I Crystal input, or oscillator input
90 RST_N I Asynchronous reset input, active low
91 TEST I Manufacturing test, tie to ground
Table 8. Miscellaneous Interface Pins
60 SER1_CLK B Debug port serial clock
61 SER1_DAT B Debug port serial data
65 SER2_CLK B Clock for 4-wire serial port (output for master mode, input
66 SER2_DI I Input data for 4-wire serial port
67 SER2_DO B Output data for 4-wire serial port – may function as bidi-
rectional data in 3-wire mode. Table 9. Serial Interface Pins
4.4 SDRAM / DRAM Interface
gives pin definitions for interfacing to EDO DRAM.
68 SER2_CS B Chip select for 4-wire serial port (output if master, input if
slave mode). Can also be used as bidirectional ready line.
69 SER3_CLK O Clock output
70 SER3_DO O Data output – up to 32 bits per transfer. 72 SER3_DI I Data input – up to 96 bits per transfer.
74 SER3_SS0 O Slave select for first peripheral (programmable polarity)
76 SER3_SS1 O Slave select for second peripheral (programmable polar-
Table 9. Serial Interface Pins (Continued)Pin Signal Name Type Description
37 DR_RAS_L O Memory Row Address Strobe
39 DR_CAS_L O Memory Column Address Strobe
41 M_WE_L O Memory Write Enable
43 DR_CKO O SDRAM Clock
45 DR_CKE O SDRAM Clock Enable
46 DR_BS_L O Bank Selection. Always connect to RAM BS or BS0 pin. 47 M_AP_OE O Memory Auto Pre-charge. Always connect to RAM AP pin. Table 10. SDRAM Interface Table 11. EDO DRAM Interface
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4.5 ROM/NVRAM Interface
47 M_AP_OE O Memory Output Enable
Table 11. EDO DRAM Interface (Continued) 46 NVM_Addr[20] O Memory Address Bus[20] (DRAM BS_L pin).
41 NVM_WE_L O NVRAM Write Enable (shared with DRAM WE_L pin)
47 NVM_OE_L O NVRAM Write Enable (shared with DRAM WE_L pin)
48 NVM_CE_L O ROM/NVRAM Chip Enable. Table 12. ROM/NVRAM Interface
4.6 Digital Audio Output Interface
op-amp based integrator circuit (contact Cirrus Logic Applications Engineering for details). 78 PCM_XCK B Audio 256x/384x/512x Clock input or output to Serial DAC. When output, it’s generated from CS7410 internal PLL. ble and is three-stated at power up. 93 PCM_LRCK O Audio Out Left/Right Clock to serial DAC. 94 PCM_DO_0 O Audio Serial PCM Data Out[0]. 95 PCM_DO_1 O Audio Serial PCM Data Out[1].
96 IEC958_O O IEC-958 Output
Table 13. Audio Output Interface
84 DAC_LP O ΔΣ left channel, positive output
85 DAC_LN O ΔΣ left channel, negative output
87 DAC_RP O ΔΣ right channel, positive output
89 DAC_RN O ΔΣ right channel, positive output
Table 14. ΔΣ Output Interface
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4.8 CD Interface
CD subcode data is read using the dedicated serial interface (SER3).
81 CD_BCLK I CD clock input – polarity is programmable
82 CD_LRCK I CD left-right clock input
83 CD_DATA I CD serial data input
80 CD_C2P0 I CD error signaling input
Table 15. CD Interface
4.9 General Purpose Input/Output (GPIO)
standardized pin usage. Table17 shows the GPIO and GPO pins that can be redefined from other functions. For redefined pins, mode control register bits select the normal function or GPIO/GPO function for the pins. Table17 also indicates which mode bit controls each pin.
59 IR_IN B General purpose I/O on dedicated pin
62 SER4_CLK B General purpose I/O on dedicated pin
63 SER4_DAT B General purpose I/O on dedicated pin
Table 16. Dedicated General Purpose I/O Pins
65 SER2_CLK B GPIO controlled by Mode bit 2
67 SER2_DO B GPIO controlled by Mode bit 2
68 SER2_CS B GPIO controlled by Mode bit 2
66 SER2_DI B GPIO controlled by Mode bit 3
69 SER3_CLK B GPIO controlled by Mode bit 4
70 SER3_DO B GPIO controlled by Mode bit 4
72 SER3_DI B GPIO controlled by Mode bit 4
74 SER3_SS0 B GPIO controlled by Mode bit 4
76 SER3_SS1 B GPIO controlled by Mode bit 5
80 CD_C2P0 B GPIO controlled by Mode bit 6
77 SERVOCK B GPIO controlled by Mode bit 7
92 PCM_BCK O GPO controlled by Mode bit 8
93 PCM_LRCK O GPO controlled by Mode bit 9
94 PCM_DO_0 O GPO controlled by Mode bit 10
95 PCM_DO_1 O GPO controlled by Mode bit 11
79 PCM_MUTE O GPO controlled by Mode bit 12
84 DAC_LP O GPO controlled by Mode bit 13
Table 17. Redefined General Purpose Pins
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4.10 Power and Ground
tween the supply types on the board. Contact Cirrus Logic applications engineering for layout guidelines.
85 DAC_LN O GPO controlled by Mode bit 13
87 DAC_RP O GPO controlled by Mode bit 13
89 DAC_RN O GPO controlled by Mode bit 13
96 IEC958_O B GPIO controlled by Mode bit 14
1 PLL_GND Ground for internal PLLs
Table 18. Power and Ground Table 17. Redefined General Purpose Pins (Continued)
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- 100-PIN MQFP PACKAGE SPECIFICATIONS (20X14X2.85mm)
Figure 18. 100-Pin MQFP Package (20x14x2.85mm)
- 100-PIN LQFP PACKAGE SPECIFICATIONS (14X14X1.4mm)
Figure 19. 100-Pin LQFP Package (14X14X1.4mm)