CS6403

CS6403 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

/c108 Applicable in: - Digital-Cellular Hands-Free Phones - Analog-Cellular Hands-Free Phones - Office Speaker Phones - Desktop & Video Teleconferencing /c108 Echo Cancellation - Up to 60 dB ERLE - 512 Tap (64 ms at 8 kHz sampling rate) - Split Mode For Two Echo Cancellers /c108 Serial Data/Control Interface /c108 On-Chip Delta-Sigma Codec - < 1% THD, 8 Ω Load On Output - > 70 dB S/(N+D) on Input - 300-3600 Hz Bandwidth (8 kHz sampling rate) - Volume Control - Microphone Preamp /c108 Automatic Gain Control (AGC) /c108 No Training Signals Generated

Description

The CS6403 is an application-specific digital signal pro- cessor optimized for network and acoustic echo cancellation applications. A high-quality codec is inte- grated with the processor to provide a complete, low- cost echo-cancellation solution. The CS6403 is a fully independent processor that re- quires no signal processing support to implement its cancellation functions. Volume control, AGC, and sleep functions are also provided. The on-chip ADC and DAC employ over-sampling tech- nology, which eliminates the need for complex external anti-aliasing and reconstruction filters, further reducing system cost. The CS6403 has a serial interface that is compatible with most DSPs and PCM codecs. Clock and sync lines con- trol the transfer of serial data via the separate serial data- in and data-out pins. Both 16-bit audio data and con- trol/status information may be multiplexed on this serial channel using a steering bit.

ORDERING INFORMATION

CS6403-IQ -40° to +85° C 44-pin TQFP CS6403-IL -40° to +85° C 44-pin PLCC CDB6403 Evaluation Board I RESET DVDD0 1 CONFIG GPIN0 RESERVED0 6 CLKIN CLKOUTSCLK_RATE0 PVDD SPKROUTP SPKROUTN PGND0 PGND1 MICIN VCM SCLK_RATE1 PLL + Clock Manager CLK_SEL NC GPIN1 GPIN3 GPIN2 GPOUT0 GPOUT1 SFRAME UALAW SMASTER SSYNC SCLK SDO_1 SYNCOUT SDI_A AVDD DGND0 1 Serial I/O AGND0 1 DSP Control Status A G C High Pass Control Nonlinear Echo Control Volume Control Echo Cancellers Nonlinear Echo Control High Pass A T T E N VREF A T T E N D/A A/D 26 dB Analog I/O MAR ‘96 DS192PP7

ADC CHARACTERISTICS (TA = 25 °C; All DVDD, AVDD, and PVDD = 5.0V, Digital Input Levels: Logic 0 = 0V, Logic 1 = DVDD; Signal test frequency 1kHz, word rate (Fs) = 8kHz, audio signal measurement bandwidth is 20Hz to 4kHz; Microphone amp gain = 0dB; SPRKOUT outputs connected to 8Ω load; CLKIN fre- quency = 8.192MHz; unless otherwise specified) Note 1. Parameter Symbol Min Typ Max Units ADC Resolution With No Missing Codes 12 - - bits Instantaneous Dynamic Range IDR 67 72 - dB Total Harmonic Distortion at -0.5dBFS signal level THD - 0.01 0.05 % Gain Drift (Note 2) - 150 - ppm/°C Offset Error - 0 2 LSB Full Scale Input Voltage (Note 3) 0.85 1.0 1.1 V p Input Resistance (at MICIN) (Note 2) 25 - - kΩ Input Capacitance (at MICIN) (Note 2) - 15 - pF Sample Rate Fs - 8 - kHz Microphone Amp Gain (switchable on/off) 24 26 28 dB Anti-aliasing Rejection - 30 - dB Power Supply Rejection (1kHz) PSR 40 - - dB Frequency Response -0.6 - 0.6 dB Transition Band 0.45 - 0.6 Fs Stop Band Rejection 70 - - dB VREF Reference Voltage Output - 2.0 - V VCM Voltage Output constant load only, >100 k Ω -1 . 0-V Group Delay (Note 4) - 1 - ms Group Delay Variations vs. Frequency (Note 4) - 0.0 - µs Notes: 1. Bench testing is done with Crystal part CXT8192 driving CLKIN, automated device testing utilizes test system provided clock sources. 2. Guaranteed by design/characterization. 3. This is the peak input voltage (in volts) with the mic amp gain set to 0 dB. Peak-to-peak voltage is 2x peak. Input signals will be properly clipped if the peak signal is greater than full scale, but less than 2x full scale. 4. This group-delay specification is for the ADC only; additional group delay is introduced by the AGC and high-pass filter that is implemented on the CS6403 in software. CS6403

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DAC CHARACTERISTICS (TA = 25 °C; All DVDD, AVDD, and PVDD = 5.0V, Digital Input Levels: Logic 0 = 0V, Logic 1 = DVDD; Signal test frequency 1kHz, word rate (Fs) = 8kHz, audio signal measurement bandwidth is 20Hz to 20kHz; Microphone amp gain = 0dB; SPRKOUT outputs connected to 8Ω load; CLKIN fre- quency = 8.192MHz; unless otherwise specified) Parameter Symbol Min Typ Max Units DAC Resolution 12 - - bits DAC step size error - - ±0.5 LSB Instantaneous Dynamic Range (20 Hz - 20 kHz) IDR 60 72 - dB Frequency Response -0.8 - +0.6 dB Programmable Output Level Attenuator Range (Note 5) -92.2 - 0 dB Gain Step Size - 2.49 - dB Gain Drift (Note 2) - 150 - ppm/°C VREF Reference Output Voltage - 2.0 - V VCM Output Voltage constant load only, >100k Ω -1 . 0 - V Offset Error - 25 50 mV Full Scale Output Voltage (SPKROUT pins) (Note 6) 1.40 1.75 1.93 V p Common Mode Output Voltage (SPKROUT pins) - 1.30 - V Total Harmonic Distortion at -0.5dBFS level, SPKROUT(Note 9) THD - - 0.8 % Output Impedance SPKROUT pins - 0.4 - Ω Load Impedance SPKROUT pins 8 - - Ω Output Capacitance - 15 - pF Audible Stop Band Attenuation (<20kHz) 68 - - dB Integrated Inaudible Energy (>20kHz to 100kHz) (Note 7) - - 30 mVrms Power Supply Rejection (1kHz) PSR 40 60 - dB Filter Transition Band 0.45 - 0.6 Fs Group Delay (Note 8) - 1 - ms Notes: 5. Attenuation settings greater than 92.2 dB will cause a full scale input signal to be completely attenuated to zero signal level. 6. This is the peak differential output voltage. The peak-to-peak signal level on each output pin is equal to the peak differential value. 7. Assuming an external 43.2 kHz RC output filter. 8. This group-delay specification is for the DAC only; additional group delay is introduced by the AGC and high-pass filter that is implemented on the CS6403 in software. 9. Room temperature only. CS6403 DS192PP6 3

PHASE-LOCKED LOOP CHARACTERISTICS (TA = 25°C; AVDD, DVDD, and PVDD = +5V; Input Levels: Logic 0 = 0V, Logic 1 = DVDD) Parameter Symbol Min Typ Max Units PLL acquisition time T ACQ 0.3 1 ms PLL frequency range 23.35 24.58 25.80 MHz PLL jitter 200 ps rms Input ref frequency 1.95 0.97 243 2.048 1.024 256 2.15 1.08 268 MHz MHz kHz DIGITAL CHARACTERISTICS (TA = 25°C; AVDD, DVDD, and PVDD = 5V) Parameter Symbol Min Typ Max Units High-level Input Voltage V IH DVDD - 1.0 - - V Low-level Input Voltage V IL -- 1 . 0 V High-level Output Voltage at I0 = -2.0 mA V OH DVDD - 0.3 - - V Low-level Output Voltage at I0 = +2.0 mA V OL -- 0 . 3 V Input Leakage Current (Digital Inputs) I IN -- 1 0 µA Output Leakage Current (High-Z Digital Outputs) - - 10 µA Output Capacitance (Note 2) C OUT -- 1 5 p F Input Capacitance (Note 2) C IN -- 1 5 p F ABSOLUTE MAXIMUM RATINGS (All voltages with respect to 0V) Parameter Symbol Min Typ Max Units Power Supplies AVDD DVDD PVDD -0.3 - 6.0 V Input Current Except Supply Pins & Driver Pins I IN --1 0 . 0 m A Short Circuit Current Limit SPKROUT pins (Note 10) ISC - - 500 mA Analog Input Voltage V INA -0.3 - AVDD + 0.3 V Digital Input Voltage V IND -0.3 - DVDD + 0.3 V Ambient Temperature (Power Applied) T AMAX -55 - 125 °C Storage Temperature T STG -65 - 150 °C ESD using human body model (100pF with series 1.5kΩ ) VESD 2000 - - V Notes: 10. SPKROUTP or SPKROUTN shorted to ground. Warning: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. CS6403

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POWER CONSUMPTION (TA = 25°C; All DVDD, AVDD and PVDD = 5.0V; Signal test frequency 1kHz; Word Rate (Fs) = 8kHz; SPRKOUT outputs connected to 8Ω load; Mode 2 SCLK = 256 kHz; unless oth- erwise specified) Full scale output. Parameter Symbol Min Typ Max Units Normal Operation Power Dissipation P D - 800 - mW High-Impedance Output (Note 11) P NS - 300 - mW RESET High P RH -5 5- m W RESET High, clocks halted (Note 12) P RNC -1 5- m W Powerdown Asserted in Software P PDN -5 5- m W Notes: 11. SPKROUT outputs connected to 1 kΩ load. 12. RESET high, CLKIN grounded (Mode 1) or SCLK grounded (Mode 2), and CLK_SEL (PIN 15Q, 21L) high to disable PLL. CLKIN tckl SCLK SYNCOUT (Master Mode) tckh tpd3 SCLK & SYNCOUT Output Timing Mode 1 - MASTER RECOMMENDED OPERATING CONDITIONS (All voltages with respect to 0V) Parameter Symbol Min Typ Max Units DC Power Supplies: AVDD DVDD PVDD 4.50 5.0 5.50 V Ambient Operating Temperature T A -40 85 °C CS6403 DS192PP6 5

SWITCHING CHARACTERISTICS (TA = 25°C; AVDD and DVDD = +5V, output loaded with 30 pF; Input Levels: Logic 0 = 0V, Logic 1 = DVDD) Parameter Symbol Min Typ Max Units Mode 1 - MASTER Input clock (CLKIN) frequency CLKIN 7.78 8.192 8.60 MHz CLKIN low time t ckl 30 - - ns CLKIN high time t ckh 30 - - ns Sample Rate Fs - 8 - kHz SCLK and SYNCOUT output delay from CLKIN rising t pd3 - - 50 ns SCLK duty cycle (Note 12) t sckw -5 0- % SCLK rising to SYNCOUT rising t sr1 -1 2 3 0 n s SCLK rising to SYNCOUT falling t sf1 - 6 30 ns SDO delay from SCLK edge t pd1 - - 70 ns SDI setup time to SCLK edge t s1 15 - - ns SDI hold time from SCLK edge t h1 10 - - ns SDO to Hi-Z state t hz - - 50 ns SDO to non-Hi-Z bit 1 t nz 5-- n s RESET pulse width high 250 - - µs Mode 2 - SLAVE Input clock (SCLK) frequency SCLK 243 0.97 1.95 256 1.024 2.048 268 1.08 2.15 kHz MHz MHz SCLK low time t ckl 150 - - ns SCLK high time t ckh 150 - - ns SYNCOUT output delay from SSYNC rising t pdsr - - 50 ns SYNCOUT output delay from SSYNC falling t pdsf - - 50 ns Sample Rate Fs - 8 - kHz SDI/SSYNC setup time to SCLK edge t s1 15 - - ns SDI/SSYNC hold time from SCLK edge t h1 10 - - ns SDO delay from SCLK edge t pd1 - - 70 ns SDO to Hi-Z state bit 16/8 t hz - - 50 ns SDO to non-Hi-Z bit 1 t nz 5-- n s RESET pulse width high 250 - - µs Notes: 12. When the CS6403 is in master mode (SSYNC and SCLK outputs), the SCLK duty cycle is 50%. The period of SCLK is 4/CLKIN. CS6403

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(Short Frame) SYNCOUT (Long Frame) SDI SDO AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AAA AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AA A AAA Note: 1. SYNCOUT is long frame when SFRAME = 1. Master Mode Serial Port Timing (Mode 1) SCLK tsckh tsckl th1ts1 SSYNC SDI SDO ts1 th1 tpd1 tpd1 tnz thz Bit 1 Bit 2 Bit 15 (Bit 7) Bit 16 (Bit 8) Bit 1 Bit 2 Bit 15 (Bit 7) Bit 16 (Bit 8) AAAA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A AAAA A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A A AA A SYNCOUT tpdsr tpdsf Slave Mode Serial Port Timing (Mode 2) CS6403 DS192PP6 7

• Echo-canceller length: 512 taps
• Echo-canceller initial conditions: zeroed filter taps, updates disabled until t=0.125s
• Sampling rate: 8 kHz
• Echo path (including microphone, speaker, and amplifiers): - spectrally flat -l i n e a r - duration < 64 ms - noise free - time invariant 60.0 40.0 20.0 0.0 ERLE (dB) Seconds ERLE Speech Training Signal -0.3 0.0 Speech (mV) 0.3

Figure 1. Typical ERLE Convergence Characteristics

• Near-end high-pass filter: enabled
• Pre-emphasis filter: enabled
• Graded-beta profile: 64 echo-canceller filter taps processed per 2x reduction in update gain
• Training signal: speech, full scale
• Unlimited S/(N+D) on linear ADC Note: Many of these conditions may be significantly different in real applications, resulting in significantly different measured ERLE performance. CS6403

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compromises conversation quality. allocated to an acoustic echo canceller (AEC). Figure 2. CS6403 Internal Block Diagram

particularly important part of this processing. the highest quality conversation. formance of the echo canceller. summing node of the Acoustic Echo Canceller. tic Echo Canceller is performed. Figure 3. Functional Diagram

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microphone and a speaker, respectively. differential input on an external amplifier. peak-to-peak signal is the maximum allowed. operate as either a system timing master or slave. SCLK_RA TE1 (PIN 30Q, 36L) pins. Table 1 shows the various options for SCLK. Table 1. Clock Options

trol signals is illustrated in Table 2. generated. Word length is always 8 bits. hands free, or in digital (ISDN) speaker phones. The SSI is the system timing slave in Mode 2. cess to control registers in 16-bit Mode. that setting the RESET pin clears the RST bit. Table 2. CS6403 Configurations Figure 4. Operating Modes

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into Data RAM from the Program ROM. in SSI Control Register 0 (SLP: SSI_CR0.10). Figure 5. External Mu-law Codec Connection Diagram

celled, and audio data is not companded. these signals is illustrated in Figure 6. registers established after Reset are used. work-echo cancellation (see Figure 3). Figure 6. External-Codec Mode Timing (Mode 1)

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the interface circuitry is shown in Figure 7. serial interface is illustrated in Figure 8. Figure 7. DSP Connection Diagram (Mode 2)

as is the case with many ISDN transceivers. can be transferred in this mode. Setting CONFIG high selects Mode 2 (16-bit). such that 8-bit data is followed by eight zeroes. destination register is read back to the DSP . Figure 8. Serial Port Timing for Mode 2 (16-bit) - SLAVE

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monitor and control the behavior of the CS6403. cessible by the serial interface in 16-bit modes. These registers are accessed by setting b15 high. access operation is a read (high) or a write (low).

00 SSI_CR0

01 SSI_CR1

10 SSI_CR2

1 RNW a1 a0 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

Table 3. Audio and Control Data Format for Mode 2

After reset (or after CR0 is written), at least four data words must be written to the CS6403 before another control-word access may be executed. For example, the following serial-data sequence will reset the CS6403, set CR0 to a new value, and initialize CR1 and CR2: hex data intent

8800 Software reset

8000 Release reset

8400 Enter "sleep" mode

8[0-3]XX Update CR0 (with "[0-3]XX") 0000 dummy data 1 0000 dummy data 2 0000 dummy data 3 0000 dummy data 4 9XXX Update CR1 AXXX Update CR2

0000 First real data item

In the following tables describing each bit of the control registers, the bit names of each 12-bit register are at the top of the page. The Reset state of each register is shown immediately be- low the bit names at the top of the page. The Reset state is also noted by an "R" beside the appropriate value in the "value" column. CS6403

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Register SSI_CR0 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 RST SLP AGCRD NECD FHPD NHPD CE PED GBC1 GBC0 AECB1 AECB0 000000001010 This register is read from the SSI by the CPU only upon exit from Reset and Sleep. This register is cleared at reset except for B3-B0 (see below). BIT NAME VALUE FUNCTION RST Reset 0 R Normal operation. Control registers and RAMs are cleared, and then control constants are loaded into Data RAM. SSI is still operational, though writes to any control bit except RST are ignored. SLP Sleep 0 R Normal operation. The CPU and AFP on the CS6403 are powered down. Control registers and RAMs are unaffected. Serial Data transactions that occur during power down are transferred directly between the SSI and the codec, bypassing the CPU. As a result, echo is passed uncancelled. AGCRD AGC-Rescale Disable 0 R SPKROUT volume is scaled to full-scale after peak-limiter. SPKROUT signal is peak-limited version of far-end input. NECD NEC Disable 0 R 10 ms of the available 64 ms of EC taps are allocated by default to network echo cancellation. No taps are allocated to network echo cancellation. FHPD FE_IN High-Pass Disable 0 R A high-pass filter ((1-D)/(1-0.75D)) is inserted in the far-end input signal path. This filter is bypassed. NHPD NE_IN High-Pass Disable 0 R A high-pass filter ((1-D)/(1-0.75D)) is inserted in the near-end input signal path. This filter is bypassed. CE Companding Enable 0 R Data in 16-bit data modes is linear (i.e., not companded). b15 is still used as the steering bit, but if b15=0, the least significant 8 bits are companded data. PED Pre-Emphasis Disable 0 R A pre-emphasis filter is placed before the input to the adaptive filter. This filter is bypassed. "R" indicates value after Reset CS6403 DS192PP6 19

Register SSI_CR0 (cont.) BIT NAME VALUE FUNCTION GBC1 GBC0- Graded-Beta Count Graded-Beta Count - These bits control the rate at which the update gain decays in the AEC as the adaptive-filter taps are updated in a particular sample time. For each setting below, some number of taps are processed, after which the update gain is divided by two. The possible settings are given below: R Taps Processed 512 128 256 Equivalent path-decay rate 0 dB/ms 0.75 dB/ms 0.38 dB/ms 0.19 dB/ms AECB1 AECB0 AEC Beta These bits scale the adaptive filter update gain that is present at the start of each sample time. R Update Gain 0.25 0.5 1.0 2.0 "R" indicates value after Reset Recommended settings for D3-D0: 0001 --No graded beta 0111 --"dead" room/car; 0.75 dB/ms path decay 1010 --medium room; (default) 0.28 dB/ms path decay 1100 --large (or "live") room; 0.19 dB/ms decay CS6403

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Register SSI_CR1 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 CB AGCD res res CAL GADCI res res NCC HDD SD ACC 000000000000 This register is read/written by the CPU every sample time. This register is cleared at Reset by the SSI. BIT NAME VALUE FUNCTION CB Codec Bypass 0 R Normal operation. Codec is bypassed by the CPU to facilitate test. AGCD AGC Disable 0 R Normal operation. AGC is disabled. Will affect volume control. res Reserved for test 0 R Must be 0. res Reserved for test 0 R Must be 0. CAL Codec Analog Loopback 0 R Normal operation. Connect ADC to DAC internally. GADCI Ground ADC Input 0 R Normal operation. ADC input is grounded to facilitate test. res Reserved for test 0 R Must be 0. res Reserved for test 0 R Must be 0. NCC NEC Coefficient Clear 0 R Normal operation. The network canceller coefficients are cleared. HDD Half-Duplex Disable 0 R Normal operation. Half-duplex mode, which is normally used during convergence, is disabled. SD Suppression Disable 0 R Normal operation. Supplementary suppression in the transmit path, which normally operates in conjunction with the echo cancellers, is disabled. ACC AEC Coefficient Clear 0 R Normal operation. The acoustic canceller coefficients are cleared. "R" indicates value after Reset CS6403 DS192PP6 21

Register SSI_CR2 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 PDC PDSD MGD res res res res res AV3 AV2 AV1 AV0 000000000000 This register is cleared at Reset by the SSI. This register is read/written by the CPU every sample time. BIT NAME VALUE FUNCTION PDC Power Down Codec 0 R Normal operation. The entire codec is powered down. PDSD Power Down Speaker Driver 0 R Normal operation. Only the speaker driver in the codec is powered down. MGD Microphone 26 dB Gain Disable 0 R Normal operation. The 26 dB microphone preamp is bypassed. res Reserved for test 00000 R Must be 00000. AV3-AV0 ADC Volume 0000 R 1111 ADC volume control is implemented in the CPU, with the attenuation being -3 dB times the ADC-volume value. "R" indicates value after Reset CS6403

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Figure 10. Suggested Layout Guideline

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Several echo-canceller controls are provided in Mode 2 (16 bit) operation via the SSI control registers. In addition, visibility and control func- tions are provided through the general-purpose I/O pins (see the pin-definition section). Graded Beta "Graded Beta" is a performance enhancement used to improve the convergence speed and as- ymptotic ERLE performance of the acoustic echo canceller on the CS6403. Given a lower limit to the decay rate of the expected echo re- sponses, the CS6403 will adjust the updates to the acoustic echo canceller to take advantage of that information. By default, the CS6403 assumes a decay rate of at least 0.38 dB per ms. Based on experiments performed at Crystal, the acoustic echo-path de- cay rate for car interiors tends to be at least one dB per ms. Offices, on the other hand, tend to be more "live", with decay rate potentially below 0.38 dB per ms. Note that the minimum-ex- pected decay rate can be set via SSI_CR0 bits 3 and 2. Half-Duplex Suppression After the CS6403 is powered up or reset, 2-3 seconds of far end and near end speech must be processed by the echo cancellers to sufficiently reduce loop-gain and therefore prevent acoustic howling. To prevent howling while the echo cancellers are not properly trained, a half-duplex echo suppressor is enabled. Once the echo can- cellers are properly trained, the half-duplex suppressor is automatically disabled. (Note that whether the CS6403 is operating in half or full duplex at any particular time is indicated via the GPOUT1 output pin). This half-duplex suppressor works like the sup- pressor in a half-duplex speakerphone; i.e., it allows signals to pass through the CS6403 in only one direction at a time. The talker at one end of a conversation cannot be heard at the other end until the talker at the other end is si- lent. The half-duplex algorithm in the CS6403 has been designed to discriminate between noise and speech, and should provide good performance in noisy environments. Full-Duplex Suppression After the echo cancellers have been trained, the half-duplex suppressor is automatically disabled. This transition occurs when the ERLE perform- ance of the echo cancellers exceeds a fixed threshold. In some cases, due to impairments like non- linearities, the echo cancellers may not provide sufficient ERLE. To accommodate such situ- ations, the CS6403 provides supplementary full-duplex suppression. This full-duplex sup- pression technique provides additional ERLE using dynamic gain-control and accounts for the "Non-linear Echo Control" block in Figure 3. Operation in Noise The CS6403 echo cancellers have been designed to give good performance in noisy environments. However, for best performance, the echo cancel- lers should be trained in a low-noise environment. If the noise level is high during the training interval, the echo canceller may not be able to achieve enough ERLE to transition out of half duplex, regardless of how much speech is received. If the noise level subsequently drops sufficiently while a speech training signal is present, the echo canceller can train, allowing the CS6403 to transition to full duplex. If the noise level then increases, the echo canceller will use the path-re- sponse estimate calculated while the noise level was low, allowing the echo canceller to remain in full duplex. CS6403 DS192PP6 25

half-duplex control, and echo canceller status. at reset and mute after reset (see Table 4). able/enable, and filter coefficient control. the CS6403 may be unnecessary or undesirable. GPIN2/1/0 to either 011 or 111. Table 4. Mute Controls.

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Increase Volume (110) Setting GPIN2/1/0 to 110 for 375µS will decre- ment the volume increment counter by one step causing an increase in the SPKROUT volume. To increase volume again, the GPIN2/1/0 pins must be changed to another state before return- ing to 110. See section entitled "V olume Control/ AGC" for more details. Decrease Volume (101) Setting GPIN2/1/0 to 101 for 375µS will incre- ment the volume increment counter by one step causing an decrease in the SPKROUT volume. To decrease volume again, the GPIN2/1/0 pins must be changed to another state before return- ing to 101. The section below entitled "V olume Control/AGC" explains this function in greater detail. Don’t Care (010, 100) When the GPIN2/1/0 pins are set to 010, or 100, the CS6403 ignores the input. This state is pro- vided in order to provide a "resting place" between consecutive volume increase or volume decrease requests. Volume Control/AGC The SPKROUT volume control of the CS6403 is implemented in two stages: the upper ten volume increments are implemented by a software peak- limiting automatic gain control (AGC); the lower 32 volume increments are controlled by a hard- ware DAC attenuation stage with software compensation at the adaptive filter to avoid changing the echo path. The volume increments range from 0 (loudest) to 41 (quietest). The AGC works by comparing the digital codes coming from SDI to a threshold value, and if the signal amplitude is greater than the threshold, it is scaled down to the threshold. These signals are subsequently scaled up so that the threshold is full scale. The threshold value which is roughly determined by the formula: Threshold = Full Scale - (10 - V olume Increment) x 3dB. For example, a volume increment of 0 (the loudest output volume possible) would force signals greater than 30dB below full scale (10 x 3dB) to 30dB below full scale and then scale all signals up 30dB so that 30dB below full scale becomes full scale. When the AGC is controlling the output volume, the steps are effectively 3dB per volume incre- ment. Note that if the signals are already strong, increasing the volume may not make the sound any louder since they are already being scaled up to full scale. Also note that the AGC is effec- tively disabled by setting the volume increment to 10. The default volume increment (set upon reset) is 4. When the DAC attenuation stage is controlling the output volume, the step size is 2.5dB per volume increment. The 32 steps (from volume increment 10 to 41) yield up to 77.5dB of addi- tional attenuation. Note that if the AGCD (SSI_CR1.10) is set in Mode 2 (16-bit), then the DAC is attenuated by 10 dB (4 x 2.5 dB), and the effective volume control range is from volume increment 0 to 31, with each increment equal to 2.5 dB of attenu- ation. The volume increment defaults to 4 upon reset. If an attempt is made to increase volume beyond volume increment 0, the GPOUT0 pin will go high for 125µS. GPOUT0 will also go high if an attempt is made to decrease volume beyond volume increment 41. CS6403 DS192PP6 27

NC SCLK_RATE1 RESERVED3 SCLK_RATE0 SDO MICIN SDI AVDD SCLK AGND1 SSYNC VREF RESERVED1 VCM CONFIG AGND0 RESERVED2 PGND1 UALAW SPKROUTP RESERVED0 PVDD CLK_SEL SPKROUTN RESERVED4 PGND0 RESERVED6 CS6403

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AGND0 - Analog ground, PIN 23Q, 29L Analog ground. AGND1 - Analog ground, PIN 26Q, 32L Analog ground. A VDD - Analog supply, PIN 27Q, 33L +5V Analog supply. DGND0 - Digital ground, PIN 37Q, 43L Digital ground. DGND1 - Digital ground, PIN 38Q, 44L Digital ground. 4042 34 3638 11 23 12 14 16 18 20 22 analogdigital CS6403 - IQ 44-pin TQFP DVDD1 DVDD0 DGND1 RESET DGND0 SMASTER RESERVED5 CLKOUT GPOUT1 CLKIN GPOUT0 SFRAME GPIN2 GPIN3 GPIN1 SYNCOUT GPIN0 NC SCLK_RATE1 RESERVED3 SCLK_RATE0 SDO MICIN SDI AVDD SCLK AGND1 SSYNC VREF RESERVED1 VCM CONFIG AGND0 RESERVED2 PGND1 UALAW SPKROUTP RESERVED0 PVDD CLK_SEL SPKROUTN RESERVED4 PGND0 RESERVED6 CS6403 DS192PP6 29

DVDD0 - Digital supply, PIN 40Q, 2L Digital +5V supply. DVDD1 - Digital supply, PIN 39Q, 1L Digital +5V supply. PGND0 - Speaker-driver ground, PIN 18Q, 24L Speaker driver ground. PGND1 - Speaker-driver ground, PIN 22Q, 28L Speaker driver ground. PVDD - Speaker-driver supply, PIN 20Q, 26L Speaker-driver +5V supply. Analog I/O MICIN - ADC input, PIN 28Q, 34L Audio analog input. SPKROUTN - DAC inverted output, PIN 19Q, 25L Negative differential speaker-driver output. The voltage on SPKROUTN will decrease if the DAC value is increased. SPKROUTP - DAC output, PIN 21Q, 27L Positive differential speaker-driver output. The voltage on SPKROUTP will increase if the DAC value is increased. VCM - Voltage reference common out, PIN 24Q, 30L No time-varying loads should be attached to VCM. Output voltage is about 1V into a load of not less than 100kΩ . Must be connected to AGND0 via a 1 µF and a 0.1 µF capacitors. Connections should be made with short, fat traces. VREF - Voltage reference bypass out, PIN 25Q, 31L V oltage reference used internal to the CS6403. Must be connected to AGND0 via a 1 µF and a 0.1 µF capacitors. Connections should be made with short, fat traces. No external loads should be connected to VREF. Reserved RESERVED0 - PIN 14Q, 20L Must be grounded in normal operation. RESERVED1 - PIN 10Q, 16L Must be held high in normal operation. CS6403

30 DS192PP6

RESERVED2 - PIN 12Q, 18L Must be grounded in normal operation. RESERVED3 - PIN 5Q, 11L Must be grounded in normal operation. RESERVED4 - PIN 16Q, 22L Must be grounded in normal operation. RESERVED5 - PIN 36Q, 42L Must be grounded in normal operation. RESERVED6 - PIN 17Q, 23L Must be grounded in normal operation. Mode Control CONFIG - Configuration-control input, PIN 11Q, 17L CONFIG is used in conjunction with other configuration-control pins to control operating mode (see Table 2). Serial data is 16-bits long in Mode 2 if CONFIG is high, 8-bits if CONFIG is low. SCLK_RATE0 - SCLK frequency control, PIN 29Q, 35L Used in conjunction with SCLK_RA TE1 to set the SCLK frequency when the CS6403 is a timing slave. Possible frequencies are 2.048 MHz, 1.024 MHz, and 256 kHz, for SCLK_RA TE1:SCLK_RA TE0 being 11, 10, and 00, respectively. However, if the CS6403 is a timing master (i.e., SMASTER is high), the SCLK frequency may only be 2.048 MHz, so in this case, SCLK_RA TE0 must be high. SCLK_RATE1 - SCLK frequency control, PIN 30Q, 36L Used in conjunction with SCLK_RA TE0 to set the SCLK frequency when the CS6403 is a timing slave. Possible frequencies are 2.048 MHz, 1.024 MHz, and 256 kHz, for SCLK_RA TE1:SCLK_RA TE0 being 11, 10, and 00, respectively. However, if the CS6403 is a timing master (i.e., SMASTER is high), the SCLK frequency may only be 2.048 MHz, so in this case, SCLK_RA TE1 must be high. SFRAME - SSYNC frame/pulse control, PIN 1Q, 7L If SFRAME is high, SYNCOUT is high during serial data transactions. If SFRAME is low, SYNCOUT is pulsed high for one SCLK period before the start of a serial-data transaction. CS6403 DS192PP6 31

SMASTER - SCLK direction control, PIN 42Q, 4L SMASTER is used in conjunction with other configuration-control pins to control operating mode (see Tables 1 and 2). If SMASTER is high, the CS6403 is a timing master, meaning that SCLK is an output, and the SCLK rate is set by the on-board crystal oscillator (nominally 2.048 MHz for an 8.192 MHz crystal). If SMASTER is low, the CS6403 is a timing slave, meaning that SCLK is an input, and the SCLK rate is set by the external DSP, but SCLK_RA TE0 and SCLK_RA TE1 must be set to reflect the nominal SCLK rate. UALA W - PIN 13Q, 19L When UALAW is high, 8-bit serial data is µ-law; when UALAW is low, 8-bit serial data is A-law. Serial Digital I/O SCLK - Serial clock, PIN 8Q, 14L SCLK is the bit clock for the serial interface. It may be an output operating at 2.048 MHz or an input operating at 256 kHz, 1.024 MHz, or 2.048 MHz depending on the states of SCLK_RA TE0, SCLK_RA TE1 and SMASTER. SDI - Serial data in, PIN 7Q, 13L SDI is the serial-data input to the CS6403. SDO - Serial data out, PIN 6Q, 12L SDO is the serial-data output from the CS6403. SSYNC - Input synchronization signal for serial port, PIN 9Q, 15L SSYNC is the serial-data synchronization strobe used when the CS6403 is a system-timing slave. Should be grounded in master mode (SMASTER = 1). SYNCOUT - Output synchronization signal for serial port, PIN 3Q, 9L SYNCOUT is the serial-data synchronization strobe used when the CS6403 is a system-timing master. Timing and duration depends on SFRAME. Miscellaneous CLK_SEL - PIN 15Q, 21L Disable the on-chip phase-locked loop when high. CLKIN - System input clock from external master, PIN 44Q, 6L If the CS6403 is a system-timing master, a 8.192 MHz clock-crystal circuit is connected between CLKIN and CLKOUT. If the CS6403 is a system-timing slave, CLKIN must be grounded. CLKOUT - System output clock, PIN 43Q, 5L If the CS6403 is a system-timing master, a 8.192 MHz clock-crystal circuit is connected between CLKIN and CLKOUT. Otherwise, CLKOUT is unconnected. CS6403

32 DS192PP6

GPOUT0 is high when a volume change request is made that exceeds the available range. GPOUT1 is high while the CS6403 is in half-duplex mode during initial convergence. NC must be left floating in normal operation. Table 5. Algorithmic Controls.

The rejection of input frequencies in the frequency range >Fs/2 of all multiples of the input sample rate (64 x Fs). This rejection is almost solely dependent on the external input RC. Audible (<20kHz) Noise The DAC audible noise floor. Measured by applying a -60dB, 1kHz sine wave. S/(N+D) is then measured (over a Fs/2 to 20kHz bandwidth). Then add 60dB to the answer, to compensate for the -60dB signal level. Convergence The process by which an echo canceller improves its path estimate, thereby improving its echo return-loss enhancement. Convergence is complete once the echo return-loss enhancement reaches its best value for a given environment. Differential Nonlinearity The worst case deviation from the ideal codewidth. Units in LSB. ERLE Echo signal-power reduction (Echo Return-Loss Enhancement) provided by an echo canceller. Maximum ERLE for an echo canceller is dependent on training-signal statistics and echo-path attributes. Units in dB. Frequency Response Worst case variation in output signal level versus frequency over the passband (20Hz to 0.45Fs), referenced to the level at 1kHz. Units in dB. Instantaneous Dynamic Range IDR is the ratio of a full-scale rms signal to the rms noise available at any instant in time, without changing the input gain or output attenuation settings. It is measured using S/(N+D) with a 1 kHz, -60 dB input signal, with 60 dB added to compensate for the small input signal. Use of a small input signal reduces the harmonic distortion components to insignificance when compared to the noise. Units in dB. Integrated Inaudible (>20kHz) Energy The integrated signal level on the analog output pin after a 20kHz hi-pass filter. Zero digital input into the DAC. Units in mVrms. Offset Error For the ADC, the deviation of the output code from the mid-scale with the selected input at VCM. For the DAC, the deviation of the output from VCM with mid-scale input code. Units in LSB’s for the ADC and millivolts for the DAC. CS6403

34 DS192PP6

The number of bits in the input words to the DAC, and in the output words from the ADC. Total Dynamic Range TDR is the ratio of the rms value of a full scale signal to the lowest obtainable noise floor. It is measured by comparing a full scale signal to the lowest noise floor possible in the codec (i.e., attenuation bits for the DAC at full attenuation). Units in dB. Total Harmonic Distortion THD is the ratio of the rms amplitude of the test signal to the rms sum of all the harmonic components. 1 kHz is used for testing. Units in dB. CS6403 DS192PP6 35

• • Notes •• CS6403

36 DS192PP6

Copyright  Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CDB6403 Evaluation Board for CS6403 /c108 Easy access to CS6403 SSI /c108 Phantom power for microphone /c108 Easy access to algorithm controls /c108 Includes far-end codec for stand-alone operation /c108 Analog and Digital Patch Area The CDB6403 allows an end-user to quickly integrate the CS6403 Echo Cancelling Codec into a system and evaluate its performance. The board provides everything needed to enable flexible setup and evaluation. Evalua- tion requires only a +5 V power supply for standalone mode testing. Connections for analog audio sources are provided on the board. I PCM Codec CS6403 Analog Patch Area SSI EPLD Reset DIP Switch+5VA +5VD AGND DGND A L G O R I T H M C O N T R O L Digital Patch Area FE_IN FE_OUT SPKROUT MICIN LEDS MAR ‘96 DS192DB3

the board and the other powers the digital side. circuitry in greater detail. allows you to connect directly to an 8Ω speaker. area and connect it to the SPKROUT connector. The MICIN connector is a 1/8" stereo jack. provide an alternative connector. ure 2 shows how this circuitry is implemented. a stable 1 V reference produced by the CS6403. stable 2.3VDC output for phantom power. sure good common mode rejection. Figure 1. Power Supply Circiutry Figure 2. Microphone Phantom Power and Supplemental Amplifier

38 DS192DB3

Figure 4. CS6403 and Associated Circuitry

40 DS192DB3

anything is connected to the SSI. signal for the CS6403 and debounces the switch. EPLD and connected switches. the echo canceller is converged. FE_OUT will be whatever is received at MICIN. the output volume of the SPKROUT pins. to go out of the volume range. mode enabled and volume level of 4. Figure 6. Synchronous Serial Interface (SSI)

42 DS192DB3

flashing the LED momentarily. Figure 7. EPLD and Algorithm Controls

The DIP switch SW7 provides access to mode setting pins on the CS6403. The default settings indicate how it is shipped from the factory (Mode 1). When a switch is in the ON position, a logic low is applied to the corresponding pin on the CS6403. Conversely, the OFF position corre- sponds to logic high. Pin Name ON Definition OFF Definition Default SFRAME Pulse-type SYNC Frame-type SYNC ON SMASTER SCLK is an input SCLK is an output OFF SCLK_RA TE1 see note OFF SCLK_RA TE0 see note OFF CONFIG Mode 1 Mode 2 ON UALAW A-law companding µ-law companding OFF GPIN3 26dB Mic gain on 26dB Mic gain off ON CLK_SEL PLL active PLL bypassed (use CLKIN) ON Note: SCLK_RATE1 and SCLK_RATE0 determine the frequency of SCLK the part should expect in Mode 1. In Mode 2, both of these switches should be OFF . Mode 1 SCLK frequency is given by the fol- lowing table: SCLK_RATE1 SCLK_RATE0 SCLK Frequency ON ON 256kHz ON OFF Invalid OFF ON 1.024MHz OFF OFF 2.048MHz Using the CDB6403 Evaluation Board General Setup The CDB6403 requires only a +5V power sup- ply capable of sourcing 200mA of current in order to work. It is important to power both the analog and digital sections. Separate power sup- plies would be ideal, however, separate leads from the same power supply is acceptable. Once power is applied, press the RESET button to en- sure the board is in a known state. Definitions We define the near-end as the end where the pri- mary echo exists. Signal comes out of the near-end output and is picked up by the near-end input. For speakerphone applications, the near- end would be the acoustic path between the microphone and speaker. For network echo can- cellers, the near-end would consist of the lossy hybrid. The near-end input of the CS6403 is the MICIN pin and the near-end output is the SPKROUT pins. The near-end input is some- times referred to as the transmit input (TXI) and the near-end output is similarly sometimes called the receive output (RXO). We define the far-end as the end where either no echo or secondary echo exists. Signal presented to the far-end input comes out the near-end out- put. Echo cancelled near-end input signal comes out the far-end output. For speakerphone appli- cations, the far-end would be the network side of the phone. The CS6403 far-end interface is digi- tal (via the SSI). For Mode 1 applications, a PCM codec is provided as an analog interface with FE_IN as the far-end input and FE_OUT as the far-end output. Mode 2 applications connect directly to the SSI of the CDB6403. Receive in- put (RXI) and transmit output (TXO) are other names commonly used to refer to far-end input and far-end output, respectively. CDB6403

44 DS192DB3

By default, the CS6403 runs with an internal 26dB gain stage on MICIN. This feature is not desirable in some applications and so GPIN3 is provided to disable this feature. If the applica- tion you wish to implement needs the additional 26dB MICIN gain, set GPIN3 to ground, other- wise set it high. The 26dB disable/enable status is read only at reset. If the state of GPIN3 is toggled anytime after reset, the CS6403 MICIN will be muted. Mode 1 Setup To configure the CDB6403 for Mode 1 opera- tion, the DIP switches should be set as follows (* indicates a non-mode specific option): Switch State Details SFRAME ON* Pulse-type SYNC (frame-type should work, also) SMASTER OFF CS6403 must source SCLK SCLK_RA TE1 OFF Mode 1 requires 2.048MHz SCLK to be generated SCLK_RA TE0 OFF Mode 1 requires 2.048MHz SCLK to be generated CONFIG ON Select Mode 1 UALAW OFF* Select µ-law companding (A- law should work, also) GPIN3 ON* Enable MIC gain (may not be necessary) CLK_SEL ON Enable on-chip PLL Connect the far-end signals to FE_IN and FE_OUT, and the near-end signals to MICIN and SPKROUT. Mode 2 Setup To configure the CDB6403 for Mode 2 opera- tion, the DIP switches should be set as follows (* indicates a non-mode specific option): Switch State Details SFRAME ON Pulse-type SYNC SMASTER ON CS6403 must slave to SCLK SCLK_RA TE1 OFF* Varies based on SCLK presented to SSI SCLK_RA TE0 OFF* Varies based on SCLK presented to SSI CONFIG OFF Select Mode 2 UALAW OFF* Since data is linear in Mode 2, this does not apply GPIN3 ON* Enable MIC gain (may not be necessary) CLK_SEL ON Enable on-chip PLL Connect the near-end signals to MICIN and SPKROUT. The far-end signals should be provided through the SSI. A DSP serial port is ideal for this. Setting the CDB6403 up to interface to line-level signals Much audio equipment is designed to expect line-level signals. These signals are a maximum of 2Vrms or approximately 5.6Vpp. The CDB6403 is not configured to handle signals of this amplitude by default, but can be easily modified to accommodate it. To configure the far-end input, FE_IN, to accom- modate 5.6Vpp, we have to scale down the signal to 3.15Vpp (full scale input of the MC145480). This is easily accomplished by merely changing R2 and R9 to 5.6kΩ , which will change the gain of the differential amplifier at the input to the MC145480 to 0.56 (3.15/5.6). CDB6403 DS192DB3 45

FE_OUT is capable of producing 6.3Vpp differ- entially or 3.15Vpp single-ended. If the equipment intended to interface to FE_OUT is capable of accepting a differential input, a resis- tive divider which attenuates the differential signal by a factor of 0.89 will be sufficient. If the equipment requires a ground reference, an external amplifier providing a gain of 1.78 to the single-ended signal is necessary. The full-scale input at MICIN is 2Vpp with the gain stage off (GPIN3 is high). The gain of the differential amplifier provided by U100 needs to be decreased to 0.36 times. Replacing R104 and R105 with 3.6kΩ resistors and changing C101 to 0.74 µF (0.68µF in parallel with 0.068µF) will change the gain appropriately while maintaining good common-mode rejection at all frequencies. It is important to make sure that the opamp is referenced around >2VDC rather than VCM, as clipping is likely to occur otherwise. This change is described in the sec- tion explaining the Microphone Circuitry. SPKROUT drives 1.75Vpp with respect to ground out of both SPKROUTP and SPKROUTN. Even taken differentially, the re- sulting 3.5Vpp is not enough to reach the required 5.6Vpp. An external amplifier provid- ing 3.2 times gain to SPKROUTP is required to produce the required output signal level. Troubleshooting Tips If the CDB6403 is not working properly or is not working as expected, this list of common setup problems may help. General hints:

• Make sure 5VDC is applied to both the digi- tal and analog supplies.
• RESET the evaluation board after powerup.
• The MICIN jack is self-shorting. Make sure there is either something in the jack or that the traces to the capacitors have been cut.
• When the 26dB gain stage is not in use, the differential amplifier provided by U100 should be referenced around >2V , not VCM.
• Signal applied at FE_IN will come out of SPKROUT. Signal applied at MICIN will come out of FE_OUT.
• The signal applied at FE_IN should only be picked up by MICIN from SPKROUT.
• Constant power signals (such as fixed ampli- tude sine waves) will attenuate after several seconds as the noise estimators determine this signal to be noise. Mode 1 hints:
• If the GPOUT1 LED is not lit after RESET, the board is not operating properly. Make sure the crystal is in the socket and make sure it is oscillating. SCLK should be 2.048MHz.
• Make sure CONFIG is ON. Otherwise the MC145480 is powered down.
• The default operation of the CS6403 will force half-duplex mode upon powerup. Sev- eral seconds of speech in both transmit and receive directions will be necessary for full- duplex operation. Mode 2 hints:
• Make sure CONFIG is OFF. This powers down the MC145480 and avoids contention on SDI.
• Make sure SCLK and SSYNC are being re- ceived. CDB6403

46 DS192DB3

Echo Return-Loss Enhancement (ERLE) is de- fined as the amount of attenuation in echo that the echo canceller provides, usually expressed in decibels. In general, half-duplex should be dis- abled for ERLE measurement. For best case performance, a sine wave is an ideal far-end input signal. Provide a -6dBFS sine wave at 1kHz to the far-end input (the SSI in Mode 2 or the far-end codec in Mode 1). It should come out the SPKROUT and couple to MICIN. The signal at MICIN will then be pre- sent at the far-end output. Measure this with coefficients cleared (RMS voltage is suggested). Measure again after the echo canceller has adapted (coefficients in normal mode). The dif- ference between the decibel value of the two is the ERLE in dB. To test with real speech, use an easily repeatable speech sample. Capture the non-cancelled speech with a Digital Storage Oscilloscope that can calculate RMS voltage. Do the same for the cancelled speech. There should be a delay of about five seconds of far-end speech before mak- ing the measurement to ensure that the echo canceller has time to adapt. Convergence Time Convergence is loosely defined to be the state at which the echo canceller has adapted sufficiently to render the echo inaudible. Therefore, conver- gence time may be defined as the time required for convergence from cleared coefficients. Convergence time may be measured using the Digital Storage Oscilloscope approach men- tioned above. Once a level of attenuation which defines convergence has been chosen, a compari- son of the pre-canceller and post-canceller voltage levels should indicate when convergence occurs. Half-Duplex The half-duplex mode of the echo canceller is provided as a fail-safe mechanism to ensure communication in situations where the echo can- celler is not providing enough ERLE for good quality conversation. To freeze the CDB6403 in half-duplex mode, push the "HD ON" switch and move the switch to the "CLEAR" position. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 CDB6403 DS192DB3 47

Figure 8. CDB6403 Silk Screen

48 DS192DB3

Figure 9. CDB6403 Component Side

Figure 10. CDB6403 Solder Side

50 DS192DB3

e MILLIMETERS INCHES DIM D/E D1/E1 e b 0.462 0° 0° 11.75 MIN MAX 1.45 MIN MAX 0.057 10.10 12.25 3.5° 0.398 0.482 b A 1.60 0.05 0.063 0.002 c 0.20 0.008 c 0.45 0.75 0.018 0.030 1.35 0.053 9.90 0.390 A

44 PIN TQFP

D E1 E ∝∝ A2 L L 0.70 0.45 0.026 0.014 0.0360.90 0.0180.30 0.09 0.004 NOM 0.15 0.006 NOM 3.5° 12.0 0.60 1.40 10.0 0.80 0.37 0.145 0.472 0.024 0.055 0.394 0.031 0.016 0.006 ccc 0.10 0.004 7° 7° ccc

44 LEAD TQFP

D D2/E2 44 pin PLCC NO. OF TERMINALS D2/E2 MAXMIN MAX MIN MILLIMETERS INCHES DIM A D/E 17.6517.40 0.685 B e AA1 B e 0.695 16.6616.51 0.650 0.656 4.574.20 0.180 0.165 0.530.33 0.021 0.013 2.29 0.090 16.0014.99 0.590 0.630 1.19 1.35 0.047 0.053 NOM 17.53 16.59 4.45 0.41 2.79 15.50 1.27 NOM 0.690 0.653 0.175 0.016 0.110 0.610 0.050 3.04 0.120 D1/E1

/G0.OTES/G0