CS61884_05 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
Industry-standard Footprint Octal E1/T1/J1 Short-haul Line Interface Unit Low Power No external component changes for 100 Ω/120 Ω/75 Ω operation. Pulse shapes can be customized by the user. Internal AMI, B8ZS, or HDB3 Encoding/Decoding LOS Detection per T1.231, ITU G.775, ETSI 300-233 G.772 Non-Intrusive Monitoring G.703 BITS Clock Recovery Crystal-less Jitter Attenuation Serial/Parallel Microprocessor Control Interfaces Transmitter Short Circuit Current Limiter (<50mA) TX Drivers with Fast High-Z and Power Down JTAG boundary scan compliant to IEEE 1149.1. 144-Pin LQFP or 160-Pin BGA Package
ORDERING INFORMATION
CS61884-IQZ 144-pin LQFP , Lead Free CS61884-IB 160-pin FBGA
Description
The CS61884 is a full-featured octal E1/T1/J1 short-haul LIU that supports both 1.544 Mbps or 2.048 Mbps data transmission. Each channel provides crystal-less jitter attenuation that complies with the most stringent stan- dards. Each channel also provides internal AMI/B8ZS/HDB3 encoding/decoding. To support en- hanced system diagnostics, channel zero can be configured for G.772 non-intrusive monitoring of any of the other 7 channels’ receive or transmit paths. The CS61884 makes use of ultra-low-power, matched- impedance transmitters and receivers to reduce power beyond that achieved by tr aditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additional- ly, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent power down and High-Z. Each receiver provides reliable data recovery with over 12 dB of cable atte nuation. The receiver also incorpo- rates LOS detection compliant to the most recent specifications. RPOS RNEG TPOS TNEG TCLK LOS RTIP RRING TTIP TRING RCLK JTAG Interface Remote Loopback Digital Loopback Analog Loopback Decoder Driver Receiver LOS G.772 Monitor Transmit Control Pulse Shaper Data Recovery Jitter Attenuator Clock Recovery Encoder Host Interface JTAG Serial Port Host Serial/Parallel Port AUG ‘05 DS485F1
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Contacting Cirrus Logic Support Visit the Cirrus Logic web site at: http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CR ITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDER- STOOD TO BE FULLY AT THE CUST OMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
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PP4 May ‘04 Preliminary release. F1 Aug ‘05 Added lead-free, 144-pin LQFP package option.
Figure 1. CS61884 144-Pin Outs
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160 FBGA
Figure 2. CS61884 160-Ball FBGA Pin Outs
- PIN DESCRIPTIONS
3.1 Power Supplies
SYMBOL LQFP FBGA TYPE DESCRIPTION VCCIO G14 Power Supply, Digital Interface: Power supply for digital interface pins; typically 3.3V. GNDIO 18 G11 Ground, Digital Interface: Power supply ground for the digital interface; typically 0 Volts RV0+ RV1+ H14 Power Supply, Core Circuitry: Power supply for all sub-cir- cuits except the transmit driver; typically +3.3 Volts RGND0 RGND1 H11 Ground, Core Circuitry: Ground for sub-circuits except the TX driver; typically 0 Volts TV+0 44 N4, P4 Power Supply, Transmit Driver 0 Power supply for transmit driver 0; typically +3.3 Volts TGND0 47 N6, P6 Ground, Transmit Driver 0 Power supply ground for transmit driver 0; typically 0 Volts TV+1 53 L4, M4 Power Supply, Transmit Driver 1 TGND1 50 L6, M6 Ground, Transmit Driver 1 TV+2 56 L11 M11 Power Supply, Transmit Driver 2 TGND2 59 L9, M9 Ground, Transmit Driver 2 TV+3 65 N11 P11 Power Supply, Transmit Driver 3 TGND3 62 N9, P9 Ground, Transmit Driver 3 TV+4 116 A11 B11 Power Supply, Transmit Driver 4 TGND4 119 A9, B9 Ground, Transmit Driver 4 TV+5 125 C11 D11 Power Supply, Transmit Driver 5 TGND5 122 C9, Ground, Transmit Driver 5 TV+6 128 C4, Power Supply, Transmit Driver 6 TGND6 131 C6, Ground, Transmit Driver 6 TV+7 137 A4, B4 Power Supply, Transmit Driver 7 TGND7 134 A6, B6 Ground, Transmit Driver 7
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3.2 Control
either 1.544 MHz for T1/J1 or 2.048 MHz for E1 operation. function as simple data slicers. Serial host, Parallel host or Hardware mode. MODE (See Section 13 on page 32). Table 1. Operation Mode Selection
face for multiplexed or non-multiplexed operation.
82 K13 O
active are maskable via internal interrupt enable registers. tion of the bus cycl e, this pin High-Z. RZ mode (No Clock Recovery). whether SDO is valid on the ri sing or falling edge of SCLK. Upon completion of the bus cycle, this pin High-Z. Table 2. Mux/Bits Clock Selection
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Data Strobe/ Write Enable/S erial Data/Line Length Input Intel Parallel Host Mode - This pin “WR” functions as a write enable. Motorola Parallel Host Mode - This pin “DS“ functions as a data strobe input. Serial Host Mode - This pin “SDI” functions as the serial data input. Hardware Mode - As LEN0, this pin controls the transmit pulse shapes for both E1 and T1/J1 modes. This pin also selects which mode is used E1 or T1/J1 (Refer to Table 5 on page 25). RD/RW/LEN1 85 J13 I Read/Write/ Read Enable/Line Length Input Intel Parallel Host Mode - This pin “RD” functions as a read enable. Motorola Parallel Host Mode - This pin “R/W” functions as the read/write input signal. Hardware Mode - As LEN1, this pin controls the transmit pulse shapes for both E1 and T1/J1 modes. This pin also selects which mode is used E1 or T1/J1 (Refer to Table 5 on page 25). ALE/AS /SCLK/LEN2 86 J12 I Address Latch Enable/Serial Clock/Address Strobe/Line Length Input Intel Parallel Host Mode - This pin “ALE” functions as the Address Latch Enable when configured for multiplexed ad- dress/data operation. Motorola Parallel Host Mode - This pin “AS” functions as the active “low” address strobe when configured for multi- plexed address/data operation. Serial Host Mode - This pin “SCLK” is the serial clock used for data I/O on SDI and SDO. Hardware Mode - As LEN2, this pin controls the transmit pulse shapes for both E1 and T1/J1 modes. This pin also selects which mode is used E1 or T1/J1 (Refer to Table 5 on page 25). CS /JASEL 87 J11 I Chip Select Input/Jitter Attenuator Select Host Mode - This active low input is used to enable ac- cesses to the microprocessor interface in either serial or parallel mode. Hardware Mode - This pin controls the position of the Jitter Attenuator. SYMBOL LQFP FBGA TYPE DESCRIPTION Pin State Jitter Attenuation Position LOW Transmit Path HIGH Receive Path OPEN Disabled
Motorola/Intel/Coder Mode Select Input Parallel Host Mode - When this pin is “Low” the micropro- cessor interface is configur ed for operation with Motorola processors. When this pin is “High” the microprocessor in- terface is configured for operation with Intel processors. Hardware Mode - When the CS61884 is configured for uni- polar operation, this pin, CODEN , configures the line encoding/decoding function. When CODEN is low, B8ZS/HDB3 encoders/decoders are enabled for T1/J1 or E1 operation respectively. When CODEN is high, AMI en- coding/decoding is activated. This is done for all eight channels. TXOE 114 E14 I Transmitter Output Enable Host mode - Operates the same as in hardware mode. In- dividual drivers can be set to a high impedance state via the Output Disable Register (12h) (See Section 14.19 on page 39). Hardware Mode - When TXOE pin is asserted Low, all the TX drivers are forced into a high impedance state. All other internal circuitry remains active. CLKE 115 E13 I Clock Edge Select In clock/data recovery mode , setting CLKE “high” will cause RPOS/RNEG to be valid on th e falling edge of RCLK and SDO to be valid on the rising edge of SCLK. When CLKE is set “low”, RPOS/RNEG is valid on the rising edge of RCLK, and SDO is valid on the fallin g edge of SCLK. When the part is operated in data recovery mode, the RPOS/RNEG output polarity is active “high” when CLKE is set “high” and active “low” when CLKE is set “low”. SYMBOL LQFP FBGA TYPE DESCRIPTION
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3.3 Address Inputs/Loopbacks
SYMBOL LQFP FBGA TYPE DESCRIPTION A4 12 F4 I Address Selector Input Parallel Host Mode - During non-multiplexed parallel host mode operation, this pin functi on as the address 4 input for the parallel interface. Hardware Mode - The A4 pin must be tied low at all times. I I I I Non-Intrusive Monitoring/Address Selector Inputs Parallel Host Mode - During non-multiplexed parallel host mode operation, these pins f unction as address A[3:0] in- puts for the parallel interface. Hardware Mode - The A[3:0] pins are used for port selec- tion during non-intrusive monitoring. In non-intrusive monitoring mode, receiver 0’s input is internally connected to the transmit or receive ports on one of the other 7 chan- nels. The recovered clock and data from the selected port are output on RPOS0/RNEG0 and RCLK0. Additionally, the data from the selected port can be output on TTIP0/TRING0 by activating th e remote loopback function for channel 0 (Refer to Performance Monitor Register (0Bh) (See Section 14.12 on page 36). LOOP0/D0 LOOP1/D1 LOOP2/D2 LOOP3/D3 LOOP4/D4 LOOP5/D5 LOOP6/D6 LOOP7/D7 I/O I/O I/O I/O I/O I/O I/O I/O Loopback Mode Selector/Parallel Data Input/Output Parallel Host Mode - In non-multiplexed microprocessor in- terface mode, these pins function as the bi-directional 8-bit data port. When operating in multiplexed microprocessor in- terface mode, these pins function as the address and data inputs/outputs. Hardware Mode - No Loopback - The CS61884 is in a normal operating state when LOOP is left open (unconnected) or tied to VCCIO/2. - Local Loopback - When LOOP is tied High, data transmit- ted on TTIP and TRING is looped back into the analog input of the corresponding chan nel’s receiver and output on RPOS and RNEG. Input Data present on RTIP and RRING is ignored. - Remote Loopback - When LOOP is tied Low the recov- ered clock and data received on RTIP and RRING is looped back for transmission on TTIP and TRING. Data on TPOS and TNEG is ignored.
3.4 Cable Select
3.5 Status
Table 3. Cable Impedance Selection
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3.6 Digital Rx/Tx Data I/O
SYMBOL LQFP FBGA TYPE DESCRIPTION TCLK0 36 N1 I Transmit Clock Input Port 0 - When TCLK is active, the TP OS and TNEG pins function as NRZ inputs that are samp led on the falling edge of TCLK. - If MCLK is active, TAOS will be generated when TCLK is held High for 16 MCLK cycles. NOTE: MCLK is used as the timing reference during TAOS and must have the appropriate stability. - If TCLK is held High in the absence of MCLK, the TPOS and TNEG inputs function as RZ inputs. In this mode, the transmit pulse width is set by the pulse-width of the signal input on TPOS and TNEG. To enter this mode, TCLK must be held high for at least 12 µS. - If TCLK is held Low, the output drivers enter a low-power, high impedance state. TPOS0/TDATA0 TNEG0/UBS I I Transmit Positive Pulse/Transmit Data Input Port 0 Transmit Negative Pulse/Unipolar-Bipolar Select Port 0 The function of the TPOS/TDATA and TNEG/UBS inputs are determined by whether Unipolar, Bipolar or RZ input mode has been selected. Bipolar Mode - In this mode, NRZ data on TPOS and TNEG are sampled on the fallin g edge of TCLK and trans- mitted onto the line at TTIP and TRING respectively. A “High” input on TPOS results in transmission of a positive pulse; a “High” input on TNEG results in a transmission of a negative pulse. The translation of TPOS/TNEG inputs to TTIP/TRING outputs is as follows: Unipolar mode - Unipolar mode is activated by holding TNEG/UBS “High” for more than 16 TCLK cycles, when MCLK is present. The falling edge of TCLK samples a uni- polar data steam on TPOS/TDATA. RZ Mode - To activate RZ mode tie TCLK “High” with the absence of MCLK. In this mode, the duty cycle of the TPOS and TNEG inputs determine the pulse width of the output signal on TTIP and TRING. TPOS TNEG OUTPUT
00 S p a c e
11 S p a c e
Receive Clock Output Port 0 - When MCLK is active, this pin outputs the recovered clock from the signal input on RTIP and RRING. In the event of LOS, the RCLK output transitions from the recovered clock to MCLK. - If MCLK is held “High”, the clock recovery circuitry is dis- abled and the RCLK output is driven by the XOR of RNEG and RPOS. - If MCLK is held “Low”, this output is in a high-impedance state. RPOS0/RDATA0 RNEG0/BPV0 O O Receive Positive Pulse/ Receive Data Output Port 0 Receive Negative Pulse/Bipolar Violation Output Port 0 The function of the RPOS /RDATA and RNEG/BPV outputs are determined by whether Unipolar, Bipolar, or RZ input mode has been selected. During LOS, the RPOS/RNEG outputs will remain active. NOTE: The RPOS/RNEG outputs can be High-Z by holding MCLK Low. Bipolar Output Mode - When configured for Bipolar opera- tion, NRZ Data is recovered from RTIP/RRING and output on RPOS/RNEG. A high signal on RPOS or RNEG corre- spond to the receipt of a positive or negative pulse on RTIP/RRING respectively. The RPOS/RNEG outputs are valid on the falling or rising edge of RCLK as configured by CLKE. Unipolar Output Mode - When unipolar mode is activated, the recovered data is output on RDATA. The decoder sig- nals bipolar Violations on the RNEG/BPV pin. RZ Output Mode - In this mode, th e RPOS/RNEG pins output RZ data recovered by s licing the signal present on RTIP/RRING. A positive pulse on RTIP with respect to RRING generates a logic 1 on RPOS; a positive pulse on RRING with respect to RTIP generates a logic 1 on RNEG. The polarity of the output on RPOS/RNEG is selectable us- ing the CLKE pin. In this mode, external circuitry is used to recover clock from the received signal. TCLK1 29 L1 I Transmit Clock Input Port 1 TPOS1/TDATA1 30 L2 I Transmit Positive Pulse/Transmit Data Input Port 1 TNEG1/UBS1 31 L3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 1 RCLK1 32 M1 O Receive Clock Output Port 1 RPOS1/RDATA1 33 M2 O Receive Positive Pulse/ Receive Data Output Port 1 RNEG1/BPV1 34 M3 O Receive Negative Pulse/Bipolar Violation Output Port 1 TCLK2 81 L14 I Transmit Clock Input Port 2 TPOS2/TDATA2 80 L13 I Transmit Positive Pulse/Transmit Data Input Port 2 TNEG2/UBS2 79 L12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 2 SYMBOL LQFP FBGA TYPE DESCRIPTION
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RCLK2 78 M14 O Receive Clock Output Port 2 RPOS2/RDATA2 77 M13 O Receive Positive Pulse/ Receive Data Output Port 2 RNEG2/BPV2 76 M12 O Receive Negative Pulse/Bipolar Violation Output Port 2 TCLK3 74 N14 I Transmit Clock Input Port 3 TPOS3/TDATA3 73 N13 I Transmit Positive Pulse/Transmit Data Input Port 3 TNEG3/UBS3 72 N12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 3 RCLK3 71 P14 O Receive Clock Output Port 3 RPOS3/RDATA3 70 P13 O Receive Positive Pulse/ Receive Data Output Port 3 RNEG3/BPV3 69 P12 O Receive Negative Pulse/Bipolar Violation Output Port 3 TCLK4 107 B14 I Transmit Clock Input Port 4 TPOS4/TDATA4 108 B13 I Transmit Positive Pulse/Transmit Data Input Port 4 TNEG4/UBS4 109 B12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 4 RCLK4 110 A14 O Receive Clock Output Port 4 RPOS4/RDATA4 111 A13 O Receive Positive Pulse/ Receive Data Output Port 4 RNEG4/BPV4 112 A12 O Receive Negative Pulse/Bipolar Violation Output Port 4 TCLK5 100 D14 I Transmit Clock Input Port 5 TPOS5/TDATA5 101 D13 I Transmit Positive Pulse/Transmit Data Input Port 5 TNEG5/UBS5 102 D12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 5 RCLK5 103 C14 O Receive Clock Output Port 5 RPOS5/RDATA5 104 C13 O Receive Positive Pulse/ Receive Data Output Port 5 RNEG5/BPV5 105 C12 O Receive Negative Pulse/Bipolar Violation Output Port 5 TCLK6 9 D1 I Transmit Clock Input Port 6 TPOS6/TDATA6 8 D2 I Transmit Positive Pulse/Transmit Data Input Port 6 TNEG6/UBS6 7 D3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 6 RCLK6 6 C1 O Receive Clock Output Port 6 RPOS6/RDATA6 5 C2 O Receive Positive Pulse/ Receive Data Output Port 6 RNEG6/BPV6 4 C3 O Receive Negative Pulse/Bipolar Violation Output Port 6 TCLK7 2 B1 I Transmit Clock Input Port 7 TPOS7/TDATA7 1 B2 I Transmit Positive Pulse/Transmit Data Input Port 7 TNEG7/UBS7 144 B3 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 7 SYMBOL LQFP FBGA TYPE DESCRIPTION
3.7 Analog RX/TX Data I/O
RCLK7 143 A1 O Receive Clock Output Port 7 RPOS7/RDATA7 142 A2 O Receive Positive Pulse/ Receive Data Output Port 7 RNEG7/BPV7 141 A3 O Receive Negative Pulse/Bipolar Violation Output Port 7 SYMBOL LQFP FBGA TYPE DESCRIPTION SYMBOL LQFP FBGA TYPE DESCRIPTION TTIP0 TRING0 O O Transmit Tip Output Port 0 Transmit Ring Output Port 0 TTIP and TRING pins are the differential outputs of the transmit driver. The driver internally matches impedances for E1 75 Ω, E1 120 Ω and T1/J1 100 Ω lines requiring only a 1:2 transformer. The CBLSEL pin is used to select the appropriate line matching impedance only in “Hardware” mode. In host mode, the appropriate line matching imped- ance is selected by the Line Length Data Register (11h) (See Section 14.18 on page 39). NOTE: TTIP and TRING are forced to a high impedance state when the TCLK pin is “Low” for over 12 µS or the TXOE pin is forced “Low”. RTIP0 RRING0 I I Receive Tip Input Port 0 Receive Ring Input Port 0 RTIP and RRING are the differential line inputs to the re- ceiver. The receiver uses either Internal Line Impedance or External Line Impedance modes to match the line imped- ances for E1 75 Ω, E1 120Ω or T1/J1 100 Ω modes. Internal Line Impedance Mode - The receiver uses the same external resistors to ma tch the line impedance (Refer to Figure 17 on page 51). External Line Impedance Mode - The receiver uses differ- ent external resistors to matc h the line impedance (Refer to Figure 18 on page 52). - In host mode, the appropriate line impedance is selected by the Line Length Data Register (11h) (See Section 14.18 on page 39). - In hardware mode, the CBLSEL pin in combination with the LEN pins select the appropriate line impedance. (Refer to Table 3 on page 15 for proper line impedance settings). NOTE: Data and clock recovered from the signal input on these pins are output via RCLK, RPOS, and RNEG. TTIP1 52 L5 O Transmit Tip Output Port 1 TRING1 51 M5 O Transmit Ring Output Port 1 RTIP1 55 M7 I Receive Tip Input Port 1 RRING1 54 L7 I Receive Ring Input Port 1
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TTIP2 57 L10 O Transmit Tip Output Port 2 TRING2 58 M10 O Transmit Ring Output Port 2 RTIP2 60 M8 I Receive Tip Input Port 2 RRING2 61 L8 I Receive Ring Input Port 2 TTIP3 64 N10 O Transmit Tip Output Port 3 TRING3 63 P10 O Transmit Ring Output Port 3 RTIP3 67 P8 I Receive Tip Input Port 3 RRING3 66 N8 I Receive Ring Input Port 3 TTIP4 117 B10 O Transmit Tip Output Port 4 TRING4 118 A10 O Transmit Ring Output Port 4 RTIP4 120 A8 I Receive Tip Input Port 4 RRING4 121 B8 I Receive Ring Input Port 4 TTIP5 124 D10 O Transmit Tip Output Port 5 TRING5 123 C10 O Transmit Ring Output Port 5 RTIP5 127 C8 I Receive Tip Input Port 5 RRING5 126 D8 I Receive Ring Input Port 5 TTIP6 129 D5 O Transmit Tip Output Port 6 TRING6 130 C5 O Transmit Ring Output Port 6 RTIP6 132 C7 I Receive Tip Input Port 6 RRING6 133 D7 I Receive Ring Input Port 6 TTIP7 136 B5 O Transmit Tip Output Port 7 TRING7 135 A5 O Transmit Ring Output Port 7 RTIP7 139 A7 I Receive Tip Input Port 7 RRING7 138 B7 I Receive Ring Input Port 7 SYMBOL LQFP FBGA TYPE DESCRIPTION
3.8 JTAG Test Interface
3.9 Miscellaneous
SYMBOL LQFP FBGA TYPE DESCRIPTION TRST 95 G12 I JTAG Reset This active Low input resets the JTAG controller. This input is pulled up internally and may be left as a NC when not used. TMS 96 F11 I JTAG Test Mode Select Input This input enables the JTAG se rial port when active High. This input is sampled on the risi ng edge of TCK. This input is pulled up internally and may be left as a NC when not used. TCK 97 F14 I JTAG Test Clock Data on TDI is valid on the rising edge of TCK. Data on TDO is valid on the falling edge of TCK. When TCK is stopped high or low, the contents of all JTAG registers re- main unchanged. Tie pin low through a 10 K Ω resistor when not used. TDO 98 F13 O JTAG Test Data Output JTAG test data is shifted out of the device on this pin. Data is output on the fa lling edge of TCK. Le ave as NC when not used. TDI 99 F12 I JTAG Test Data Input JTAG test data is shifted into the device using this pin. The pin is sampled on the rising edge of TCK. TDI is pulled up internally and may be left as a NC when not used. SYMBOL LQFP FBGA TYPE DESCRIPTION REF 94 H13 I Reference Input This pin must be tied to ground through 13.3 K Ω 1% resis- tor. This pin is used to set the internal current level.
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need for matching resist ors on the transmit side. the CS61884 to operate incorrectly. Table 4. G.772 Address Selection
0000 Monitoring Disabled
0001 Receiver Channel # 1
0010 Receiver Channel # 2
0011 Receiver Channel # 3
0100 Receiver Channel # 4
0101 Receiver Channel # 5
0110 Receiver Channel # 6
0111 Receiver Channel # 7
1000 Monitoring Disabled
1001 Transmitter Channel # 1
1010 Transmitter Channel # 2
1011 Transmitter Channel # 3
1100 Transmitter Channel # 4
1101 Transmitter Channel # 5
1110 Transmitter Channel # 6
1111 Transmitter Channel # 7
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configured for E1 operation mode. Mode (See Section 9.3 on page 25). NOTE: In host mode the CBLSEL pin is not used. Figure 6. Pulse Mask at T1/J1 Interface Figure 7. Pulse Mask at E1 Interface
dard cables, transformers , or protection circuitry.
9.1 Bipolar Mode
on TPOS/TNEG for transmission on TTIP/TRING.
9.2 Unipolar Mode
TPOS/TDATA pin on the falling edge of TCLK. ister (0Fh) (See Section 14.16 on page 38).
9.3 RZ Mode
9.4 Transmitter Powerdown / High-Z
useful in applications that require redundancy.
9.5 Transmit All Ones (TAOS)
and TNEG inputs are ignored. TCLK “High” for more than 16 MCLK cycles. Table 5. Hardware Mode Line Length Configuration Selection
001 DS1, Option A (undershoot) 100 Ω T1/J1
010 DS1, Option A (0 dB) 100 Ω T1/J1
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In host mode, TAOS is ge nerated for a particular channel by asserting the associated bit in the TAOS Enable Register (03h) (See Section 14.4 on page 35). Since MCLK is the reference clock, it should be of adequate stability.
9.6 Automatic TAOS
While a given channel is in the LOS condition, if the corresponding bit in the Automatic TAOS Register (0Eh) (See Section 14.15 on page 37) is set, the device will drive that channel’s TTIP and TRING with the all ones pattern. This function is only available in host mode. Refer to Loss-of-Sig- nal (LOS) (See Section 10.5 on page 27).
9.7 Driver Failure Monitor
In host mode, the Driver Failure Monitor (DFM) function monitors the out put of each channel and sets a bit in the DFM Status Register (05h) (See Section 14.6 on page 35) if a secondary short cir- cuit is detected between TTIP and TRING. This generates an interrupt if the respective bit in the DFM Interrupt Enable Register (07h) (See Sec- tion 14.8 on page 36) is also set. Any change in the DFM Status Register (05h) (See Section 14.6 on page 35) will result in the corresponding bit in the DFM Interrupt Status Register (09h) (See Sec- tion 14.10 on page 36) being set. The interrupt is cleared by reading the DFM Interrupt Status Register (09h) (See Section 14.10 on page 36). This feature works in all modes of operation E1 75 Ω, E1 120 Ω and T1/J1 100 Ω.
9.8 Driver Short Circuit Protection
The CS61884 provides driver short circuit protec- tion when current on the secondary exceeds 50 mA RMS during E1/T1/J1 operation modes. 10. RECEIVER The CS61884 contains eight identical receivers that utilize an internal ma tched impedance technique that provides for the use of a common set of exter- nal components for 100Ω (T1/J1), 120 Ω (E1), and 75Ω (Ε1) operation (Refer to Figure 17 on page 51). This feature enab les the use of a one stuffing option for all E1 /T1/J1 line impedances. The appropriate E1/T1/J1 line matching is selected via the LEN[2:0] and the CBLSEL pins in hard- ware mode, or via the Line Length Channel ID Register (10h) (See Section 14.17 on page 38) and bits[3:0] of the Line Length Data Register (11h) (See Section 14.18 on page 39) in host mode. The receivers can also be configured to use different ex- ternal resistors to match the line impedance for E1 75Ω, E1 120 Ω or T1/J1 100 Ω modes (Refer to Figure 18 on page 52). The CS61884 receiver provides all of the circuitry to recover both data and clock from the data signal input on RTIP and RRING. The matched imped- ance receiver is capable of recovering signals with 12 dB of attenuation (referenced to 2.37 V or 3.0V nominal) while providing su perior return loss. In addition, the timing recovery circuit along with the jitter attenuator provide jitter tolerance that far ex- ceeds jitter specifi cations (Refer to Figure 20 on page 58). The recovered data and clock is output from the CS61884 on RPOS/RNEG and RCLK. These pins output the data in one of three formats: bipolar, un- ipolar, or RZ. The CLKE pi n is used to configure RPOS/RNEG, so that data is valid on either the ris- ing or falling edge of RCLK.
10.1 Bipolar Output Mode
Bipolar mode provides a transparent clock/data re- covery for applications in which the line decoding is performed by an external framing device. The re- covered clock and data are output on RCLK, RNEG/BPV, and RPOS/RDATA.
10.2 Unipolar Output Mode
In unipolar mode, the CS61884 decodes the recov- ered data with either B8ZS, HDB3 or AMI line de- coding. The decoded data is output on the
RPOS/RDATA pin. When bipolar violations are detected by the decoder, the RNEG/BPV pin is as- serted “High”. This pin is driven “high” one RCLK period for every bipolar violation that is not part of the zero substitution rules. Unipolar mode is en- tered by holding the TNEG pin “High” for more than 16 MCLK cycles. In hardware mode, the B8ZS/HDB3/AMI encod- ing/Decoding is activated via the CODEN pin. In host mode, the Global Control Register (0Fh) (See Section 14.16 on page 38) is used to select the encoding/decoding for all channels.
10.3 RZ Output Mode
In this mode the RTIP and RRING inputs are sliced to data values that are output on RPOS and RNEG. This mode is used in app lications that have clock recovery circuitry external to the LIU. To support external clock recovery, the RPOS and RNEG out- puts are XORed and output on an edge of RCLK. This mode is entered when MCLK is tied high. NOTE: The valid RCLK edge of the RPOS/RNEG data is controlled by the CLKE pin.
10.4 Receiver Powerdown/High-Z
All eight receivers are powered down when MCLK is held low. In addition, this will force the RCLK, RPOS, and RNEG outputs into a high impedance state.
10.5 Loss-of-Signal (LOS)
The CS61884 makes use of both analog and digital LOS detection circuitry that is compliant to the lat- est specifications. Du ring T1/J1 operation ANSI T1.231 is supported and in E1 operation mode, ei- ther ITU G.775 or ETSI 300 233 is supported. The LOS condition in E1 mode is changed from ITU G.775 to ETSI 300 233 in the LOS/AIS Mode En- able Register (0Dh) (See Section 14.14 on page 37). The LOS detector increments a counter each time a zero is received, and resets the counter each time a one “mark” is received. Depending on LOS detec- tion mode, the LOS signal is set when a certain number of consecutive zeros are received. In Clock/Data recovery mode, this forces the recov- ered clock to be replaced by MCLK at the RCLK output. In addition the RPOS/RNEG outputs are forced “high” for the length of the LOS period ex- cept when local and an alog loopback are enabled. Upon exiting LOS, the r ecovered clock replaces MCLK on the RCLK output . In Data recovery mode, RCLK is not replaced by MCLK when LOS is active. The LOS dete ction modes are summa- rized below. NOTE: T1.231, G.775 and ETSI 300 233 are all avail- able in host mode, but in hardware mode only ETSI 300 233 and T1.231 are available. ANSI T1.231 (T1/J1 Mode Only) - LOS is detect- ed if the receive signal is less than 200 mV for a pe- riod of 176 continuous pulse periods. The channel exits the LOS condition when the pulse density ex- ceeds 12.5% over 176 pulse periods since the re- ceipt of the last pulse. An incoming signal with a pulse amplitude exceedi ng 250 mV will cause a pulse transition on the RPOS/RDATA or RNEG outputs. ITU G.775 (E1 Mode Only) - LOS is declared when the received signal level is less than 200 mV for 32 consecutive pulse periods (typical). The de- vice exits LOS when the received signal achieves 12.5% ones density with no more than 15 consecu- tive zeros in a 32 bit sliding window and the signal level exceeds 250 mV. ETSI 300 233 (E1 Host Mode Only) - The LOS indicator becomes active when the receive signal level drops below 200 mV for more than 2048 pulse periods (1 msec). The channel exits the LOS state when the input signal exceeds 250 mV and has transitions for more than 32 pulse periods (16 µsec). This LOS detection method can only be selected while in host mode.
28 DS485F1
10.6 Alarm Indication Signal (AIS)
the relevant ANSI, ITU, and ETSI specifications. two consecutive 512 bit windows. switched into either the receive or transmit paths. reduce the propagation delay. ther overflow nor underflow. bits to 32 bits in order to reduce propagation delay. on page 58 and Figure 20 on page 58). Table 6. Jitter Attenuator Configurations
A brief summary of the CS61884 operations in hardware and host mode is provided in Table 7.
12.1 Loopbacks
signal on TTIP and TRIN G to RTIP and RRING.
12.2 Analog Loopback
Loopback is selected by driving LOOP[7:0] high. Table 7. Operational Summary
30 DS485F1
12.3 Digital Loopback
RCLK, RPOS, and RNEG (or RDATA) outputs. TRING (Refer to Figure 10 on page 31).
12.4 Remote Loopback
mode, TAOS overrides Remote Loopback. Figure 8. Analog Loopback Block Diagram Figure 9. Analog Loopback with TAOS Block Diagram
32 DS485F1
Parallel Host and Serial Host modes.
13.1 SOFTWARE RESET
13.2 Serial Port Operation
format of serial port data transfers. data byte immediately follows the ACB. data on SDO is valid on the falling edge of SCLK. tional I/O port, SDI and SDO may be tied together. Table 8. Host Control Signal Descriptions
13.3 Parallel Port Operation
Figure 30, Figure 31, Figure 32 and Figure 33. Figure 33. The CS or RD pin. Raising CS ends the cycle. again to indicate that data has been written or read. Figure 13. Serial Read/Write Format (SPOL = 0)
34 DS485F1
13.4 Register Set
Table 9. Host Mode Register Set
- REGISTER DESCRIPTIONS
14.1 Revision/IDcode Register (00h)
14.2 Analog Loopback Register (01h)
14.3 Remote Loopback Register (02h)
14.4 TAOS Enable Register (03h)
14.5 LOS Status Register (04h)
14.6 DFM Status Register (05h)
[7:4] REVI 7-4 Bits [7:4] are taken from the least-significant nibble of the Device IDCode, which are 0100. (Refer to Device ID Register (IDR) (See Section 16.3 on page 48). [3:0] REVI 3-0 Bits [3:0] are the revision bits from the JTAG IDCODE register, CS61884 Revision A = 0000. These bits are subject to change with the revision of the device (Refer to Device ID Register (IDR) (See Section 16.3 on page 48). BIT NAME Description [7:0] ALBK 7-0 Enables analog loopbacks. A “1” in bit n enables the loopback for channel n. Refer to Analog Loopback (See Section 12.2 on page 29) for a complete explanation. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] RLBK 7-0 Enables remote loopbacks. A “1” in bit n enables the loopback for channel n. Refer to Remote Loopback (See Section 12.4 on page 30) for a complete explanation. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] TAOE 7-0 A “1” in bit n of this register turns on the TAOS generator in channel n. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] LOSS 7-0 Register bit n is read as “1” when LOS is detected on channel n. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] DFMS 7-0 Driver Failure Monitor. The DFM will set bit n to “1” when it detects a short circuit in channel n. Register bits default to 00h after power-up or reset.
36 DS485F1
14.7 LOS Interrupt Enable Register (06h)
14.8 DFM Interrupt Enable Register (07h)
14.9 LOS Interrupt Status Register (08h)
14.10 DFM Interrupt Status Register (09h)
14.11 Software Reset Register (0Ah)
14.12 Performance Monitor Register (0Bh)
[7:0] LOSE 7-0 Any change in a LOS St atus Register bits will cause the INT pin to go low if corresponding bit in this register is set to “1”. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] DFME 7-0 Enables interrupts for failures detected by the DFM. Any change in a DFM Status Register bit will cause an interrupt if the corresponding bit is set to “1” in this register. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] LOSI 7-0 Bit n of this register is set to “1” to indicate a status change in bit n of the LOS Status Regis- ter. The bits in this register indicate a change in status since the last cleared LOS interrupt. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] DFMI 7-0 Bit n of this register is set to “1” to indicate a status change in bit n of the DFM Status Regis- ter. The bits in this register indicate a change in status since the last cleared DFM interrupt. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] SRES 7-0 Writing to this register initializes all registers to their default settings. Register bits default to 00h after power-up or reset. BIT NAME Description [7:4] RSVD 7-4 RESERVED (These bits must be set to 0.)
14.13 Digital Loopback Reset Register (0Ch)
14.14 LOS/AIS Mode Enable Register (0Dh)
14.15 Automatic TAOS Register (0Eh)
[3:0] A[3:0] The G.772 Monitor is directed to a given channel based on the state of the four least signifi- cant bits of this register. Register bits default to 00h after power-up or reset. The follow- ing table shows the settings needed to select a specific channel’s receiver or transmitter to perform G.772 monitoring. A[3:0] Channel Selection
0001 RX Channel #1
0010 RX Channel #2
0011 RX Channel #3
0100 RX Channel #4
0101 RX Channel #5
0110 RX Channel #6
0111 RX Channel #7
1001 TX Channel #1
1010 TX Channel #2
1011 TX Channel #3
1100 TX Channel #4
1101 TX Channel #5
1110 TX Channel #6
1111 TX Channel #7
[7:0] DLBK 7-0 Setting register bit n to “1” enables the digital loopback for channel n. Refer to Digital Loop- back (See Section 12.3 on page 30) for a complete explanation. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] LAME 7-0 T1/J1 MODE - These bits are “Do Not Care”, T1.231 Compliant LOS/AIS already used. E1 Mode - Setting bit n to “1” enables ETSI 300 233 compliant LOS/AIS for channel n; set- ting bit n to “0” enables ITU G.775 compliant LOS/AIS for channel n. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] ATAO 7-0 Setting bit n to “1” enables automatic TAOS generation on channel n when LOS is detected. Register bits default to 00h after power-up or reset. (Continued) BIT NAME Description
38 DS485F1
14.16 Global Control Register (0Fh)
14.17 Line Length Channel ID Register (10h)
This register is the global control for the AWG Auto-Increment, Automatic AIS insertion, encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for all eight channels. Register bits default to 00h after power-up or reset. [7] AWG Auto- Increment The AWG Auto-Increment bit indicates whether to auto-increment the AWG Phase Address Register (17h) (See Section 14.24 on page 40) after each access. Thus, when this bit is set, the phase samples address portion of the address register increments after each read or write access. This bit must be set before any bit in the AWG Enable register is set, if this function is required. [6] RAISEN On LOS, this bit controls the automatic AIS insertion into all eight receiver paths. 0 = Disabled 1 = Enabled [5] RSVD RESERVED (This bit must be set to 0.) [4] CODEN Line encoding/decoding Selection 0 = B8ZS/HDB3 (T1/J1/E1 respectively) 1 = AMI [3] FIFO LENGTH Jitter Attenuator FIFO length Selection 0 = 32 bits 1 = 64 bits [2] JACF Jitter Attenuator Corner Frequency Selection E1 T1/J1 0 = 1.25Hz 3.78Hz 1 = 2.50Hz 7.56Hz [1:0] JASEL [1:0] These bits select the position of the Jitter Attenuator. BIT NAME Description [7:3] RSVD 7-3 RESERVED (These bi ts must be set to 0.) [2:0] LLID 2-0 The value written to these bits specify the LIU channel for which the Pulse Shape Configura- tion Data (register 11h) applies. For example, writing a value of a binary 000 to the 3-LSBs will select channel 0. The pulse shape configuration data for the channel specified in this reg- ister are written or read through the Line Length Data Register (11h). Register bits default to 00h after power-up or reset. JASEL 1 JASEL 0 POSITION 0 0 Disabled 0 1 Transmit Path 1 0 Disabled 1 1 Receive Path
14.18 Line Length Data Register (11h)
14.19 Output Disable Register (12h)
14.20 AIS Status Register (13h)
14.21 AIS Interrupt Enable Register (14h)
The value written to the 4-LSBs of this register specifies whether the device is operating in either T1/J1 or E1 modes and the associated pulse shape as shown below is being transmit- ted. Register bits default to 00h after power-up or reset. [7:5] RSVD RESERVED (These bi ts must be set to 0.) [4] INT_EXTB This bit specifies the use of internal (Int_ExtB = 1) or external (Int_ExtB = 0) receiver line matching. The line impedance for both the receiver and transmitter are chosen through the LEN [3:0] bits in this register. [3:0] LEN[3:0] These bits setup the line impedance for both the receiver and the transmitter path and the desired pulse shape for a specific channel. The channel is selected with the Line Length Channel ID register (0x10). The following table shows the available transmitter pulse shapes. LEN [3:0] Operation Mode Line Length Selection Phase Samples per UI 0000 E1 120 Ω 3.0V 12
0001 T1/J1 100 Ω DS1, Option A (undershoot) 14
0010 T1/J1 100 Ω DS1, Option A (0dB) 14
0011 T1/J1 100 Ω 0 - 133Ft (0.6dB) 13 0100 T1/J1 100 Ω 133 - 266Ft (1.2dB) 13 0101 T1/J1 100 Ω 266 - 399Ft (1.2dB) 13 0110 T1/J1 100 Ω 399 - 533Ft (2.4dB) 13 0111 T1/J1 100 Ω 533 - 655Ft (3.0dB) 13 1000 E1 75 Ω 2.37V 12 BIT NAME Description [7:0] OENB 7-0 Setting bit n of this register to “1” Hig h-Z the TX output driver on channel n of the device. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] AISS 7-0 A “1” in bit position n indicates that the receiver has detected an AIS condition on channel n, which generates an interrupt on the INT pin. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] AISE 7-0 This register enables changes in the AIS Status register to be reflected in the AIS Interrupt Status register, thus causing an interrupt on the INT pin. Register bits default to 00h after power-up or reset.
40 DS485F1
14.22 AIS Interrupt Status Register (15h)
14.23 AWG Broadcast Register (16h)
14.24 AWG Phase Address Register (17h)
14.25 AWG Phase Data Register (18h)
14.26 AWG Enable Register (19h)
[7:0] AISI 7-0 Bit n is set to “1” to indicate a change of status of bit n in the AIS Status Register. The bits in this register indicate which channel changed in status since the last cleared AIS interrupt. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] AWGB 7-0 Setting bit n to “1” causes the phase data in the AWG Phase Data Register to be written to the corresponding channel or channels simultaneously. (Refer to Arbitrary Waveform Gen- erator (See Section 15 on page 43). Register bits default to 00h after power-up or reset. BIT NAME Description [7:5] AWGA These bits specify the target channel 0-7. (Refer to Arbitrary Waveform Generator (See Section 15 on page 43). Register bits default to 00h after power-up or reset. [4:0] PA[4:0] These bits specify 1 of 24 (E1) or 26/2 8 (T1/J1) phase sample address locations of the AWG, that the phase data in the AWG Phase Data Register is written to or read from. The other locations in each channel’s phase sample addresses are not used, and should not be accessed. Register bits default to 00h after power-up or reset. BIT NAME Description [7] RSVD RESERVED (This bit must be set to 0.) [6:0] AWGD [6:0] These bits are used for the pulse shape data that will be written to the AWG phase location specified by the AWG Phase Address Register. The value written to or read from this register will be written to or read from the AWG phase sample location specified by the AWG Phase Address register. A software reset through the Software Reset Register does not effect the contents of this register. The data in each phase is a 7-bit 2’s complement number (the max- imum positive value is 3Fh and the maximum negative value is 40h). (Refer to Arbitrary Waveform Generator (See Section 15 on page 43). Register bits default to 00h after power-up. BIT NAME Description [7:0] AWGN 7-0 The AWG enable register is used for selecting the source of the customized transmission pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the ROM is selected for transmission on channel n. (Refer to Arbitrary Waveform Generator (See Section 15 on page 43). Register bits default to 00h after power-up or reset.
14.27 AWG Overflow Interrupt Enable Register (1Ah)
14.28 AWG Overflow Interrupt Status Register (1Bh)
14.29 Reserved Register (1Ch)
14.30 Reserved Register (1Dh)
14.31 Bits Clock Enable Register (1Eh)
14.32 Reserved Register (1Fh)
[7:0] AWGE 7-0 This register enables changes in the overflow status to be reflected in the AWG Interrupt Sta- tus register, thus causing as interrupt on the INT pin. Interrupts are maskable on a per-chan- nel basis. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] AWGI 7-0 The bits in this register indicate a change in status since the last AWG overflow interrupt. An AWG overflow occurs when invalid phase data are entered, such that a sample-by-sample addition of UI0 and UI1 results in values that exceed the arithmetic range of the 7-bit repre- sentation. Reading this register clears the interrupt, which deactivates the INT pin. Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] RSVD 7-0 RESERVED (These bi ts must be set to zero.) BIT NAME Description [7:0] RSVD 7-0 RESERVED (These bi ts must be set to zero.) BIT NAME Description [7:0] BITS 7-0 Setting a “1” to bit n in this register changes channel n to a stand-alone timing recovery unit used for G.703 clock recovery. (Refer to BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE (See Section 8 on page 23) for a better description of the G.703 clock recovery function). Register bits default to 00h after power-up or reset. BIT NAME Description [7:0] RSVD 7-0 RESERVED (These bi ts must be set to zero.)
42 DS485F1
14.33 Status Registers
The following Status registers are read-only: LOS Status Register (04h) (See Section 14.5 on page 35), DFM Status Register (05h) (See Sec- tion 14.6 on page 35) and AIS Status Register (13h) (See Section 14.20 on page 39). The CS61884 generates an interrupt on the INT pin any time an unmasked status register bit changes.
14.33.1 Interrupt Enable Registers
The Interrupt Enable registers: LOS Interrupt En- able Register (06h) (See Section 14.7 on page 36), DFM Interrupt Enable Register (07h) (See Sec- tion 14.8 on page 36), AIS Interrupt Enable Reg- ister (14h) (See Section 14.21 on page 39) and AWG Overflow Interrupt Enable Register (1Ah) (See Section 14.27 on page 41) , enable changes in status register state to cause an interrupt on the INT pin. Interrupts are maskable on a per channel basis. When an Interrupt Enable register bit is 0, the corresponding Status register bit is dis- abled from causing an interrupt on the INT pin. NOTE: Disabling an interrupt has no effect on the sta- tus reflected in the associated status register.
14.33.2 Interrupt Status Registers
The following interrupt status registers: LOS In- terrupt Status Register (08h) (See Section 14.9 on page 36), DFM Interrupt Status Register (09h) (See Section 14.10 on page 36), AIS Inter- rupt Status Register (15h) (See Section 14.22 on page 40) and AWG Overflow Interrupt Status Register (1Bh) (See Section 14.28 on page 41), in- dicate a change in status of the corresponding status registers in host mode. Reading these registers clears the interrupt, which deactivates the INT pin.
44 DS485F1
channel or channels. To enable the AWG function for a specific channel or channels the correspond- ing bit(s) in the AWG Enable Register (19h) (See Section 14.26 on page 40) must be set to “1”. When the corresponding bit(s) in the AWG Enable Regis- ter are set to “0” pre-programmed pulse shapes are selected for transmission. In order to access and wr ite data for a customized pulse shape to a specific channel or channels, the following steps are required. First the desired chan- nel and phase sample addresses must be written to the AWG Phase Data Register (18h) (See Section 14.25 on page 40). Once the channel and phase sample address have been selected, the actual phase sample data may be entered into the AWG Phase Data Register at the selected phase sample address selected by the lower five bits of the AWG Phase Address Register (17h) (See Section 14.24 on page 40)). To change the phase sample address of the selected channel the user may use either of the following steps. First, the user can re-write the phase sample address to the AWG Phase Address Register or set the Auto-Increment bit (Bit 7) in the Global Con- trol Register (0Fh) (See Section 14.16 on page 38)) to “1”. When this bit is set to “1” only the first phase sample address (00000 binary) needs to be written to the AWG Phase Address Register (17h) (See Section 14.24 on page 40), and each subsequent access (read or write) to the AWG Phase Data Register (18h) (See Section 14.25 on page 40) will automatically increment the phase sample address. The channel address, however, re- mains unaffected by the Auto-Increment mode. Since the number of phase samples forming the customized pulse shape varies with the mode of op- eration (E1/T1/J1), the AWG Phase Address Reg- ister (17h) (See Section 14.24 on page 40) needs to be re-written in order to re-start the phase sample address sequence from zero. The AWG Broadcast function allows the same data to be written to different channels simultaneously. This is done with the use of the AWG Broadcast Register (16h) (See Section 14.23 on page 40)), each bit in the AWG Br oadcast Register corre- sponds to a different channel (bit 0 is channel 0, and bit 3 is channel 3 & etc.). To write the same pulse shaping data to multiple channels, simple set the corresponding bit to “1” in the AWG Broadcast Register (16h) (See Section 14.23 on page 40). This function only requires that one of the eight channel addresses be written to the AWG Phase Address Register (17h) (See Section 14.24 on page 40). During an AWG read sequence, the bits in the AWG Broa dcast Register are ig- nored. During an AWG write sequence, the select- ed channel or channels are specified by both the channel address specified by the upper bits of the AWG Phase Address Register (17h) (See Section 14.24 on page 40) and the selected channel or chan- nels in the AWG Broadcast Register (16h) (See Section 14.23 on page 40). During a multiple channel write the first channel that is written to, is the channel that was address by the AWG Phase Address Re gister. This channel’s bit in the AWG Broadcast Register can be set to ei- ther “1” or “0”. For a more descriptive explanation of how to use the AWG re fer to the “How To Use The CS61880/CS61884 Arbitrary Waveform Gen- erator” application note AN204.
the TAP controller through its various states. ister contains an 32-bit device identifier.
16.1 TAP Controller
Figure 16. The value shown next to each state tran- TMS when it is sampled by the rising edge of TCK.
16.1.1 JTAG Reset
TRST resets all JTAG circuitry.
16.1.2 Test-Logic-Reset
logic when the part is in normal mode of operation. TRST or forcing TMS High for 5 TCK periods.
16.1.3 Run-Test-Idle
The run-test-idle state is used to run tests. Figure 15. Test Access Port Architecture
46 DS485F1
16.1.4 Select-DR-Scan
This is a temporary controller state.
16.1.5 Capture-DR
16.1.6 Shift-DR
16.1.7 Exit1-DR
16.1.8 Pause-DR
16.1.9 Exit2-DR
16.1.10 Update-DR
latched parallel output changes only in this state. Figure 16. TAP Controller State Diagram
16.1.11 Select-IR-Scan
16.1.12 Capture-IR
level serial test data path.
16.1.13 Shift-IR
output on each rising edge of TCK.
16.1.14 Exit1-IR
16.1.15 Pause-IR
16.1.16 Exit2-IR
16.1.17 Update-IR
16.2 Instruction Register (IR)
performed and/or the data register to be accessed.
16.2.1 EXTEST
connects the BSR to the TDI and TDO pins.
16.2.2 SAMPLE/PRELOAD
16.2.3 IDCODE
16.2.4 BYPASS
is used to bypass the device. Table 10. JTAG Instructions
000 EXTEST
100 SAMPLE/PRELOAD
110 IDCODE
111 BYPASS
48 DS485F1
16.3 Device ID Register (IDR)
from the last three digits of the part number (884). The LSB is a constant 1, as defined by IEEE 1149.1.
- BOUNDARY SCAN REGISTER (BSR)
pin to scan cell mapping is given in the BSR description shown in Table 11. NOTE: Data is shifted LSB first into the BSR register. Table 11. Boundary Scan Register
0 LOS7 O LOS7
1 RNEG7 O RNEG7
2 RPOS7 O RPOS7
3 RCLK7 O RCLK7
5 TNEG7 I TNEG7
6 TPOS7 I TPOS7
7 TCLK7 I TCLK7
8 LOS6 O LOS6_B
9 RNEG6 O RNEG6
10 RPOS6 O RPOS6
11 RCLK6 O RCLK6
13 TNEG6 I TNEG6
14 TPOS6 I TPOS6
15 TCLK6 I TCLK6
16 MCLK I MCLK
17 MODE I MODE_TRI
18 MODE I MODE_IN
19 ADDR4 I ADDR4
20 ADDR3 I ADDR3
21 ADDR2 I ADDR2
22 ADDR1 I ADDR1
23 ADDR0 I ADDR0
24 LOOP0/D0 I LPT0
25 LOOP0/D0 I LPI0
26 LOOP0/D0 O LPO0
27 LOOP1/D1 I LPT1
28 LOOP1/D1 I LPI1
29 LOOP1/D1 O LPO1
30 LOOP2/D2 I LPT2
31 LOOP2/D2 I LPI2
32 LOOP2/D2 O LPO2
33 LOOP3/D3 I LPT3
34 LOOP3/D3 I LPI3
35 LOOP3/D3 O LPO3
36 LOOP4/D4 I LPT4
37 LOOP4/D4 I LPI4
38 LOOP4/D4 O LPO4
39 LOOP5/D5 I LPT5
40 LOOP5/D5 I LPI5
41 LOOP5/D5 O LPO5
42 LOOP6/D6 I LPT6
43 LOOP6/D6 I LPI6
44 LOOP6/D6 O LPO6
45 LOOP7/D7 I LPT7
46 LOOP7/D7 I LPI7
47 LOOP7/D7 O LPO7
49 TCLK1 I TCLK1
50 TPOS1 I TPOS1
51 TNEG1 I TNEG1
52 RCLK1 O RCLK1
53 RPOS1 O RPOS1
54 RNEG1 O RNEG1
56 LOS1 O LOS1
57 TCLK0 I TCLK0
58 TPOS0 I TPOS0
59 TNEG0 I TNEG0
60 RCLK0 O RCLK0
61 RPOS0 O RPOS0
62 RNEG0 O RNEG0
64 LOS0 O LOS0
65 MUX I MUX
66 LOS3 O LOS3
67 RNEG3 O RNEG3
68 RPOS3 O RPOS3
69 RCLK3 O RCLK3
71 TNEG3 I TNEG3
72 TPOS3 I TPOS3
Table 11. Boundary Scan Register (Continued)
50 DS485F1
73 TCLK3 I TCLK3
74 LOS2 O LOS2
75 RNEG2 O RNEG2
76 RPOS2 O RPOS2
77 RCLK2 O RCLK2
79 TNEG2 I TNEG2
80 TPOS2 I TPOS2
81 TCLK2 I TCLK2
82 INT_B O INT_B
83 RDY O RDYOUT
85 WR_B I WR_B
86 RD_B I RD_B
87 ALE I ALE
88 CS_B I CS_B
89 CS_B I CS_B_TRI
90 INTL I INTL
91 CBLSEL I CBLSEL_TRI
92 CBLSEL I CBLSEL_IN
93 TCLK5 I TCLK5
94 TPOS5 I TPOS5
95 TNEG5 I TNEG5
96 RCLK5 O RCLK5
97 RPOS5 O RPOS5
98 RNEG5 O RNEG5
100 LOS5 O LOS5
101 TCLK4 I TCLK4
102 TPOS4 I TPOS4
103 TNEG4 I TNEG4
104 RCLK4 O RCLK4
105 RPOS4 O RPOS4
106 RNEG4 O RNEG4
108 LOS4 O LOS4
109 TXOE I TXOE
110 CLKE I CLKE
the input values driven to these LOOP[7:0] can be read via LPI[7:0]. Low, the outputs are placed in a high impedance state (High-Z).
Figure 17. Internal RX/TX Impedance Matching 2) Common decoupling capacitor for all TVCC and TGND pins.
52 DS485F1
Figure 18. Internal TX, External RX Impedance Matching 2)Common decoupling capacitor for all TVCC and TGND pins.
18.1 Transformer specifications
18.2 Crystal Oscillator Specifications
of + 100ppm for both E1 and T1/J1 applications.
18.3 Designing for AT&T 62411
18.4 Line Protection
“Secondary Line Protection for T1 and E1 Cards”. Table 12. Transformer Specifications
54 DS485F1
- CHARACTERISTICS AND SPECIFICATIONS
19.1 Absolute Maximum Ratings
CAUTION: Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
19.2 Recommended Operating Conditions
Notes: 1. Human Body Model 2. Transient current of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. 3. Power consumption while driving line load over the full operating temperature and power supply voltage range. Includes all IC channels and loads. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50pF capacitive load. 4. Typical consumption corresponds to 50% ones de nsity for E1/T1/J1 modes and medium line length setting for T1/J1 mode at 3.3Volts. 5. Maximum consumption corresponds to 100% ones density for E1/T1/J1 modes and maximum line length settings for T1/J1 mode at 3.465Volts. 6. This specification guar antees TTL compatibility (VOH = 2.4 V @ IOUT = -400 µA). 7. Output drivers are TTL compatible. 8. Pulse amplitude measured at the output of the transformer across a 75 Ω load. 9. Pulse amplitude measured at the output of the transformer across a 120 Ω load. 10. Pulse amplitude measured at the output of the transformer across a 100 Ω load for all line length settings. Parameter Symbol Min. Max Units DC Supply (referenced to RGND = TGND = 0V) RV+ TV+ 4.0 4.0 V V DC Supply VCCIO -0.5 4.6 V Input Voltage, Any Digital Pin except CBLSEL, MODE and LOOP(n) pins (referen ced to GNDIO = 0V) V IH GNDIO -0.5 5.3 V Input Voltage CBLSEL, MODE & LOOP(n) Pins (referenced to GNDIO = 0V) VIH GNDIO -0.5 VCCIO +0.5 V Input voltage, RTIP and RRING Pins TGND -0.5 TV+ +0.5 V ESD voltage, Any pin Note 1 2k - V Input current, Any Pin Note 2 IIH -10 +10 mA Maximum Power Dissipation, In package P p -1 . 7 3 W Ambient Operating Temperature T A -40 85 C Storage Temperature T stg -65 150 C Parameter Symbol Min. Typ Max Units DC Supply RV+, TV+ 3.135 3.3 3.465 V DC Supply VCCIO 3.135 3.3 3.465 V Ambient operating Temperature T A -40 25 85 C Power Consumption, T1/J1 Mode, 100 Ω line load Notes 3, 4, 5 - - 970 1900 mW Power Consumption, E1 Mode, 75 Ω line load Notes 3, 4, 5 - - 810 1400 mW Power Consumption, E1 Mode, 120 Ω line load Notes 3, 4, 5 - - 750 1300 mW
19.3 Digital Characteristics
(TA = -40°C to 85°C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)
19.4 Transmitter Analog Characteristics
(TA = -40°C to 85°C; TV+, RV+ = 3.3 V ±5%; GND = 0 V) Parameter Symbol Min. Typ Max Units High-Level Input Voltage Note 6 VIH 2.0 - - V Low-Level Input Voltage Note 6 VIL -- 0 . 8 V LOOP[7:0] Low-Level Input Voltage V IHL - - 1/3 VCCIO-0.2 V LOOP[7:0] Mid-Level Input Voltage V IHM 1/3 VCCIO +0.2 1/2 VCCIO 2/3 VCCIO-0.2 V LOOP[7:0] High-Level Input Voltage V IHH 2/3 VCCIO +0.2 - - V High-Level Output Voltage Notes 6, 7 IOUT = -400 µA VOH 2.4 - - V Low-Level Output Voltage Notes 6, 7 IOUT = 1.6 mA VOL -- 0 . 4 V Input Leakage Current -10 - +10 µA Input leakage for LOOP pins -150 - +150 µA Parameter Min. Typ Max Units Output Pulse Amplitudes E1 75 Ω Notes 8, 9, 10 E1 120Ω T1/J1 100Ω 2.14 2.7 2.4 2.37 3.0 3.0 2.6 3.3 3.6 V V V Ratio of Positive to Negative pulses T1/J1 100 Ω Notes 8, 9, 10 E1, amplitude at center of pulse interval E1, width at 50% of nominal amplitude 0.95 0.95 0.95 1.05 1.05 1.05 Pulse Amplitude of a space T1/J1 100 Ω E1 120 Ω E1 75 Ω -0.15 -0.3 -0.237 0.15 0.3 0.237 V V V Power in 2 kHz band about 772 kHz Notes 11, 12 (T1/J1 100 Ω only) 12.6 - - dBm Power in 2 kHz band about 1.544 MHz Notes 11, 12 (referenced to power in 2 kHz band at 772 kHz, T1/J1 100 Ω only) -29 - - dBm Transmit Return Loss - E1 51 kHz to 102 kHz 102 kH to 2048 kHz Notes 11, 12, 13 2048 kHz to 3072 kHz - 14 - 14 - 14 - 20 - 19 - 18 dB Transmit Return Loss - T1/J1 51 kHz to 102 kHz 102 kHz to 2048 kHz Notes 11, 12, 13 2048 kHz to 3072 kHz - 14 - 14 - 14 - 19 - 19 - 18 dB Jitter Added by the Transmitter 10 Hz - 8 kHz 8 kHz - 40 kHz Notes 11, 14 10 Hz - 40 kHz Broad Band 0.010 0.009 0.007 0.015 0.020 0.025 0.025 0.050 UI Transmitter Short Circuit Current per channel - - 50 mA RMS
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19.5 Receiver Analog Characteristics
(TA = -40°C to 85°C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)) Notes: 11. Parameters guaranteed by design and characterization. 12. Using components on the CDB61884 evaluation board in Internal Match Impedance Mode. 13. Return loss = 20log10 ABS((Z 1 + Z0) / (Z1 - Z0)) where Z1 - impedance of the transmitter or receiver, and Z0 = cable impedance. 14. Assuming that jitter free clock is input to TCLK. 15. Jitter tolerance for 0 dB for T1/J1 input signal levels and 6 dB for E1 input signal levels. Jitter tolerance increases at lower frequencies. HDB3/B8ZS coders enabled. 16. In Data Recovery Mode. 17. Jitter Attenuator in the receive path. Parameter Min. Typ Max Units Allowable Cable Attenuation @ 1024kHz and 772kHz - - - 12 dB RTIP/RRING Input Impedance T1/J1 100 Ω Load (Internal Line matching mode) E1 120 Ω Load Note 11 E1 75 Ω Load 140 14k Ω RTIP/RRING Input Impedance T1/J1 100 Ω Load (External Line matching mode) E1 120 Ω Load Note 11 E1 75 Ω Load 14K 14k 14K Ω Receiver Dynamic Range 0.5 - - Vp Signal to Noise margin (Per G.703, O151 @ 6dB cable Atten). Note 11 -- 1 8- d B Receiver Squelch Level - 150 - mV LOS Threshold - 200 - mV LOS Hysteresis - 50 - mV Data Decision Threshold E1 Modes Note 11 41 50 59 % of peak Data Decision Threshold T1/J1 Modes Note 11 56 65 74 % of peak Input Jitter Tolerance - E1 1 Hz - 1.8 Hz Notes 11, 15, 17 20 Hz - 2.4 kHz 18 kHz - 100 kHz 1.5 0.2 UI Input Jitter Tolerance - T1/J1 0.1 Hz - 1 Hz Notes 11, 15, 17 4 . 9H z - 3 0 0k H z 10kHz - 100 kHz 138 0.4 UI Input Return Loss - E1/T1/J1 51 kHz - 102 kHz 102 kHz - 2048 kHz Notes 11, 12, 13 2048 kHz - 3072 kHz - 18 - 18 - 18 - 28 - 30 - 27 dB
19.6 Jitter Attenuator Characteristics
(TA = -40°C to 85°C; TV+, RV+ = 3.3 V ±5%; GND = 0 V) Notes: 18. Attenuation measured with sinuso idal input filter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. Output jitter can increase significantly when more than 28 UI’s are input to the attenuator. 19. Measurement is not effected by the position of the Jitter Attenuator. Parameter Min. Typ Max Units Jitter Attenuator Corner Frequency T1/J1 Modes Note 11, 19 T1/J1 Modes E1 Modes (Depends on JACF Bit in host mode) E1 Modes 3.78 7.56 1.25 2.50 Hz E1 Jitter Attenuation 3 Hz to 40 Hz Note 11, 18 400 Hz to 100 kHz + 0.5 - 19.5 dB T1/J1 Jitter Attenuation 1 Hz to 20 Hz 1 kHz Note 11, 18 1.4KHz to 100KHz - 33.3 - 40 dB Attenuator Input Jitter Tolerance before FIFO 32-bit FIFO over flow and under flow Note 11 64-bit FIFO UI UI Delay through Jitter Attenuator Only 32-bit FIFO Note 11 64-bit FIFO UI UI Intrinsic Jitter in Remote Loopback Notes 11, 17 -- 0 . 1 1 U I
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Figure 19. Jitter Transfer Characteristic vs. G.736, TBR 12/13 & AT&T 62411 Figure 20. Jitter Tolerance Characteristic vs. G.823 & AT&T 62411
19.7 Master Clock Switching Characteristics
19.8 Transmit Switching Characteristics
19.9 Receive Switching Characteristics
- All parameters guaranteed by production, characterization or design. Notes: 20. Output load capacitance = 50pF. 21. MCLK is not active. 22. Parameters guaranteed by design and characterization. Parameter Symbol Min. Typ Max Units MASTER CLOCK (MCLK) Master Clock Frequency E1 Modes MCLK 2.048 MHz Master Clock Frequency T1/J1 Modes MCLK 1.544 MHz Master Clock Tolerance - -100 +100 ppm Master Clock Duty Cycle - 40 50 60 % Parameter Symbol Min. Typ Max Units E1 TCLK Frequency 1/t pw2 -2 . 0 4 8- M H z E1 TPOS/TNEG Pulse Width (RZ Mode) 236 244 252 nS T1/J1 TCLK Frequency 1/t pw2 -1 . 5 4 4- M H z TCLK Tolerance (NRZ Mode) -50 - 50 PPM TCLK Duty Cycle t pwh2/tpw2 -- 9 0 % TCLK Pulse Width 20 - - nS TCLK Burst Rate Note 22 -- 2 0 M H z TPOS/TNEG to TCLK Falling Setup Time (NRZ Mode) t su2 25 - - nS TCLK Falling to TPOS/TNEG Hold time (NRZ Mode) t h2 25 - - nS TXOE Asserted Low to TX Driver HIGH-Z - - 1 µS TCLK Held Low to Driver HIGH-Z Note 21 81 2 2 0 µS Parameter Symbol Min. Typ Max Units RCLK Duty Cycle 40 50 60 % E1 RCLK Pulse Width 196 244 328 nS E1 RPOS/RNEG Pulse Width (RZ Mode 200 244 300 nS E1 RPOS/RNEG to RCLK rising setup time t su 150 244 - nS E1 RPOS/RNEG to RCLK hold time t h 200 244 - nS T1/J1 RCLK Pulse Width 259 324 388 nS T1/J1 RPOS/RNEG Pulse Width (RZ Mode) 250 324 400 nS T1/J1 POS/RNEG to RCLK rising setup time t su 150 324 - nS T1/J1 RPOS/RNEG to RCLK hold time t h 200 324 - nS RPOS/RNEG Output to RCLK Output (RZ Mode) - - 10 nS Rise/Fall Time, RPOS, RNEG, RCLK, LOS outputs t r, tf - - 85 nS
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Figure 21. Recovered Clock and Data Switching Characteristics Figure 22. Transmit Clock and Data Switching Characteristics Figure 23. Signal Rise and Fall Characteristics
19.10 Switching Characteristics - Serial Port
Figure 24. Serial Port Read Timing Diagram Figure 25. Serial Port Write Timing Diagram
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19.11 Switching Characteristics - Parallel Port (Multiplexed Mode)
- All paramters guaranteed by production, characterization or design. Parameter Ref. # Min. Typ. Max Unit Pulse Width AS or ALE High 1 25 - - ns Muxed Address Setup Time to AS or ALE Low 2 10 - - ns Muxed Address Hold Time 3 5 - - ns Delay Time AS or ALE to WR, RD or DS 45-- n s CS & R/W Setup Time Before WR, RD or DS Low 5 0 - - ns CS & R/W Hold Time 6 0 - - ns Pulse Width, WR, RD, or DS 77 0- - n s Write Data Setup Time 8 30 - - ns Write Data Hold Time 9 30 - - ns Output Data Delay Time from RD or DS Low 10 - - 100 ns Read Data Hold Time 11 5 - - ns Delay Time WR , RD, or DS to ALE or AS Rise 12 30 - - ns WR or RD Low to RDY Low 13 - - 55 ns WR or RD Low to RDY High 14 - - 100 ns WR or RD High to RDY HIGH-Z 15 - - 40 ns DS Low to ACK High 16 - - 65 ns DS Low to ACK Low 17 - - 100 ns DS High to ACK HIGH-Z 18 - - 40 ns
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Figure 28. Parallel Port Timing - Write in Motorola Multiplexed Address / Data Bus Figure 29. Parallel Port Timing - Read in Motorola Multiplexed Address / Data Bus
19.12 Switching Characteristics- Parallel Port (Non-multiplexed Mode)
- All paramters guaranteed by production, characterization or design. Parameter Ref. # Min. Typ. Max Unit Address Setup Time to WR, RD or DS Low 1 10 - - ns Address Hold Time 2 5 - - ns CS & R/W Setup Time Before WR, RD or DS Low 3 0 - - ns CS & R/W Hold Time 4 0 - - ns Pulse Width, WR, RD, or DS 57 0- - n s Write Data Setup Time 6 30 - - ns Write Data Hold Time 7 30 - - ns Output Data Delay Time from RD or DS 8-- 1 0 0 n s Read Data Hold Time 9 5 - - ns WR or RD Low to RDY Low 10 - - 55 ns WR, RD or DS Low to RDY High 11 - - 100 ns WR, RD or DS High to RDY HIGH-Z 12 - - 40 ns DS Low to ACK High 13 - - 65 ns DS Low to ACK Low 14 - - 100 ns DS High to ACK HIGH-Z 15 - - 40 ns
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Figure 30. Parallel Port Timing - Write in Intel Non-Multiplexed Address / Data Bus Mode Figure 31. Parallel Port Timing - Read in Intel Non-Multiplexed Address / Data Bus Mode
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19.13 Switching Characteristics - JTAG
Figure 34. JTAG Switching Characteristics
- COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS AT&T Pub 62411 FCC Part 68 ANSI T1.102 ANSI T1.105 ANSI T1.231 ANSI T1.403 ANSI T1.408 Bell Core TR-TSY-000009 Bell Core GR-253-Core Sonet Bell Core GR-499-Core ETSI ETS 300-011 ETSI ETS 300-166 ETSI ETS 300-233 IEEE 1149.1 ETSI TBR 12/13 ITU-T I.431 ITU-T G.703 ITU-T G.704 ITU-T G.706 ITU-T G.732 ITU-T G.735 ITU-T G.736 ITU-T G.742 ITU-T G.772 ITU-T G.775 ITU-T G.783 ITU-T G.823 ITU-T O.151 OFTEL OTR-001
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- FBGA PACKAGE DIMENSIONS
- LQFP PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX * Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 144L LQFP PACKAGE DRAWING E D1D e L B A