CS61880

CS61880 CIRRUS | Alldatasheet

Document overview

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Technical content

Features

Octal E1 Short-haul Line Interface Unit Low Power No External Component Changes for 120 Ω / 75 Ω Operation Pulse Shapes can be customized by the user Internal AMI, or HDB3 Encoding/Decoding LOS Detection per ITU G.775 or ETSI 300- 233 G.772 Non-Intrusive Monitoring G.703 BITS Clock Recovery Crystal-less Jitter Attenuation Serial/Parallel Microprocessor Control Interfaces Transmitter Short Circuit Current Limiter (<50 mA) TX Drivers with Fast High-Z and Power Down JTAG Boundary Scan compliant to IEEE 1149.1 144-Pin LQFP or 160-Pin FBGA Package

ORDERING INFORMATION

Description

The CS61880 is a full-featured Octal E1 short-haul LIU that supports 2.048 Mbps data transmission for both E1 75 Ω and E1 120 Ω applications. Each channel provides crystal-less jitter attenuation that complies with the most stringent standards. Each channel also provides internal AMI/HDB3 encoding/decoding. To support enhanced system diagnostics, channel zero can be configured for G.772 non-intrusive monitoring of any of the other 7 channels’ receive or transmit paths. The CS61880 makes use of ultra low power matched im- pedance transmitters and receivers to reduce power beyond that achieved by traditional driver designs. By achieving a more precise line match, this technique also provides superior return loss characteristics. Additional- ly, the internal line matching circuitry reduces the external component count. All transmitters have controls for independent power down and High-Z. Each receiver provides reliable data recovery with over 12 dB of cable attenuation. The receiver also incorpo- rates LOS detection compliant to the most recent specifications. RPOS RNEG TPOS TNEG TCLK LOS RTIP RRING TTIP TRING RCLK JTAG Interface Remote Loopback Digital Loopback Analog Loopback Decoder Driver Receiver LOS G.772 Monitor Transmit Control Pulse Shaper Data Recovery Jitter Attenuator Clock Recovery Encoder Host Interface JTAG Serial Port Host Serial/Parallel Port JUL ‘03 DS450PP3

Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to: http://www.cirrus.com/ IMPORTANT NOTICE “Preliminary” product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained here- in and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technologies described in this ma- terial and controlled under the “Foreign Exchange and Foreign Trade Law” is to be exported or taken out of Japan. An export license and/or quota needs to be obtained from the competent authorities of the Chinese Government if any of the products or technologies described in this material is subject to the PRC Foreign Trade Law and is to be exported or taken out of the PRC. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOM- ER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trade- marks or service marks of their respective owners. Intel is a registered trademark of Intel Corporation. Motorola is a registered trademark of Motorola, Inc.

1. PIN OUT - 144-PIN LQFP PACKAGE

Figure 1. CS61880 144-Pin LQFP Package Pin Outs

1. PIN OUT - 160-BALL FBGA PACKAGE

160 FBGA

Figure 2. CS61880 160-Ball FBGA Package Pin Outs

1. PIN DESCRIPTIONS

3.1 Power Supplies

Power Supply, Digital Interface: Power supply for digital interface pins; typically 3.3 V GNDIO G11 Ground, Digital Interface: Power supply ground for the digital interface; typically 0 V RV0+ RV1+ H14 Power Supply, Core Circuitry: Power supply for all sub-cir- cuits except the transmit driver; typically +3.3 V RGND0 RGND1 H11 Ground, Core Circuitry: Ground for sub-circuits except the TX driver; typically 0 V TV+0 N4, P4 Power Supply, Transmit Driver 0 Power supply for transmit driver 0; typically +3.3 V TGND0 N6, P6 Ground, Transmit Driver 0 Power supply ground for transmit driver 0; typically 0 V TV+1 L4, M4 Power Supply, Transmit Driver 1 TGND1 L6, M6 Ground, Transmit Driver 1 TV+2 L11 M11 Power Supply, Transmit Driver 2 TGND2 L9, M9 Ground, Transmit Driver 2 TV+3 N11 P11 Power Supply, Transmit Driver 3 TGND3 N9, P9 Ground, Transmit Driver 3 TV+4 116 A11 B11 Power Supply, Transmit Driver 4 TGND4 119 A9, B9 Ground, Transmit Driver 4 TV+5 125 C11 D11 Power Supply, Transmit Driver 5 TGND5 122 C9, Ground, Transmit Driver 5 TV+6 128 C4, Power Supply, Transmit Driver 6 TGND6 131 C6, Ground, Transmit Driver 6 TV+7 137 A4, B4 Power Supply, Transmit Driver 7 TGND7 134 A6, B6 Ground, Transmit Driver 7

3.2 Control

I Master Clock Input This pin is a free running reference clock that should be 2.048 MHz. This timing reference is used as follows: - Timing reference for the clock recovery and jitter attenua- tion circuitry. - RCLK reference during Loss of Signal (LOS) conditions - Transmit clock reference during Transmit all Ones (TAOS) condition - Wait state timing for microprocessor interface - When this pin is held “High”, the PLL clock recovery cir- cuit is disabled. In this mode, the CS61880 receivers function as simple data slicers. - When this pin is held “Low”, the receiver paths are pow- ered down and the output pins RCLK, RPOS, and RNEG are High-Z. MODE I Mode Select This pin is used to select whether the CS61880 operates in Serial host, Parallel host or Hardware mode. Host Mode - The CS61880 is controlled through either a serial or a parallel microprocessor interface (Refer to HOST MODE (See Section 13 on page 32). Hardware Mode - The microprocessor interface is disabled and the device control/status are provided through the pins on the device. NOTE: For serial host mode connect this pin to a resistor divider consisting of two 10 kΩ resistors between VCCIO and GNDIO. Table 1. Operation Mode Selection

I Multiplexed Interface/Bits Clock Select Host Mode -This pin configures the microprocessor inter- face for multiplexed or non-multiplexed operation. Hardware mode - This pin is used to enable channel 0 as a G.703 BITS Clock recovery channel (Refer to BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE (See Section 8 on page 23). Channel 1 through 7 are not affected by this pin during hardware mode. During host mode the G.703 BITS Clock recovery function is enabled by the Bits Clock Enable Register (1Eh) (See Section 14.31 on page 40). NOTE: The MUX pin only controls the BITS Clock function in Hardware Mode INT K13 O Interrupt Output This active low output signals the host processor when one of the CS61880’s internal status register bits has changed state. When the status register is read, the interrupt is cleared. The various status changes that would force INT active are maskable via internal interrupt enable registers. NOTE: This pin is an open drain output and requires a 10 kΩ pull-up resistor. RDY/ACK/SDO K14 O Ready/Data Transfer Acknowledge/Serial Data Output Intel Parallel Host Mode - During a read or write register access, RDY is asserted “Low” to acknowledge that the de- vice has been accessed. An asserted “High” acknowledges that data has been written or read. Upon completion of the bus cycle, this pin High-Z. Motorola Parallel Host Mode - During a data bus read operation this pin, “ACK”, is asserted “High” to indicate that data on the bus is valid. An asserted “Low” on this pin dur- ing a write operation acknowledges that a data transfer to the addressed register has been accepted. Upon comple- tion of the bus cycle, this pin High-Z. NOTE: Wait state generation via RDY/ACK is disabled in RZ mode (No Clock Recovery). Serial Host Mode - When the microprocessor interface is configured for serial bus operation, “SDO” is used as a seri- al data output. This pin is forced into a high impedance state during a serial write access. The CLKE pin controls whether SDO is valid on the rising or falling edge of SCLK. Upon completion of the bus cycle, this pin High-Z. Hardware Mode - This pin is not used and should be left open. SYMBOL LQFP FBGA TYPE Table 2. Mux/Bits Clock Selection

I Write Enable/Data Strobe/Serial Data Intel Parallel Host Mode - This pin, “WR”, functions as a write enable. Motorola Parallel Host Mode - This pin, “DS“, functions as a data strobe input. Serial Host Mode - This pin, “SDI”, functions as the serial data input. Hardware Mode - This pin is not used and should be con- nected to ground. RD/RW J13 I Read Enable/Read/Write Intel Parallel Host Mode - This pin, “RD”, functions as a read enable. Motorola Parallel Host Mode - This pin, “R/W”, functions as the read/write input signal. Hardware Mode - This pin is not used and should be con- nected to ground. ALE/AS/SCLK J12 I Address Latch Enable/Address Strobe/Serial Clock Intel Parallel Host Mode - This pin, “ALE”, functions as the Address Latch Enable when configured for multiplexed ad- dress/data operation. Motorola Parallel Host Mode - This pin, “AS”, functions as the active “low” address strobe when configured for multi- plexed address/data operation. Serial Host Mode - This pin, “SCLK”, is the serial clock used for data I/O on SDI and SDO. Hardware Mode - This pin is not used and should be con- nected to ground. CS/JASEL J11 I Chip Select Input/Jitter Attenuator Select Host Mode - This active low input is used to enable ac- cesses to the microprocessor interface in either serial or parallel mode. Hardware Mode - This pin controls the position of the Jitter Attenuator. SYMBOL LQFP FBGA TYPE Table 3. Jitter Attenuation Selection

I Intel/Motorola/Coder Mode Select Input Parallel Host Mode - When this pin is “Low” the micropro- cessor interface is configured for operation with Motorola processors. When this pin is “High” the microprocessor in- terface is configured for operation with Intel processors. Hardware Mode - When the CS61880 is configured for uni- polar operation, this pin, CODEN, configures the line encoding/decoding function. When CODEN is low, HDB3 encoders/decoders are enabled. When CODEN is high, AMI encoding/decoding is activated. This is done for all eight channels. TXOE 114 E14 I Transmitter Output Enable Host mode - Operates the same as in hardware mode. In- dividual drivers can be set to a high impedance state via the Output Disable Register (12h) (See Section 14.19 on page 38). Hardware Mode - When TXOE pin is asserted Low, all the TX drivers are forced into a high impedance state. All other internal circuitry remains active. CLKE 115 E13 I Clock Edge Select In clock/data recovery mode, setting CLKE “high” will cause RPOS/RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge of SCLK. When CLKE is set “low”, RPOS/RNEG is valid on the rising edge of RCLK, and SDO is valid on the falling edge of SCLK. When the part is operated in data recovery mode, the RPOS/RNEG output polarity is active “high” when CLKE is set “high” and active “low” when CLKE is set “low”. SYMBOL LQFP FBGA TYPE

3.3 Address Inputs/Loopbacks

I Address Selector Input Parallel Host Mode - During non-multiplexed parallel host mode operation, this pin function as the address 4 input for the parallel interface. Hardware Mode - The A4 pin must be tied low at all times. I I I I Non-Intrusive Monitoring/Address Selector Inputs Parallel Host Mode - During non-multiplexed parallel host mode operation, these pins function as address A[3:0] in- puts for the parallel interface. Hardware Mode - The A[3:0] pins are used for port selec- tion during non-intrusive monitoring. In non-intrusive monitoring mode, receiver 0’s input is internally connected to the transmit or receive ports on one of the other 7 chan- nels. The recovered clock and data from the selected port are output on RPOS0/RNEG0 and RCLK0. Additionally, the data from the selected port can be output on TTIP0/TRING0 by activating the remote loopback function for channel 0 (Refer to Performance Monitor Register (0Bh) (See Section 14.12 on page 36). LOOP0/D0 LOOP1/D1 LOOP2/D2 LOOP3/D3 LOOP4/D4 LOOP5/D5 LOOP6/D6 LOOP7/D7 I/O I/O I/O I/O I/O I/O I/O I/O Loopback Mode Selector/Parallel Data Input/Output Parallel Host Mode - In non-multiplexed microprocessor in- terface mode, these pins function as the bi-directional 8-bit data port. When operating in multiplexed microprocessor in- terface mode, these pins function as the address and data inputs/outputs. Hardware Mode - No Loopback - The CS61880 is in a normal operating state when LOOP is left open (unconnected) or tied to VCCIO/2. - Local Loopback - When LOOP is tied High, data transmit- ted on TTIP and TRING is looped back into the analog input of the corresponding channel’s receiver and output on RPOS and RNEG. Input Data present on RTIP and RRING is ignored. - Remote Loopback - When LOOP is tied Low the recov- ered clock and data received on RTIP and RRING is looped back for transmission on TTIP and TRING. Data on TPOS and TNEG is ignored.

3.4 Cable Select

3.5 Status

I Cable Impedance Select Host Mode - The input voltage to this pin does not effect normal operation. Hardware Mode - This pin is used to select the transmitted pulse shape and set the line impedance for all eight receiv- ers and transmitters. This pin also selects whether or not all eight receivers use an internal or external line matching network (Refer to the Table 4 below for proper settings). NOTE: Refer to Figure 16 on page 50 and Figure 17 on page 51 for appropriate external line matching com- ponents. All transmitters use internal matching net- works. Table 4. Cable Impedance Selection O O O O O O O O Loss of Signal Output The LOS output pins can be configured to indicate a loss of signal (LOS) state that is compliant to either ITU G.775 or ETSI 300 233. These pins are asserted “High” to indicate LOS. The LOS output returns low when an input signal is present for the time period dictated by the associated speci- fication (Refer to Loss-of-Signal (LOS) (See Section 10.5 on page 27)).

3.6 Digital Rx/Tx Data I/O

I Transmit Clock Input Port 0 - When TCLK is active, the TPOS and TNEG pins function as NRZ inputs that are sampled on the falling edge of TCLK. - If MCLK is active, TAOS will be generated when TCLK is held High for 16 MCLK cycles. NOTE: MCLK is used as the timing reference during TAOS and must have the appropriate stability. - If TCLK is held High in the absence of MCLK, the TPOS and TNEG inputs function as RZ inputs. In this mode, the transmit pulse width is set by the pulse-width of the signal input on TPOS and TNEG. To enter this mode, TCLK must be held high for at least 12 µs. - If TCLK is held Low, the output drivers enter a low-power, high impedance state. TPOS0/TDATA0 TNEG0/UBS I I Transmit Positive Pulse/Transmit Data Input Port 0 Transmit Negative Pulse/Unipolar-Bipolar Select Port 0 The function of the TPOS/TDATA and TNEG/UBS inputs are determined by whether Unipolar, Bipolar or RZ input mode has been selected. Bipolar Mode - In this mode, NRZ data on TPOS and TNEG are sampled on the falling edge of TCLK and trans- mitted onto the line at TTIP and TRING respectively. A “High” input on TPOS results in transmission of a positive pulse; a “High” input on TNEG results in a transmission of a negative pulse. The translation of TPOS/TNEG inputs to TTIP/TRING outputs is as follows: Unipolar mode - Unipolar mode is activated by holding TNEG/UBS “High” for more than 16 TCLK cycles, when MCLK is present. The falling edge of TCLK samples a uni- polar data steam on TPOS/TDATA. RZ Mode - To activate RZ mode tie TCLK “High” in the absence of MCLK. In this mode, the duty cycle of the TPOS and TNEG inputs determine the pulse width of the output signal on TTIP and TRING. Table 5. Bipolar Mode Translations

O Receive Clock Output Port 0 - When MCLK is active, this pin outputs the recovered clock from the signal input on RTIP and RRING. In the event of LOS, the RCLK output transitions from the recovered clock to MCLK. - If MCLK is held “High”, the clock recovery circuitry is dis- abled and the RCLK output is driven by the XOR of RNEG and RPOS. - If MCLK is held “Low”, this output is in a high-impedance state. RPOS0/RDATA0 RNEG0/BPV0 O O Receive Positive Pulse/ Receive Data Output Port 0 Receive Negative Pulse/Bipolar Violation Output Port 0 The function of the RPOS/RDATA and RNEG/BPV outputs are determined by whether Unipolar, Bipolar, or RZ input mode has been selected. During LOS, the RPOS/RNEG outputs will remain active. NOTE: The RPOS/RNEG outputs can be High-Z by holding MCLK Low. Bipolar Output Mode - When configured for Bipolar opera- tion, NRZ Data is recovered from RTIP/RRING and output on RPOS/RNEG. A high signal on RPOS or RNEG corre- spond to the receipt of a positive or negative pulse on RTIP/RRING respectively. The RPOS/RNEG outputs are valid on the falling or rising edge of RCLK as configured by CLKE. Unipolar Output Mode - When unipolar mode is activated, the recovered data is output on RDATA. The decoder sig- nals bipolar violations are output on the RNEG/BPV pin. RZ Output Mode - In this mode, the RPOS/RNEG pins output RZ data recovered by slicing the signal present on RTIP/RRING. A positive pulse on RTIP with respect to RRING generates a logic 1 on RPOS; a positive pulse on RRING with respect to RTIP generates a logic 1 on RNEG. The polarity of the output on RPOS/RNEG is selectable us- ing the CLKE pin. In this mode, external circuitry is used to recover clock from the received signal. TCLK1 I Transmit Clock Input Port 1 TPOS1/TDATA1 I Transmit Positive Pulse/Transmit Data Input Port 1 TNEG1/UBS1 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 1 RCLK1 O Receive Clock Output Port 1 RPOS1/RDATA1 O Receive Positive Pulse/ Receive Data Output Port 1 RNEG1/BPV1 O Receive Negative Pulse/Bipolar Violation Output Port 1 TCLK2 L14 I Transmit Clock Input Port 2 TPOS2/TDATA2 L13 I Transmit Positive Pulse/Transmit Data Input Port 2 TNEG2/UBS2 L12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 2 SYMBOL LQFP FBGA TYPE

O Receive Clock Output Port 2 RPOS2/RDATA2 M13 O Receive Positive Pulse/ Receive Data Output Port 2 RNEG2/BPV2 M12 O Receive Negative Pulse/Bipolar Violation Output Port 2 TCLK3 N14 I Transmit Clock Input Port 3 TPOS3/TDATA3 N13 I Transmit Positive Pulse/Transmit Data Input Port 3 TNEG3/UBS3 N12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 3 RCLK3 P14 O Receive Clock Output Port 3 RPOS3/RDATA3 P13 O Receive Positive Pulse/ Receive Data Output Port 3 RNEG3/BPV3 P12 O Receive Negative Pulse/Bipolar Violation Output Port 3 TCLK4 107 B14 I Transmit Clock Input Port 4 TPOS4/TDATA4 108 B13 I Transmit Positive Pulse/Transmit Data Input Port 4 TNEG4/UBS4 109 B12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 4 RCLK4 110 A14 O Receive Clock Output Port 4 RPOS4/RDATA4 111 A13 O Receive Positive Pulse/ Receive Data Output Port 4 RNEG4/BPV4 112 A12 O Receive Negative Pulse/Bipolar Violation Output Port 4 TCLK5 100 D14 I Transmit Clock Input Port 5 TPOS5/TDATA5 101 D13 I Transmit Positive Pulse/Transmit Data Input Port 5 TNEG5/UBS5 102 D12 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 5 RCLK5 103 C14 O Receive Clock Output Port 5 RPOS5/RDATA5 104 C13 O Receive Positive Pulse/ Receive Data Output Port 5 RNEG5/BPV5 105 C12 O Receive Negative Pulse/Bipolar Violation Output Port 5 TCLK6 I Transmit Clock Input Port 6 TPOS6/TDATA6 I Transmit Positive Pulse/Transmit Data Input Port 6 TNEG6/UBS6 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 6 RCLK6 O Receive Clock Output Port 6 RPOS6/RDATA6 O Receive Positive Pulse/ Receive Data Output Port 6 RNEG6/BPV6 O Receive Negative Pulse/Bipolar Violation Output Port 6 TCLK7 I Transmit Clock Input Port 7 TPOS7/TDATA7 I Transmit Positive Pulse/Transmit Data Input Port 7 TNEG7/UBS7 144 I Transmit Negative Pulse/Unipolar-Bipolar Select Port 7 SYMBOL LQFP FBGA TYPE

3.7 Analog RX/TX Data I/O

O Receive Clock Output Port 7 RPOS7/RDATA7 142 O Receive Positive Pulse/ Receive Data Output Port 7 RNEG7/BPV7 141 O Receive Negative Pulse/Bipolar Violation Output Port 7 SYMBOL LQFP FBGA TYPE O O Transmit Tip Output Port 0 Transmit Ring Output Port 0 These pins are the differential outputs of the transmit driver. The driver internally matches impedances for E1 75 Ω or E1 120 Ω lines requiring only a 1:1.15 transformer. The CBLSEL pin is used to select the appropriate line matching impedance only in “Hardware” mode. In host mode, the ap- propriate line matching impedance is selected by the Line Length Data Register (11h) (See Section 14.18 on page 38). NOTE: TTIP and TRING are forced to a high impedance state when the TCLK or the TXOE pin is forced “Low”. RTIP0 RRING0 I I Receive Tip Input Port 0 Receive Ring Input Port 0 These pins are the differential line inputs to the receiver. The receiver uses either Internal Line Impedance or Exter- nal Line Impedance modes to match the line impedances for E1 75Ω or E1 120Ω modes. Internal Line Impedance Mode - The receiver uses the same external resistors to match the line impedance (Refer to Figure 16 on page 50). External Line Impedance Mode - The receiver uses differ- ent external resistors to match the line impedance (Refer to Figure 17 on page 51). - In host mode, the appropriate line impedance is selected by the Line Length Data Register (11h) (See Section 14.18 on page 38). - In hardware mode, the CBLSEL pin selects the appropri- ate line impedance. (Refer to Table 4 on page 15 for proper line impedance settings). NOTE: Data and clock recovered from the signal input on these pins are output via RCLK, RPOS, and RNEG. TTIP1 O Transmit Tip Output Port 1 TRING1 O Transmit Ring Output Port 1 RTIP1 I Receive Tip Input Port 1 RRING1 I Receive Ring Input Port 1 TTIP2 L10 O Transmit Tip Output Port 2

O Transmit Ring Output Port 2 RTIP2 I Receive Tip Input Port 2 RRING2 I Receive Ring Input Port 2 TTIP3 N10 O Transmit Tip Output Port 3 TRING3 P10 O Transmit Ring Output Port 3 RTIP3 I Receive Tip Input Port 3 RRING3 I Receive Ring Input Port 3 TTIP4 117 B10 O Transmit Tip Output Port 4 TRING4 118 A10 O Transmit Ring Output Port 4 RTIP4 120 I Receive Tip Input Port 4 RRING4 121 I Receive Ring Input Port 4 TTIP5 124 D10 O Transmit Tip Output Port 5 TRING5 123 C10 O Transmit Ring Output Port 5 RTIP5 127 I Receive Tip Input Port 5 RRING5 126 I Receive Ring Input Port 5 TTIP6 129 O Transmit Tip Output Port 6 TRING6 130 O Transmit Ring Output Port 6 RTIP6 132 I Receive Tip Input Port 6 RRING6 133 I Receive Ring Input Port 6 TTIP7 136 O Transmit Tip Output Port 7 TRING7 135 O Transmit Ring Output Port 7 RTIP7 139 I Receive Tip Input Port 7 RRING7 138 I Receive Ring Input Port 7 SYMBOL LQFP FBGA TYPE

3.8 JTAG Test Interface

3.9 Miscellaneous

I JTAG Reset This active Low input resets the JTAG controller. This input is pulled up internally and may be left as a NC when not used. TMS F11 I JTAG Test Mode Select Input This input enables the JTAG serial port when active High. This input is sampled on the rising edge of TCK. This input is pulled up internally and may be left as a NC when not used. TCK F14 I JTAG Test Clock Data on TDI is valid on the rising edge of TCK. Data on TDO is valid on the falling edge of TCK. When TCK is stopped high or low, the contents of all JTAG registers re- main unchanged. Tie pin low through a 10 kΩ resistor when not used. TDO F13 O JTAG Test Data Output JTAG test data is shifted out of the device on this pin. Data is output on the falling edge of TCK. Leave as NC when not used. TDI F12 I JTAG Test Data Input JTAG test data is shifted into the device using this pin. The pin is sampled on the rising edge of TCK. TDI is pulled up internally and may be left as a NC when not used. SYMBOL LQFP FBGA TYPE I Reference Input This pin must be tied to ground through 13.3 kΩ 1% resis- tor. This pin is used to set the internal current level.

sistor values for all E1 settings. the CS61880 to operate incorrectly. Table 6. G.772 Address Selection

circuit for E1 120 Ω, and E1 75 Ω applications. dard cables, transformers, or protection circuitry.

9.1 Bipolar Mode

on TPOS/TNEG for transmission on TTIP/TRING.

9.2 Unipolar Mode

Figure 6. Pulse Mask at E1 Interface

TNEG/UBS “High” for more than 16 TCLK cy- cles. Transmit data is input to the part via the TPOS/TDATA pin on the falling edge of TCLK. When operating the part in hardware mode, the CODEN pin is used to select between HDB3 or AMI encoding. During host mode operation, the line coding is selected via the Line Length Chan- nel ID Register (10h) (See Section 14.17 on page 38). NOTE: The encoders/decoders are selected for all eight channels in both hardware and host mode.

9.3 RZ Mode

In RZ mode, the internal pulse shape circuitry is bypassed and RZ data driven into TPOS/TNEG is transmitted on TTIP/TRING. In this mode, the pulse width of the transmitter output is determined by the width of the RZ signal input to TPOS/TNEG pins. This mode is entered when MCLK is inactive and TCLK is held “High” for at least 12 µs.

9.4 Transmitter Powerdown / High-Z

The transmitters can be forced into a high imped- ance, low power state by holding TCLK of the ap- propriate channel low for at least 12 µs or 140 MCLK cycles. In hardware and host mode, the TXOE pin forces all eight transmitters into a high impedance state within 1 µs. In host mode, each transmitter is individually con- trollable using the Output Disable Register (12h) (See Section 14.19 on page 38). The TXOE pin can be used in host mode, but does not effect the con- tents of the Output Enable Register. This feature is useful in applications that require redundancy.

9.5 Transmit All Ones (TAOS)

When TAOS is activated, continuous ones are transmitted on TTIP/TRING using MCLK as the transmit timing reference. In this mode, the TPOS and TNEG inputs are ignored. In hardware mode, TAOS is activated by pulling TCLK “High” for more than 16 MCLK cycles. In host mode, TAOS is generated for a particular channel by asserting the associated bit in the TAOS Enable Register (03h) (See Section 14.4 on page 35). Since MCLK is the reference clock, it should be of adequate stability.

9.6 Automatic TAOS

While a given channel is in the LOS condition, if the corresponding bit in the Automatic TAOS Register (0Eh) (See Section 14.15 on page 37) is set, the device will drive that channel’s TTIP and TRING with the all ones pattern. This function is only available in host mode. Refer to Loss-of-Sig- nal (LOS) (See Section 10.5 on page 27).

9.7 Driver Failure Monitor

In host mode, the Driver Failure Monitor (DFM) function monitors the output of each channel and sets a bit in the DFM Status Register (05h) (See Section 14.6 on page 35) if a secondary short cir- cuit is detected between TTIP and TRING. This generates an interrupt if the respective bit in the DFM Interrupt Enable Register (07h) (See Sec- tion 14.8 on page 36) is also set. Any change in the DFM Status Register (05h) (See Section 14.6 on page 35) will result in the corresponding bit in the DFM Interrupt Status Register (09h) (See Sec- tion 14.10 on page 36) being set. The interrupt is cleared by reading the DFM Interrupt Status Register (09h) (See Section 14.10 on page 36).

9.8 Driver Short Circuit Protection

The CS61880 provides driver short circuit protec- tion when current on the secondary exceeds 50 mA RMS.

1. RECEIVER The CS61880 contains eight identical receivers that utilize an internal matched impedance technique that provides for the use of a common set of exter- nal components for 120 Ω (E1), and 75 Ω (Ε1) op- eration (Refer to Figure 16 on page 50). This feature enables the use of a one stuffing option for all E1 line impedances. The receivers can also be configured to use different external resistors to match the line impedance for E1 75 Ω or E1 120 Ω modes (Refer to Figure 17 on page 51). In hardware mode, the CBLSEL pin is used to se- lect the proper line impedance (75 Ω or 120 Ω) and either internal or external line impedance matching mode. In host mode, each receiver’s line impedance is se- lected individually via the Line Length Channel ID Register (10h) (See Section 14.17 on page 38) and bits[3:0] and the LEN[3:0] bits of the Line Length Data Register (11h) (See Section 14.18 on page 38). The INT_EXTB bit of the Line Length Data Register (11h) (See Section 14.18 on page 38) is used to select between internal or exter- nal line impedance matching modes for all eight channels. The CBLSEL pin is not used in host mode. The CS61880 receiver provides all of the circuitry to recover both data and clock from the data signal input on RTIP and RRING. The matched imped- ance receiver is capable of recovering signals with 12 dB of attenuation (referenced to 2.37 V or 3.0 V nominal) while providing superior return loss. In addition, the timing recovery circuit along with the jitter attenuator provide jitter tolerance that far ex- ceeds jitter specifications (Refer to Figure 19 on page 57). The recovered data and clock are output from the CS61880 on the RPOS/RDATA, RNEG and RCLK pins. These pins output the data in one of three formats: bipolar, unipolar, or RZ. The CLKE pin is used to configure RPOS/RDATA and RNEG, so that data is valid on either the rising or falling edge of RCLK. Refer to the CLKE pin de- scription on page 13 for CLKE settings.

10.1 Bipolar Output Mode

Bipolar mode provides a transparent clock/data re- covery for applications in which the line decoding is performed by an external framing device. The re- covered clock and data are output on RCLK, RNEG and RPOS.

10.2 Unipolar Output Mode

In unipolar mode, the CS61880 decodes the recov- ered data with either HDB3 or AMI line decoding. The decoded data is output on the RPOS/RDATA pin. When bipolar violations are detected by the de- coder, the RNEG/BPV pin is asserted “high”. This pin is driven “high” for one RCLK period for every bipolar violation that is not part of the zero substi- tution rules. Unipolar mode is entered by holding the TNEG pin “high” for more than 16 TCLK cy- cles. In hardware mode, the HDB3/AMI encoding/de- coding is activated via the CODEN pin. In host mode, Bit 4 of the Line Length Channel ID Register (10h) (See Section 14.17 on page 38) is used to select the encoding/decoding for all chan- nels.

10.3 RZ Output Mode

In this mode the RTIP and RRING inputs are sliced to data values that are output on RPOS and RNEG pins. This mode is used in applications that have clock recovery circuitry external to the device. To support external clock recovery, the RPOS and RNEG outputs are XORed and output as RCLK. This mode is entered when MCLK is tied high. The polarity of the RPOS/RNEG data are controlled by the CLKE pin. Refer to the CLKE pin description on page 13 for CLKE settings.

10.4 Receiver Powerdown/High-Z

All eight receivers are powered down when MCLK is held low. In addition, this will force the RCLK, RPOS/RDATA and RNEG outputs into a high im- pedance state.

10.5 Loss-of-Signal (LOS)

The CS61880 makes use of both analog and digital LOS detection circuitry that is compliant to the lat- est specifications. The LOS condition can be set to either ITU G.775 or ETSI 300 233. This change is done through the LOS/AIS Mode Enable Regis- ter (0Dh) (See Section 14.14 on page 37). The LOS detector increments a counter each time a zero is received, and resets the counter each time a one “mark” is received. Depending on LOS detec- tion mode, the LOS signal is set when a certain number of consecutive zeros are received. In Clock/Data recovery mode, this forces the recov- ered clock to be replaced by MCLK at the RCLK output. In addition the RPOS/RDATA and RNEG outputs remain active for the length of the LOS pe- riod, except when local and analog loopbacks are enabled. Upon exiting LOS, the recovered clock re- places MCLK on the RCLK output. In Data recov- ery mode, RCLK is not replaced by MCLK when LOS is active. The LOS detection modes are sum- marized below. NOTE: G.775 and ETSI 300 233 are both available in host mode, but in hardware mode only ETSI 300 233 is available. ITU G.775 (E1 Mode Only) - LOS is declared when the received signal level is less than 200 mV for 32 consecutive pulse periods (typical). The de- vice exits LOS when the received signal achieves 12.5% ones density with no more than 15 consecu- tive zeros in a 32-bit sliding window and the signal level exceeds 250 mV. ETSI 300 233 (E1 Host Mode Only) - The LOS indicator becomes active when the receive signal level drops below 200 mV for more than 2048 pulse periods (1 ms). The channel exits the LOS state when the input signal exceeds 250 mV and has transitions for more than 32 pulse periods (16 µs). This LOS detection method can only be se- lected while in host mode. During host mode operation, LOS is reported in the LOS Status Monitor Register. Both the LOS pins and the register bits reflect LOS status in host mode operation. The LOS pins and status bits are set high (indicating loss of signal) during reset, power-up, or channel powered-down.

10.6 Alarm Indication Signal (AIS)

The CS61880 detects all ones alarm condition per the relevant ITU, and ETSI specifications. In gen- eral, AIS is indicated when the one’s density of the receive signal exceeds that dictated by the relevant specification. This feature is only available in host mode (Refer to LOS/AIS Mode Enable Register (0Dh) (See Section 14.14 on page 37)). ITU G.775 AIS (E1 Mode) - The AIS condition is declared when less than 3 zeros are received within two consecutive 512-bit windows. The AIS condi- tion is cleared when 3 or more zeros are received in two consecutive 512-bit windows. ETSI 300 233 (E1 Mode) - The AIS condition is declared when less than 3 zeros are received in a 512-bit window. The AIS condition is cleared when a 512-bit window is received containing 3 or more zeros.

switched into either the receive or transmit paths. reduce the propagation delay. are set to 32 bits and 1.25 Hz. length (bit 3) and corner frequency (bit 2). ther overflow nor underflow. bits to 32 bits in order to reduce propagation delay. Table 7. Jitter Attenuator Configurations

A brief summary of the CS61880 operations in hardware and host mode is provided in Table 8.

12.1 Loopbacks

signal on TTIP and TRING to RTIP and RRING.

12.2 Analog Loopback

Loopback is selected by driving LOOP[7:0] high. Table 8. Operational Summary

12.3 Digital Loopback

RCLK, RPOS, and RNEG (or RDATA) outputs. TRING (Refer to Figure 9 on page 31).

12.4 Remote Loopback

mode, TAOS overrides Remote Loopback. Figure 7. Analog Loopback Block Diagram Figure 8. Analog Loopback with TAOS Block Diagram

Parallel Host and Serial Host modes. scribed in Table 9 on page 32.

13.1 SOFTWARE RESET

13.2 Serial Port Operation

format of serial port data transfers. data byte immediately follows the ACB. data on SDO is valid on the falling edge of SCLK. Table 9. Host Control Signal Descriptions

13.3 Parallel Port Operation

Figure 29, Figure 30, Figure 31 and Figure 32. Figure 31. The CS pin initiates the cycle, followed or RD pin. Raising CS ends the cycle. again to indicate that data has been written or read. Figure 12. Serial Read/Write Format (SPOL = 0)

13.4 Register Set

Table 10. Host Mode Register Set

1. REGISTER DESCRIPTIONS

14.1 Revision/IDcode Register (00h)

14.2 Analog Loopback Register (01h)

14.3 Remote Loopback Register (02h)

14.4 TAOS Enable Register (03h)

14.5 LOS Status Register (04h)

14.6 DFM Status Register (05h)

[7:4] REVI 7-4 Bits [7:4] are taken from the least-significant nibble of the Device IDCode, which are 0000. (Refer to Device ID Register (IDR) (See Section 16.3 on page 47). [3:0] REVI 3-0 Bits [3:0] are the revision bits from the JTAG IDCODE register, CS61880 Revision A = 0000. These bits are subject to change with the revision of the device (Refer to Device ID Register (IDR) (See Section 16.3 on page 47). BIT NAME [7:0] ALBK 7-0 Enables analog loopbacks. A “1” in bit n enables the loopback for channel n. Refer to Analog Loopback (See Section 12.2 on page 29) for a complete explanation. Register bits default to 00h after power-up or reset. BIT NAME [7:0] RLBK 7-0 Enables remote loopbacks. A “1” in bit n enables the loopback for channel n. Refer to HOST MODE (See Section 13 on page 32) for a complete explanation. Register bits default to 00h after power-up or reset. BIT NAME [7:0] TAOE 7-0 A “1” in bit n of this register turns on the TAOS generator in channel n. Register bits default to 00h after power-up or reset. BIT NAME [7:0] LOSS 7-0 Register bit n is read as “1” when LOS is detected on channel n. Register bits default to 00h after power-up or reset. BIT NAME [7:0] DFMS 7-0 Driver Failure Monitor. The DFM will set bit n to “1” when it detects a short circuit in channel n. Register bits default to 00h after power-up or reset.

14.7 LOS Interrupt Enable Register (06h)

14.8 DFM Interrupt Enable Register (07h)

14.9 LOS Interrupt Status Register (08h)

14.10 DFM Interrupt Status Register (09h)

14.11 Software Reset Register (0Ah)

14.12 Performance Monitor Register (0Bh)

14.13 Digital Loopback Reset Register (0Ch)

[7:0] LOSE 7-0 Any change in a LOS Status Register will cause the INT pin to go low if corresponding bit in this register is set to “1”. Register bits default to 00h after power-up or reset. BIT NAME [7:0] DFME 7-0 Enables interrupts for failures detected by the DFM. Any change in a DFM Status Register bit will cause an interrupt if the corresponding bit is set to “1” in this register. Register bits default to 00h after power-up or reset. BIT NAME [7:0] LOSI 7-0 Bit n of this register is set to “1” to indicate a status change in bit n of the LOS Status Regis- ter. The bits in this register indicate a change in status since the last cleared LOS interrupt. Register bits default to 00h after power-up or reset. BIT NAME [7:0] DFMI 7-0 Bit n of this register is set to “1” to indicate a status change in bit n of the DFM Status Regis- ter. The bits in this register indicate a change in status since the last cleared DFM interrupt. Register bits default to 00h after power-up or reset. BIT NAME [7:0] SRES 7-0 Writing to this register initializes all registers to their default settings. Register bits default to 00h after power-up or reset. BIT NAME [7:4] RSVD 7-4 RESERVED (These bits must be set to 0.) [3:0] A[3:0] The G.772 Monitor is directed to a given channel based on the state of the four least signifi- cant bits of this register. Register bits default to 00h after power-up or reset. The follow- ing table shows the settings needed to select a specific channel’s receiver or transmitter to perform G.772 monitoring. See Table 6 on page 22 for G.772 Monitor Settings. BIT NAME [7:0] DLBK 7-0 Setting register bit n to “1” enables the digital loopback for channel n. Refer to Digital Loop- back (See Section 12.3 on page 30) for a complete explanation. Register bits default to 00h after power-up or reset.

14.14 LOS/AIS Mode Enable Register (0Dh)

14.15 Automatic TAOS Register (0Eh)

14.16 Global Control Register (0Fh)

[7:0] LAME 7-0 Setting bit n to “1” enables ETSI 300 233 compliant LOS/AIS for channel n; setting bit n to “0” enables ITU G.775 compliant LOS/AIS for channel n. Register bits default to 00h after power-up or reset. BIT NAME [7:0] ATAO 7-0 Setting bit n to “1” enables automatic TAOS generation on channel n when LOS is detected. Register bits default to 00h after power-up or reset. BIT NAME This register is the global control for the AWG Auto-Increment, Automatic AIS insertion, encoding/decoding and the jitter attenuators location, FIFO length and corner frequency for all eight channels. Register bits default to 00h after power-up or reset. [7] AWG Auto- Increment The AWG Auto-Increment bit indicates whether to auto-increment the AWG Phase Address Register (17h) (See Section 14.24 on page 39) after each access. Thus, when this bit is set, the phase samples address portion of the address register increments after each read or write access. This bit must be set before any bit in the AWG Enable register is set, if this function is required. [6] RAISEN On LOS, this bit controls the automatic AIS insertion into all eight receiver paths. 0 = Disabled 1 = Enabled [5] RSVD RESERVED (This bit must be set to 0.) [4] CODEN Line encoding/decoding Selection 0 = HDB3 1 = AMI [3] FIFO LENGTH Jitter Attenuator FIFO length Selection 0 = 32 bits 1 = 64 bits [2] JACF Jitter Attenuator Corner Frequency Selection 0 = 1.25 Hz 1 = 2.50 Hz [1:0] JASEL [1:0] These bits select the position of the Jitter Attenuator. Table 11. Jitter Attenuator Position Selection

14.17 Line Length Channel ID Register (10h)

14.18 Line Length Data Register (11h)

14.19 Output Disable Register (12h)

14.20 AIS Status Register (13h)

[7:3] RSVD 7-3 RESERVED (These bits must be set to 0.) [2:0] LLID 2-0 The value written to these bits specify the LIU channel for which the Pulse Shape Configura- tion Data (register 11h) applies. For example, writing a value of a binary 000 to the 3-LSBs will select channel 0. The pulse shape configuration data for the channel specified in this reg- ister are written or read through the Line Length Data Register (11h). Register bits default to 00h after power-up or reset. BIT NAME The value written to the 4-LSBs of this register specifies whether the device is operating in either E1 75 Ω or E1 120 Ω mode and the associated pulse shape as shown below is being transmitted. Register bits default to 00h after power-up or reset. [7:5] RSVD RESERVED (These bits must be set to 0.) [4] INT_EXTB This bit specifies the use of internal (Int_ExtB = 1) or external (Int_ExtB = 0) receiver line matching. The line impedance for both the receiver and transmitter are chosen through the LEN [3:0] bits in this register. [3:0] LEN[3:0] These bits set the line impedance for both the receiver and the transmitter path and the desired pulse shape for a specific channel. The channel is selected with the Line Length Channel ID register (0x10). The following table shows the available transmitter pulse shapes. BIT NAME [7:0] OENB 7-0 Setting bit n of this register to “1” High-Z the TX output driver on channel n of the device. Register bits default to 00h after power-up or reset. BIT NAME [7:0] AISS 7-0 A “1” in bit position n indicates that the receiver has detected an AIS condition on channel n, which generates an interrupt on the INT pin. Register bits default to 00h after power-up or reset. Table 12. Transmitter Pulse Shape Selection

14.21 AIS Interrupt Enable Register (14h)

14.22 AIS Interrupt Status Register (15h)

14.23 AWG Broadcast Register (16h)

14.24 AWG Phase Address Register (17h)

14.25 AWG Phase Data Register (18h)

[7:0] AISE 7-0 This register enables changes in the AIS Status register to be reflected in the AIS Interrupt Status register, thus causing an interrupt on the INT pin. Register bits default to 00h after power-up or reset. BIT NAME [7:0] AISI 7-0 Bit n is set to “1” to indicate a change of status of bit n in the AIS Status Register. The bits in this register indicate which channel changed in status since the last cleared AIS interrupt. Register bits default to 00h after power-up or reset. BIT NAME [7:0] AWGB 7-0 Setting bit n to “1” causes the phase data in the AWG Phase Data Register to be written to the corresponding channel or channels simultaneously. (Refer to Arbitrary Waveform Gen- erator (See Section 15 on page 42). Register bits default to 00h after power-up or reset. BIT NAME [7:5] AWGA These bits specify the target channel 0-7. (Refer to Arbitrary Waveform Generator (See Section 15 on page 42). Register bits default to 00h after power-up or reset. [4:0] PA[4:0] These bits specify 1 of 24 phase sample address locations of the AWG, that the phase data in the AWG Phase Data Register is written to or read from. Register bits default to 00h after power-up or reset. BIT NAME [7] RSVD RESERVED (This bit must be set to 0.) [6:0] AWGD [6:0] These bits are used for the pulse shape data that will be written to or read from the AWG phase location specified by the AWG Phase Address Register. The value written to or read from this register will be written to or read from the AWG phase sample location specified by the AWG Phase Address register. A software reset through the Software Reset Register does not effect the contents of this register. The data in each phase is a 7-bit 2’s complement number (the maximum positive value is 3Fh and the maximum negative value is 40h). (Refer to Arbitrary Waveform Generator (See Section 15 on page 42). Register bits default to 00h after power-up.

14.26 AWG Enable Register (19h)

14.27 Reserved Register (1Ah)

14.28 Reserved Register (1Bh)

14.29 Reserved Register (1Ch)

14.30 Reserved Register (1Dh)

14.31 Bits Clock Enable Register (1Eh)

14.32 Reserved Register (1Fh)

14.33 Status Registers

The following Status registers are read-only: LOS Status Register (04h) (See Section 14.5 on page 35), DFM Status Register (05h) (See Sec- tion 14.6 on page 35) and AIS Status Register (13h) (See Section 14.20 on page 38). The CS61880 generates an interrupt on the INT pin any time an unmasked status register bit changes. BIT NAME [7:0] AWGN 7-0 The AWG enable register is used for selecting the source of the customized transmission pulse-shape. Setting bit n to “1” in this register selects the AWG as the source of the output pulse shape for channel n. When bit n is set to “0” the pre-programmed pulse shape in the ROM is selected for transmission on channel n. (Refer to Arbitrary Waveform Generator (See Section 15 on page 42). Register bits default to 00h after power-up or reset. BIT NAME [7:0] RSVD 7-0 RESERVED BIT NAME [7:0] RSVD 7-0 RESERVED BIT NAME [7:0] RSVD 7-0 RESERVED BIT NAME [7:0] RSVD 7-0 RESERVED BIT NAME [7:0] BITS 7-0 Writing a “1” to bit n in this register changes channel n to a stand-alone timing recovery unit used for G.703 clock recovery. (Refer to BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODE (See Section 8 on page 23) for a better description of the G.703 clock recovery function). Register bits default to 00h after power-up or reset. BIT NAME [7:0] RSVD 7-0 RESERVED

14.33.1 Interrupt Enable Registers

The Interrupt Enable registers: LOS Interrupt En- able Register (06h) (See Section 14.7 on page 36), DFM Interrupt Enable Register (07h) (See Sec- tion 14.8 on page 36), AIS Interrupt Enable Reg- ister (14h) (See Section 14.21 on page 39), enable changes in status register state to cause an interrupt on the INT pin. Interrupts are maskable on a per channel basis. When an Interrupt Enable register bit is 0, the corresponding Status register bit is dis- abled from causing an interrupt on the INT pin. NOTE: Disabling an interrupt has no effect on the sta- tus reflected in the associated status register.

14.33.2 Interrupt Status Registers

The following interrupt status registers: LOS In- terrupt Status Register (08h) (See Section 14.9 on page 36), DFM Interrupt Status Register (09h) (See Section 14.10 on page 36), AIS Inter- rupt Status Register (15h) (See Section 14.22 on page 39), indicate a change in status of the corre- sponding status registers in host mode. Reading these registers clears the interrupt, which deacti- vates the INT pin.

AWG, while the device is in host mode. ter (17h) (See Section 14.24 on page 39)). Figure 13. Arbitrary Waveform UI

sample address (00000 binary) needs to be written to the AWG Phase Address Register (17h) (See Section 14.24 on page 39), and each subsequent ac- cess (read or write) to the AWG Phase Data Reg- ister (18h) (See Section 14.25 on page 39) will automatically increment the phase sample address. The channel address, however, remains unaffected by the Auto-Increment mode. The AWG Phase Address Register (17h) (See Section 14.24 on page 39) needs to be re-written in order to re-start the phase sample address sequence from the new phase sample address. The AWG Broadcast function allows the same data to be written to multiple channels simultaneously. This is done with the use of the AWG Broadcast Register (16h) (See Section 14.23 on page 39), each bit in the AWG Broadcast Register corre- sponds to a different channel (e.g. bit 0 is channel 0, and bit 3 is channel 3 and etc.). To use the AWG Broadcast function MCLK must be present. When MCLK is inactive the AWG Broadcast function is disabled. To write the same pulse shaping data to multiple channels, simple set the corresponding bit to “1” in the AWG Broadcast Register (16h) (See Section 14.23 on page 39) before accessing the AWG phase data register. This function only requires that one of the eight channel addresses be written to the AWG Phase Address Register (17h) (See Section 14.24 on page 39). During an AWG read sequence, the bits in the AWG Broadcast Register are ig- nored. During an AWG write sequence, the select- ed channel or channels are specified by both the channel address specified by the upper bits of the AWG Phase Address Register (17h) (See Section 14.24 on page 39) and the selected channel or chan- nels in the AWG Broadcast Register (16h) (See Section 14.23 on page 39). During a multiple channel write the first channel that is written to, is the channel that was addressed by the AWG Phase Address Register. This chan- nel’s bit in the AWG Broadcast Register can be set to either “1” or “0”. For a more descriptive explanation of how to use the AWG function refer to the Application Note AN204, How To Use The CS61880/CS61884 Arbi- trary Waveform Generator. 16. JTAG SUPPORT The CS61880 supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 stan- dards. A Test Access Port (TAP) is provided that consists of the TAP controller, the instruction reg- ister (IR), by-pass register (BPR), device ID regis- ter (IDR), the boundary scan register (BSR), and the 5 standard pins (TRST, TCK, TMS, TDI, and TDO). A block diagram of the test access port is shown in Figure 14 on page 44. The test clock in- put (TCK) is used to sample input data on TDI, and shift output data through TDO. The TMS input is used to step the TAP controller through its various states. The instruction register is used to select test execu- tion or register access. The by-pass register pro- vides a direct connection between the TDI input and the TDO output. The device identification reg- ister contains a 32-bit device identifier. The Boundary Scan Register is used to support test- ing of IC inter-connectivity. Using the Boundary Scan Register, the digital input pins can be sampled and shifted out on TDO. In addition, this register can also be used to drive digital output pins to a user defined state.

16.1 TAP Controller

Figure 15. The value shown next to each state tran- TMS when it is sampled by the rising edge of TCK.

16.1.1 JTAG Reset

TRST resets all JTAG circuitry.

16.1.2 Test-Logic-Reset

logic when the part is in normal mode of operation. TRST or forcing TMS High for 5 TCK periods.

16.1.3 Run-Test-Idle

The run-test-idle state is used to run tests.

16.1.4 Select-DR-Scan

This is a temporary controller state.

16.1.5 Capture-DR

16.1.6 Shift-DR

16.1.7 Exit1-DR

Figure 14. Test Access Port Architecture

16.1.8 Pause-DR

16.1.9 Exit2-DR

16.1.10 Update-DR

latched parallel output changes only in this state.

16.1.11 Select-IR-Scan

16.1.12 Capture-IR

level serial test data path.

16.1.13 Shift-IR

output on each rising edge of TCK. Figure 15. TAP Controller State Diagram

16.1.14 Exit1-IR

16.1.15 Pause-IR

16.1.16 Exit2-IR

16.1.17 Update-IR

16.2 Instruction Register (IR)

performed and/or the data register to be accessed.

16.2.1 EXTEST

connects the BSR to the TDI and TDO pins.

16.2.2 SAMPLE/PRELOAD

16.2.3 IDCODE

16.2.4 BYPASS

is used to bypass the device. Table 13. JTAG Instructions

16.3 Device ID Register (IDR)

from the last three digits of the part number (880). The LSB is a constant 1, as defined by IEEE 1149.1.

1. BOUNDARY SCAN REGISTER (BSR)

pin to scan cell mapping is given in the Boundary Scan Register description shown in Table 14. NOTE: Data is shifted LSB first into the BSR register. Table 14. Boundary Scan Register

Table 14. Boundary Scan Register (Continued)

the input values driven to these LOOP[7:0] can be read via LPI[7:0]. Low, the outputs are placed in a high impedance state (High-Z).

Figure 16. Internal RX/TX Impedance Matching 2) Common decoupling capacitor for all TVCC and TGND pins.

Figure 17. Internal TX, External RX Impedance Matching 2)Common decoupling capacitor for all TVCC and TGND pins.

18.1 Transformer Specifications

18.2 Crystal Oscillator Specifications

18.3 Line Protection

ondary Line Protection for T1 and E1 Cards. Table 15. Transformer Specifications

16 V - µs min

1. CHARACTERISTICS AND SPECIFICATIONS

19.1 Absolute Maximum Ratings

CAUTION: Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.

19.2 Recommended Operating Conditions

Notes: Human Body Model Transient current of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. Power consumption while driving line load over the full operating temperature and power supply voltage range. Includes all IC channels and loads. Digital inputs are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. Typical consumption corresponds to 50% ones density for at 3.3 V. Maximum consumption corresponds to 100% ones density at 3.465 V. This specification guarantees TTL compatibility (VOH = 2.4 V @ IOUT = -400 µA). Output drivers are TTL compatible. Pulse amplitude measured at the output of the transformer across a 75 Ω load. Pulse amplitude measured at the output of the transformer across a 120 Ω load. Parameter Symbol Min. Max Units DC Supply (referenced to RGND = TGND = 0V) RV+ TV+ 4.0 4.0 V V DC Supply VCCIO -0.5 4.6 V Input Voltage, Any Digital Pin except CBLSEL, MODE and LOOP(n) pins (referenced to GNDIO = 0V) VIH GNDIO -0.5 5.3 V Input Voltage CBLSEL, MODE & LOOP(n) Pins (referenced to GNDIO = 0V) VIH GNDIO -0.5 VCCIO +0.5 V Input voltage, RTIP and RRING Pins TGND -0.5 TV+ +0.5 V ESD voltage, Any pin Note 1 V Input current, Any Pin Note 2 IIH -10 +10 mA Maximum Power Dissipation, In package Pp 1.73 W Ambient Operating Temperature TA -40 C Storage Temperature Tstg -65 150 C Parameter Symbol Min. Typ Max Units DC Supply RV+, TV+ 3.135 3.3 3.465 V DC Supply VCCIO 3.135 3.3 3.465 V Ambient operating Temperature TA -40 C Power Consumption, E1 Mode, 75 Ω line load Notes 3, 4, 5 660 1040 mW Power Consumption, E1 Mode, 120 Ω line load Notes 3, 4, 5 640 950 mW

19.3 Digital Characteristics

(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)

19.4 Transmitter Analog Characteristics

(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V) Parameter Symbol Min. Typ Max Units High-Level Input Voltage Note 6 VIH 2.0 V Low-Level Input Voltage Note 6 VIL 0.8 V LOOP[7:0] Low-Level Input Voltage VIHL 1/3 VCCIO-0.2 V LOOP[7:0] Mid-Level Input Voltage VIHM 1/3 VCCIO +0.2 1/2 VCCIO 2/3 VCCIO-0.2 V LOOP[7:0] High-Level Input Voltage VIHH 2/3 VCCIO +0.2 V High-Level Output Voltage Notes 6, 7 IOUT = -400 µA VOH 2.4 V Low-Level Output Voltage Notes 6, 7 IOUT = 1.6 mA VOL 0.4 V Input Leakage Current -10 +10 µA Input leakage for LOOP pins -150 +150 µA Parameter Min. Typ Max Units Output Pulse Amplitudes E1 75 Ω Notes 8, 9, 11 E1 120 Ω 2.14 2.7 2.37 3.0 2.6 3.3 V V Ratio of Positive to Negative pulses Notes 8, 9, 11 Amplitude at center of pulse interval Width at 50% of nominal amplitude 0.95 0.95 1.05 1.05 Pulse Amplitude of a space E1 120 Ω E1 75 Ω -0.3 -0.237 0.3 0.237 V V Transmit Return Loss 51 kHz to 102 kHz 102 kH to 2048 kHz Notes 10, 11, 12 2048 kHz to 3072 kHz -14 -14 -14 -20 -19 -18 dB Jitter Added by the Transmitter

10 Hz - 8 kHz

Notes 10, 13

10 Hz - 40 kHz

0.010 0.009 0.007 0.015 0.020 0.025 0.025 0.050 UI Transmitter Short Circuit Current per channel mA RMS

19.5 Receiver Analog Characteristics

(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)) Notes: 10. Parameters guaranteed by design and characterization. 11. Using components on the CDB61880 evaluation board in Internal Match Impedance Mode. 12. Return loss = 20log10 ABS((Z1 + Z0) / (Z1 - Z0)) where Z1 - impedance of the transmitter or receiver, and Z0 = cable impedance. 13. Assuming that jitter free clock is input to TCLK. 14. Jitter tolerance for 6 dB input signal levels. Jitter tolerance increases at lower frequencies. HDB3 coders enabled. 15. In Data Recovery Mode. 16. Jitter Attenuator in the receive path. Parameter Min. Typ Max Units Allowable Cable Attenuation @ 1024 kHz - 12 dB RTIP/RRING Input Impedance E1 120 Ω Load (Internal Line matching mode) E1 75 Ω Load Note 10 13k Ω RTIP/RRING Input Impedance E1 120 Ω Load (External Line matching mode) E1 75 Ω Load Note 10 13k 13k Ω Receiver Dynamic Range 0.5 Vp Signal to Noise margin (Per G.703, O151 @ 6 dB cable Atten). -18 dB Receiver Squelch Level 150 mV LOS Threshold 200 mV LOS Hysteresis mV Data Decision Threshold Note 10 % of peak Input Jitter Tolerance 1 Hz - 1.8 Hz Notes 10, 14, 16 20 Hz - 2.4 kHz 18 kHz - 100 kHz 1.5 0.2 UI Input Return Loss 51 kHz - 102 kHz 102 kHz - 2048 kHz Notes 10, 11, 12 2048 kHz - 3072 kHz -18 -18 -18 -28 -30 -27 dB

19.6 Jitter Attenuator Characteristics

when more than 28 UI’s are input to the attenuator. Measurement is not effected by the position of the Jitter Attenuator.

3 Hz to 40 Hz

400 Hz to 100 kHz

Figure 18. Jitter Transfer Characteristic vs. G.736 & TBR 12/13

Figure 19. Jitter Tolerance Characteristic vs. G.823

19.7 Master Clock Switching Characteristics

19.8 Transmit Switching Characteristics

19.9 Receive Switching Characteristics

Notes: 19. Output load capacitance = 50 pF. 20. MCLK is not active. Parameter Symbol Min. Typ Max Units MASTER CLOCK (MCLK) Master Clock Frequency MCLK 2.048 MHz Master Clock Tolerance -100 +100 ppm Master Clock Duty Cycle Parameter Symbol Min. Typ Max Units TCLK Frequency 1/tpw2 2.048 MHz TPOS/TNEG Pulse Width (RZ Mode) 236 244 252 ns TCLK Tolerance (NRZ Mode) -50 PPM TCLK Duty Cycle tpwh2/tpw2 TCLK Pulse Width ns TCLK Burst Rate Note 10 MHz TPOS/TNEG to TCLK Falling Setup Time (NRZ Mode) tsu2 ns TCLK Falling to TPOS/TNEG Hold time (NRZ Mode) th2 ns TXOE Asserted Low to TX Driver HIGH-Z µs TCLK Held Low to Driver HIGH-Z Note 20 µs Parameter Symbol Min. Typ Max Units RCLK Duty Cycle Note 10 RCLK Pulse Width Note 10 196 244 328 ns RPOS/RNEG Pulse Width (RZ Mode) Note 10 200 244 300 ns RPOS/RNEG to RCLK rising setup time Note 10 tsu 200 244 ns RPOS/RNEG to RCLK hold time Note 10 th 200 244 ns RPOS/RNEG Output to RCLK Output (RZ Mode) Note 10 ns Rise/Fall Time, RPOS, RNEG, RCLK, LOS outputs Note 19 tr, tf ns

19.10 Switching Characteristics - Serial Port

Figure 23. Serial Port Read Timing Diagram Figure 24. Serial Port Write Timing Diagram

19.11 Switching Characteristics - Parallel Port (Multiplexed Mode)

Ref. # Min. Typ. Max Unit Pulse Width AS or ALE High ns Muxed Address Setup Time to AS or ALE Low ns Muxed Address Hold Time ns Delay Time AS or ALE to WR, RD or DS ns CS & R/W Setup Time Before WR, RD or DS Low ns CS & R/W Hold Time ns Pulse Width, WR, RD, or DS ns Write Data Setup Time ns Write Data Hold Time ns Output Data Delay Time from RD or DS Low 100 ns Read Data Hold Time ns Delay Time WR, RD, or DS to ALE or AS Rise ns WR or RD Low to RDY Low ns WR or RD Low to RDY High 100 ns WR or RD High to RDY HIGH-Z ns DS Low to ACK High ns DS Low to ACK Low 100 ns DS High to ACK HIGH-Z ns

19.12 Switching Characteristics- Parallel Port (Non-Multiplexed Mode)

Ref. # Min. Typ. Max Unit Address Setup Time to WR, RD or DS Low ns Address Hold Time ns CS & R/W Setup Time Before WR, RD or DS Low ns CS & R/W Hold Time ns Pulse Width, WR, RD, or DS ns Write Data Setup Time ns Write Data Hold Time ns Output Data Delay Time from RD or DS 100 ns Read Data Hold Time ns WR or RD Low to RDY Low ns WR, RD or DS Low to RDY High 100 ns WR, RD or DS High to RDY HIGH-Z ns DS Low to ACK High ns DS Low to ACK Low 100 ns DS High to ACK HIGH-Z ns

19.13 Switching Characteristics - JTAG

Figure 33. JTAG Switching Characteristics

1. COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS ETSI ETS 300-011 ETSI ETS 300-166 ETSI ETS 300-233 ETSI TBR 12/13 IEEE 1149.1 ITU-T I.431 ITU-T G.703 ITU-T G.704 ITU-T G.706 ITU-T G.732 ITU-T G.735 ITU-T G.736 ITU-T G.742 ITU-T G.772 ITU-T G.775 ITU-T G.783 ITU-T G.823 ITU-T O.151 OFTEL OTR-001

1. 160-BALL FBGA PACKAGE DIMENSIONS

Figure 34. 160-Ball FBGA Package Drawing

1. 144-PIN LQFP PACKAGE DIMENSIONS

Table 16. 144-Pin Package Dimensions

0.866 BSC

22.0 BSC

0.787 BSC

20.0 BSC

0.50 BSC

Figure 35. 144-Pin LQFP Package Drawing