CS61577

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Technical content

&EATURES

• Provides Analog Transmission Line Interface for T1 and E1 Applications
• Drop-in Replacement for CS61574 with the Following Enhancements: - Lower Power Consumption - Transmitter Short-Circuit Current Limiting - Greater Transmitter Immunity to Line Reflections - Software Selection Between 75 Ω and 120Ω E1 Output Options - Internally Controlled E1 Pulse Width - B8ZS/HDB3/AMI Encoder/Decoder 'ENERAL$ESCRIPTION The CS61577 is a drop-in replacement for the CS61574, and combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. The CS61577 supports processor-based or stand- alone operation and interfaces with industry standard T1 and E1 framers. The receiver uses a digital Delay-Locked-Loop which is continuously calibrated from a crystal reference to pro- vide excellent stability and jitter tolerance. The receiver includes a jitter attenuator optimized for minimum delay in switching and transmission applications. The trans- mitter provides internal pulse shaping to insure compliance with T1 and E1 pulse template specifica- tions. !PPLICATIONS
• Interfacing Network Equipment such as DACS and Channel Banks to a DSX-1 Cross Connect
• Building Channel Service Units CS61577-IL1Z 2 8-pin PLCC, Lead Free CS61577-IL1Z 28-pin P LCC MAY ’96 DS155PP2 #RYSTAL3EMICONDUCTOR#ORPORATION P. O. Box 17847, Austin, Texas, 78760 (512) 445-7222 FAX:(512) 445-7581 4%,INE)NTERFACE TTIP TCLK

7 RRING

(SCLK) 25 24 (INT) LEN0 (SDI) LEN1 (SDO) LEN2 28 23 (CLKE) TAOS MODE TPOS [TDATA] RPOS [RDATA] RNEG [BPV] TNEG [TCODE] MTIP [RCODE] DPM [AIS] LOS 12 21 RV+ RGND MRING [PCS] XTALIN XTALOUT ACLKI ( ) = Pin Function in (OST-ODE [ ] = Pin Function in %XTENDED(ARDWARE-ODE RLOOP (CS) R E M O T E L O O P B A C K AMI, B8ZS, HDB3, CODER JITTER ATTENUATOR PULSE SHAPER CLOCK & DATA RECOVERY SIGNAL QUALITY MONITOR DRIVER MONITOR TV+ L O C A L L O O P B A C K Copyright © Crystal Semiconductor Corporation 1996 (All Rights Reserved) This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice.Preliminary Product Information Copyright /g164 Cirrus Logic, Inc. 200/g28 (All Rights Reserved)http://www.cirrus.com CS61577 T1/E1 Line Interface DS155F/g21

0ARAMETER 3YMBOL -IN -AX 5NITS DC Supply (referenced to RGND=TGND=0V) RV+ TV+ 6.0 (RV+) + 0.3 V V Input Voltage, Any Pin (Note 1) V in RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) I in -10 10 mA Ambient Operating Temperature TA -40 85 °C Storage Temperature Tstg -65 150 °C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. 0ARAMETER 3YMBOL -IN 4YP -AX 5NITS DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature TA -40 25 85 °C Power Consumption (Notes 4,5) P C -4 0 0 5 0 0 m W Power Consumption (Notes 4,6) P C -2 3 0- m W Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 5. Assumes 100% ones density and maximum line length at 5.25V. 6. Assumes 50% ones density and 300ft. line length at 5.0V. 0ARAMETER 3YMBOL -IN 4YP -AX 5NITS High-Level Input Voltage (Notes 7, 8) PINS 1-4, 17, 18, 23-28 VIH 2.0 - - V Low-Level Input Voltage (Notes 7, 8) PINS 1-4, 17, 18, 23-28 VIL -- 0 . 8 V High-Level Output Voltage (Notes 7, 8, 9) IOUT = -40 μA PINS 6-8, 11, 12, 25 VOH 4.0 - - V Low-Level Output Voltage (Notes 7, 8, 9) IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 VOL -- 0 . 4 V Input Leakage Current (Except Pin 5) - - ±10 μA Low-Level Input Voltage, PIN 5 V IL -- 0 . 2 V High-Level Input Voltage, PIN 5 V IH (RV+) - 0.2 - - V Mid-Level Input Voltage, PIN 5 (Note 10) V IM 2.3 - 2.7 V Notes: 7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output. 8. This specification guarantees TTL compatibility (VOH = 2.4V @ I OUT = -40μA). 9. Output drivers will drive CMOS logic levels into a CMOS load. 10. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating. $300 CS61577

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0ARAMETER -IN 4YP -AX 5NITS 4RANSMITTER AMI Output Pulse Amplitudes (Note 11) E1, 75 Ω (Note 12) E1, 120 Ω (Note 13) T1, (FCC Part 68) (Note 14) T1, DSX-1 (Note 15) 2.14 2.7 2.7 2.4 2.37 3.0 3.0 3.0 2.6 3.3 3.3 3.6 V V V V Load Presented To Transmitter Output (Note 11) - 25 - Ω Jitter Added During Remote Loopback (Note 16) 10Hz - 8kHz 8kHz - 40kHz 10Hz - 40kHz Broad Band 0.005 0.008 0.010 0.015 UI UI UI UI Power in 2kHz band about 772kHz (Notes 11, 17) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 11, 17) (referenced to power in 2kHz band at 772kHz) -29 -38 - dB Positive to Negative Pulse Imbalance (Notes 11, 17) - 0.2 0.5 dB Transmitter Output Impedance (Notes 17, 18) - - 10 Ω Transmitter Short Circuit Current (Notes 11, 19) - - 50 mA RMS Notes: 11. Using a 0.47 μF capacitor in series with the primary of a transformer recommended in the Applications Section. 12. Pulse amplitude measured at the output of the transformer across a 75 Ω load for line length settings LEN2/1/0 = 0/0/1 and 0/0/0. For LEN2/1/0 = 0/0/0 only, a 4.4 Ω resistor is required in series with the transformer primary. 13. Pulse amplitude measured at the output of the transformer across a 120 Ω load for line length setting LEN2/1/0 = 0/0/0. 14. Pulse amplitude measured at the output of the transformer across a 100 Ω load for line length setting LEN2/1/0 = 0/1/0. 15. Pulse amplitude measured at the DSX-1 Cross-Connect for all line length settings from 16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 17. Not production tested. Parameters guaranteed by design and characterization. 18. Measured between the TTIP and TRING pins at 772 kHz during marks and spaces. 19. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern with LEN2/1/0 = 0/0/0 or 0/0/1. $300 CS61577 DS155F/g21 3

0ARAMETER -IN 4YP -AX 5NITS 2ECEIVER RTIP/RRING Input Impedance - 50k - Ω Sensitivity Below DSX (0dB = 2.4V) -13.6 500 dB mV Loss of Signal Threshold - 0.30 - V Data Decision Threshold T1, DSX-1 (Note 20) T1, DSX-1 (Note 21) T1, (FCC Part 68) and E1 (Note 22) % of peak % of peak % of peak Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 23) 10kHz - 100kHz 2kHz 10Hz and below 0.4 6.0 300 UI UI UI *ITTER!TTENUATOR Jitter Attenuation Curve Corner Frequency (Notes 17, 24) - 6 - Hz Attenuation at 10kHz Jitter Frequency (Notes 17, 24) - 50 - dB Attenuator Input Jitter Tolerance (Before Onset of FIFO Overflow or Underflow Protection) (Notes 17, 24) 12 23 - UI Notes: 20. For input amplitude of 1.2 V pk to 4.14 Vpk. 22. For input amplitude of 1.05 V pk to 3.3 Vpk. 23. Jitter tolerance increases at lower frequencies. See Figure 11. 24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase significantly when more than 12 UI’s are input to the attenuator. See discussion in the text section. $300 CS61577

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GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) 0ARAMETER 3YMBOL -IN 4YP -AX 5NITS Crystal Frequency (Note 25) f c - 8.192000 - MHz TCLK Frequency f tclk -2 . 0 4 8- M H z TCLK Duty Cycle for LEN2/1/0 = 0/0/0 (Note 32) t pwh2/tpw2 40 50 60 % ACLKI Frequency (Note 26) f aclki -2 . 0 4 8- M H z RCLK Duty Cycle (Note 27) t pwh1/tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 28) t r - - 85 ns Fall Time, All Digital Outputs (Note 28) t f - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time t su2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time t h2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 29) t su1 100 194 - ns RDATA Valid Before RCLK Falling (Note 30) t su1 100 194 - ns RPOS/RNEG Valid Before RCLK Rising (Note 31) t su1 100 194 - ns RPOS/RNEG Valid After RCLK Falling (Note 29) t h1 100 194 - ns RDATA Valid After RCLK Falling (Note 30) t h1 100 194 - ns RPOS/RNEG Valid After RCLK Rising (Note 31) t h1 100 194 - ns GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) 0ARAMETER 3YMBOL -IN 4YP -AX 5NITS Crystal Frequency (Note 25) f c - 6.176000 - MHz TCLK Frequency f tclk -1 . 5 4 4- M H z ACLKI Frequency (Note 26) f aclki -1 . 5 4 4- M H z RCLK Duty Cycle (Note 27) t pwh1/tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 28) t r - - 85 ns Fall Time, All Digital Outputs (Note 28) t f - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time t su2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time t h2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 29) t su1 150 274 - ns RDATA Valid Before RCLK Falling (Note 30) t su1 150 274 - ns RPOS/RNEG Valid Before RCLK Rising (Note 31) t su1 150 274 - ns RPOS/RNEG Valid After RCLK Falling (Note 29) t h1 150 274 - ns RDATA Valid After RCLK Falling (Note 30) t h1 150 274 - ns RPOS/RNEG Valid After RCLK Rising (Note 31) t h1 150 274 - ns Notes: 25. Crystal must meet specifications described in Appendix A . 26. ACLKI provided by an external source or TCLK. 27. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 28. At max load of 1.6 mA and 50 pF. 29. Host Mode (CLKE = 1). 30. Extended Hardware Mode. 31. Hardware Mode, or Host Mode (CLKE = 0) 32. The transmitted pulse width does not depend on the TCLK duty cycle. $300 CS61577 DS155F/g21 5

Figure 1. Signal Rise and Fall Characteristics Figure 2. Recovered Clock and Data Switching Characteristics

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component or system software.

• Selection of 75 Ω or 120 Ω E1 output op- tions under software or hardware control,
• 50 mA RMS transmitter short-circuit current limiting for E1 (per OFTEL OTR-001),
• internally controlled pulse width for E1 output options,
• 35% lower power consumption,
• Increased transmitter immunity to signal re- flections for improved signal quality,
• Optional AMI, B8ZS, HDB3 encoder/de- coder or external line coding support,
• Receiver AIS (unframed all ones) detection,
• Improved receiver Loss of Signal handling (LOS set at power-up, reset upon receipt of 3 ones in 32 bit periods with no more than 15 consecutive zeros),
• Transmitter TTIP and TRING outputs are forced low when TCLK is static,
• The Driver Performance Monitor operates over a wider range of input signal levels. Introduction to Operating Modes The CS61577 supports three operating modes which are selected by the level of the MODE pin as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. The modes are Hardware Mode, Extended Hard- ware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Ex- tended Hardware Mode provides a parallel chip select input which latches the control inputs al- lowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the device through a serial interface. There are thir- teen multi-function pins whose functionality is determined by the operating mode. (see Table 2). Hardware Mode Extended Hardware Mode Host Mode Control Method Control Pins Control Pins with Parallel Chip Select Serial Interface MODE Pin Level <0.2 V Floating or 2.5 V >(RV+)-0.2 V Line Coding External Internal- AMI, B8ZS, or HDB3 External AIS Detection No Yes No Driver Performance Monitor Yes No Yes

Table 1. Differences Between Operating Modes

6 RNEG BPV RNEG

11 DPM AIS DPM

17 MTIP

18 MRING - MRING

23 LEN0 LEN0 INT

24 LEN1 LEN1 SDI

25 LEN2 LEN2 SDO

26 RLOOP RLOOP

27 LLOOP LLOOP SCLK

28 TAO S TAOS C L KE

Table 2. Pin Definitions

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Figure 7. Overview of Operating Modes

on the falling edge of the input clock, TCLK. CCITT G.703 pulse shapes may be selected. "line length select" inputs as shown in Table 3. based upon the "line length" selection made. in Figure 9, and specified in Table 4. must adjust to the new frequency. Figure 8. Typical Pulse Shape at DSX-1 Cross Connect Table 3. Line Length Selection

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o r A L B O ( A u t o m a t i c L i n e B u i l d O u t ) c i r c u i t s . Figure 9. Mask of the Pulse at the 2048 kbps Interface primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications

appropriate intervals to recover the data. pede analog circuit performance. data should be sampled as shown in Table 5. Figure 11. Minimum Input Jitter Tolerance of Receiver Figure 10. Receiver Block Diagram

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periods with no more than 15 consecutive zeros. ously available from both the register and pin 12. recovered clock and the ACLKI reference clock. Publications 43802 and REC. G.742. transfer characteristic shown in Figure 12. Table 6. RCLK Status at LOS Table 5. Data Output/Clock Relationship

flow. During this activity, data will never be lost. ous ones are transmitted at the TCLK frequency. when local loopback is in effect. curs in response to RLOOP going high.

62411 Requirements

Figure 12. Typical Jitter Transfer Function

00 T D A T A T C L K

1 X RTIP & RRING RTIP & RRING (RCLK)

1. Logic 1 indicates that Loopback or All Ones

Table 7. Interaction of RLOOP with TAOS

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back modes is not valid (see Reset). are detected out of 2048 bit periods. RCODE pins as shown in Table 8. ance or the performance of a neighboring driver. DPM is available from the register and pin 11. Table 8. Encoder/Decoder Selection

system transmit and receive timing. CS, low ( CS must initially be high). SCLK cycle corresponding to the last write bit. the hold period of data bit D7. 16 (0010000). The last bit is ignored.

00 D7D6D5D4D3D2D1D0

Figure 13. Input/Output Timing

1 ADD0 LSB of address, Must be 0

2 ADD1 Must be 0

3 ADD2 Must be 0

4 ADD3 Must be 0

5 ADD4 Must be 1

Table 9. Address/Command Byte

2 LEN0 Bit 0 - Line Length Select

3 LEN1 Bit 1 - Line Length Select

4 LEN2 Bit 2 - Line Lenght Select

5 RLOOP Remote Loopback

6 LLOOP Local Loopback

Table 10. Input Data Register

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or DPM will be prevented from occurring. selected via the serial interface. signal and/or driver problems. clock for the transmitter is provided by TCLK. available which will clear all registers.

1 DPM Driver Performance Monitor

Table 11. Output Data Bits 0 - 4 0 0 0 Reset has occurred or no program input. 0 1 1 T AOS/LLOOP in effect. last "clear LOS" and "clear DPM". Table 12. Coding for Serial Output bits 5,6,7

the register. In either mode, a reset will set all reg- isters to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Power Supply The device operates from a single +5 V olt supply. Separate pins for transmit and receive supplies provide internal isolation. These pins should be connected externally near the device and decou- pled to their respective grounds. TV+ must not exceed RV+ by more than 0.3V . Decoupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits in both the transmit and receive paths. A 1.0 μF capacitor should be connected between TV+ and TGND, and a 0.1 μF capacitor should be con- nected between RV+ and RGND. Use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. A 68 μF tantalum capacitor should be added close to the RV+/RGND supply. Wire-wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. 3CHEMATIC,AYOUT2EVIEW3ERVICE Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. #ALL $300 CS61577

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/g40/g91/g87/g72/g81/g71/g72/g71/g3/g43/g68/g85/g71/g90/g68/g85/g72/g3/g48/g82/g71/g72 top view 2532 7242 6 281 12 14 16 1813 15 17 !#,+) 4#,+ 4!/3 40/3 ,,//0 4.%' 2,//0 -/$% ,%. 2.%' ,%. 20/3 ,%. 2#,+ 2'.$ 84!,). 26 84!,/54 22).' $0- 24)0 ,/3 -2).' 44)0 -4)0 4'.$ 42).' $300 /g43/g82/g86/g87/g3/g48/g82/g71/g72 top view 2532 7242 6 281 12 14 16 1813 15 17 !#,+) 4#,+ #,+% 40/3 3#,+ 4.%' #3 -/$% 3$/ 2.%' 3$) 20/3 ).4 2#,+ 2'.$ 84!,). 26 84!,/54 22).' $0- 24)0 ,/3 -2).' 44)0 -4)0 4'.$ 42).' CS61577 DS155F/g21 19

RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 V olts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 V olts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 V olts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 V olts. TV+ must not exceed RV+ by more than 0.3 V . Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or

2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying

XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10. Overdriving the oscillator with an external clock is not supported./g3/g54/g72/g72/g3/g36/g83/g83/g72/g81/g71/g76/g91/g3/g36/g17 Control ACLKI - Alternate External Clock Input, Pin 1. A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground. During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. $300 CS61577

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LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. Also controls the receiver slicing level and the line code in Extended Hardware Mode. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial control port is used to control the line interface and determine its status. Grounding the MODE pin puts the line interface in the Hardware Mode , where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 Vselects the Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. In the Host Mode, simultaneous selection of RLOOP & TAOS enables a factory test mode. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Data for the on-chip register. Sampled on the rising edge of SCLK. SDO - Serial Data Output, Pin 25. (Host Mode) Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. $300 CS61577 DS155F/g21 21

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. In the Host Mode, simultaneous selection of RLOOP & TAOS enables a factory test mode. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK. RCLK - Recovered Clock, Pin 8. The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator.. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data and clock are recovered and output on RCLK and RPOS/RNEG or RDTA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDA TA - Transmit Data, Pin 3. (Extended Hardware Mode) Transmitter NRZ input data which passes through the line code encoder, and is then driven on to the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. $300 CS61577

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TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 25 Ω load between TTIP and TRING. A transformer is required as shown in Table A1. Status AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones are received within 32 bit periods with no more than 15 consecutive zeros. When in the loss of signal state RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor. $300 CS61577 DS155F/g21 23

D D2/E2 PIN0,## -!8-). -!8-). -),,)-%4%23 ).#(%3 $)- ! 4.574.20 0.180 0.165 $% 12.32 12.57 0.485 0.495 " 0.530.33 0.021 0.013 E AA1 B e 2.29 0.090 11.43 11.58 0.450 0.456 9.91 10.92 0.390 0.430 1.19 1.35 0.047 0.053 ./- 4.45 12.45 0.41 2.79 11.51 10.41 1.27 ./- 0.175 0.490 0.016 0.110 0.453 0.410 0.050 3.04 0.120 $300 CS61577

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APPLICATIONS

Figures A1-A3 show typical T1 and E1 line inter- face application circuits. Table A1 shows the external components which are specific to each application. Figure A1 illustrates a T1 interface in the Host Mode. Figure A2 illustrates a 120 Ω E1 interface in the Hardware Mode. Figure A3 illus- trates a 75 Ω E1 interface in the Extended Hardware Mode. The 1:2 receiver transformer has a grounded cen- ter tap on the IC side. Resistors R1 and R2 between the RTIP and RRING pins to ground provide the termination for the receive line. The transmitter also uses a 1:2 transformer. A 0.47 μF capacitor is required in series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting in a DC current through the transformer primary. This current might saturate the transformer pro- ducing an output offset level shift. Control Monitor Frame Format Encoder/ Decoder (/34 -/$% RECEIVE LINE TRANSMIT LINE XTL RV+ + 68 μF RGND 0.1 μF +5V 21 15 + 1.0 μF TGND RV+ TV+CLKE ACLKI LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND 22 14 SCLK CS INT SDI SDO RTIP RRING MTIP MRING TRING TTIP 0.47 μF 1:2CT PE-65351 2CT:1 PE-65351 μP Serial Port +5V 100 kΩ Figure A1. T1 Host Mode Configuration Frequency MHz Crystal XTL Cable Ω LEN2/1/0 R3 Ω R1 and R2 Ω 1.544 (T1) 6.176 MHz 100 0/1/1 - 1/1/1 not used 20 0 2.048 (E1) 8.192 MHz 120 0/0/0 not used 240 75 0/0/0 4.4 150 0/0/1 not used Table A1. External Component Values $300 CS61577 DS155F/g21 25

(!2$7!2% -/$% Line Length Setting RECEIVE LINE TRANSMIT LINE 10XTL + 68 μF RGND 0.1 μF +5V 21 15 + 1.0 μF TGND RV+ TV+TAOS ACLKI RLOOP LLOOP MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND 22 14 LEN0 LEN1 LEN2 RTIP RRING MTIP MRING TRING TTIP 0.47 μF 1:2CT PE-65351 2CT:1 PE-65351 LOS DPM Figure A2. 120 Ω, E1 Hardware Mode Configuration Control Monitor Frame Format Encoder/ Decoder %84%.$%$ (!2$7!2% -/$% Line Length Setting RECEIVE LINE TRANSMIT LINE 10XTL + 68 μF RGND 0.1 μF +5V 21 15 + 1.0 μF TGND RV+ TV+RCODE PCS BPV TAOS MODE RDATA RCLK TDATA TCLK XTALIN XTALOUT RGND TGND 22 14 LEN0 LEN1 LEN2 RTIP RRING TRING TTIP 0.47 μF 1:2CT PE-65351 2CT:1 PE-65351 ACLKI RLOOP LLOOP LOS

11 AIS

4 TCODE

.OTE R3 is used for LEN2/1/0 = 0/0/0, but not required with LEN2/1/0 = 0/0/1. Figure A3. 75 Ω, E1 Extended Hardware Mode Configuration $300 CS61577

26 DS155F/g21

Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with the CS61577. Refer to the "Telecom Transformer Selection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the jitter attenuator. It is rec- ommended that /g68/g3/g25/g17/g20/g26/g25/g3/g48/g43/g93/g3/g70/g85/g92/g86/g87/g68/g79/g3/g69/g72/g3/g88/g86/g72/g71 /g73/g82/g85/g3/g55/g20/g3/g68/g83/g83/g79/g76/g70/g68/g87/g76/g82/g81/g86/g3/g68/g81/g71/g3/g68/g81/g3/g27/g17/g20/g28/g21/g3/g48/g43/g93/g3/g70/g85/g92/g86/g87/g68/g79/g3/g69/g72 /g88/g86/g72/g71/g3/g73/g82/g85/g3/g40/g20/g3/g68/g83/g83/g79/g76/g70/g68/g87/g76/g82/g81/g86./g3/g54/g72/g72/g3/g36/g83/g83/g72/g81/g71/g76/g91/g3/g36/g17 Transmit Side Jitter Attenuation In some applications it is desirable to attenuate jitter from the signal to be transmitted. A CS61577 in local loopback mode can be used as a jitter attenuator. The inputs to the jitter attenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK. Line Protection Secondary protection components can be added to provide lightning surge and AC power-cross immunity. Refer to the "Telecom Line Protection Application Note" for detailed information on the different electrical safety standards and specific application circuit recommendations. Turns Ratio 1:2 CT ± 5% Primary Inductance 600 μH min. @ 772 kHz Primary Leakage Inductance 1.3 μH max. @ 772 kHz Secondary Leakage Inductance 0.4 μH max. @ 772 kHz Interwinding Capacitance 23 pF max. ET-constant 16 V-μs min. for T1 12 V-μs min. for E1 Table A2. Transformer Specifications Turns Ratio(s) Manufacturer Part Number Package Type 1:2CT Pulse Engineering PE-65351 1.5 kV through-hole, single Schott 67129300 Bel Fuse 0553-0013-HC dual 1:2CT Pulse Engineering PE-64951 1.5 kV through-hole, dual Bel Fuse 0553-0013-1J dual 1:2CT Pulse Engineering PE-65761 1.5 kVsurface-mount, dual Bel Fuse S553-0013-03 1:2CT Pulse Engineering PE-65835 3 kV through-hole, single EN60950, EN41003 approved Table A3. Recommended Transformers $300 CS61577 DS155F/g21 27

28 DS155F2

APPENDIX A. RECOMMENDED CRYSTAL SPECIFICATIONS Cirrus Logic telecommunication devices that offer jitter attenuation require crystals with specifications for frequency pullability. The crystal oscillation freque ncy is dictated by capaci tive loading, which is con- trolled by the chip. Therefore, the crystals must meet the following specifications.

6.176 MHz Crystal Performance Specifications

8.192 MHz Crystal Performance Specifications

Notes: 1. With C load varying from 11.6 to 37.0 pF at a given temperature. 2. Measured at -40 to 85°C. 3. Measured with Saunders 150D meter at 25 °C. Parameter Min Typ Max Units Total Frequency Range (Note 1) - 370 390 ppm Operating Frequency C load = 11.6 pF (Note 2) Cload = 19.0 pF (Note 3) Cload = 37.0 pF (Note 2) 6.176803 6.175846 6.176000 6.176154 6.175197 MHz MHz MHz Parameter Min Typ Max Units Total Frequency Range (Note 1) - 210 245 ppm Operating Frequency C load = 11.6 pF (Note 2) Cload = 19.0 pF (Note 3) Cload = 37.0 pF (Note 2) 8.192410 8.191795 8.192000 8.192205 8.191590 MHz MHz MHz

REVISION HISTORY

F Jul ’09 Removed devel opment system info. (No longer supported). Removed PDIP option. Changed PLCC package option to lead-free.

30 DS155F2

Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to http://www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the inf ormation contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRIT- ICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUD- ING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.