CS61574A-IL1

CS61574A CIRRUS | Alldatasheet

Document overview

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Technical content

Features

• Provides Analog Transmission Line Interface for T1 and E1 Applications
• Provides Line Driver, Jitter Attenuator and Clock Recovery Functions
• Fully Compliant with AT&T 62411 Stratum 4 Jitter Requirements
• Low Power Consumption (typically 175 mW)
• B8ZS/HDB3/AMI Encoder/Decoder
• 14 dB of Transmitter Return Loss General Description The CS61574A and CS61575 combine the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. Both devices support processor- based or stand-alone operation and interface with industry standard T1 and E1 framers. The receiver uses a digital Delay-Locked-Loop which is continuously calibrated from a crystal reference to pro- vide excellent stability and jitter tolerance. The CS61574A has a receiver jitter attenuator optimized for minimum delay in switching and transmission applica- tions, while the CS61575 attenuator is optimized for CPE applications subject to AT&T 62411 requirements. The transmitter features internal pulse shaping and a matched, constant impedance output stage to insure signal quality on mismatched, poorly terminated lines.

Applications

• Interfacing Network Equipment such as DACS and Channel Banks to a DSX-1 Cross Connect
• Interfacing Customer Premises Equipment to a CSU
• Building Channel Service Units ORDERING INFORMATION - See page 26. MAY ’96 DS154F2 Crystal Semiconductor Corporation P. O. Box 17847, Austin, Texas, 78760 (512) 445-7222 FAX:(512) 445-7581 T1/E1 Line Interface CS61574A CS61575 TTIP TCLK

7 RRING

(SCLK) 2524 (INT) LEN0 (SDI) LEN1 (SDO) LEN2 28 23 (CLKE) TAOS MODE TPOS [TDATA] RPOS [RDATA] RNEG [BPV] TNEG [TCODE] MTIP [RCODE] DPM [AIS] LOS 12 21 RV+ RGND MRING [PCS] XTALIN XTALOUT ACLKI ( ) = Pin Function in Host Mode [ ] = Pin Function in Extended Hardware Mode RLOOP (CS) R E M O T E L O O P B A C K AMI, B8ZS, HDB3, CODER JITTER ATTENUATOR PULSE SHAPER CLOCK & DATA RECOVERY SIGNAL QUALITY MONITOR DRIVER MONITOR TV+ L O C A L L O O P B A C K Copyright  Crystal Semiconductor Corporation 1996 (All Rights Reserved)

Parameter Symbol Min Max Units DC Supply (referenced to RGND, TGND=0V) RV+ TV+ 6.0 (RV+) + 0.3 V V Input Voltage, Any Pin (Note 1) V in RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) I in -10 10 mA Ambient Operating Temperature T A -40 85 °C Storage Temperature T stg -65 150 °C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature T A -40 25 85 °C Power Consumption (Notes 4,5) P C -2 9 0 3 5 0 m W Power Consumption (Notes 4,6) P C -1 7 5- m W Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 5. Assumes 100% ones density and maximum line length at 5.25V. 6. Assumes 50% ones density and 300ft. line length at 5.0V. DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Symbol Min Typ Max Units High-Level Input Voltage (Notes 7, 8) PINS 1-4, 17, 18, 23-28 VIH 2.0 - - V Low-Level Input Voltage (Notes 7, 8) PINS 1-4, 17, 18, 23-28 VIL -- 0 . 8 V High-Level Output Voltage (Notes 7, 8, 9) IOUT = -40 µA PINS 6-8, 11, 12, 25 VOH 4.0 - - V Low-Level Output Voltage (Notes 7, 8, 9) IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 VOL -- 0 . 4 V Input Leakage Current (Except Pin 5) - - ±10 µA Low-Level Input Voltage, PIN 5 V IL -- 0 . 2 V High-Level Input Voltage, PIN 5 V IH (RV+) - 0.2 - - V Mid-Level Input Voltage, PIN 5 (Note 10) V IM 2.3 - 2.7 V Notes: 7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output. 8. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40µA). 9. Output drivers will drive CMOS logic levels into a CMOS load. 10. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating. CS61574A CS61575

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ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Transmitter AMI Output Pulse Amplitudes (Note 11) E1, 75 Ω (Note 12) E1, 120 Ω (Note 13) T1, FCC Part 68 (Note 14) T1, DSX-1 (Note 15) 2.14 2.7 2.7 2.4 2.37 3.0 3.0 3.0 2.6 3.3 3.3 3.6 V V V V E1 Zero (space) level (LEN2/1/0 = 0/0/0) 1:1 transformer and 75Ω load 1:1.26 transformer and 120Ω load -0.237 -0.3 0.237 0.3 V V Recommended Output Load at TTIP and TRING - 75 - Ω Jitter Added During Remote Loopback (Note 16) 10Hz - 8kHz 8kHz - 40kHz 10Hz - 40kHz Broad Band 0.005 0.008 0.010 0.015 0.02 0.025 0.025 0.05 UI UI UI UI Power in 2kHz band about 772kHz (Notes 11, 17) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 11, 17) (referenced to power in 2kHz band at 772kHz) -29 -38 - dB Positive to Negative Pulse Imbalance (Notes 11, 17) T1, DSX-1 E1 amplitude at center of pulse E1 pulse width at 50% of nominal amplitude 0.2 0.5 dB Transmitter Return Loss (Notes 11, 17, 18) 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz dB dB dB Transmitter Short Circuit Current (Notes 11, 19) - - 50 mA RMS Driver Performance Monitor MTIP/MRING Sensitivity: Differential Voltage Required for Detection - 0.6 - V Notes: 11. Using a 0.47 µF capacitor in series with the primary of a transformer recommended in the Applications section. 12. Pulse amplitude measured at the output of a 1:1 or 1:1.26 transformer across a 75 Ω load for line length setting LEN2/1/0 = 0/0/0. 13. Pulse amplitude measured at the output of a 1:1.26 transformer across a 120 Ω load for line length setting LEN2/1/0 = 0/0/0. 14. Pulse amplitude measured at the output of a 1:1.15 transformer across a 100 Ω load for line length setting LEN2/1/0 = 0/1/0. 15. Pulse amplitude measured at the DSX-1 cross-connect across a 100 Ω load for line length settings LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0, or 1/1/1 using a 1:1.15 transformer and the length of #22 AWG, ABAM, or equivalent cable specified in Table 3. 16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 17. Not production tested. Parameters guaranteed by design and characterization. 18. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0 and a 1:1 transformer terminated with a 75Ω load, or a 1:1.26 transformer terminated with a 120Ω load. 19. Measured broadband through a 0.5 Ω resistor across the secondary of a 1:1.26 transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0. CS61574A CS61575 DS154F2 3

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Receiver RTIP/RRING Input Impedance - 50k - Ω Sensitivity Below DSX (0dB = 2.4V) -13.6 500 dB mV Data Decision Threshold T1, DSX-1 (Note 20) T1, DSX-1 (Note 21) T1, FCC Part 68 and E1 (Note 22) % of peak % of peak % of peak Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 23) 10kHz - 100kHz 2kHz 10Hz and below 0.4 6.0 300 UI UI UI Loss of Signal Threshold (Note 24) 0.25 0.30 0.50 V Notes: 20. For input amplitude of 1.2 V pk to 4.14 Vpk. 22. For input amplitude of 1.05 Vpk to 3.3 Vpk. 23. Jitter tolerance increases at lower frequencies. See Figure 11. 24. The analog input squelch circuit shall operate when the input signal amplitude above ground on the RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low. CS61574A CS61575

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ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Notes 17, 25) CS61574A CS61575 Hz Hz CS61574A T1 Receiver Jitter Transfer (Notes 25, 26) Jitter Freq. [Hz] Amplitude [UIpp] 10 10 100 10 500 10 1k 5 10k, 40k 0.3 3.0 6.0 dB dB dB dB dB CS61575 T1 Receiver Jitter Transfer (Notes 25, 26) Jitter Freq. [Hz] Amplitude [UIpp] 10 10 100 10 500 10 1k 5 10k, 40k 0.3 6.0 9.0 dB dB dB dB dB CS61574A E1 Receiver Jitter Transfer (Notes 26, 27, 28) Jitter Freq. [Hz] Amplitude [UIpp] 10 1.5 20 1.5 100 1.5 400 1.5 1k 1.5 10k, 100k 0.2 3.0 6.0 6.0 dB dB dB dB dB dB CS61575 E1 Receiver Jitter Transfer (Notes 26, 27, 28) Jitter Freq. [Hz] Amplitude [UIpp] 10 1.5 20 1.5 100 1.5 400 1.5 1k 1.5 10k, 100k 0.2 6.0 dB dB dB dB dB dB Attenuator Input Jitter Tolerance (Notes 17, 28) (Before Onset of FIFO Overflow or Underflow Protection) CS61574A CS61575 138 UI UI Notes: 25. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of measured jitter tolerance using a measurement bandwidth of 1 Hz (10<f<100Hz), 4Hz (100<f<1000 Hz) and 10 Hz (f> 1kHz) centered around the jitter frequency. With a 2 15-1 PRBS data pattern. 26. Crystal must meet specifications described in CXT6176/CXT8192 data sheet. 27. Jitter measured at the demodulator output of an HP3785A (or equivalent) using a measurement bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 215-1 PRBS data pattern. 28. Jitter below 100 kHz and within the attenuator’s input jitter tolerance is not translated or aliased to other frequencies. Output jitter increases significantly when attenuator input jitter tolerance is exceeded. CS61574A CS61575 DS154F2 5

E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 26) f c - 8.192000 - MHz TCLK Frequency f tclk -2 . 0 4 8- M H z TCLK Pulse Width (Note 29) t pwh2 150 - 340 ns ACLKI Duty Cycle t pwh3 /tpw3 40 - 60 % ACLKI Frequency (Note 30) f aclki -2 . 0 4 8- M H z RCLK Duty Cycle (Note 31) t pwh1 /tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 32) t r - - 85 ns Fall Time, All Digital Outputs (Note 32) t f - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time t su2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time t h2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 33) t su1 100 194 - ns RDATA Valid Before RCLK Falling (Note 34) t su1 100 194 - ns RPOS/RNEG Valid Before RCLK Rising (Note 35) t su1 100 194 - ns RPOS/RNEG Valid After RCLK Falling (Note 33) t h1 100 194 - ns RDATA Valid After RCLK Falling (Note 34) t h1 100 194 - ns RPOS/RNEG Valid After RCLK Rising (Note 35) t h1 100 194 - ns T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 26) f c - 6.176000 - MHz TCLK Frequency f tclk -1 . 5 4 4- M H z TCLK Pulse Width (Note 29) t pwh2 150 - 500 ns ACLKI Duty Cycle t pwh3 /tpw3 40 - 60 % ACLKI Frequency (Note 30) f aclki -1 . 5 4 4- M H z RCLK Duty Cycle (Note 31) t pwh1 /tpw1 45 50 55 % Rise Time, All Digital Outputs (Note 32) t r - - 85 ns Fall Time, All Digital Outputs (Note 32) t f - - 85 ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time t su2 25 - - ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time t h2 25 - - ns RPOS/RNEG Valid Before RCLK Falling (Note 33) t su1 150 274 - ns RDATA Valid Before RCLK Falling (Note 34) t su1 150 274 - ns RPOS/RNEG Valid Before RCLK Rising (Note 35) t su1 150 274 - ns RPOS/RNEG Valid After RCLK Falling (Note 33) t h1 150 274 - ns RDATA Valid After RCLK Falling (Note 34) t h1 150 274 - ns RPOS/RNEG Valid After RCLK Rising (Note 35) t h1 150 274 - ns Notes: 29. The transmitted pulse width does not depend on the TCLK duty cycle. 30. ACLKI provided by an external source or TCLK. 31. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 32. At max load of 1.6 mA and 50 pF. 33. Host Mode (CLKE = 1). 34. Extended Hardware Mode. 35. Hardware Mode, or Host Mode (CLKE = 0). CS61574A CS61575

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Figure 4. Serial Port Write Timing Diagram Figure 5. Serial Port Read Timing Diagram Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram

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• AT&T 62411, Stratum 4 compliant jitter at- tenuation over the full range of operating frequency and jitter amplitude (CS61575),
• 50% lower power consumption,
• Internally matched transmitter output im- pedance for improved signal quality,
• Optional AMI, B8ZS, HDB3 encoder/de- coder or external line coding support,
• Receiver AIS (unframed all ones) detection,
• ANSI T1.231-1993 compliant receiver LOS (Loss of Signal) handling,
• Transmitter TTIP and TRING outputs are forced low when TCLK is static,
• The Driver Performance Monitor operates over a wider range of input signal levels. Existing designs using the CS61574 can be con- verted to the higher performance, pin-compatible CS61574A or CS61575 if the transmit trans- former is replaced by a pin-compatible transformer with a new turns ratio. Understanding the Difference Between the CS61575 and CS61574A The CS61574A and CS61575 provide receiver jitter attenuation performance optimized for dif- ferent applications. The CS61575 is optimized to attenuate large amplitude, low frequency jitter for T1 Customer Premises Equipment (CPE) applica- tions as required by AT&T 62411. The CS61574A is optimized to minimize data delay in T1 and E1 switching or transmission applications. Refer to the "Jitter Attenuator" section for addi- tional information. Introduction to Operating Modes The CS61574A and CS61575 support three oper- ating modes which are selected by the level of the MODE pin as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. The modes are Hardware Mode, Extended Hard- ware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Ex- tended Hardware Mode provides a parallel chip select input which latches the control inputs al- lowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the device through a serial interface. There are thir- teen multi-function pins whose functionality is determined by the operating mode. (see Table 2). Hardware Mode Extended Hardware Mode Host Mode Control Method Control Pins Control Pins with Parallel Chip Select Serial Interface MODE Pin Level <0.2 V Floating or 2.5 V >(RV+)-0.2 V Line Coding External Internal- AMI, B8ZS, or HDB3 External AIS Detection No Yes No Driver Performance Monitor Yes No Yes

Table 1. Differences Between Operating Modes

Figure 7. Overview of Operating Modes

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CCITT G.703 pulse shapes may be selected. "line length select" inputs as shown in Table 3. signed to drive a 75 Ω equivalent load. are provided for T1 applications. Figure 8. Typical Pulse Shape at DSX-1 Cross Connect

6 RNEG BPV RNEG

11 DPM AIS DPM

17 MTIP

18 MRING - MRING

23 LEN0 LEN0 INT

24 LEN1 LEN1 SDI

25 LEN2 LEN2 SDO

26 RLOOP RLOOP

27 LLOOP LLOOP SCLK

Table 2. Pin Definitions Table 3. Line Length Selection

shown in Figure 9, and specified in Table 4. prevent transmission when data is not present. cuitry must adjust to the new frequency. o r A L B O ( A u t o m a t i c L i n e B u i l d O u t ) c i r c u i t s . Figure 9. Mask of the Pulse at the 2048 kbps Interface primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications

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data should be sampled as shown in Table 5. recovered clock and the ACLKI reference clock. quirements of Publications 43802 and REC. tude exceeds approximately 23 UIs. Table 6. RCLK Status at LOS Table 5. Data Output/Clock Relationship

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flow. During this activity, data will never be lost. jitter before it reaches the synchronizer. and E1 switching or transmission applications. formance comparable to the CS61574. ous ones are transmitted at the TCLK frequency. when local loopback is in effect.

62411 Requirements

Figure 12. Typical Jitter Transfer Function

ance or the performance of a neighboring driver. RCODE pins as shown in Table 8. Table 8. Encoder/Decoder Selection

00 T D A T A T C L K

1 X RTIP & RRING RTIP & RRING (RCLK)

1. Logic 1 indicates that Loopback or All Ones

Table 7. Interaction of RLOOP with TAOS

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In the Extended Hardware Mode, the receiver sets the output pin AIS high when less than 9 zeros are detected out of 8192 bit periods. AIS returns low when 9 or more zeros are detected out of 8192 bit periods. Parallel Chip Select In the Extended Hardware Mode, PCS can be used to gate the digital control inputs: TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS. Inputs are accepted on these pins only when PCS is low and will immediately change the operating state of the device. Therefore, when cycling PCS to update the operating state, the digital control inputs should be stable for the en- tire PCS low period. The digital control inputs are ignored when PCS is high. Power On Reset / Reset Upon power-up, the IC is held in a static state until the supply crosses a threshold of approxi- mately 3 V olts. When this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. After this delay, calibration of the delay lines used in the transmit and receive sections commences. The delay lines can be calibrated only if a reference clock is present. The reference clock for the re- ceiver is provided by the crystal oscillator, or ACLKI if the oscillator is disabled. The reference clock for the transmitter is provided by TCLK. The initial calibration should take less than 20 ms. In operation, the delay lines are continuously cali- brated, making the performance of the device independent of power supply or temperature vari- ations. The continuous calibration function forgoes any requirement to reset the line interface when in operation. However, a reset function is available which will clear all registers. In the Hardware and Extended Hardware Modes, a reset request is made by simultaneously setting both the RLOOP and LLOOP pins high for at least 200 ns. Reset will initiate on the falling edge of the reset request (falling edge of RLOOP and LLOOP). In the Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to the register. In either mode, a reset will set all reg- isters to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Serial Interface In the Host Mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. One on-board register can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through this register, a host controller can be used to control operational characteristics and monitor device status. The se- rial port read/write timing is independent of the system transmit and receive timing. Data transfers are initiated by taking the chip se- lect input, CS, low (CS must initially be high). Address and input data bits are clocked in on the rising edge of SCLK. The clock edge on which output data is stable and valid is determined by CLKE as shown in Table 5. Data transfers are ter- minated by setting CS high. CS may go high no sooner than 50 ns after the rising edge of the SCLK cycle corresponding to the last write bit. For a serial data read, CS may go high any time to terminate the output. Figure 13 shows the timing relationships for data transfers when CLKE = 1. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held until the rising edge of the 17th clock cycle. SDO goes High-Z after CS goes high or at the end of the hold period of data bit D7. CS61574A CS61575 DS154F2 17

16 (0010000). The last bit is ignored. or DPM will be prevented from occurring.

2 LEN0 Bit 0 - Line Length Select

3 LEN1 Bit 1 - Line Length Select

4 LEN2 Bit 2 - Line Length Select

5 RLOOP Remote Loopback

6 LLOOP Local Loopback

7 T AOS T ransmit All Ones Select

Table 10. Input Data Register

00 D7D6D5D4D3D2D1D0

Figure 13. Input/Output Timing Table 11. Output Data Bits 0 - 4

1 ADDP LSB of address, Must be 0

2 ADD1 Must be 0

3 ADD2 Must be 0

4 ADD3 Must be 0

5 ADD4 Must be 1

Table 9. Address/Command Byte

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The device operates from a single +5 V olt supply. exceed RV+ by more than 0.3V . defeat the function of the decoupling capacitors. Call Applications Engineering. 0 0 0 Reset has occurred or no program input. 0 1 1 T AOS/LLOOP in effect. last "clear LOS" and "clear DPM". Table 12. Coding for Serial Output bits 5,6,7

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22 DS154F2

RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 V olts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 V olts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 V olts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 V olts. TV+ must not exceed RV+ by more than 0.3 V . Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or

2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying

XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10. Overdriving the oscillator with an external clock is not supported. Control ACLKI - Alternate External Clock Input, Pin 1. A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground. During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. CS61574A CS61575 DS154F2 23

LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. Also controls the receiver slicing level and the line code in Extended Hardware Mode. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial control port is used to control the line interface and determine its status. Grounding the MODE pin puts the line interface in the Hardware Mode, where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 Vselects the Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Data for the on-chip register. Sampled on the rising edge of SCLK. SDO - Serial Data Output, Pin 25. (Host Mode) Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. CS61574A CS61575

24 DS154F2

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RCLK - Recovered Clock, Pin 8. The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator.. RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data and clock are recovered and output on RCLK and RPOS/RNEG or RDATA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDA TA - Transmit Data, Pin 3. (Extended Hardware Mode) Transmitter NRZ input data which passes through the line code encoder, and is then driven on to the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. CS61574A CS61575 DS154F2 25

TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 75 Ω load between TTIP and TRING. A transformer is required as shown in Table A1. Status AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor , Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. LOS returns low when the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consectutive zeros) as prescribed in ANSI T1.231-1993. When in the loss of signal state RPOS/RNEG or RDA TA are forced low, and ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. MTIP , MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor. Ordering Guide Model Frequency FIFO Depth (Bits) Package CS61575-IP1 T1 & E1 192 28-pin Plastic DIP CS61575-IL1 T1 & E1 192 28-pin PLCC CS61574A-IP1 T1 & E1 32 28-pin Plastic DIP CS61574A-IL1 T1 & E1 32 28-pin PLCC CS61574A CS61575

26 DS154F2

D B A L C 13.72 14.22 0.540 0.560 36.45 1.02 0.36 0.51 3.94 3.18 0.20 15.24 37.21 1.65 0.56 1.02 5.08 3.81 0.38 15° 1.435 0.040 0.014 0.020 0.155 0.125 0.600 0.008 1.465 0.065 0.022 0.040 0.200 0.150 0.015 15° 15.87 0.625 2.41 2.67 0.095 0.105 C eA D B SEATING PLANE A B1 e1 A1 L NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. NOM 13.97 36.83 1.27 0.46 0.76 4.32 0.25 2.54 NOM 0.550 1.450 0.050 0.018 0.030 0.170 0.010 0.100 eA EE1 D D2/E2 28-pin PLCC D2/E2 MAXMIN MAX MIN MILLIMETERS INCHES DIM A 4.574.20 0.180 0.165 D/E 12.32 12.57 0.485 0.495 B 0.530.33 0.021 0.013 e AA1 B e 2.29 0.090 11.43 11.58 0.450 0.456 9.91 10.92 0.390 0.430 1.19 1.35 0.047 0.053 NOM 4.45 12.45 0.41 2.79 11.51 10.41 1.27 NOM 0.175 0.490 0.016 0.110 0.453 0.410 0.050 3.04 0.120 D1/E1 CS61574A CS61575 DS154F2 27

Figures A1-A3 show typical T1 and E1 line inter- face application circuits. Table A1 shows the external components which are specific to each application. Figure A1 illustrates a T1 interface in the Host Mode. Figure A2 illustrates a 120 Ω E1 interface in the Hardware Mode. Figure A3 illus- trates a 75 Ω E1 interface in the Extended Hardware Mode The receiver transformer has a grounded center tap on the IC side. Resistors between the RTIP and RRING pins to ground provide the termina- tion for the receive line. The transmitter transformer matches the 75 Ω transmitter output impedance to the line imped- ance. Figures A1-A3 show a 0.47 µF capacitor in series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting in a DC current through the transformer primary. This current might satu- rate the transformer producing an output offset level shift. Control Monitor Frame Format Encoder/ Decoder CS61574A OR CS61575 IN HOST MODE RECEIVE LINE TRANSMIT LINE XTL RV+ + 68 µF RGND 0.1 µF +5V 21 15 + 1.0 µF TGND RV+ TV+CLKE ACLKI LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND 22 14 SCLK CS INT SDI SDO RTIP RRING MTIP MRING TRING TTIP 0.47 µF 1:1.15 PE-65388 2CT:1 PE-65351 µP Serial Port +5V 100 kΩ Figure A1. T1 Host Mode Configuration Frequency MHz Cable Ω R1 and R2 Ω Transmit Transformer Crystal XTL 1.544 (T1) 100 200 1:1.15 CXT6176 2.048 (E1) 120 240 1:1.26 CXT8192 75 150 1:1 Table A1. External Component Values CS61574A CS61575

28 DS154F2

+ 68 µF RGND 0.1 µF +5V 21 15 + 1.0 µF TGND RV+ TV+TAOS ACLKI RLOOP LLOOP MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND 22 14 LEN0 LEN1 LEN2 RTIP RRING MTIP MRING TRING TTIP 0.47 µF 1:1.26 PE-65389 2CT:1 PE-65351 LOS DPM Figure A2. 120 Ω, E1 Hardware Mode Configuration Control Monitor Frame Format Encoder/ Decoder CS61574A OR CS61575 IN EXTENDED HARDWARE MODE Line Length Setting RECEIVE LINE TRANSMIT LINE 10XTL + 68 µF RGND 0.1 µF +5V 21 15 + 1.0 µF TGND RV+ TV+RCODE PCS BPV TAOS MODE RDATA RCLK TDATA TCLK XTALIN XTALOUT RGND TGND 22 14 LEN0 LEN1 LEN2 RTIP RRING TRING TTIP 0.47 µF 1:1 PE-65389 2CT:1 PE-65351 ACLKI RLOOP LLOOP LOS

11 AIS

4 TCODE

Figure A3. 75 Ω, E1 Extended Hardware Mode Configuration CS61574A CS61575 DS154F2 29

Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with the CS61574A and CS61575. Refer to the "Telecom Transformer Se- lection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer. In applications where it is advantageous to use a single transmitter transformer for 75Ω and 120Ω E1 applications, a 1:1.26 transformer may be used. Although transmitter return loss will be re- duced for 75Ω applications, the pulse amplitude will be correct across a 75Ω load. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the jitter attenuator. It is rec- ommended that the Crystal Semiconductor CXT6176 crystal be used for T1 applications and the CXT8192 crystal be used for E1 applications. Designing for AT&T 62411 For additional information on the requirements of AT&T 62411 and the design of an appropriate system synchronizer, please refer to the Crystal Semiconductor Application Notes: "AT&T 62411 Design Considerations – Jitter and Synchroniza- tion" and "Jitter Testing Procedures for Compliance with AT&T 62411". Transmit Side Jitter Attenuation In some applications it is desirable to attenuate jitter from the signal to be transmitted. A CS61575 in local loopback mode can be used as a jitter attenuator. The inputs to the jitter attenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK. Line Protection Secondary protection components can be added to provide lightning surge and AC power-cross immunity. Refer to the application note "Secon- dary Line Protection for T1 and E1 Line Cards" for detailed information on the different electrical safety standards and specific application circuit recommendations. Parameter Receiver Transmitter Turns Ratio 1:2 CT ± 5% 1:1 ± 1.5 % for 75 Ω E1 1:1.15 ± 5 % for 100 Ω T1 1:1.26 ± 1.5 % for 120 Ω E1 Primary Inductance 600 µH min. @ 772 kHz 1.5 mH min. @ 772 kHz Primary Leakage Inductance 1.3 µH max. @ 772 kHz 0.3 µH max. @ 772 kHz Secondary Leakage Inductance 0.4 µH max. @ 772 kHz 0.4 µH max. @ 772 kHz Interwinding Capacitance 23 pF max. 18 pF max. ET-constant 16 V-µs min. for T1 12 V-µs min. for E1 16 V-µs min. for T1 12 V-µs min. for E1 Table A2. Transformer Specifications CS61574A CS61575

30 DS154F2

Interfacing The CS61575 and CS61574A With the CS62180B T1 Transceiver To interface with the CS62180B, connect the de- vices as shown in Figure A4. In this case, the line interface and CS62180B are in Host Mode con- trolled by a microprocessor serial interface. If the line interface is used in Hardware Mode, then the line interface RCLK output must be inverted be- fore being input to the CS62180B. If the CS61575 or CS61574A is used in Extended Hardware Mode, the RCLK output does not have to be inverted before being input to the CS62180B. Application Turns Ratio(s) Manufacturer Part Number Package Type RX: T1 & E1 1:2CT Pulse Engineering PE-65351 1.5 kV through-hole, single Schott 67129300 Bel Fuse 0553-0013-HC TX: 1:1.15 Pulse Engineering PE-65388 1.5 kV through-hole, single Schott 67129310 Bel Fuse 0553-0013-RC TX: E1 (75 & 120 Ω) 1:1.26 1:1 Pulse Engineering PE-65389 1.5 kV through-hole, single Schott 67129320 Bel Fuse 0553-0013-SC RX &TX: 1:2CT 1:1.15 Pulse Engineering PE-65565 1.5 kV through-hole, dual Bel Fuse 0553-0013-7J RX &TX: E1 (75 & 120 Ω) 1:2CT 1:1.26 1:1 Pulse Engineering PE-65566 1.5 kV through-hole, dual Bel Fuse 0553-0013-8J RX &TX: 1:2CT 1:1.15 Pulse Engineering PE-65765 1.5 kVsurface-mount, dual Bel Fuse S553-0013-06 RX &TX: E1 (75 & 120 Ω) 1:2CT 1:1.26 1:1 Pulse Engineering PE-65766 1.5 kV surface-mount, dual Bel Fuse S553-0013-07 RX : T1 & E1 1:2CT Pulse Engineering PE-65835 3 kV through-hole, single EN60950, EN41003 approved TX: E1 (75 & 120 Ω ) 1:1.26 1:1 Pulse Engineering PE-65839 3 kV through-hole, single EN60950, EN41003 approved Table A3. Recommended Transformers ACLK TCLK RCLK RPOS RNEG TPOS TNEG CS62180B CLKE SCLK INT SDO SDI TCLK TPOS TNEG RNEG RPOS RCLK SCLK SDO SDI TO HOST CONTROLLER 100k

1.544 MHz

Figure A4. Interfacing the CS61574A or CS61575 with a CS62180B (Host Mode) CS61574A CS61575 DS154F2 31

• Notes •

• Socketed Line Interface Device
• All Required Components for Complete Line Interface Evaluation
• Configuration by DIP Switch or Serial Interface
• LED Status Indicators for Alarm Conditions
• Support for Host, Hardware, and Extended Hardware Modes General Description The evaluation board includes a socketed line interface device and all support components necessary for evaluation. The board is powered by an external 5 Volt supply. The board may be configured for 100 Ω twisted-pair T1, 75 Ω coax E1, or 120 Ω twisted-pair E1 operation. Binding posts are provided for line connections. Sev- eral BNC connectors are available to provide system clocks and data I/O. Two LED indicators monitor de- vice alarm conditions. The board supports all line interface operating modes. ORDERING INFORMATION: CDB61534, CDB61535. CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB61304A, CDB61305A SEP ’95 DS40DB3 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 Line Interface Evaluation Board CDB61534, CDB61535, CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB615304A, & CDB61305A ACLKI TCLK TPOS (TDATA) TNEG RNEG (BPV) RPOS (RDATA) RCLK CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A Reset Circuit Mode Select Circuit (TCODE) +5V 0V LED Status Indicators Hardware Control Circuit Serial Interface Control Circuit TTIP TRING RTIP RRING XTL

to the two binding posts labeled +5V and GND. pacitor C2 are used to decouple RV+ to RGND. mit line length selection (LEN2,LEN1,LEN0). and RCODE have no function in Hardware mode. JP1 should not be used in the Hardware mode. JP1 - Connector for external processor in Host operating mode. JP2, JP6, JP7 A-A Extended Hardware operating mode. B-B Hardware or Host operating modes. JP3 IN Hardware or Extended Hardware operating modes. JP4 C-C Connects the ACLKI BNC input to pin 1 of device. D-D Grounds the ACLKI BNC input through 51Ω resistor R1. JP5 E-E Transmit line connection for all applications except those listed for "F-F" on the next line. F-F 75Ω coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1. JP8 IN Shorts resistor R2 for all applications except those listed for "OUT" on the next line. OUT Inserts resistor R2 for 75Ω coax E1 applications using the CS61534, 35, 58, 74, or 77. Table 1. Evaluation Board Jumper Settings

34 DS40DB3

Figure 1. Evaluation Board Schematic

has detected a loss of signal. line interface is configured using DIP switch S2. used in Extended Hardware mode. has detected a loss of signal. if any S2 switch, other than CLKE, is closed. nector and TNEG is not used. Figure 1. The signal is available at the TTIP and

36 DS40DB3

The evaluation board supports 100Ω twisted-pair T1, 75Ω coax E1, and 120Ω twisted-pair E1 op- eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The CDB61535A, CDB6158A, CDB61574A, CDB61575, CDB61304A, and CDB61305A are supplied with a 1:1.15 transmit transformer in- stalled for T1 applications. An additional 1:1:1.26 transformer for E1 applications is provided with the board. This transformer requires JP5 to be jumpered across F-F for 75Ω coax E1 applica- tions. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 require the JP8 jumper to be out for 75Ω coax E1 applications. This inserts resistor R2 to reduce the transmit pulse amplitude and meet the 2.37 V nominal pulse amplitude requirement in CCITT G.703. In addition, R2 increases the equivalent load imped- ance across TTIP and TRING. RECEIVE CIRCUIT The receive line interface signal is input at the RTIP and RRING binding posts. The receive sig- nal is transformer coupled to the line interface de- vice through a center-tapped 1:2 transformer. The transformer produces ground referenced pulses of equal amplitude and opposite polarity on RTIP and RRING. The receive line interface is terminated by resis- tors R9 and R10. The evaluation boards are sup- plied from the factory with 200Ω resistors for ter- minating 100Ω T1 twisted-pair lines. Resistors R9 and R10 should be replaced with 240Ω resis- tors for terminating 120Ω E1 twisted-pair lines or 150Ω resistors for terminating 75Ω E1 coaxial lines. Two 243Ω resistors and two 150Ω resistors are included with the evaluation board for this purpose. The recovered clock and data signals are avail- able on BNC outputs labeled RCLK, RPOS(RDA TA), and RNEG(BPV). In the Hard- ware and Host operating modes, data is output on the RPOS(RDA TA) and RNEG(BPV) connectors in dual NRZ format. In the Extended Hardware operating mode, data is output in NRZ format on the RPOS(RDATA) connector and bipolar viola- tions are reported on the RNEG(BPV) connector. QUARTZ CRYSTAL A quartz crystal must be installed in socket Y1 for all devices except the CS6158 and CS6158A. A Crystal Semiconductor CXT6176 crystal is rec- ommended for T1 operation and a CXT8192 is recommended for E1 operation. The evaluation board has a CXT6176 installed at the factory and a CXT8192 is also provided with the board. The CDB6158 and CDB6158A have resistor R13 installed instead of a crystal. This connects the RT pin of the device to the +5 V olt supply. ALTERNATE CLOCK INPUT The ACLKI BNC input provides the alternate clock reference for the line interface device (ACLK for the CS61534) when JP4 is jumpered across C-C. This clock is required for the CS61534, CS61535, CS6158, and CS6158A op- eration but is optional for all other line interface devices. If ACLKI is provided, it may be desir- able to connect both C-C and D-D positions on JP4 to terminate the external clock source provid- ing ACLKI with the 51Ω resistor R1. If ACLKI is optional and not used, connector JP4 should be jumpered across D-D to ground pin 1 of the de- vice through resistor R1. TRANSFORMER SELECTION To permit the evaluation of other transformers, Table 2 lists the transformer and line interface de- vice combinations that can be used in T1 and E1 LINE INTERFACE EVALUATION BOARD DS40DB3 37

applications. A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated on the drawing in Table 2. For exam- ple, the Pulse Engineering PE-65388 transformer may be used with the transmitter of the CS61575 device for 100Ω T1 applications only (as indi- cated by note 3) when installed in transformer socket T1 with pin 1 at position D (upper right). PROTOTYPING AREA A prototyping area with power supply and ground connections is provided on the evaluation board. This area can be used to develop and test a vari- ety of additional circuits like a data pattern gener- ator, CS2180B framer, system synchronizer PLL, or specialized interface logic. EVALUATION HINTS 1. Properly terminate TTIP/TRING when evaluat- ing the transmit output signal. For more informa- tion concerning pulse shape evaluation, refer to the Crystal application note entitled "Measure- ment and Evaluation of Pulse Shapes in T1/E1 Transmission Systems." 2. Change the receiver terminating resistors R9 and R10 when evaluating E1 applications. Resis- tors R9 and R10 should be replaced with 240Ω resistors for terminating 120Ω E1 twisted-pair lines or 150Ω resistors for terminating 75Ω E1 coaxial lines. Two 243Ω resistors and two 150Ω resistors are included with the evaluation board for this purpose. 3. Closing a DIP switch on S2 towards the label sets the device control pin of the same name to logic 1 (+5 V olts). 4. To avoid damage to the external host controller connected to JP1, all S2 switch positions (except CLKE) should be open. In the Host operating mode, the CLKE switch selects the active edge of SCLK and RCLK. LINE INTERFACE EVALUATION BOARD

38 DS40DB3

1. A letter at the intersection of a row and column in T able 2 indicates

that the selected transformer is supported for use with the device. sitioned to match the letter illustrated in the drawing to the left.

1. The receive transformer (RX) is soldered at location T2 on the

board and may be changed according to the application.

1. For use in 100Ω T1 twisted-pair applications only.
2. For use in 75Ω and 120Ω E1 applications only. Place jumper JP5

in position F-F for 75Ω E1 applications requiring a 1:1 turns ratio.

1. Transmitter return loss improves when using a 1:2 turns ratio trans-

former with the appropriate transmit resistors. Table 2. Transformer Applications

Figure 2. Silk Screen Layer (NOT TO SCALE)

40 DS40DB3

Figure 3. Top Ground Plane Layer (NOT TO SCALE)

Figure 4. Bottom Trace Layer (NOT TO SCALE)

42 DS40DB3

• Notes •

Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation