CS61535A

CS61535A CIRRUS | Alldatasheet

Document overview

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Technical content

Features

• Provides Analog PCM Line Interface for T1 and E1 Applications
• Provides Line Driver, and Data and Clock Recovery Functions
• Transmit Side Jitter Attenuation Starting at 6 Hz, with > 300 UI of Jitter Tolerance
• Low Power Consumption (typically 175 mW)
• B8ZS/HDB3/AMI Encoders/Decoders
• 14 dB of Transmitter Return Loss
• Compatible with SONET, M13 , CCITT G.742, and Other Asynchronous Muxes General Description The CS61535A combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. The device features a transmitter jitter attenuator mak- ing it ideal for use in asynchronous multiplexor systems with gapped transmit clocks. The CS61535A provides a matched, constant impedance output stage to insure signal quality on mismatched, poorly terminated lines. Both ICs use a digital Delay-Locked-Loop clock and data recovery circuit which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance.

Applications

• Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX-1 cross connect.
• Interfacing customer premises equipment to a CSU.
• Interfacing to E1 links.

Ordering Information

CS61535A-IP1 28 Pin Plastic DIP CS61535A-IL1 28 Pin PLCC (j-leads) MAY ’96 DS40F2 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 SIGNAL QUALITY MONITOR

13 TTIP

7 RRING

(SCLK) RLOOP (CS) 2524 (INT) LEN0 (SDI) LEN1 (SDO) LEN2 28 23 (CLKE) TAOS MODE AMI, B8ZS, HDB3 CODER TPOS [TDATA] RPOS [RDATA] RNEG [BPV] TNEG [TCODE] MTIP [RCODE] MRING [PCS] DPM [AIS] LOS 12 21 RV+ RGND CLOCK & DATA RECOVERY XTALIN XTALOUT JITTER ATTENUATOR LOOP BACK TV+ [ ] = Pin Function in Extended Hardware Mode ( ) = Pin Function in Host Mode Copyright  Crystal Semiconductor Corporation 1996 (All Rights Reserved) CS61535A T1/E1 Line Interface

Parameter Symbol Min Max Units DC Supply (referenced to RGND,TGND=0V) RV+ TV+ 6.0 (RV+) + 0.3 V V Input Voltage, Any Pin (Note 1) V in RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) I in -10 10 mA Ambient Operating Temperature T A -40 85 °C Storage Temperature T stg -65 150 °C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature T A -40 25 85 °C Power Consumption (Notes 4, 5) P C -2 9 0 3 5 0 m W Power Consumption (Notes 4, 6) P C -1 7 5- m W Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF load. 5. Assumes 100% ones density and maximum line length at 5.25V. 6. Assumes 50% ones density and 300ft. line length at 5.0V. CS61535A

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DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Symbol Min Typ Max Units High-Level Input Voltage Pins 1-4, 17, 18, 23-28 (Notes 7, 8, 9) VIH 2.0 - - V Low-Level Input Voltage Pins 1-4, 17, 18, 23-28 (Notes 7, 8, 9) VIL -- 0 . 8 V High-Level Output Voltage (IOUT = -40 µA) Pins 6-8, 11, 12, 25 (Notes 7, 8, 10) VOH 4.0 - - V Low-Level Output Voltage (IOUT = 1.6 mA) Pins 6-8, 11, 12, 23, 25 (Notes 7, 8, 10) VOL -- 0 . 4 V Input Leakage Current (Except Pin 5) - - ±10 µA Low-Level Input Voltage, Pin 5 V IL -- 0 . 2 V High-Level Input Voltage, Pin 5 V IH (RV+) - 0.2 - - V Mid-Level Input Voltage, Pin 5 (Note 11) V IM 2.3 - 2.7 V Notes: 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40µA). 8. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output. 9. Pins 17 and 18 of the CS61535A are digital inputs in the Extended Hardware Mode. 10. Output drivers will drive CMOS logic levels into a CMOS load. 11. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating. ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Note 12) - 6 - Hz T1 Jitter Attenuation in Remote Loopback (Note 13) Jitter Freq. [Hz] Amplitude [UIpp] 10 10 100 10 500 10 1k 5 10k, 40k 0.3 3.0 6.0 dB dB dB dB dB E1 Jitter Attenuation in Remote Loopback (Note 14) Jitter Freq. [Hz] Amplitude [UIpp] 10 1.5 100 1.5 400 1.5 1k 1.5 10k, 100k 0.2 3.0 6.0 dB dB dB dB dB Attenuator Input Jitter Tolerance (Note 15) 12 23 - UI Notes: 12. Not production tested. Parameters guaranteed by design and characterization. 13. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of measured jitter tolerance using a measurement bandwidth of 1 Hz (10<f<100Hz), 4Hz (100<f<1000 Hz) and 10 Hz (f> 1kHz) centered around the jitter frequency. With a 2 15-1 PRBS data pattern. Crystal must meet specifcations in CXT6176/8192 datasheet. 14. Jitter measured at the demodulator output of an HP3785A using a measurement bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 215-1 PRBS data pattern. Crystal must meet specifications in CXT6176/8192 datasheet. 15. Output jitter increases significantly when attenuator input jitter tolerance is exceeded. CS61535A DS40F2 3

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Transmitter AMI Output Pulse Amplitudes (Note 16) E1, 75 Ω (Note 17) E1, 120 Ω (Note 18) T1, FCC Part 68 (Note 19) T1, DSX-1 (Note 20) 2.14 2.7 2.7 2.4 2.37 3.0 3.0 3.0 2.6 3.3 3.3 3.6 V V V V E1 Zero (space) level (LEN2/1/0 = 0/0/0) 75Ω application (Note 17) 120Ω application (Note 18) -0.237 -0.3 0.237 0.3 V V Recommended Output Load at TTIP and TRING - 75 - Ω Jitter Added During Remote Loopback (Note 21) 10Hz - 8kHz 8kHz - 40kHz 10Hz - 40kHz Broad Band 0.005 0.008 0.010 0.015 0.02 0.025 0.025 0.05 UI UI UI UI Power in 2kHz band about 772kHz (Notes 12, 16) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 12, 16) (referenced to power in 2kHz band at 772kHz) -29 -38 - dB Positive to Negative Pulse Imbalance (Notes 12, 16) T1, DSX-1 E1 amplitude at center of pulse E1 pulse width at 50% of nominal amplitude 0.2 0.5 dB Transmitter Return Loss (Notes 12, 16, 22) 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz dB dB dB Transmitter Short Circuit Current (Notes 12, 23) - - 50 mA RMS Notes: 16. Using a 0.47 µF capacitor in series with the primary of a transformer recommended in the Applications Section. 17. Amplitude measured at the transformer (CS61535A-1:1 or 1:1.26) output across a 75 Ω load for line length setting LEN2/1/0 = 0/0/0. 18. Amplitude measured at the transformer (CS61535A-1:1.26) output across a 120 Ω load for line length setting LEN2/1/0 = 0/0/0. 19. Amplitude measured at the transformer (CS61535A-1:1.15) output across a 100 Ω load for line length setting LEN2/1/0 = 0/1/0. 20. Amplitude measured across a 100 Ω load at the DSX-1 cross-connect for line length settings LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0 and 1/1/1 after the length of #22 AWG ABAM equivalent cable specified in Table 3. The CS61535A requires a 1:1.15 transformer. 21. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 22. Return loss = 20 log

10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and

z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0 and a 1:1 transformer terminated with a 75Ω load, or a 1:1.26 transformer terminated with a 120Ω load. 23. Measured broadband through a 0.5 Ω resistor across the secondary of a 1:1.26 transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0. CS61535A

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ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Driver Performance Monitor MTIP/MRING Sensitivity: Differential Voltage Required for Detection -0 . 6 0- V Receiver RTIP/RRING Input Impedance - 50k - Ω Sensitivity Below DSX (0dB = 2.4V) -13.6 - - dB Data Decision Threshold T1, DSX-1 (Note 24) T1, DSX-1 (Note 25) T1, FCC Part 68 and E1 (Note 26) % of peak % of peak % of peak Data Decision Threshold T1 % of peak % of peak Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 27) 10kHz - 100kHz 2kHz 10Hz and below 0.4 6.0 300 UI UI UI Loss of Signal Threshold (Note 28) 0.25 0.30 0.50 V Notes: 24. For input amplitude of 1.2 V pk to 4.14 Vpk. 26. For input amplitude of 1.05 Vpk to 3.3 Vpk. 27. Jitter tolerance increases at lower frequencies. See Figure 11. 28. LOS goes high after 160 to 190 consecutive zeros are received. A zero is output on RPOS and RNEG (or RDATA) for each bit period where the input signal amplitude remains below the data decision threshold. The analog input squelch circuit operates when the input signal amplitude above ground on the RTIP and RRING pins falls within the squelch range long enough for the internal slicing threshold to decay within this range. Operation of the squelch causes zeros to be output on RPOS and RNEG as long as the input amplitude remains below 0.25V. During receive LOS, pulses greater than 0.25V in amplitude may be output on RPOS and RNEG. LOS returns low after the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consecutive zeros) as prescribed in ANSI T1.231-1993. CS61535A DS40F2 5

Notes: 29. Crystal must meet specifications described in CXT6176/CXT8192 data sheet.

1. ACLKI provided by an external source or TCLK, but not RCLK.
2. Hardware Mode, or Host Mode (CLKE = 0).
3. RCLK cycle width will vary with extent by which pulses displaced by jitter. Specified under worst case

jitter conditions: 0.4 UI AMI data displacement for T1 and 0.2 UI AMI data displacement for E1.

1. At max load of 1.6 mA and 50 pF.
2. The maximum TCLK burst rate is 5 MHz and t

be tolerated on TCLK is 12 VI.

1. The transmitted pulse width does not depend on the TCLK duty cycle.

Figure 1. Recovered Clock and Data Switching Characteristics

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Notes: 38. For CLKE = 0, CS must remain low at least 50 ns after the 16th falling edge of SCLK.

1. Output load capacitance = 50pF.

Figure 4. Serial Port Write Timing Diagram

8 DS40F2

• 50% lower power consumption,
• Internally matched transmitter output imped- ance for improved signal quality,
• Optional AMI, B8ZS, HDB3 encoder/decoder or external line coding support,
• Receiver AIS (unframed all ones) detection,
• ANSI T1.231-1993 compliant receiver Loss of Signal (LOS) handling,
• Transmitter TTIP and TRING outputs are forced low when TCLK is static,
• The Driver Performance Monitor operates over a wider range of input signal levels.
• Elimination of the requirement that a refer- ence clock be input on the ACLKI pin. Existing designs using the CS61535 can be converted to the higher performance, pin-compatible CS61535A if the transmit transformer is replaced by a pin-com- patible transformer with a new turns ratio and the 4.4 Ω resistor used in E1 75 Ω applications is shorted. Introduction to Operating Modes The CS61535A supports three operating modes which are selected by the level of the MODE pin as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. The CS61535A modes are Hardware Mode, Ex- tended Hardware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Extended Hardware Mode provides a parallel chip select input which latches the control inputs allowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the de- vice through a serial interface. There are thirteen multi-function pins whose functionality is deter- mined by the operating mode (see Table 2). Transmitter The transmitter takes data from a T1 (or E1) ter- minal, attenuates jitter, and produces pulses of appropriate shape. The transmit clock, TCLK, and transmit data, TPOS & TNEG or TDA TA, are supplied synchronously. Data is sampled on the falling edge of the input clock, TCLK. Either T1 (DSX-1 or Network Interface) or E1 G.703 pulse shapes may be selected. Pulse shap- ing and signal level are determined by "line length select" inputs as shown in Table 3. The MODE HARDWARE EXTENDED HARDWARE HOST MODE-PIN INPUT LEVEL <0.2V FLOAT, or 2.5V >(RV+) - 0.2V CONTROL METHOD INDIVIDUAL CONTROL LINES INDIVIDUAL CONTROL LINES & PARALLEL CHIP SELECT SERIAL µ-PROCESSOR PORT LINE CODE ENCODER & DECODER NONE AMI, B8ZS, HDB3 NONE AIS DETECTION NO YES NO DRIVER PERFORM- ANCE MONITOR YES NO YES

Table 1. Differences in Operating Modes

6 RNEG BPV RNEG

7 RPOS RDATA RPOS

11 DPM AIS DPM

17 MTIP RCODE MTIP

18 MRING - MRING

23 LEN0 LEN0 INT

24 LEN1 LEN1 SDI

25 LEN2 LEN2 SDO

26 RLOOP RLOOP

27 LLOOP LLOOP SCLK

28 TAOS TAOS CLKE

Table 2. Pin Definitions

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Figure 7. Overview of Operating Modes

shape requirements for 1.544 MHz operation. based upon the "line length " selection made. shown in Figure 9, and specified in Table 4. Figure 8. Typical Pulse Shape at DSX-1 Cross Connect

001 AT&T CB113

Table 3. Line Length Selection primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications

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tolerance increases as jitter frequency decreases. amended, TR-TSY-000170, and CCITT REC. with the slicing level selected by LEN2/1/0). Figure 11. Receiver Block Diagram

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period will be 648 ns. Similar calculations hold for the E1 rate. The clock recovery circuit is designed to accept at least 0.4 UI of jitter at the receiver. Since the data stream contains information only when ones are transmitted, a clock/data recovery circuit must as- sume a zero when no signal is measured during a bit period. Likewise, when zeros are received, no information is present to update the clock recov- ery circuit regarding the trend of a signal which is jittered. The result is that two ones that are sepa- rated by a string of zeros can exhibit maximum deviation in pulse arrival time. For example, one half of a period of jitter at 100 kHz occurs in 5 µs, which is 7.7 T1 bit periods. If the jitter ampli- tude is 0.4 UI, then a one preceded by seven zeros can have maximum displacement in arrival time, the CS61535A, the data recovery circuit correctly assigns a received bit to its proper clock period if it is displaced by less than 6/13 of a bit period from its optimal location. Theoretically, this would give a jitter tolerance of 0.46 UI. The ac- tual jitter tolerance of the CS61535A is only slightly less than the ideal. In the event of a maximum jitter hit, the RCLK clock period immediately adjusts to align itself with the incoming data and prepare to accurately place the next one, whether it arrives one period later, or after another string of zeros and is dis- placed by jitter. For a maximum early jitter hit, RCLK will have a period of 7/13 * 648 ns = 349 ns (2,865,961 Hz). For a maximum late jitter hit, RCLK will have a period of 19/13 * 648 ns = 947 ns (1,055,880 Hz). Loss of Signal Receiver loss of signal is indicated upon receiv- ing 175 consecutive zeros. A digital counter counts received zeros based on RCLK cycles. A zero input is determined either when zeros are re- ceived, or when the received signal amplitude drops below a 0.3 V peak threshold. The receiver reports loss of signal by setting the Loss of Signal pin, LOS, high. If the serial inter- face is used, the LOS bit will be set and an interrupt issued on INT. LOS will go low (and flag the INT pin again if serial I/O is used) when a valid signal is detected. Note that in the Host Mode, LOS is simultaneously available from both the register and pin 12. In a loss of signal state, the RCLK frequency will be equal to the ACLKI frequency since ACLKI is being used to calibrate the clock recovery circuit. Received data is output on RPOS and RNEG (or RDA TA) regardless of LOS status. The LOS re- turns to logic zero when the ones density reaches 12.5% (based upon 175 bit periods staring with a one and containing less than 100 consecutive ze- ros) as prescribed in ANSI T1.231-1993. A power-up or manual reset will also set LOS high. Local Loopback The local loopback mode takes clock and data presented on TCLK, TPOS, and TNEG (or TDATA) and outputs it at RCLK, RPOS and RNEG (or RDATA). Local loopback is selected by taking pin 27 high, or LLOOP may be selected using the serial interface. The data on the trans- mitter inputs is transmitted on the line unless TAOS is selected to cause the transmission of an all ones signal instead. Receiver inputs are ig- nored when local loopback is in effect. The jitter attenuator is not included in the local loopback data path. Selection of local loopback overrides the chip’s loss of signal response. Remote Loopback In remote loopback, the recovered clock and data input on RTIP and RRING are sent through the jitter attenuator and back out on the line via TTIP and TRING. The recovered incoming signals are also sent to RCLK, RPOS and RNEG (or CS61535A

16 DS40F2

ance or the performance of a neighboring driver. level within a time-out period. ately change the operating state of the device. inputs are ignored when PCS is high. Table 6. Selection of Encoder/Decoder

allow the power supply to reach operating voltage. in the transmit and receive sections commences. initial calibration should take less than 20 ms. is available which will clear all registers. a reset will set all registers to 0 and set LOS high. tem transmit and receive timing. CS, low (CS must initially be high). SCLK cycle corresponding to the last write bit.

00 D7D6D5D4D3D2D1D0

Figure 13. Input/Output Timing

1 ADD0 LSB of address, Must be 0

2 ADD1 Must be 0

3 ADD2 Must be 0

4 ADD3 Must be 0

5 ADD4 Must be 1

Table 7. Address/Command Byte

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the end of the hold period of data bit D7. 16 (0010000). The last bit is ignored. bit 0. This holds for DPM as well. or DPM will be prevented from occuring).

2 LEN0 Bit 0 - Line Length Select

3 LEN1 Bit 1 - Line Length Select

4 LEN2 Bit 2 - Line Lenght Select

5 RLOOP Remote Loopback

6 LLOOP Local Loopback

Table 8. Input Data Register

1 DPM Driver Performance Monitor

Table 9. Output Data Bits 0 - 4 000 Reset has occurred or no program input.

100 RLOOP in effect

101 DPM changed state since last "clear DPM"

110 LOS changed state since last "clear LOS"

111 LOS and DPM have changed state since

last "clear LOS" and "clear DPM". Table 10. Coding for Serial Output Bits 5, 6, 7

The device operates from a single +5 V olt supply. Separate pins for transmit and receive supplies provide internal isolation. These pins should be connected externally near the device and decou- pled to their respective grounds. TV+ must not exceed RV+ by more than 0.3V . Decoupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits in both the transmit and receive paths. A 1.0 µF capacitor should be connected between TV+ and TGND, and a 0.1 µF capacitor should be con- nected between RV+ and RGND. Use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. A 68 µF tantalum capacitor should be added close to the RV+/RGND supply. Wire wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. Call: (512) 445-7222 CS61535A

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22 DS40F1

RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 V olts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 V olts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 V olts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 V olts. TV+ must not exceed RV+ by more than 0.3 V . Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or

2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying

XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10. Overdriving the oscillator with an external clock is not supported. Control ACLKI - Alternate External Clock Input, Pin 1. The CS61535A does not require a clock signal to be input on ACLKI when a crystal is connected between pins 9 and 10. If a clock is not provided on ACLKI, this input must be grounded. If ACLKI is grounded, the oscillator in the jitter attenuator is used to calibrate the clock recovery circuit and TAOS is not available. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "Clear LOS" or "Clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. CS61535A

24 DS40F1

LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. Also controls the receiver slicing level and the line code in Extended Hardware Mode. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through to the receive clock and data pins. TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the CS61535A line interface in the Host Mode. In the host mode, a serial control port is used to control the CS61535A line interface and determine its status. Grounding the MODE pin puts the CS61535A line interface in the Hardware Mode, where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 V puts the CS61535A in Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS high causes the CS61535A line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Data for the on-chip register. Sampled on the rising edge of SCLK. SDO - Serial Data Output, Pin 25. (Host Mode) Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. CS61535A DS40F1 25

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by ACLKI. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RCLK - Recovered Clock, Pin 8. The receiver recovered clock is output on this pin. RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data and clock are recovered and output on RCLK and RPOS/RNEG or RDATA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) Transmitter NRZ input data which passes through the line code encoder, and is then driven on to the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. In the CS61535A, this output is designed to drive a 75 Ω load. A 1:1, 1:1.15 or 1:1.26 transformer is required as shown in Figure A1. CS61535A

26 DS40F1

AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor , Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. For the CS61535A, LOS returns low when the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consecutive zeros) as prescribed by ANSI T1.231-1993. MTIP , MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a CS61535A. If the INT pin in the host mode is used, and the monitor is not used, writing "Clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor. CS61535A DS40F1 27

D B A L C 13.72 14.22 0.540 0.560 36.45 1.02 0.36 0.51 3.94 3.18 0.20 15.24 37.21 1.65 0.56 1.02 5.08 3.81 0.38 15° 1.435 0.040 0.014 0.020 0.155 0.125 0.600 0.008 1.465 0.065 0.022 0.040 0.200 0.150 0.015 15° 15.87 0.625 2.41 2.67 0.095 0.105 C eA D B SEATING PLANE A B1 e1 A1 L NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. NOM 13.97 36.83 1.27 0.46 0.76 4.32 0.25 2.54 NOM 0.550 1.450 0.050 0.018 0.030 0.170 0.010 0.100 eA EE1 D D2/E2 28-pin PLCC D2/E2 MAXMIN MAX MIN MILLIMETERS INCHES DIM A 4.574.20 0.180 0.165 D/E 12.32 12.57 0.485 0.495 B 0.530.33 0.021 0.013 e AA1 B e 2.29 0.090 11.43 11.58 0.450 0.456 9.91 10.92 0.390 0.430 1.19 1.35 0.047 0.053 NOM 4.45 12.45 0.41 2.79 11.51 10.41 1.27 NOM 0.175 0.490 0.016 0.110 0.453 0.410 0.050 3.04 0.120 D1/E1 CS61535A

28 DS40F1

Figures A1-A3 show the typical configurations for interfacing the I.C. to a line through transmit and receive transformers. The receiver transformer is center tapped and center grounded with resistors between the center tap and each leg on the I.C. side. These resistors provide the termination for the line. Figures A1-A3 show a 0.47 µF capacitor in series with the transmit transformer primary. This ca- pacitor is needed to prevent any buildup in the core of the transformer due to any DC imbalance that may be present at the differential outputs, TTIP and TRING. If DC saturates the trans- former, a DC offset will result during the transmission of a space (zero) as the transformer tries to dump the charge and return to equilib- rium. The blocking capacitor will keep DC current from flowing in the transformer. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the CS61535A. It is recom- mended that the CXT6176 from Crystal Control Monitor Frame Format Encoder/ Decoder CS61535A IN HOST MODE RECEIVE LINE TRANSMIT LINE XTL RV+ + 68 µF RGND 0.1 µF +5V 21 15 + 1.0 µF TGND RV+ TV+CLKE ACLKI LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND 22 14 SCLK CS INT SDI SDO RTIP RRING MTIP MRING TRING TTIP 0.47 µF CT 2:1 µP Serial Port +5V 100 kΩ DEVICE FREQUENCY MHz CABLE Ω R1&2 Ω Transmit Transformer CS61535A 1.544 2.048 2.048 100 120 200 240 150 1:1.15 1:1.26 1:1 Figure A1. Host Mode Configuration CS61535A DS40F2 29

+ 68 µF RGND 0.1 µF +5V 21 15 + 1.0 µF TGND RV+ TV+TAOS ACLKI RLOOP LLOOP MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND 22 14 LEN0 LEN1 LEN2 RTIP RRING MTIP MRING TRING TTIP 0.47 µF CT 2:1 LOS DPM Figure A2. Hardware Mode Configuration Control Monitor Frame Format Encoder/ Decoder CS61535A IN EXTENDED HARDWARE MODE Line Length Setting RECEIVE LINE TRANSMIT LINE XTL + 68 µF RGND 0.1 µF +5V 21 15 + 1.0 µF TGND RV+ TV+RCODE PCS BPV TAOS MODE RDATA RCLK TDATA TCLK XTALIN XTALOUT RGND TGND 22 14 LEN0 LEN1 LEN2 RTIP RRING TRING TTIP 0.47 µF CT 2:1 ACLKI RLOOP LLOOP LOS

11 AIS

4 TCODE

Figure A3. Extended Hardware Mode Configuration CS61535A

30 DS40F2

Semiconductor be used for T1 applications, and that the CXT8192 be used for E1 applications. Interfacing The CS61535A With the CS62180B T1 Transceiver To interface with the CS62180B, connect the de- vices as shown in Figure A4. In this case, the CS61535A and CS62180B are in Host Mode con- trolled by a microprocessor serial interface. If the CS61535A is used in Hardware Mode, then the CS61535A RCLK output must be inverted before being input to the CS62180B. If the CS61535A is used in Extended Hardware Mode, the CS61535A RCLK output does not need to be inverted before being input to the CS62180B. CS61534 Compatibility The CS61535A is pin compatible with the CS61534. The CS61535A has greater jitter toler- ance for both transmitter and receiver, and it provides more jitter attenuation starting at jitter frequencies of 6 Hz. The greater jitter tolerance and attenuation in the transmit path makes the CS61535A more suitable for CCITT demultiplex- ing applications where eight bits can be dropped from the clock/data stream at once. Similarly, these parts can be used in SONET applications with the addition of some external circuitry. The main differences of the CS61535A relative to the CS61534 is: 1) On the CS61535A, selection of LEN 2/1/0 = 0/0/0 changes the voltage at which the receiver accepts an input as a pulse (slicing level) from 65% to 50% of the peak pulse amplitude. Lower- ing the data slicing level will improve receiver sensitivity at long cable lengths when the data is jittered. A 50% slicing level will also improve crosstalk sensitivity for channels where received pulses do not have undershoot. 2) There are differences in the functionality of the ACLKI (ACLK) input on the CS61534 and CS61535A. ACKLI (ACLK) is used as the trans- mit clock in the transmit all ones (TAOS) mode. On the CS61535A, ACLKI is used as a calibra- tion reference for the receiver clock recovery circuit and therefore may not be supplied by RCLK. On the CS61534, ACLK may be supplied by RCLK . If an external clock is not provide on the ACLKI input of the CS61535A, the crystal oscillator is used to calibrate the receiver clock recovery circuit. 3) On the CS61535A, the Host Mode status regis- ter bits 5, 6 and 7 are encoded so that state changes on LOS and DPM may be reported. 4) RCLK on the CS61534 has a 50% duty cycle, while RCLK on the CS61535A has a duty cycle which is typically 30% or 70%. Also, the CS61535A RCLK duty cycle and instantaneous frequency vary with received jitter and may ex- hibit 1/13 UIpp quantization jitter even when the incoming signal is jitter free. 5) The CS61535A requires 25 ns of setup time on TPOS and TNEG before the falling edge of TCLK and 25 ns of hold time on these inputs af- ACLKI TCLK RGND RCLK RV+ +5V 0V 0.1uFRPOS RNEG TPOS TNEG CS62180B MODEV+ CLKE SCLK SDO SDI TCLK TPOS TNEG RNEG RPOS RCLK SCLK SDO SDI TO HOST CONTROLLER 100k 100k1.544 MHz CLOCK CS61535A CS 22k SIGNAL 68uF CS INT Figure A4. Interfacing the CS61535A with the CS62180B (Host Mode) CS61535A DS40F2 31

ter the falling edge of TCLK. The CS61534 re- quires 50 ns of hold time on TPOS and TNEG after the falling edge of TCL, and 0 ns of setup time. 6) LOS occurs after 31 consecutive zeros on the CS61534. For the CS61535A LOS occurs after 175 zeros. 7) Since the CS61535A receivers are continu- ously calibrated, there is no need to issue a reset to initialize the receiver timing as with the CS61534. Using the CS61535A for SONET The CS61535A can be applied to SONET VT1.5 and VT2.0 interface circuits as shown in Fig- ure A5. The SONET data rate is 51.84 MHz, and has 6480 bits per frame (125 us per frame). An individual T1 frame (193 bits per frame) or PCM- 30 frame (256 bits per frame) has its data mapped into the 6480 bit SONET frame. The mapping does not result in a uniform spacing between sucessive T1 (or E1) bits. Rather, for locked VT applications, gaps as large as 24 T1 bit periods or

32 E1 bit periods can exist between successive

bits. With floating VTs, the gaps can be even larger. The circuit in Figure A5 eliminates the demulti- plexing jitter in a two-step approach. The first step uses a FIFO which is filled at a 51.84 MHz rate (when T1 or E1 bits are present), and which is emptied at a sub-multiple of the 51.84 rate. The FIFO is emptied only when it contains data. When the FIFO is empty the output clock is not pulsed. The sub-multiple rate chosen should be slightly faster than the target rate (1.544 or 2.048 MHz), but as close to the target rate as possible. For TPOS TCLK2 TNEG RPOS RNEG RCLK2 TCLK1 TSER RSER RCLK1 FIFO FIFO

51.84 MHz

(or 256 bit) Mapping Circuit Jitter Attenuator Figure A5. SONET Application CS61535A

32 DS40F2

locked VT operation, Table A1 shows potential sub-multiple data rates, and the impact on those rates on the maximum gap in the output clock of the FIFO, and depth of FIFO required. FIFO depth will have to be increased for floating VT operation, with 8 bits of FIFO depth being added for each pointer alignment change that can occur. The objective that should be met in picking a FIFO depth and clock divider is keep the maxi- mum gap on the output of the FIFO at 12 bits or less. Twelve bits is the maximum jitter which can be input to the CS61535A’s jitter attenuator with- out causing the overflow/undeflow protection circuit to operate. The CS61535A then removes the remaining jitter from the signal. The receive path also requires a bit mapping (from 193 or 256 bits to 6480 bits). This mapping requires an input buffer with the same depth as use on the transmit path. This buffer also absorbs the output jitter generated by the CS61535A’s digital clock recovery. Transformers Recommended transmitter and receiver trans- former specifications for the CS61535A are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with the CS61535A. Refer to the "Telecom Trans- former Selection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer. In applications with the CS61535A where it is ad- vantageous to use a single transmitter transformer for both 75Ω and 120Ω E1 applications, a 1:1.26 transforer may be used. Although transmitter re- turn loss will be reduced for 75Ω applications, the pulse amplitude will be correct across a 75 Ω load. T arget Rate (MHz) Clock Divider Resultant Rate (MHz) Maximum Gap FIFO Depth Required(µs) bits 1.544 32 1.620 6.2 10 21 1.544 33 1.571 3.9 6 26 2.048 25 2.074 3.4 7 34 Table A1. Locked VT FIFO Analysis Parameter CS61535A Receiver CS61535A Transmitter Turns Ratio 1:2 CT ± 5% 1:1 ± 1.5 % for 75 Ω E1 1:1.15 ± 5 % for 100 Ω T1 1:1.26 ± 1.5 % for 120 Ω E1 Primary Inductance 600 µH min. @ 772 kHz 1.5 mH min. @ 772 kHz Primary Leakage Inductance 1.3 µH max. @ 772 kHz 0.3 µH max. @ 772 kHz Secondary Leakage Inductance 0.4 µH max. @ 772 kHz 0.4 µH max. @ 772 kHz Interwinding Capacitance 23 pF max. 18 pF max. ET-constant 16 V-µs min. for T1 12 V-µs min. for E1 16 V-µs min. for T1 12 V-µs min. for E1 Table A2. Transformer Specifications CS61535A DS40F2 33

Ratio(s) Manufacturer Part Number Package Type RX: T1 & E1 1:2CT Pulse Engineering PE-65351 1.5 kV through-hole, single Schott 67129300 Bel Fuse 0553-0013-HC TX: 1:1.15 Pulse Engineering PE-65388 1.5 kV through-hole, single Schott 67129310 Bel Fuse 0553-0013-RC TX: E1 (75 & 120 Ω) 1:1.26 1:1 Pulse Engineering PE-65389 1.5 kV through-hole, single Schott 67129320 Bel Fuse 0553-0013-SC RX &TX: 1:2CT 1:1.15 Pulse Engineering PE-65565 1.5 kV through-hole, dual Bel Fuse 0553-0013-7J RX &TX: E1 (75 & 120 Ω) 1:2CT 1:1.26 1:1 Pulse Engineering PE-65566 1.5 kV through-hole, dual Bel Fuse 0553-0013-8J RX &TX: 1:2CT 1:1.15 Pulse Engineering PE-65765 1.5 kVsurface-mount, dual Bel Fuse S553-0013-06 RX &TX: E1 (75 & 120 Ω) 1:2CT 1:1.26 1:1 Pulse Engineering PE-65766 1.5 kV surface-mount, dual Bel Fuse S553-0013-07 RX : T1 & E1 1:2CT Pulse Engineering PE-65835 3 kV through-hole, single EN60950, EN41003 approved TX: E1 (75 & 120 Ω ) 1:1.26 1:1 Pulse Engineering PE-65839 3 kV through-hole, single EN60950, EN41003 approved Table A3. Recommended Transformers For The CS61535A CS61535A

34 DS40F2

• Socketed Line Interface Device
• All Required Components for Complete Line Interface Evaluation
• Configuration by DIP Switch or Serial Interface
• LED Status Indicators for Alarm Conditions
• Support for Host, Hardware, and Extended Hardware Modes General Description The evaluation board includes a socketed line interface device and all support components necessary for evaluation. The board is powered by an external 5 Volt supply. The board may be configured for 100 Ω twisted-pair T1, 75 Ω coax E1, or 120 Ω twisted-pair E1 operation. Binding posts are provided for line connections. Sev- eral BNC connectors are available to provide system clocks and data I/O. Two LED indicators monitor de- vice alarm conditions. The board supports all line interface operating modes. ORDERING INFORMATION: CDB61534, CDB61535. CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB61304A, CDB61305A SEP ’95 DS40DB3 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 Line Interface Evaluation Board CDB61534, CDB61535, CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB615304A, & CDB61305A ACLKI TCLK TPOS (TDATA) TNEG RNEG (BPV) RPOS (RDATA) RCLK CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A Reset Circuit Mode Select Circuit (TCODE) +5V 0V LED Status Indicators Hardware Control Circuit Serial Interface Control Circuit TTIP TRING RTIP RRING XTL

to the two binding posts labeled +5V and GND. pacitor C2 are used to decouple RV+ to RGND. mit line length selection (LEN2,LEN1,LEN0). and RCODE have no function in Hardware mode. JP1 should not be used in the Hardware mode. JP1 - Connector for external processor in Host operating mode. JP2, JP6, JP7 A-A Extended Hardware operating mode. B-B Hardware or Host operating modes. JP3 IN Hardware or Extended Hardware operating modes. JP4 C-C Connects the ACLKI BNC input to pin 1 of device. D-D Grounds the ACLKI BNC input through 51Ω resistor R1. JP5 E-E Transmit line connection for all applications except those listed for "F-F" on the next line. F-F 75Ω coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1. JP8 IN Shorts resistor R2 for all applications except those listed for "OUT" on the next line. OUT Inserts resistor R2 for 75Ω coax E1 applications using the CS61534, 35, 58, 74, or 77. Table 1. Evaluation Board Jumper Settings

36 DS40DB3

Figure 1. Evaluation Board Schematic

has detected a loss of signal. line interface is configured using DIP switch S2. used in Extended Hardware mode. has detected a loss of signal. if any S2 switch, other than CLKE, is closed. nector and TNEG is not used. Figure 1. The signal is available at the TTIP and

38 DS40DB3

The evaluation board supports 100Ω twisted-pair T1, 75Ω coax E1, and 120Ω twisted-pair E1 op- eration. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The CDB61535A, CDB6158A, CDB61574A, CDB61575, CDB61304A, and CDB61305A are supplied with a 1:1.15 transmit transformer in- stalled for T1 applications. An additional 1:1:1.26 transformer for E1 applications is provided with the board. This transformer requires JP5 to be jumpered across F-F for 75Ω coax E1 applica- tions. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 require the JP8 jumper to be out for 75Ω coax E1 applications. This inserts resistor R2 to reduce the transmit pulse amplitude and meet the 2.37 V nominal pulse amplitude requirement in CCITT G.703. In addition, R2 increases the equivalent load imped- ance across TTIP and TRING. RECEIVE CIRCUIT The receive line interface signal is input at the RTIP and RRING binding posts. The receive sig- nal is transformer coupled to the line interface de- vice through a center-tapped 1:2 transformer. The transformer produces ground referenced pulses of equal amplitude and opposite polarity on RTIP and RRING. The receive line interface is terminated by resis- tors R9 and R10. The evaluation boards are sup- plied from the factory with 200Ω resistors for ter- minating 100Ω T1 twisted-pair lines. Resistors R9 and R10 should be replaced with 240Ω resis- tors for terminating 120Ω E1 twisted-pair lines or 150Ω resistors for terminating 75Ω E1 coaxial lines. Two 243Ω resistors and two 150Ω resistors are included with the evaluation board for this purpose. The recovered clock and data signals are avail- able on BNC outputs labeled RCLK, RPOS(RDA TA), and RNEG(BPV). In the Hard- ware and Host operating modes, data is output on the RPOS(RDA TA) and RNEG(BPV) connectors in dual NRZ format. In the Extended Hardware operating mode, data is output in NRZ format on the RPOS(RDATA) connector and bipolar viola- tions are reported on the RNEG(BPV) connector. QUARTZ CRYSTAL A quartz crystal must be installed in socket Y1 for all devices except the CS6158 and CS6158A. A Crystal Semiconductor CXT6176 crystal is rec- ommended for T1 operation and a CXT8192 is recommended for E1 operation. The evaluation board has a CXT6176 installed at the factory and a CXT8192 is also provided with the board. The CDB6158 and CDB6158A have resistor R13 installed instead of a crystal. This connects the RT pin of the device to the +5 V olt supply. ALTERNATE CLOCK INPUT The ACLKI BNC input provides the alternate clock reference for the line interface device (ACLK for the CS61534) when JP4 is jumpered across C-C. This clock is required for the CS61534, CS61535, CS6158, and CS6158A op- eration but is optional for all other line interface devices. If ACLKI is provided, it may be desir- able to connect both C-C and D-D positions on JP4 to terminate the external clock source provid- ing ACLKI with the 51Ω resistor R1. If ACLKI is optional and not used, connector JP4 should be jumpered across D-D to ground pin 1 of the de- vice through resistor R1. TRANSFORMER SELECTION To permit the evaluation of other transformers, Table 2 lists the transformer and line interface de- vice combinations that can be used in T1 and E1 LINE INTERFACE EVALUATION BOARD DS40DB3 39

applications. A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated on the drawing in Table 2. For exam- ple, the Pulse Engineering PE-65388 transformer may be used with the transmitter of the CS61575 device for 100Ω T1 applications only (as indi- cated by note 3) when installed in transformer socket T1 with pin 1 at position D (upper right). PROTOTYPING AREA A prototyping area with power supply and ground connections is provided on the evaluation board. This area can be used to develop and test a vari- ety of additional circuits like a data pattern gener- ator, CS2180B framer, system synchronizer PLL, or specialized interface logic. EVALUATION HINTS 1. Properly terminate TTIP/TRING when evaluat- ing the transmit output signal. For more informa- tion concerning pulse shape evaluation, refer to the Crystal application note entitled "Measure- ment and Evaluation of Pulse Shapes in T1/E1 Transmission Systems." 2. Change the receiver terminating resistors R9 and R10 when evaluating E1 applications. Resis- tors R9 and R10 should be replaced with 240Ω resistors for terminating 120Ω E1 twisted-pair lines or 150Ω resistors for terminating 75Ω E1 coaxial lines. Two 243Ω resistors and two 150Ω resistors are included with the evaluation board for this purpose. 3. Closing a DIP switch on S2 towards the label sets the device control pin of the same name to logic 1 (+5 V olts). 4. To avoid damage to the external host controller connected to JP1, all S2 switch positions (except CLKE) should be open. In the Host operating mode, the CLKE switch selects the active edge of SCLK and RCLK. LINE INTERFACE EVALUATION BOARD

40 DS40DB3

1. A letter at the intersection of a row and column in T able 2 indicates

that the selected transformer is supported for use with the device. sitioned to match the letter illustrated in the drawing to the left.

1. The receive transformer (RX) is soldered at location T2 on the

board and may be changed according to the application.

1. For use in 100Ω T1 twisted-pair applications only.
2. For use in 75Ω and 120Ω E1 applications only. Place jumper JP5

in position F-F for 75Ω E1 applications requiring a 1:1 turns ratio.

1. Transmitter return loss improves when using a 1:2 turns ratio trans-

former with the appropriate transmit resistors. Table 2. Transformer Applications

Figure 2. Silk Screen Layer (NOT TO SCALE)

42 DS40DB3

Figure 3. Top Ground Plane Layer (NOT TO SCALE)

Figure 4. Bottom Trace Layer (NOT TO SCALE)

44 DS40DB3

• Notes •

• Notes •

• Notes •

Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation