CS61304A CIRRUS | Alldatasheet

Document overview

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Technical content

Features

  • Provides Analog Transmission Line Interface for T1 and E1 Applications
  • Provides Line Driver, Jitter Attenuator and Clock Recovery Functions
  • Fully Compliant with AT&T 62411 Stratum 4, Type II Jitter Requirements
  • Low Power Consumption
  • B8ZS/HDB3/AMI Encoder/Decoder
  • 50 mA Transmitter Short-Circuit Current Limiting General Description The CS61304A combines the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. The CS61304A is a pin-compatible replacement for the LXT304A. The receiver uses a digital Delay-Locked-Loop which is continuously calibrated from a crystal reference to pro- vide excellent stability and jitter tolerance. The CS61304A has a receiver jitter attenuator optimized for T1 CPE applications subject to AT&T 62411 and E1 ISDN PRI applications. The transmitter features inter- nal pulse shaping and a low impedance output stage allowing the use of external resistors for transmitter im- pedance matching.

Applications

  • Primary Rate ISDN Network/Termination Equipment
  • Channel Service Units

ORDERING INFORMATION

See page 31. MAY 96 DS156PP2 Crystal Semiconductor Corporation P. O. Box 17847, Austin, Texas, 78760 (512) 445-7222 FAX:(512) 445-7581 T1/E1 Line Interface TTIP TCLK RRING RTIP TRING TGND CONTROL LINE RECEIVER LINE DRIVER RCLK LLOOP (SCLK) (INT) LEN0 (SDI) LEN1 (SDO) LEN2 (CLKE) TAOS MODE TPOS [TDATA] RPOS [RDATA] RNEG [BPV] TNEG [TCODE] MTIP [RCODE] DPM [AIS] LOS RV+ RGND MRING [PCS] XTALIN XTALOUT ACLKI ( ) = Pin Function in Host Mode [ ] = Pin Function in Extended Hardware Mode RLOOP (CS) R E M O T E L O O P B A C K AMI, B8ZS, HDB3, CODER JITTER ATTENUATOR L O C A L L O O P B A C K CLOCK & DATA RECOVERY SIGNAL QUALITY MONITOR DRIVER MONITOR PULSE SHAPER TV+ Copyright  Crystal Semiconductor Corporation 1996 (All Rights Reserved) CS61304A This document contains information for a new product. Crystal Semiconductor reserves the right to modify this product without notice. Preliminary Product Information Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) http://www.cirrus.com CS61304A T1/E1 Line Interface SEP ‘05 DS156F1

(referenced to RGND=TGND=0V) RV+ TV+ 6.0 (RV+) + 0.3 V V Input Voltage, Any Pin (Note 1) Vin RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) Iin -10 mA Ambient Operating Temperature TA -40 Storage Temperature Tstg -65 150 WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. RECOMMENDED OPERATING CONDITIONS Parameter Symbol Min Typ Max Units DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 V Ambient Operating Temperature TA -40 Power Consumption (Notes 4,5) PC 350 mW Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and load. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 5. Assumes 100% ones density, 5.25 V, LEN2/1/0=1/1/1, a 100 Ω load and a 1:1.15 transformer. DIGITAL CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Symbol Min Typ Max Units High-Level Input Voltage (Notes 6, 7) PINS 1-4, 17, 18, 23-28 VIH 2.0 V Low-Level Input Voltage (Notes 6, 7) PINS 1-4, 17, 18, 23-28 VIL 0.8 V High-Level Output Voltage (Notes 6, 7, 8) IOUT = -400 µA PINS 6-8, 11, 12, 25 VOH 2.4 V Low-Level Output Voltage (Notes 6, 7, 8) IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 VOL 0.4 V Input Leakage Current (Except Pin 5) ±10 µA Low-Level Input Voltage, PIN 5 VIL 0.2 V High-Level Input Voltage, PIN 5 VIH (RV+) - 0.2 V Mid-Level Input Voltage, PIN 5 (Note 9) VIM 2.3 2.7 V Notes: 6. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate digital output. 7. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40µA). 8. Output drivers will drive CMOS logic levels into a CMOS load. 9. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating. CS61304A DS156PP2 CS61304A DS156F1

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Transmitter AMI Output Pulse Amplitudes (Note 10) E1, 75 Ω (Note 11) E1, 120 Ω (Note 12) T1, FCC Part 68 (Note 13) T1, DSX-1 (Note 14) 2.14 2.7 2.7 2.4 2.37 3.0 3.0 3.0 2.6 3.3 3.3 3.6 V V V V E1 Zero (space) level (LEN2/1/0 = 0/0/0) 1:1 transformer and 75Ω load 1:1.26 transformer and 120Ω load -0.237 -0.3 0.237 0.3 V V Load Presented To Transmitter Output (Note 10) Ω Jitter Added by the Transmitter (Note 15) 10Hz - 8kHz 8kHz - 40kHz 10Hz - 40kHz Broad Band 0.01 0.025 0.025 0.05 UI UI UI UI Power in 2kHz band about 772kHz (Notes 10, 16) 12.6 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 10, 16) (referenced to power in 2kHz band at 772kHz) -29 -38 dB Positive to Negative Pulse Imbalance (Notes 10, 16) T1, DSX-1 E1 amplitude at center of pulse E1 pulse width at 50% of nominal amplitude 0.2 0.5 dB E1 Transmitter Return Loss (Notes 10, 16, 17) 51 kHz to 102 kHz 102 kHz to 2.048 MHz 2.048 MHz to 3.072 MHz dB dB dB E1 Transmitter Short Circuit Current (Notes 10, 18) mA RMS Notes: 10. Using a 0.47 µF capacitor in series with the primary of a transformer recommended in the Applications Section. 11. Pulse amplitude measured at the output of a 1:1 transformer across a 75 Ω load for line length setting LEN2/1/0 = 0/0/0. 12. Pulse amplitude measured at the output of a 1:1.26 transformer across a 120 Ω load for line length setting LEN2/1/0 = 0/0/0 or at the output of a 1:1 transformer across a 120 Ω load for LEN2/1/0=0/0/1. 13. Pulse amplitude measured at the output of a 1:1.15 transformer across a 100 Ω load for line length setting LEN2/1/0 = 0/1/0. 14. Pulse amplitude measured at the DSX-1 Cross-Connect across a 100 Ω load for all line length settings from LEN2/1/0 = 0/1/1 to LEN2/1/0 = 1/1/1 using a 1:1.5 transformer. 15. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 16. Not production tested. Parameters guaranteed by design and characterization. 17. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0 and a 1:2 transformer with two 9.4 Ω series resistors terminated by a 75Ω load, or for LEN2/1/0 = 0/0/1 with a 1:2 transformer and two 15 Ω series resistors terminated by a 120Ω load. 18. Measured broadband through a 0.5 Ω resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0 or 0/0/1with a 1:2 transformer and the series resistors specified in Table A1. CS61304A DS156PP2 CS61304A DS156F1

ANALOG SPECIFICATIONS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V) Parameter Min Typ Max Units Receiver RTIP/RRING Input Impedance 50k Ω Sensitivity Below DSX (0dB = 2.4V) -13.6 500 dB mV Data Decision Threshold T1, DSX-1 (Note 19) T1, DSX-1 (Note 20) T1, FCC Part 68 and E1 (Note 21) % of peak % of peak % of peak Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 22) 10kHz - 100kHz 2kHz 10Hz and below 0.4 6.0 300 UI UI UI Loss of Signal Threshold (Note 23) 0.25 0.30 0.50 V Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Notes 16, 24) Hz Attenuation at 10kHz Jitter Frequency (Notes 16, 24) dB Attenuator Input Jitter Tolerance (Notes 16, 24) (Before Onset of FIFO Overflow or Underflow Protection) 138 UI Notes: 19. For input amplitude of 1.2 Vpk to 4.14 Vpk. 21. For input amplitude of 1.05 Vpk to 3.3 Vpk. 22. Jitter tolerance increases at lower frequencies. See Figure 11. 23. The analog input squelch circuit shall operate when the input signal amplitude above ground on the RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low. 24. Attenuation measured with input jitter equal to 3/4 of measured jitter tolerance. Circuit attenuates jitter at 20 dB/decade above the corner frequency. See Figure 12. Output jitter can increase significantly when more than 138 UI’s are input to the attenuator. See discussion in the text section. CS61304A DS156PP2 CS61304A DS156F1

E1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 25) fc 8.192000 MHz TCLK Frequency ftclk 2.048 MHz TCLK Pulse Width (Note 26) tpwh2 150 340 ns ACLKI Duty Cycle tpwh3/tpw3 ACLKI Frequency (Note 27) faclki 2.048 MHz RCLK Duty Cycle (Note 28) tpwh1/tpw1 Rise Time, All Digital Outputs (Note 29) tr ns Fall Time, All Digital Outputs (Note 29) tf ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 ns RPOS/RNEG Valid Before RCLK Falling (Note 30) tsu1 100 194 ns RDATA Valid Before RCLK Falling (Note 31) tsu1 100 194 ns RPOS/RNEG Valid Before RCLK Rising (Note 32) tsu1 100 194 ns RPOS/RNEG Valid After RCLK Falling (Note 30) th1 100 194 ns RDATA Valid After RCLK Falling (Note 31) th1 100 194 ns RPOS/RNEG Valid After RCLK Rising (Note 32) th1 100 194 ns T1 SWITCHING CHARACTERISTICS (TA = -40°C to 85°C; TV+, RV+ = 5.0V ±5%; GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter Symbol Min Typ Max Units Crystal Frequency (Note 25) fc 6.176000 MHz TCLK Frequency ftclk 1.544 MHz TCLK Pulse Width (Note 26) tpwh2 150 500 ns ACLKI Duty Cycle tpwh3/tpw3 ACLKI Frequency (Note 27) faclki 1.544 MHz RCLK Duty Cycle (Note 28) tpwh1/tpw1 Rise Time, All Digital Outputs (Note 29) tr ns Fall Time, All Digital Outputs (Note 29) tf ns TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 ns TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 ns RPOS/RNEG Valid Before RCLK Falling (Note 30) tsu1 150 274 ns RDATA Valid Before RCLK Falling (Note 31) tsu1 150 274 ns RPOS/RNEG Valid Before RCLK Rising (Note 32) tsu1 150 274 ns RPOS/RNEG Valid After RCLK Falling (Note 30) th1 150 274 ns RDATA Valid After RCLK Falling (Note 31) th1 150 274 ns RPOS/RNEG Valid After RCLK Rising (Note 32) th1 150 274 ns Notes: 25. Crystal must meet specifications described in CXT6176/CXT8192 data sheet. 26. The transmitted pulse width does not depend on the TCLK duty cycle. 27. ACLKI provided by an external source or TCLK. 28. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 29. At max load of 1.6 mA and 50 pF. 30. Host Mode (CLKE = 1). 31. Extended Hardware Mode. 32. Hardware Mode, or Host Mode (CLKE = 0). CS61304A DS156PP2 CS61304A DS156F1

A1-A3 of the Applications section. determined by the operating mode. (see Table 2). Table 1. Differences Between Operating Modes Table 2. Pin Definitions

Figure 7. Overview of Operating Modes

CCITT G.703 pulse shapes may be selected. "line length select" inputs as shown in Table 3. based upon the "line length" selection made. length selections LEN2/1/0 = 0/0/0 and 0/0/1. must adjust to the new frequency. Figure 8. Typical Pulse Shape at DSX-1 Cross Connect Table 3. Line Length Selection

or ALBO (Automatic Line Build Out) circuits. Figure 9. Mask of the Pulse at the 2048 kbps Interface primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications

interrupt will be issued on INT (unless disabled). periods with no more than 15 consecutive zeros. ously available from both the register and pin 12. recovered clock and the ACLKI reference clock. Table 6. RCLK Status at LOS Table 5. Data Output/Clock Relationship

62411 Requirements

Figure 12. Typical Jitter Transfer Function

ous ones are transmitted at the TCLK frequency. when local loopback is in effect. curs in response to RLOOP going high. back modes is not valid (see Reset).

  1. Logic 1 indicates that Loopback or All Ones

Table 7. Interaction of RLOOP with TAOS

ance or the performance of a neighboring driver. RCODE pins as shown in Table 8. clock for the transmitter is provided by TCLK. Table 8. Encoder/Decoder Selection

or DPM will be prevented from occurring. Table 10. Input Data Register Table 11. Output Data Bits 0 - 4 0 Reset has occurred or no program input.

0 RLOOP in effect

1 DPM changed state since last "clear DPM"

0 LOS changed state since last "clear LOS"

1 LOS and DPM have changed state since

last "clear LOS" and "clear DPM". Table 12. Coding for Serial Output bits 5,6,7

The device operates from a single +5 Volt supply. Separate pins for transmit and receive supplies provide internal isolation. These pins should be connected externally near the device and decou- pled to their respective grounds. TV+ must not exceed RV+ by more than 0.3V. Decoupling and filtering of the power supplies is crucial for the proper operation of the analog cir- cuits in both the transmit and receive paths. A 1.0 µF capacitor should be connected between TV+ and TGND, and a 0.1 µF capacitor should be con- nected between RV+ and RGND. Use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. A 68 µF tantalum capacitor should be added close to the RV+/RGND supply. Wire-wrap bread- boarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2 CS61304A DS156PP2 CS61304A DS156F1

RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 Volts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than 0.3 V. Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or

2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying

XTALIN, Pin 9 to RV+ through a 1 kΩ resistor, and floating XTALOUT, Pin 10. Overdriving the oscillator with an external clock is not supported. Control ACLKI - Alternate External Clock Input, Pin 1. A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground. During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor. CS61304A DS156PP2 CS61304A DS156F1

LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. Also controls the receiver slicing level and the line code in Extended Hardware Mode. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial control port is used to control the line interface and determine its status. Grounding the MODE pin puts the line interface in the Hardware Mode, where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 V selects the Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Data for the on-chip register. Sampled on the rising edge of SCLK. SDO - Serial Data Output, Pin 25. (Host Mode) Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output. CS61304A DS156PP2 CS61304A DS156F1

TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RCLK - Recovered Clock, Pin 8. The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data and clock are recovered and output on RCLK and RPOS/RNEG or RDATA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) Transmitter NRZ input data which passes through the line code encoder, and is then driven on to the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted. CS61304A DS156PP2 CS61304A DS156F1

TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 75 Ω load between TTIP and TRING. A transformer is required as shown in Table A1. Status AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. LOS returns low when 3 ones are received within 32 bit periods with no more than 15 consecutive zeros. When in the loss of signal state RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the Host mode is used, and the monitor is not used, writing a 1 to the "clear DPM" bit will prevent an interrupt from the driver performance monitor. CS61304A DS156PP2 CS61304A DS156F1

D B A L C 13.72 14.22 0.540 0.560 36.45 1.02 0.36 0.51 3.94 3.18 0.20 15.24 37.21 1.65 0.56 1.02 5.08 3.81 0.38 15° 1.435 0.040 0.014 0.020 0.155 0.125 0.600 0.008 1.465 0.065 0.022 0.040 0.200 0.150 0.015 15° 15.87 0.625 2.41 2.67 0.095 0.105 C eA D B SEATING PLANE A L NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. NOM 13.97 36.83 1.27 0.46 0.76 4.32 0.25 2.54 NOM 0.550 1.450 0.050 0.018 0.030 0.170 0.010 0.100 eA E D D2/E2 28-pin PLCC D2/E2 MAX MIN MAX MIN MILLIMETERS INCHES DIM A 4.57 4.20 0.180 0.165 D/E 12.32 12.57 0.485 0.495 B 0.53 0.33 0.021 0.013 e A B e 2.29 0.090 11.43 11.58 0.450 0.456 9.91 10.92 0.390 0.430 1.19 1.35 0.047 0.053 NOM 4.45 12.45 0.41 2.79 11.51 10.41 1.27 NOM 0.175 0.490 0.016 0.110 0.453 0.410 0.050 3.04 0.120 D1/E1 CS61304A DS156PP2 CS61304A DS156F1

Figures A1-A3 show typical T1 and E1 line inter- face application circuits. Table A1 shows the external components which are specific to each application. Figure A1 illustrates a T1 interface in the Host Mode. Figure A2 illustrates a 120 Ω E1 interface in the Hardware Mode. Figure A3 illus- trates a 75 Ω E1 interface in the Extended Hardware Mode. Control Monitor Frame Format Encoder/ Decoder CS61304A IN HOST MODE µP Serial Port RECEIVE LINE TRANSMIT LINE XTL RV+ 68 µF RGND 0.1 µF +5V 1.0 µF TGND RV+ TV+ CLKE ACLKI LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND SCLK CS INT SDI SDO RTIP RRING MTIP MRING TRING TTIP 0.47 µF 1:1.15 PE-65388 2CT:1 PE-65351 +5V 100 k Ω Figure A1. T1 Host Mode Configuration Frequency MHz Crystal XTL Cable Ω R1 and R2 Ω LEN2/1/0 Transmit Transformer R3 and R4 Ω Typical TX Return Loss dB 1.544 (T1) CXT6176 100 200 0/1/1 - 1/1/1 1:1.15 1:2 1:2.3 9.4 9.4 0.5 2.048 (E1) CXT8192 120 240 0/0/0 0/0/0 0/0/1 0/0/1 1:1.26 1:2 1:1 1:2 8.7 0.5 0.5 150 0/0/0 0/0/0 0/0/1 0/0/1 1:1 1:2 1:1 1:2 9.4 14.3 0.5 Table A1. External Component Values CS61304A DS156PP2

68 µF RGND 0.1 µF +5V + 1.0 µF TGND RV+ TV+ TAOS ACLKI RLOOP LLOOP MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND TGND LEN0 LEN1 LEN2 RTIP RRING MTIP MRING TRING TTIP 0.47 µF 1:1.26 PE-65389 2CT:1 PE-65351 LOS DPM Figure A2. 120 Ω, E1 Hardware Mode Configuration Control Monitor Frame Format Encoder/ Decoder CS61304A IN EXTENDED HARDWARE MODE Line Length Setting RECEIVE LINE TRANSMIT LINE XTL 68 µF RGND 0.1 µF +5V + 1.0 µF TGND RV+ TV+ RCODE PCS BPV TAOS MODE RDATA RCLK TDATA TCLK XTALIN XTALOUT RGND TGND LEN0 LEN1 LEN2 RTIP RRING TRING TTIP 0.47 µF 1:1 PE-65389 2CT:1 PE-65351 ACLKI RLOOP LLOOP LOS AIS TCODE Figure A3. 75 Ω, E1 Extended Hardware Mode Configuration CS61304A DS156PP2

The receiver transformer has a grounded center tap on the IC side. Resistors between the RTIP and RRING pins to ground provide the termina- tion for the receive line. The transmitter transformer matches the 75 Ω transmitter output impedance to the line imped- ance. Figures A1-A3 show a 0.47 µF capacitor in series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting in a DC current through the transformer primary. This current might satu- rate the transformer producing an output offset level shift. Transformers Recommended transmitter and receiver trans- former specifications are shown in Table A2. The transformers in Table A3 are recommended for use with the CS61304A. Refer to the "Telecom Transformer Selection Guide" for detailed sche- matics which show how to connect the line interface IC with a particular transformer. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the jitter attenuator. It is rec- ommended that the Crystal Semiconductor CXT6176 crystal be used for T1 applications and the CXT8192 crystal be used for E1 applications. Designing for AT&T 62411 For additional information on the requirements of AT&T 62411 and the design of an appropriate system synchronizer, please refer to the Crystal Semiconductor Application Notes: "AT&T 62411 Design Considerations – Jitter and Synchroniza- tion" and "Jitter Testing Procedures for Compliance with AT&T 62411". Transmit Side Jitter Attenuation In some applications it is desirable to attenuate jitter from the signal to be transmitted. A CS61304A in local loopback mode can be used as a jitter attenuator. The inputs to the jitter at- tenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK. Line Protection Secondary protection components can be added to provide lightning surge and AC power-cross immunity. Refer to the "Telecom Line Protection Application Note" for detailed information on the different electrical safety standards and specific application circuit recommendations. Parameter Receiver Transmitter Turns Ratio 1:2 CT ± 5% 1:1 ± 1.5 % for 75 Ω E1 1:1.15 ± 5 % for 100 Ω T1 1:1.26 ± 1.5 % for 120 Ω E1 Primary Inductance 600 µH min. @ 772 kHz 1.5 mH min. @ 772 kHz Primary Leakage Inductance 1.3 µH max. @ 772 kHz 0.3 µH max. @ 772 kHz Secondary Leakage Inductance 0.4 µH max. @ 772 kHz 0.4 µH max. @ 772 kHz Interwinding Capacitance 23 pF max. 18 pF max. ET-constant 16 V-µs min. for T1 12 V-µs min. for E1 16 V-µs min. for T1 12 V-µs min. for E1 Table A2. Transformer Specifications CS61304A DS156PP2

Interfacing The CS61304A With the CS62180B T1 Transceiver To interface with the CS62180B, connect the de- vices as shown in Figure A4. In this case, the line interface and CS62180B are in Host Mode con- trolled by a microprocessor serial interface. If the line interface is used in Hardware Mode, then the line interface RCLK output must be inverted be- fore being input to the CS62180B. If the CS61304A is used in Extended Hardware Mode, the RCLK output does not have to be inverted be- fore being input to the CS62180B. Application Turns Ratio(s) Manufacturer Part Number Package Type RX: T1 & E1 1:2CT Pulse Engineering PE-65351 1.5 kV through-hole, single Schott 67129300 Bel Fuse 0553-0013-HC TX: 1:1.15 Pulse Engineering PE-65388 1.5 kV through-hole, single Schott 67129310 Bel Fuse 0553-0013-RC TX: E1 (75 & 120 Ω) 1:1.26 1:1 Pulse Engineering PE-65389 1.5 kV through-hole, single Schott 67129320 Bel Fuse 0553-0013-SC RX &TX: 1:2CT 1:1.15 Pulse Engineering PE-65565 1.5 kV through-hole, dual Bel Fuse 0553-0013-7J RX &TX: E1 (75 & 120 Ω) 1:2CT 1:1.26 1:1 Pulse Engineering PE-65566 1.5 kV through-hole, dual Bel Fuse 0553-0013-8J RX &TX: 1:2CT 1:1.15 Pulse Engineering PE-65765 1.5 kVsurface-mount, dual Bel Fuse S553-0013-06 RX &TX: E1 (75 & 120 Ω) 1:2CT 1:1.26 1:1 Pulse Engineering PE-65766 1.5 kV surface-mount, dual Bel Fuse S553-0013-07 RX : T1 & E1 1:2CT Pulse Engineering PE-65835 3 kV through-hole, single EN60950, EN41003 approved TX: E1 (75 & 120 Ω) 1:1.26 1:1 Pulse Engineering PE-65839 3 kV through-hole, single EN60950, EN41003 approved Table A3. Recommended Transformers ACLK TCLK RCLK RPOS RNEG TPOS TNEG CS62180B CLKE SCLK INT SDO SDI TCLK TPOS TNEG RNEG RPOS RCLK SCLK SDO SDI TO HOST CONTROLLER 100k

1.544 MHz

Figure A4. Interfacing the CS61304A with a CS62180B (Host Mode) CS61304A DS156PP2

  • Notes • CS61304A DS156F1

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

REVISION HISTORY

-40 to +85 °C Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS61304A-IL 225 °C

365 Days

Updated device ordering info. Updated legal notice. Added MSL data.. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

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