CS5530-IS

DATASHEET SEARCH SITE | WWW.ALLDATASHEET.COM

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 36

Technical content

Copyright  Cirrus Logic, Inc. 2009 (All Rights Reserved)http://www.cirrus.com CS5530 24-bit ADC with Ultra-low-noise Amplifier Features & Description Chopper-stabilized Instrumentation Amplifier, 64X

• 12 nV/√Hz @ 0.1 Hz (No 1/f noise)
• 1200 pA Input Current Digital Gain Scaling up to 40x Delta-sigma Analog-to-digital Converter
• Linearity Error: 0.0015% FS
• Noise Free Resolution: Up to 19 bits Scalable VREF Input: Up to Analog Supply Simple Three-wire Serial Interface
• SPI™ and Microwire™ Compatible
• Schmitt-trigger on Serial Clock (SCLK) Onboard Offset and Gain Calibration Registers Selectable Word Rates: 6.25 to 3,840 Sps Selectable 50 or 60 Hz Rejection Power Supply Configurations
• VA+ = +5 V; VA- = 0 V; VD+ = +3 V to +5 V
• VA+ = +2.5 V; VA- = -2.5 V; VD+ = +3 V to +5 V
• VA+ = +3 V; VA- = -3 V; VD+ = +3 V General Description The CS5530 is a highly integrated ΔΣ Analog-to-Digital Converter (ADC) which uses charge-balance techniques to achieve 24-bit performance. The ADC is optimized for measuring low-level unipolar or bipolar signals in weigh scale, process control, scientific, and medical applications. To accommodate these applications, the ADC includes a very-low-noise, chopper- stabilized instrumentation amplifier (12 nV/√Hz @ 0.1 Hz) with a gain of 64X. This device also includes a fourth-order ΔΣ modulator fol- lowed by a digital filter which provides twenty selectable output word rates of 6.25, 7.5, 12.5, 15, 25, 30, 50, 60, 100, 120, 200, 240, 400, 480, 800, 960, 1600, 1920, 3200, and 3840 Sps (MCLK = 4.9152 MHz). To ease communication between the ADC and a micro- controller, the converter includes a simple three-wire se- rial interface which is SPI and Microwire compatible with a Schmitt-trigger input on the serial clock (SCLK). High dynamic range, programmable output rates, and flexible power supply options make this device an ideal solution for weigh scale and process control applications.

ORDERING INFORMATION

See page 35. VA+ C1 C2 VREF+ VREF- VD+ DIFFERENTIAL 4TH ORDER ΔΣ MODULATOR PROGRAMMABLE SINC FIR FILTER AIN1+ AIN1- SERIAL INTERFACE LATCH CLOCK GENERATOR CALIBRATION SRAM/CONTROL LOGIC DGND CS SDI SDO SCLK OSC2OSC1A1A0VA- 64X MAY ‘09 DS742F2

2 DS742F2

4 DS742F2

1. CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARCTERISTICS (VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MHz; OWR (Output Word Rate) = 60 Sps; Bipolar Mode) (See Notes 1 and 2.) Notes: 1. Applies after system calibration at any temperature within -40 °C to +85 °C. 2. Specifications guaranteed by design, charac terization, and/or test. LSB is 24 bits. 3. This specification applies to the device only and does not include any effects by external parasitic thermocouples. 4. Drift over specified temperature range after calibration at power-up at 25 °C. Parameter CS5530-CS UnitMin Typ Max Accuracy Linearity Error - ±0.0015 ±0.003 %FS No Missing Codes 24 - - Bits Bipolar Offset - ±16 ±32 LSB Unipolar Offset - ±32 ±64 LSB 24 Offset Drift (Notes 3 and 4) - 10 - nV/°C Bipolar full-scale Error - ±8 ±31 ppm Unipolar full-scale Error - ±16 ±62 ppm full-scale Drift (Note 4) - 2 - ppm/°C

ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) Notes: 5. See the section of the data sheet which discusses input models. 6. Input current on VREF+ or VREF- may increase to 250 nA if operated within 50 mV of VA+ or VA-. This is due to the rough charge buffer being saturated under these conditions. Parameter Min Typ Max Unit Analog Input Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode (VA-) + 1.6 - (VA+) - 1.6 V CVF Current on AIN+ or AIN- - 1200 - pA Input Current Noise - 1 - pA/ √Hz Open Circuit Detect Current 100 300 - nA Common Mode Rejection DC 50, 60 Hz 130 120 dB dB Input Capacitance - 10 - pF Voltage Reference Input Range (VREF+) - (VREF-) 1 2.5 (VA+)-(VA-) V CVF Current (Note 5, 6) - 50 - nA Common Mode Rejection DC 50, 60 Hz 120 120 dB dB Input Capacitance 11 - 22 pF System Calibration Specifications Full-scale Calibration Range Bi polar/Unipolar Mode 3 - 110 %FS Offset Calibration Range Bipolar Mode -100 - 100 %FS Offset Calibration Range Unipolar Mode -90 - 90 %FS

6 DS742F2

ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) 7. All outputs unloaded. All input CMOS levels. 8. Tested with 100 mV change on VA+ or VA-. TYPICAL NOISE-FREE RESOLUTION (BITS) (See Notes 9 and 10) 9. Noise Free Resolution listed is for Bipolar operation, and is calculated as LOG((Input Span)/(6.6xRMS Noise))/LOG(2) rounded to the nearest bit. For Unipolar operation, the input span is 1/2 as large, so one bit is lost. The input span is calculated in the analog input span section of the data sheet. The Noise Free Resolution table is computed with a value of 1.0 in the gain register. Values other than 1.0 will scale the noise, and change the Noise Free Resolution accordingly. 10. “Noise Free Resolution” is not the same as “Effective Resolution”. Effective Resolution is based on the RMS noise value, while Noise Free Resolution is based on a peak-to-peak noise value specified as 6.6 times the RMS noise value. Effective Resolution is calculated as LOG((Input Span)/(RMS Noise))/LOG(2). Specifications are subject to change without notice. Parameter CS5530-CS Min Typ Max Unit Power Supplies DC Power Supply Currents (Normal Mode) I A+, IA- ID+ 0.6 1.0 mA mA Power Consumption Normal Mode (Note 7) Standby Sleep 500 mW mW µW Power Supply Rejection (Note 8) DC Positive Supplies DC Negative Supply 115 115 dB dB Output Word Rate (Sps) -3 dB Filter Frequency (Hz) Noise-free Bits Noise (nV rms) 7.5 1.94 19 17 15 3.88 19 24 30 7.75 18 34 60 15.5 18 48 120 31 17 68 240 62 16 115 480 122 16 163 960 230 15 229 1,920 390 15 344 3,840 780 13 1390

5 V DIGITAL CHARACTERISTICS

(VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 11.)

3 V DIGITAL CHARACTERISTICS

(TA = 25 °C; VA+ = 5V ±5%; VD+ = 3.0V±10%; VA-, DGND = 0V; See Notes 2 and 11.) 11. All measurements performed under static conditions. Parameter Symbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLK SCLK VIH 0.6 VD+ (VD+) - 0.45 VD+ VD+ V Low-Level Input Voltage All Pins Except SCLK SCLK VIL 0.0 0.0 -0 . 8 0.6 V High-Level Output Voltage A0 and A1, I out = -1.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 1.0 (VD+) - 1.0 --V Low-Level Output Voltage A0 and A1, I out = 1.0 mA SDO, Iout = 5.0 mA VOL - - (VA-) + 0.4 0.4 V Input Leakage Current I in -± 1 ± 1 0 µ A SDO 3-State Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9-p F Parameter Symbol Min Typ Max Unit High-Level Input Voltage All Pins Except SCLK SCLK VIH 0.6 VD+ (VD+) - 0.45 -V D + VD+ V Low-Level Input Voltage All Pins Except SCLK SCLK VIL 0.0 0.0 -0 . 8 0.6 V High-Level Output Voltage A0 and A1, I out = -1.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 1.0 (VD+) - 1.0 -- V Low-Level Output Voltage A0 and A1, I out = 1.0 mA SDO, Iout = 5.0 mA VOL - - (VA-) + 0.4 0.4 V Input Leakage Current I in -± 1 ± 1 0 µ A SDO 3-State Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9-p F

8 DS742F2

1. The ADCs use a Sinc 5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5 filter followed by a Sinc3 filter for the other OWRs. OWRsinc5 refers to the 3200 Sps (FRS = 1) or 3840 Sps (FRS = 0) word rate associated with the Sinc5 filter. 13. The single conversion mode only outputs fully se ttled conversions. See Table 1 for more details about single conversion mode timing. OWRSC is used here to designate the different conversion time associated with single conversions. 14. The continuous conversion mode ou tputs every conversion. This means that the filter’s settling time with a full-scale step input in the continuous conversion mode is dictated by the OWR. ABSOLUTE MAXIMUM RATINGS (DGND = 0 V; See Note 15.) Notes: 15. All voltages with respect to ground. 16. VA+ and VA- must satisfy {(VA+) - (VA-)} ≤ +6.6 V. 17. VD+ and VA- must sati sfy {(VD+) - (VA-)} ≤ +7.5 V. 18. Applies to all pins including continuous overvo ltage conditions at the analog input (AIN) pins. 19. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 20. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Ratio Unit Modulator Sampling Rate f s MCLK/16 Sps Filter Settling Time to 1/2 LSB (full-scale Step Input) Single Conversion mode (Notes 12, 13, and 14) Continuous Conversion mode, OWR < 3200 Sps Continuous Conversion mode, OWR ≥ 3200 Sps t s ts ts 1/OWRSC 5/OWRsinc5 + 3/OWR 5/OWR s s s Parameter Symbol Min Typ Max Unit DC Power Supplies (Notes 16 and 17) Positive Digital Positive Analog Negative Analog VD+ VA+ VA- -0.3 -0.3 +0.3 +6.0 +6.0 -3.75 V V V Input Current, Any Pin Except Supplies (Notes 18 and 19) I IN -- ± 1 0 m A Output Current I OUT -- ± 2 5 m A Power Dissipation (Note 20) PDN - - 500 mW Analog Input Voltage VREF pins AIN Pins VINR VINA (VA-) -0.3 (VA-) -0.3 (VA+) + 0.3 (VA+) + 0.3 V V Digital Input Voltage V IND -0.3 - (VD+) + 0.3 V Ambient Operating Temperature T A -40 - 85 °C Storage Temperature T stg -65 - 150 °C

(VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF; See Figures 1 and 2.) Notes: 21. Device parameters are specified with a 4.9152 MHz clock. 22. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 23. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. Parameter Symbol Min Typ Max Unit Master Clock Frequency (Note 21) External Clock or Crystal Oscillator MCLK 1 4.9152 5 MHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 22) Any Digital Input Except SCLK SCLK Any Digital Output t rise 1.0 100 µs µs ns Fall Times (Note 22) Any Digital Input Except SCLK SCLK Any Digital Output t fall 1.0 100 µs µs ns Start-up Oscillator Start-up Time XTAL = 4.9152 MHz (Note 23) t ost -2 0- m s Serial Port Timing Serial Clock Frequency SCLK 0 - 2 MHz Serial Clock Pulse Width High Pulse Width Low 250 250 ns ns SDI Write Timing CS Enable to Valid Latch Clock t 3 50 - - ns Data Set-up Time prior to SCLK rising t 4 50 - - ns Data Hold Time After SCLK Rising t 5 100 - - ns SCLK Falling Prior to CS Disable t 6 100 - - ns SDO Read Timing CS to Data Valid t 7 -- 1 5 0 n s SCLK Falling to New Data Bit t 8 -- 1 5 0 n s CS Rising to SDO Hi-Z t 9 -- 1 5 0 n s

10 DS742F2

Figure 1. SDI Write Timing (Not to Scale) Figure 2. SDO Read Timing (Not to Scale)

per second (MCLK = 4.9152 MHz).

2.1 Analog Input

Figure 3 illustrates a block diagram of the CS5530. mentation amplifier with a gain of 64X.

4 Order

3 Serial

Figure 3. Front End Configuration Figure 4. Input Model for AIN+ and AIN- Pins

12 DS742F2

2.1.1 Analog Input Span

applied to the VREF+ and VREF- pins on the part. See section 2.3.4 for more details. verter to set full scales from 1 mV to 40 mV.

2.1.2 Voltage Noise Density Performance

30 Sps OWR, bipolar mo de, and with the input

2.1.3 No Offset DAC

2.2 Overview of ADC Register Structure

on-chip controller’s internal registers. the gain slope of the converter. converter and perform offset and gain calibrations. first 8-bits into the serial port).

2.2.1 System Initialization

The CS5530 provide no pow er-on-reset function. Figure 5. Measured Voltage Noise Density, 64x

register clears the RV bit back to logic 0. tions section lists all valid commands. Figure 6. CS5530 Register Diagram

14 DS742F2

2.2.2 Command Register Descriptions

READ/WRITE OFFSET REGISTER R/W (Read/Write) 0 Write offset register. 1 Read offset register. READ/WRITE GAIN REGISTER R/W (Read/Write) 0 Write gain register. 1 Read gain register. READ/WRITE CONFIGURATION REGISTER Function: These commands are used to read from or write to the configuration register. R/W (Read/Write) 0 Write configuration register. 1 Read configuration register. PERFORM CONVERSION MC (Multiple Conversions) 0 Perform a single conversion. 1 Perform continuous conversions. PERFORM SYSTEM OFFSET CALIBRATION PERFORM SYSTEM GAIN CALIBRATION SYNC1 Function: Part of the serial port re-initialization sequence. D7(MSB) D6 D5 D4 D3 D2 D1 D0

0000 R / W 001

D7(MSB) D6 D5 D4 D3 D2 D1 D0

0000 R / W 010

D7(MSB) D6 D5 D4 D3 D2 D1 D0

0000 R / W 011

D7(MSB) D6 D5 D4 D3 D2 D1 D0

1 M C 000000

D7(MSB) D6 D5 D4 D3 D2 D1 D0 10000101 D7(MSB) D6 D5 D4 D3 D2 D1 D0 10000110 D7(MSB) D6 D5 D4 D3 D2 D1 D0 11111111

Function: End of the serial port re-initialization sequence. NULL Function: This command is used to clear a port flag and keep the converter in the continuous conversion mode. D7(MSB) D6 D5 D4 D3 D2 D1 D0 11111110 D7(MSB) D6 D5 D4 D3 D2 D1 D0 00000000

16 DS742F2

2.2.3 Serial Port Interface

the command and data word timing. the port can function as a three wire interface.

8 SCLKs Clear SDO FlagSDO

details about conversion timing. Figure 7. Command and Data Word Timing

2.2.4 Reading/Writing On-Chip Registers

The CS5530’s offset, gain, and configuration regis- ters are readable and writable while the conversion data register is read only. As shown in Figure 7, to write to a particular regis- ter the user must transmit the appropriate write command and then follow that command by 32 bits of data. For example, to write 0x80000000 (hexa- decimal) to the gain regi ster, the user would first transmit the command byte 0x02 (hexadecimal) followed by the data 0x80000000 (hexadecimal). Similarly, to read a particular register the user must transmit the appropriate read command and then acquire the 32 bits of data. Once a register is written to or read from, the serial port returns to the com- mand mode.

2.3 Configuration Register

To ease the architectural design and simplify the serial interface, the configuration register is thirty- two bits long, however, only fifteen of the thirty two bits are used. The following sections detail the bits in the configuration register.

2.3.1 Power Consumption

The CS5530 accommodates three power consump- tion modes: normal, standby, and sleep. The default mode, “normal mode”, is entered after power is ap- plied. In this mode, the CS5530 typically consumes 35 mW. The other two modes are referred to as the power save modes. They power down most of the analog portion of the chip and stop filter convolu- tions. The power save modes are entered whenever the power down (PDW) bit of the configuration register is set to logic 1. The particular power save mode entered depends on state of the PSS (Power Save Select) bit. If PSS is logic 0, the converter en- ters the standby mode reducing the power con- sumption to 4 mW. The st andby mode leaves the oscillator and the on-chip bias generator for the an- alog portion of the chip active. This allows the con- verter to quickly return to the normal mode once PDW is set back to a logic 0. If PSS and PDW are both set to logic 1, the sleep mode is entered reduc- ing the consumed power to around 500 μW. Since this sleep mode disables the oscillator, approxi- mately a 20 ms oscillator start-up delay period is required before returning to the normal mode. If an external clock is used, there will be no delay.

2.3.2 System Reset Sequence

The reset system (RS) bit permits the user to per- form a system reset. A system reset can be initiated at any time by writing a logic 1 to the RS bit in the configuration register. Af ter the RS bit has been set, the internal logic of the chip will be initialized to a reset state. The reset valid (RV) bit is set indi- cating that the internal logic was properly reset. The RV bit is cleared after the configuration regis- ter is read. The on-chip registers are initialized to the following default states: After reset, the RS bit should be written back to logic 0 to complete the reset cycle. The ADC will return to the command mode where it waits for a valid command. Also, the RS bit is the only bit in the configuration register that can be set when ini- tiating a reset (i.e. a second write command is need- ed to set other bits in the Configuration Register after the RS bit has been cleared).

2.3.3 Input Short

The input short bit allows the user to internally ground the inputs of the ADC. This is a useful func- tion because it allows the user to easily test the grounded input performance of the ADC and elim- inate the noise effects due to the external system components.

2.3.4 Voltage Reference Select

The voltage reference sele ct (VRS) bit selects the size of the sampling capacitor used to sample the voltage reference. The bit should be set based upon Configuration Register: 00000000(H) Offset Register: 00000000(H) Gain Register 01000000(H)

18 DS742F2

VA+ and the VREF- pin can not go below VA-. established before the reference voltage.

2.3.5 Output Latch Pins

2.3.6 Filter Rate Select

early with the clock frequency that is used.

2.3.7 Word Rate Select

picted in the Configurati on Register Descriptions.

2.3.8 Unipolar/Bipolar Select

either a unipolar or bipolar input span.

2.3.9 Open Circuit Detect

source as a means to test for open thermocouples. Figure 8. Input Reference Model when VRS = 1 Figure 9. Input Reference Model when VRS = 0

2.3.10 Configuration Register Description

PSS (Power Save Select)[31] 0 Standby Mode (Oscillator active, allows quick power-up). 1 Sleep Mode (Oscillator inactive). PDW (Power Down Mode)[30]

0 Normal Mode

1 Activate the power save select mode. RS (Reset System)[29] 0 Normal Operation. 1 Activate a Reset cycle. See System Re set Sequence in the datasheet text. RV (Reset Valid)[28]

0 Normal Operation

1 System was reset. This bit is read only. Bit is cleared to logic zero after the configuration register is read. IS (Input Short)[27]

0 Normal Input

1 All signal input pairs for each channel are disco nnected from the pins and shorted internally. NU (Not Used)[26] 0 Must always be logic 0. Reserved for future upgrades. VRS (Voltage Reference Select)[25] 0 2.5 V < V REF ≤ [(VA+) - (VA-)] 11 V ≤ VREF ≤ 2.5V A1-A0 (Output Latch bits)[24:23] The latch bits (A1 and A0) will be set to the logic state of these bits when the Configuration register is written. Note that these logic outputs are powered from VA+ and VA-.

00 A1 = 0, A0 = 0

01 A1 = 0, A0 = 1

10 A1 = 1, A0 = 0

11 A1 = 1, A0 = 1

NU (Not Used)[22:20] 0 Must always be logic 0. Reserved for future upgrades. Filter Rate Select, FRS[19] 0 Use the default output word rates. 1 Scale all output word rates and their correspondi ng filter characteristics by a factor of 5/6. NU (Not Used)[18:15] 0 Must always be logic 0. Reserved for future upgrades. D31(MSB) D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 PSS PDW RS RV IS NU VRS A1 A0 NU NU NU FRS NU NU NU D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9 D 8D 7D 6D 5D 4D 3D 2D 1D 0 NU WR3 WR2 WR1 WR0 UP/BP O C D N UN UN UN UN UN UN UN UN U

20 DS742F2

WR3-WR0 (Word Rate) [14:11] The listed Word Rates are for continuous conversion mode using a 4.9152 MHz clock. All word rates will scale linearly with the clock frequency used. The very first conversion using continuous conversion mode will last longer, as will conversions done with the single conversion mode. See the section on Performing Conversions and Tables 1 and 2 for more details. Bit WR (FRS = 0) WR (FRS = 1) 0000 120 Sps 100 Sps 0001 60 Sps 50 Sps 0010 30 Sps 25 Sps 0011 15 Sps 12.5 Sps 0100 7.5 Sps 6.25 Sps 1000 3840 Sps 3200 Sps 1001 1920 Sps 1600 Sps 1010 960 Sps 800 Sps 1011 480 Sps 400 Sps 1100 240 Sps 200 Sps All other combinations are not used. U/B (Unipolar / Bipolar) [10] 0 Select Bipolar mode. 1 Select Unipolar mode. OCD (Open Circuit Detect Bit) [9] When set, this bit activates a 300 nA current source on the input channel (AIN+) selected by the channel select bits. Note that the 300nA current source is rated at 25°C. This feature is particularly useful in ther- mocouple applications when the user wants to drive a suspected open thermocouple lead to a supply rail. 0 Normal mode. 1 Activate current source. NU (Not Used) [8:0] 0 Must always be logic 0. Reserved for future upgrades.

2.4 Calibration

Calibration is used to set the zero and gain slope of the ADC’s transfer function. The CS5530 provides system calibration. Note: After the ADC is reset, it is functional and can perform measurements without being calibrated (remember that the VRS bit in the configuration register must be properly configured). If the converter is operated without calibraton, the converter will utilize the initialized values of the on-chip registers (Offset = 0.0; Gain = 1.0) to calculate output words. Any initial offset and gain errors in the internal circuitry of the chip will remain.

2.4.1 Calibration Registers

The CS5530 converter has an offset register that is used to set the zero point of the converter’s transfer function. As shown in Offset Register section, one LSB in the offset register is 1.835007966 X 2 -24 proportion of the input span (bipolar span is 2 times the unipolar span, gain register = 1.000...000 deci- mal). The MSB in the offset register determines if the offset to be trimmed is positive or negative (0 positive, 1 negative). No te that the magnitude of the offset that is trimmed from the input is mapped through the gain register. The converter can typi- cally trim ±100 percent of the input span. As shown in the Gain Register section, the gain register spans from 0 to (64 - 2 -24). The decimal equivalent mean- ing of the gain register is where the binary numbers have a value of either zero or one (b D29 is the binary value of bit D29). While gain register se ttings of up to 64 - 2 -24 are available, the gain regist er should never be set to values above 40.

2.4.2 Gain Register

The gain register span is from 0 to (64-2-24). After Reset D24 is 1, all other bits are ‘0’.

2.4.3 Offset Register

One LSB represents 1.835007966 X 2-24 proportion of the input span (bipolar span is 2 times unipolar span). Offset and data word bits align by MSB. After reset, all bits are ‘0’. The offset register is stored as a 32-bit, two’s complement number, where the last 8 bits are all 0. Db D2925 bD2824 bD2723 … bD02 24– )+++ + bDi 2 24– i+() i 0= == Decimal Point MSB D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 NU NU 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7 2-8 0000000100000000 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 2-17 2-18 2-19 2-20 2-21 222 2-23 2-24 0000000000000000 MSB D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 Sign 2-2 2-3 2-4 2-5 2-6 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15 2-16 0000000000000000 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB 2-17 2-18 2-19 2-20 2-21 2-22 2-23 2-24 NU NU NU NU NU NU NU NU 0000000000000000

22 DS742F2

2.4.4 Performing Calibrations

replace the effects from the previous calibration.

2.4.5 System Calibration

illustrates system offset calibration. to the System Calibration Specifications).

2.4.6 Calibration Tips

prematurely halt the calibration cycle. Figure 10. System Calibration of Offset Figure 11. System Calibration of Gain

For maximum accuracy, calibrations should be per- formed for both offset and gain. When the device is used without calibration, the uncalibrated gain accuracy is about ±1 percent. Note that the gain from the offset register to the output is 1.83007966 decimal, not 1. If a user wants to adjust the calibration coefficients externally, they will need to divide the information to be writ- ten to the offset regist er by the scale factor of 1.83007966. (This discussion assumes that the gain is also multiplied by the gain register before being applied to the output conversion words).

2.4.7 Limitations in Calibration Range

System calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. For gain calibration, the full-scale input signal can be reduced to 3% of the nominal full- scale value. At this point, the gain register is ap- proximately equal to 33.33 (decimal). While the gain register can hold numbers all the way up to 64 - 2 -24, gain register sett ings above a decimal value of 40 should not be used. With the convert- er’s intrinsic gain error, this minimum full-scale in- put signal may be higher or lower. In defining the minimum full-scale Calibration Range (FSCR) un- der Analog Characteristics, margin is retained to accommodate the intrinsic gain error. Inversely, the input full-scale signal can be increased to a point in which the modulator reaches its 1’s density limit of 86 percent, which under nominal conditions occurs when the full-scale input signal is 1.1 times the nominal full-scale value. Wi th the chip’s intrinsic gain error, this maximum full-scale input signal maybe higher or lower. In defining the maximum FSCR, margin is again incorporated to accommo- date the intrinsic gain error.

2.5 Performing Conversions

The CS5530 offers two distinctly different conver- sion modes. The paragraphs that follow detail the differences in the conversion modes.

2.5.1 Single Conversion Mode

When the user transmits the perform single conver- sion command, a single, fully settled conversion is performed using the word rate and polarity selec- tions set in the configur ation register. Once the command byte is transmitted, the serial port enters data mode where it wait s until the conversion is complete. When the convers ion data is available, SDO falls to logic 0 to act as a flag to indicate that the data is available. Forty SCLKs are then needed to read the conversion data word. The first 8 SCLKs are used to clear the SDO flag. During the first 8 SCLKs, SDI must be logic 0. The last 32 SCLKs are needed to read the conversion result. Note that the user is forc ed to read the conversion in single conversion mode as the serial port will re- main in data mode until SCLK transitions 40 times. After reading the data, the serial port returns to the command mode, where it waits for a new command to be issued. The single conversion mode will take longer than conversions performed in the continu- ous conversion mode. The number of clock cycles a single conversion takes for each Output Word Rate (OWR) setting is listed in Table 1. The ± 8 (FRS = 0) or ± 10 (FRS = 1) clock ambiguity is due to internal synchronization between the SCLK in- put and the oscillator. Note: In the single conversion mode, more than one conversion is actually performed, but only the final, fully settled result is output to the conversion data register.

24 DS742F2

2.5.2 Continuous Conversion Mode

before the converter returns to command mode. Table 2. The first conversion from the part in con- following conversi ons due to start-up overhead. SCLK input and the oscillator. Table 1. Conversion Timing for Single Mode Table 2. Conversion Timing for Continuous Mode

2.6 Using Multiple ADCs Synchronously

from the same oscillator source. CS5530 devices is shown in Figure 12.

2.7 Conversion Output Coding

The CS5530 outputs 24-bit data conversion words. -VFS to VFS in bipolar mode. Figure 12. Synchronizing Multiple ADCs Table 3. Output Coding

26 DS742F2

2.7.1 Conversion Data Output Descriptions

CS5530 (24-BIT CONVERSIONS) Conversion Data Bits [31:8] These bits depict the latest output conversion. OF (Over-range Flag Bit) [2] 0 Bit is clear when over-range condition has not occurred. 1 Bit is set when input signal is more positive than th e positive full-scale, more negative than zero (unipolar mode) or when the input is more negative than the negative full-scale (bipolar mode). Other Bits [7:3], [1:0] These bits are masked logic zero. D31(MSB) D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 M S B 2 22 12 01 91 8 1 7 1 61 51 41 31 21 11 0 9 8 D 1 5 D 1 4 D 1 3 D 1 2 D 1 1 D 1 0D 9 D 8D 7D 6D 5D 4D 3D 2D 1D 0 7 65432 1 L S B 00000 O F 00

2.8 Digital Filter

60 Sps filter, while Figu res 14 and 15 show the

The converter’s digital fi lters scale with MCLK. Figure 13. Digital Filter Response (Word Rate = 60 Sps) Figure 14. 120 Sps Filter Magnitude Plot to 120 Hz Figure 15. 120 Sps Filter Phase Plot to 120 Hz Figure 16. Z-Transforms of Digital Filters

28 DS742F2

2.9 Clock Generator

2.10 Power Supply Arrangements

dual analog supplies and a single digital supply. sure ground referenced bipolar signals. should not be added externally. Figure 17. On-chip Oscillator Model

2 AIN1-

4.9152 MHz

7 A08 A1

Figure 18. CS5530 Configured with a Single +5 V Supply Figure 19. CS5530 Configured with ±2.5 V Analog Supplies

30 DS742F2

Figure 20. CS5530 Configured with ±3 V Analog Supplies

2.11 Getting Started

This A/D converter has se veral features. From a software programmer’s prospective, what should be done first? To begin, a 4.9152 MHz or 4.096 MHz crystal takes approximately 20 ms to start. To accommodate for this, it is recommended that a software delay of approximately 20 ms be inserted before the start of the processor’s ADC initializa- tion code. Next, since the CS5530 does not provide a power-on-reset function, th e user must first ini- tialize the ADC to a known state. This is accom- plished by resetting the ADC’s serial port with the Serial Port Initializati on sequence. This sequence resets the serial port to the command mode and is accomplished by transm itting 15 SYNC1 com- mand bytes (0xFF hexade cimal), followed by one SYNC0 command (0xFE he xadecimal). Once the serial port of the ADC is in the command mode, the user must reset all the internal logic by performing a system reset sequence (see 2.3.2 System Reset Sequence). After the conve rter is properly reset, the configuration register bits should be configured as appropriate, for exampl e, the voltage reference selection, word rate, signal polarity(unipolar or bi- polar) should be configured. Calibrations or conversions can then be performed as appropriate.

2.12 PCB Layout

For optimal performance, the CS5530 should be placed entirely over an analog ground plane. All grounded pins on the ADC, including the DGND pin, should be connected to the analog ground plane that runs beneath th e chip. In a split-plane system, place the analog-di gital plane split imme- diately adjacent to the digital portion of the chip.

32 DS742F2

1. PIN DESCRIPTIONS Clock Generator OSC1; OSC2 – Master Clock An inverting amplifier inside the chip is connected between these pins and can be used with a crystal to provide the master clock for the devic e. Alternatively, an external (CMOS compatible) clock (powered relative to VD+) can be supplied into the OSC2 pin to provide the master clock for the device. Control Pins and Serial Data I/O CS – Chip Select When active low, the port will recognize SCLK. When high the SDO pin will output a high impedance state. CS should be changed when SCLK = 0. SDI – Serial Data Input SDI is the input pin of the serial input port. Da ta will be input at a rate determined by SCLK. SDO – Serial Data Output SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK – Serial Clock Input A clock signal on this pin determines the input/ output rate of the data for the SDI/SDO pins respectively. This input is a Schmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0 – Logic Output (Analog), A1 – Logic Output (Analog) The logic states of A1-A0 mimic the A1-A0 bits in the Configuration Register. Logic Output 0 = VA-, and Logic Output 1 = VA+. 81 3 VREF+ VREF- SCLK CS DGND VA- VA+ AIN1- AIN1+ 10 11

12 SDO

LOGIC OUTPUT (ANALOG) POSITIVE ANALOG POWER AMPLIFIER CAPACITOR CONNECT AMPLIFIER CAPACITOR CONNECT DIFFERENTIAL ANALOG INPUT CHIP SELECT VOLTAGE REFERENCE INPUT VOLTAGE REFERENCE INPUT SERIAL CLOCK INPUT POSITIVE DIGITAL POWER DIGITAL GROUND SERIAL DATA OUT MASTER CLOCK CS5530 DIFFERENTIAL ANALOG INPUT NC NC SDI VD+NEGATIVE ANALOG POWER MASTER CLOCK LOGIC OUTPUT (ANALOG)

Measurement and Reference Inputs AIN1+, AIN1- – Differ ential Analog Input Differential input pins into the device. VREF+, VREF- – Voltage Reference Input Fully differential inputs which establish the voltage reference for the on-chip modulator. C1, C2 – Amplifier Capacitor Inputs Connections for the instrumentation amplifier’s capacitor. Power Supply Connections VA+ – Positive Analog Power Positive analog supply voltage. VD+ – Positive Digital Power Positive digital supply voltage (nominally +3.0 V or +5 V). VA- – Negative Analog Power Negative analog supply voltage. DGND – Digital Ground Digital Ground. 4. SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the ADC transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full- scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full-scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset the voltage on the AIN- pin). When in bipolar mode (U/B bit = 0). Units are in LSBs.

34 DS742F2

1. PACKAGE DRAWINGS Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the flat section of t he lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN MAX MIN MAX A -- 0.084 -- 2.13 A1 0.002 0.010 0.05 0.25 A2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.272 0.295 6.90 7.50 1 E 0.291 0.323 7.40 8.20 E1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 L 0.025 0.040 0.63 1.03 ∝ 0° 8° 0° 8°

20 PIN SSOP PACKAGE DRAWING

E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

1. ORDERING INFORMATION 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION Model Number Bits Channels Linearity Error (Max) Temperature Range Package CS5530-IS 24 1 ±0.003% -40 °C to +85°C 20-pin 0.2" Plastic SSOP CS5530-ISZ 24 1 ±0.003% -40 °C to +85°C 20-pin 0.2" Plastic SSOP, Lead Free Model Number Peak Reflow Temp MSL Rating Max Floor Life CS5530-IS 240 °C 2 365 Days CS5530-ISZ 260 °C 3 7 Days

36 DS742F2

Revision History

A1 OCT 2006 Advance Release A2 NOV 2006 Updated power consumption values. A3 NOV 2006 Updated noise density plot. A4 NOV 2006 Updated temperature range specification. F1 JAN 2007 Corrected input current on p1 to 1200 pA. Changed temp range to -40 to +85. F2 MAY 2009 Increased input current noise spec. to 1.0 pA / √Hz. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circui ts or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SA FETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANT- ABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, IN- CLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.