CS5526-BP

CS5525_05 CIRRUS | Alldatasheet

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Technical content

Features

zDelta-sigma A/D Converter - Linearity Error: 0.0015%FS - Noise-free Resolution: 18-bits zBipolar/Unipolar Input Ranges - 25 mV, 55 mV, 100 mV, 1 V, 2.5 V and 5 V zChopper Stabilized Instrumentation Amplifier zOn-chip Charge Pump Drive Circuitry z4-bit Output Latch zSimple three-wire serial interface - SPI™ and Microwire™ Compatible - Schmitt Trigger on Serial Clock (SCLK) zProgrammable Output Word Rates - 3.76 Sps to 202 Sps (XIN = 32.768 kHz) - 11.47 Sps to 616 Sps (XIN = 100 kHz) zOutput Settles in One Conversion Cycle zSimultaneous 50/60 Hz Noise Rejection zSystem and Self-calibration with Read/Write Registers zSingle +5 V Analog Supply +3.0 V or +5 V Digital Supply zLow-power Mode Consumption: 4.9 mW - 1.8 mW in 1 V, 2.5 V, and 5 V Input Ranges General Description The 16-bit CS5525 and the 20-bit CS5526 are highly in- tegrated ∆Σ A/D converters which include an instrumentation amplifier, a PGA (programmable gain amplifier), eight digital filters, and self and system cali- bration circuitry. The converters are designed to provide their own nega- tive supply which enables their on-chip instrumentation amplifiers to measure bipolar ground-referenced signals ≤±100 mV. By directly supp lying NBV with -2.5 V and with VA+ at 5 V, ±2.5 V signals (with respect to ground) can be measured. The digital filters provide programmable output update rates between 3.76 Sps to 202 Sps (XIN = 32.768 kHz). Output word rates can be increased by approximately 3X by using XIN = 100 kHz. Each filter is designed to settle to full accuracy for its output update rate in one conver- sion cycle. The filters with word rates of 15 Sps or less (XIN = 32.768 kHz) reject both 50 and 60 Hz ( ±3 Hz) line interference simultaneously. Low power, single conversion settling time, programma- ble output rates, and the ability to handle negative input signals make these single supply products ideal solu- tions for isolated and non-isolated applications.

ORDERING INFORMATION

See page 29. AIN+ AIN- X20 Programmable Gain VA+ AGND VREF+ VREF- VD+ DGND XIN XOUT SDO SDINBV Latch Differential Digital Filter Calibration Register Control Register Output Register 4th Order Delta-Sigma Modulator Calibration Memory Calibration µC Clock Gen. SCLK CS CPD AUG ‘05 DS202F5

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ANALOG CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5 V ±5%; VREF+ = 2.5 V, VREF- = AGND, NBV = -2.1 V, FCLK = 32.768 kHz, OWR (Output Word Rate) = 15 Sps, Bipolar Mode, Input Range = ±100 mV; See Notes 1 and 2.) Notes: 1. Applies after system calibration at any temperature within -40 °C ~ +85 °C. 2. Specifications guaranteed by desi gn, characterization, and/or test. 3. Specification applies to the device only and does not include any effects by external parasitic thermocouples. LSB = LSB16 for the CS5525, and LSB20 for the CS5526. 4. Drift over specified temperature range after calibration at power-up at 25 °C. 5. See the section of the data sheet which discusses input models on page 15. RMS NOISE (Notes 6 and 7) Notes: 6. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25 °C. 7. For Peak-to-Peak Noise multiply by 6.6 for all ranges and output rates. 8. For input ranges <100 mV and output word rate s >60 Sps, 32.768 kHz chopping frequency is used. Specifications are subject to change without notice. Parameter CS5525 CS5526 Min Typ Max Min Typ Max Unit Accuracy Linearity Error - ±0.0015 ±0.003 - ±0.0007 ±0.0015 %FS No Missing Codes 16 - - 20 - - Bits Bipolar Offset (Note 3) - ±1± 2 - ±16 ±32 LSB Unipolar Offset (Note 3) - ±2 ±4- ±32 ±64 LSB Offset Drift (Notes 3 and 4) - 20 - - 20 - nV/°C Bipolar Gain Error - ±8 ±31 - ±8 ±31 ppm Unipolar Gain Error - ±16 ±62 - ±16 ±62 ppm Gain Drift (Note 4) - 1 3 - 1 3 ppm/°C Voltage Reference Input Range (VREF+) - (VREF-) 1 2.5 3.0 1 2.5 3.0 V Common Mode Rejection dc 50, 60 Hz 110 130 110 130 dB dB Input Capacitance - 16 - - 16 - pF CVF Current (Note 5) - 0.6 - - 0.6 - µA/V Output Rate (Sps) -3 dB Filter Frequency Input Range, (Bipolar/Unipolar Mode) 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 7.51 6.55 110 nV 130 nV 190 nV 1.5 µV 3.0 µV 7 µV 15.0 12.7 170 nV 200 nV 250 nV 2.0 µV 5.0 µV 10 µV 30.1 25.4 250 nV 300 nV 500 nV 4.0 µV 10 µV 15 µV 60.0 50.4 500 nV 1.0 µV 1.5 µV 15 µV 45 µV 85 µV 168.9 (Note 8) 141.3 10 µV 20.0 µV 30 µV 340 µV 900 µV 2.0 mV

ANALOG CHARACTERISTICS (Continued) Notes: 9. The minimum Full-scale Calibra tion Range (FSCR) is limited by the maximum allowed gain register value (with margin). The maximum FSCR is limited by the ∆Σ modulator’s 1’s density range. 10. The maximum full-scale signal can be limited by satu ration of circuitry within the internal signal path. 11. All outputs unloaded. All input CMOS levels. Parameter Min Typ Max Unit Analog Input Common Mode + Signal on AIN+ or AIN- Bipolar/Unipolar Mode NBV = -1.8 to -2.5 V Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V NBV = AGND Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V -0.150 NBV 1.85 0.0 0.950 VA+ 2.65 VA+ V V V V Common Mode Rejection dc 50, 60 Hz 120 120 dB dB Input Capacitance - 10 - pF CVF Current on AIN+ or AIN- (Note 5) Range = 25 mV, 55 mV, or 100 mV Range = 1 V, 2.5 V, or 5 V 100 1.2 300 pA µA/V System Calibration Specifications Full-scale Calibration Range Bi polar/Unipolar Mode (Note 9) 25 mV 55 mV 100 mV 1 V 2.5 V 5 V 17.5 38.5 0.70 1.75 3.50 32.5 71.5 105 1.30 3.25 VA+ mV mV mV V V V Offset Calibration Range Bipolar/Unipolar Mode 25 mV 55 mV 100 mV (Note 10) 1 V 2.5 V 5 V ±12.5 ±27.5 ±50 ±0.5 ±1.25 ±2.50 mV mV mV V V V Power Supplies DC Power Supply Currents (Normal Mode) I ID+ INBV 1.65 475 2.2 700 mA µA µA Power Consumption Normal Mode (Note 11) Low Power Mode Standby Sleep 9.4 4.9 1.2 500 12.7 8.5 mW mW mW µW Power Supply Rejection dc Positive Supplies dc NBV 110 dB dB

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5 V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+, VD+ = 5 V ±5%; GND = 0;

See Notes 2 and 12.)) Notes: 12. All measurements performed under static conditions. 13. I out = -100 µA unless stated otherwise. (VOH = 2.4 V @ Iout = -40 µA.) 3.0 V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10%; GND = 0; See Notes 2 and 12.)) Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except XIN and SCLK XIN SCLK VIH 0.6 VD+ 3.5 (VD+) - 0.45 VD+ V V V Low-level Input Voltage All Pins Except XIN and SCLK XIN SCLK V IL - 0.0 0.8 1.5 0.6 V V V High-level Output Voltage All Pins Except CPD and SDO (Note 13) CPD, I out = -4.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 1.0 (VD+) - 1.0 (VD+) - 1.0 V V V Low-level Output Voltage All Pins Except CPD and SDO, I out = 1.6 mA CPD, Iout = 2 mA SDO, Iout = 5.0 mA VOL 0.4 0.4 0.4 V V V Input Leakage Current I in -± 1 ± 1 0 µ A 3-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9 - p F Parameter Symbol Min Typ Max Unit High-level Input Voltage All Pins Except XIN and SCLK XIN SCLK VIH 0.6 VD+

0.54 VA+

(VD+) - 0.45 VD+ V V V Low-level Input Voltage All Pins Except XIN and SCLK XIN SCLK V IL - 0.0

0.16 VD+

1.5 0.6 V V V High-level Output Voltage All Pins Except CPD and SDO, I out = -400 µA CPD, Iout = -4.0 mA SDO, Iout = -5.0 mA VOH (VA+) - 0.3 (VD+) - 1.0 (VD+) - 1.0 V V V Low-level Output Voltage All Pins Except CPD and SDO, I out = 400 µA CPD, Iout = 2 mA SDO, Iout = 5.0 mA VOL 0.3 0.4 0.4 V V V Input Leakage Current I in -± 1 ± 1 0 µ A 3-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -9 - p F

RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0 V; See Note 14.)) Notes: 14. All voltages with respect to ground. ABSOLUTE MAXIMUM RATINGS (AGND, DGND = 0 V; See Note 14.) Notes: 15. No pin should go more negative than NBV - 0.3 V. 16. Applies to all pins including continuous overvo ltage conditions at the analog input (AIN) pins. 17. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 18. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Ratio Unit Modulator Sampling Frequency f s XIN/2 Hz Filter Settling Time to 1/2 LSB (Full Scale Step) t s 1/fout s Parameter Symbol Min Typ Max Unit DC Power Supplies Positive Digital Positive Analog VD+ VA+ 2.7 4.75 5.0 5.0 5.25 5.25 V V Analog Reference Voltage (VREF+) - (VREF-) VRef diff 1.0 2.5 3.0 V Negative Bias Voltage NBV -1.8 -2.1 -2.5 V Parameter Symbol Min Max Unit DC Power Supplies (Note 15) Positive Digital Positive Analog VD+ VA+ -0.3 -0.3 +6.0 +6.0 V V Negative Bias Voltage Negative Potential NBV +0.3 -3.0 V Input Current, Any Pin Except Supplies (Note 16 and 17) I IN -± 1 0 m A Output Current I OUT -± 2 5 m A Power Dissipation (Note 18) PDN - 500 mW Analog Input Voltage VREF pins AIN Pins V INR VINA -0.3 NBV - 0.3 (VA+) + 0.3 (VA+) + 0.3 V V Digital Input Voltage V IND -0.3 (VD+) + 0.3 V Ambient Operating Temperature T A -40 85 °C Storage Temperature T stg -65 150 °C

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SWITCHING CHARACTERISTICS (TA = 25 °C; VA+ = 5 V ±5%; VD+ = 3.0 V ±10% or 5 V ±5%; Input Levels: Logic 0 = 0 V, Logic 1 = VD+; CL = 50 pF.)) Notes: 19. Device parameters are specified with a 32.768 kH z clock; however, clocks up to 100 kHz can be used for increased throughput. 20. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 21. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. 22. Applicable when SCLK is continuously running. Parameter Symbol Min Typ Max Unit Master Clock Frequency (Note 19) Internal Clock External Clock XIN 32.768 32.768 100 kHz Master Clock Duty Cycle 40 - 60 % Rise Times (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output t rise 1.0 100 µs µs ns Fall Times (Note 20) Any Digital Input Except SCLK SCLK Any Digital Output t fall 1.0 100 µs µs ns Start-up Oscillator Start-up Time XTAL = 32.768 kHz (Note 21) t ost -5 0 0- m s Power-on Reset Period t por - 1003 - XIN cycles Serial Port Timing Serial Clock Frequency SCLK 0 - 2 MHz SCLK Falling to CS Falling for continuous running SCLK (Note 22) t0 100 - - ns Serial Clock Pulse Width High Pulse Width Low 250 250 ns ns SDI Write Timing CS Enable to Valid Latch Clock t 3 50 - - ns Data Set-up Time prior to SCLK rising t 4 50 - - ns Data Hold Time After SCLK Rising t 5 100 - - ns SCLK Falling Prior to CS Disable t 6 100 - - ns SDO Read Timing CS to Data Valid t 7 -- 1 5 0 n s SCLK Falling to New Data Bit t 8 -- 1 5 0 n s CS Rising to SDO Hi-Z t 9 -- 1 5 0 n s

Continuous Running SCLK Timing (Not to Scale) CS SCLK MSB MSB-1 LSBSDI t4 t 5 t1 SDI Write Timing (Not to Scale) CS SCLK MSB MSB-1 LSB SDO t 8 t 1 t 2 SDO Read Timing (Not to Scale)

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different output update rates. thermocouple temperature measurements. Characteristics section on page 3 for details. Voltage, approximately - 2.1 V in this example). tive divider as illustrated in Figure 3. Figure 1. CS5525/26 Configured to use on-chip charge pump to supply NBV.

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(Reset System) bit in th e configuration register. are ready to perform conversions. Figure 5. CS5525/26 Configured for Single Supply Bridge Measurement.

sary to write to, or read from the serial port. Logic 1 for executable commands. Single Conversion not active. Continuous Conversions not active. Perform conversions continuously. Read from selected register. Table 1. Command Set

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D23-D20 Latch Outputs, A3-A0 0000 R* Latch Output Pins A3-A0 mimic the D23-D20 Register bits. D19 Not Used, NU 0 R Must always be logic 0.

32768 Hz Amplifier chop frequency

D17 Not Used, NU 0 R Must always be logic 0.

30.1 Sps (1090 XIN cycles)

60.0 Sps (546 XIN cycles)

123.2 Sps (266 XIN cycles)

168.9 Sps (194 XIN cycles)

202.3 Sps (162 XIN cycles)

3.76 Sps (8722 XIN cycles)

7.51 Sps (4362 XIN cycles)

For PD = 1, the CPD pin goes to a Hi-Z output state. Activate a Reset cycle. To return to Normal Operation write bit to zero. No reset has occurred or bit has been cleared (read only). R Done Flag bit is cleared (read only). Calibration or Conversion cycle completed (read only). Table 2. Configuration Register

8 SCLKs

8 SCLKs Clear SDO Flag

24 SCLKs

Figure 6. Command and Data Word Timing.

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signal and its common mode voltage.

2.65 V to ensure that the amplifier operates prop-

AIN+ and AIN- must stay between NBV and VA+.

5 V by performing a system calibration within the

ence section for more details. Figure 7. Block Diagram of Analog Signal Path

divide VREF (2.5 V) by the Gain Factor (2.2727). ues in Table 3 must be scaled accordingly. is lowest with the CFS bit cleared to logic 0.

32768 Hz eliminating the residual noise, but increasing the

current. Note that C=48pF is for input current modeling only. ification under ‘Analog Characteristics’ on page 3. table assume a 2.5 V VREF voltage. Table 3. Relationship between Full Scale Input, Gain Factors, and Internal Analog Signal Limitations Figure 8. Input models for AIN+ and AIN- pins Figure 9. Input model for VREF+ and VREF- pins.

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The CPD (Charge Pump Drive) pin of the convert- ers can be used with external components (shown in Figure 1) to develop an appropriate negative bias voltage for the NBV pin. When CPD is used to gen- erate the NBV, the NBV vol tage is regulated with an internal regulator loop referenced to VA+. Therefore, any change on VA+ results in a propor- tional change on NBV. Wi th VA+ = 5 V, NBV’s regulation is set proporti onal to VA+ at approxi- mately -2.1 V. Figure 3 illustrates a means of supplying NBV volt- age from a -5 V suppl y. For ground based signals with the instrumentation amplifier engaged (when in the 25mV, 55mV, or 100mV ranges), the voltage on the NBV pin should at no time be less negative than -1.8 V or more negati ve than -2.5 V. To pre- vent excessive voltage stress to the chip the NBV voltage should not be more negative than -3.0 V. The components in Figure 1 are the preferred com- ponents for the CPD filter. However, smaller ca- pacitors can be used with acceptable results. The µF ensures very low ripple on NBV. Intrinsic safety requirements prohibit the use of electrolytic capacitors. In this case, two 0.47 µF ceramic capac- itors in parallel can be used. The CPD pin itself is a tr i-state output and enters tri-state whenever the converters are placed into the Sleep Mode, Standby Mode, or when the charge pump is disabled (when th e Pump Disable bit, bit D8 in the configuration register, is set). Once in tri- state, the digital current can increase if this CPD output floats near 1/2 digital supply. To ensure the CPD pin stays near ground and to minimize the digital current, add a 5M Ω resistor between it and DGND (see Figure 1). If the resistor is left out, the digital supply current may increase from 2 µA to 10 µA. Voltage Reference The CS5525/26 are specified for operation with a

2.5 V reference voltage between the VREF+ and

VREF- pins of the devices. For a single-ended ref- erence voltage, such as the LT1019-2.5, the refer- ence’s output is connected to the VREF+ pin of the CS5525/26. The ground reference for the LT1019- 2.5 is connected to the VREF- pin. The differential voltage between the VREF+ and VREF- can be any voltage from 1.0 V up to 3.0 V, however, the VREF- pin can not go below analog ground. Calibration The CS5525/26 offer five different calibration functions including self calibration and system cal- ibration. However, after the CS5525/26 are reset, they can perform measurements without being cal- ibrated. In this case, the converters will utilize the initialized values of the on-chip registers (Gain = 1.0, Offset = 0.0) to calculate output words for the ±100 mV range. Any initial offset and gain errors in the internal circuitry of the chips will remain. The gain and offset registers, which are used for both self and system calibration, are used to set the zero and full-scale points of the converter’s transfer function. One LSB in the offset register is 2 -24 pro- portion of the input span (bipolar span is 2 times the unipolar span). The MSB in the offset register de- termines if the offset to be trimmed is positive or negative (0 positive, 1 ne gative). The converters can typically trim ±50 pe rcent of the input span. The gain register spans from 0 to (2 - 2 -23). The decimal equivalent meaning of the gain register is where the binary numbers have a value of either zero or one (b0 corresponds to the MSB). Refer to Table 4 for details. Db 020 b12 1– b22 2– … bN2 N–+++ + bi2 i– i 0= N ∑==

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cy, except for the 2.5 V range. Figure 12. Self Calibration of Gain (All Ranges). Figure 13. System Calibration of Offset (Low Ranges). Figure 14. System Calibration of Offset (High Ranges). Figure 15. System Calibration of Gain (Low Ranges) Figure 16. System Calibration of Gain (High Ranges).

Assuming a system can provide two known voltag- es, equations can allow th e user to manually com- pute the calibration register’s values based on two uncalibrated conversions. The offset and gain cali- bration registers are used to adjust a typical conver- sion as follows: Rc = (Ru + Co>>4) * Cg / 223. Calibration can be perfor med using the following equations: Co = (Rc0/G - Ru0) << 4 Cg = 223 * G where G = (Rc1 - Rc0)/(Ru1-Ru0). Note: Uncalibrated conversions imply that the gain and offset registers are at default {gain register = 0x800000 (Hex) and offset register = 0x000000 (Hex)}. The variables are defined below. V0 = First calibration voltage V1 = Second calibration voltage (greater than V0) Ru = Result of any uncalibrated conversion Ru0 = Result of uncalibrated conversion V0 (20-bit integer or 2’s complement) Ru1 = Result of uncalibrated conversion of V1 (20-bit integer or 2’s complement) Rc = Result of any conversion Rc0 = Desired calibration result of converting V0 (20-bit integer or 2’s complement) Rc1 = Desired calibration result of converting V1 (20-bit integer or 2’s complement) Co = Offset calibration register value (24-bit 2’s complement) Cg = Gain calibration register value (24-bit integer) >> = The shift right operator (e.g. x >>2 is x shift- ed right 2 bits) << = The shift left operator (e .g. x<<2 is x shifted left 2 bits) Note: The shift operators are used here to align the decimal points of words of various lengths. Data to the right of the decimal point may be used in the calculations shown. For the CS5525 all conversion results (Ru, Rc...) are 16 bits instead of 20 bits. To get the equations to work correctly pad the 16 bit results with four zeros (on the right). Calibration Tips Calibration steps are performed at the output word rate selected by the WR2-WR0 bits of the configu- ration register. Since high er word rates result in conversion words with more peak-to-peak noise, calibration should be pe rformed at lower output word rates. Also, to minimize digital noise near the devices, the user s hould wait for each calibra- tion step to be completed before reading or writing to the serial port. For maximum accuracy, calibrations should be per- formed for offset and gain for each gain setting (se- lected by changing the G2-G0 bits of the configuration register). And if factory calibration is performed using the system calibration capabilities of the CS5525/26, the offset and gain register con- tents can be read by the system microcontroller and recorded in EEPROM. These same calibration words can then be uploaded into the offset and gain registers of the converters when power is first ap- plied to the system, or when the gain range is changed. Two final tips include two ways to determine when calibration is complete: 1) wait for SDO to fall. It falls to logic 0 if the PF (Port Flag) bit of the con- figuration register is set to logic 1; or 2) poll the DF (Done Flag) bit in the configuration register which is set at completion of calibration. Whichever method is used, the calibra tion control bits (CC2- CC0) will return to logic 0 upon completion of any calibration. Limitations in Calibration Range System calibration can be limited by signal head- room in the analog signal path inside the chip as discussed under the Analog Input section of this data sheet. System calibra tion can also be limited by the intrinsic gain errors of the instrumentation amplifier and the modulator . For gain calibrations

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the input signal can be reduced to the point in which the gain register reaches its upper limit of 2.0 (decimal) [FFFFFF Hex] (this is most likely to oc- cur with an input signa l approximately 1/2 the nominal range). Alternatively, the input signal can be increased to a point in which the modulator reaches its one’s density upper limit of 80% (this is most likely to occur with an input signal approxi- mately 1.5 times the nominal range). Also, for full scale inputs larger than the nominal full scale value of the range selected, th ere is some voltage at which the various internal circuits may saturate due to limited amplifier headroom (this is most likely to occur on the 100 mV range setting when NBV = - 1.8 V). Analog Output Latch Pins The A3-A0 pins of the converters mimic the D23- D20 bits of the configur ation register. A3-A0 can be used to control mult iplexers and other logic functions outside the c onverter. The outputs can sink or source at least 1 mA, but it is recommended to limit drive currents to less than 20 µA to reduce self-heating of the chip. These outputs are powered from VA+, hence, their output voltage for a logic 1 will be limited to the VA+ voltage. Serial Port Interface The CS5525/26 serial interface consist of four pins, SCLK, SDO, SDI, and CS . The CS pin must be held low (logic 0) before SCLK transitions can be recognized by the port logic. The SDO output will be held at high impedance any time CS is a logic 1. If the CS pin is tied low, the port can function as a three wire interface. The SCLK input is designed with a Schmitt-trigger input to allow an optoisolator with slower rise and fall times to directly drive the pin. The SDO output is capabl e of sinking or sourcing up to 5 mA to directly drive an optoisolator LED. SDO will have less than a 400 mV loss in the drive voltage when sinking or sourcing 5 mA. Serial Port Initialization The serial port is initialized to the command mode whenever a power-on reset is performed inside the converter, when the port initialization sequence is completed, or whenever a command byte, data word sequence is completed. The port initialization sequence involves clocking 15 (or more) bytes of all 1's, followed by one byte with the following bit contents (11111110). This sequence places the chips in the command mode where it waits for a valid command. Performing Conversions (With PF bit = 0) Setting the SC (Single Conversion) bit of the com- mand word to a logic 1 with the CB bit = 1, all other command bits = 0, th e CS5525/CS5526 will per- form one conversion. At the completion of the con- version the DF (Done Flag) bit of the configuration register will be set to a logic 1. The user can read the configuration register to determine if the DF bit is set. If DF has been set, a command can be issued to read the conversion data register to obtain the conversion data word. The DF bit of the configu- ration register will be cl eared to logic 0 when the data register, the gain register, the offset register, or the set-up registers are read. Reading only the con- figuration register will not clear the DF flag bit. If an SC command is issued to the converters while they are performing a conversion, the filter will re- start a convolution cycle to perform a new conver- sion. Performing Conversions (With PF bit = 1) Setting the PF bit of the configuration register to a logic 1 enables the SDO output pin to behave as a flag signal whenever conversions are completed. This eliminates the need for the user to read the DF flag bit of the configuration register to determine if the conversion data word is available. If the SC (Single Convers ion) command is issued (SC = 1, CB= 1, all other command bits = 0) the SDO pin will go low at the completion of a conver-

in the table assume a master clock of 32.768 kHz. output word rate of 15.0 Sps. mized to reduce stray capacitance. both initial frequency and for drift over temperature. as shown in Figure 18, be used. Figure 17. High Speed Clock Performance

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1. The filters are optimized to settle to full accura-

the filter’s corner frequency moves to 25.4 Hz. ment when operating in bipolar mode. logic 0 and the two flag bits. Figure 18. Tuning Fork Crystal Connection Diagram Figure 19. Filter Response Table 5. Data Conversion Word

the conversion data bits can be completely erroneous. put coding for the CS5525/26. tion modes: normal, low power, standby, and sleep. two modes are referred to as the power save modes. bit is set back to a logic 1. pins of the device connect ed to the analog plane. cent to the digital portion of the chip. the CPD pin trace away from XIN. Table 6. 5525/26 Output Coding

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XIN; XOUT - Crystal In; Crystal Out, Pins 9, 10. A gate inside the chip is connect ed to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device. Control Pins and Serial Data I/O CS - Chip Select, Pin 18. When active low, the port will recognize SCLK. When hi gh the SDO pin will output a high impedance state. CS should be changed when SCLK = 0. SDI - Serial Data Input, Pin 17. SDI is the input pin of the serial input port. Data will be input at a rate determined by SCLK. SDO - Serial Data Output, Pin 14. SDO is the serial data output. It will output a high impedance state if CS = 1. SCLK - Serial Clock Input, Pin 11. A clock signal on this pin determines the input/ output rate of the data for the SDI/SDO pins respectively. This input is a Sc hmitt trigger to allow for slow rise time signals. The SCLK pin will recognize clocks only when CS is low. A0, A1, A2, A3 - Logic Outputs, Pin 6, 7, 15, 16. The logic states of A0-A3 mimic the states of the D20-D23 bits of the configuration register. Logic Output 0 = AGND, and Logic Output 1 = V A+. 10 11 ANALOG GROUND AGND VREF+ VOLTAGE REFERENCE INPUT POSITIVE ANALOG POWER VA+ VREF- VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT AIN+ CS CHIP SELECT DIFFERENTIAL ANALOG INPUT AIN- SDI SERIAL DATA INPUT NEGATIVE BIAS VOLTAGE NBV A3 LOGIC OUTPUT LOGIC OUTPUT A0 A2 LOGIC OUTPUT LOGIC OUTPUT A1 SDO SERIAL DATA OUTPUT CHARGE PUMP DRIVE CPD VD+ POSITIVE DIGITAL POWER CRYSTAL IN XIN DGND DIGITAL GROUND CRYSTAL OUT XOUT SCLK SERIAL CLOCK INPUT

Measurement and Reference Inputs AIN+, AIN- - Differential Analog Input, Pins 3, 4. Differential input pins into the device. VREF+, VREF- - Voltage Reference Input, Pins 20, 19. Fully differential inputs whic h establish the voltage refere nce for the on-chip modulator. NBV - Negative Bias Voltage, Pin 5. Input pin to supply the negative supply voltage for the 20X gain inst rumentation amplifier. May be tied to AGND if AIN+ and AIN- inputs are centered ar ound +2.5 V; or it may be tied to a negative supply voltage (-2.1 V typical) to allow the amplifier to handle low level signals more negative than ground. CPD - Charge Pump Drive, Pin 8. Square wave output used to provide energy for the charge pump. Power Supply Connections V A+ - Positive Analog Power, Pin 2. Positive analog supply voltage. Nominally +5 V . VD+ - Positive Digital Power, Pin 13. Positive digital supply voltage. Nominally +3.0 V or +5 V . AGND - Analog Ground, Pin 1. Analog Ground. DGND - Digital Ground, Pin 12. Digital Ground.

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The deviation of a code from a straight line which connect s the two endpoints of the A/D Converter transfer function. One endpoint is lo cated 1/2 LSB below the first code transition and the other endpoint is locat ed 1/2 LSB beyond the code tran sition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width fr om the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(V REF+) - (VREF-)} - 3/2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above the voltage on the AIN- pin.). When in unipolar mode (U/B bit = 1). Units are in LSBs. Bipolar Offset the voltage on the AIN- pin) . When in bipolar mode (U/B bit = 0). Units are in LSBs.

Notes: 1. Positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. Dimension eA to center of leads when formed parallel. 3. Dimension E does not include mold flash. INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.155 0.180 3.94 4.57 A1 0.020 0.040 0.51 1.02 b 0.015 0.022 0.38 0.56 b1 0.050 0.065 1.27 1.65 c 0.008 0.015 0.20 0.38 D 0.960 1.040 24.38 26.42 E 0.240 0.260 6.10 6.60 e 0.095 0.105 2.41 2.67 eA 0.300 0.325 7.62 8.25 L 0.125 0.150 3.18 3.81 ∝ 0° 15° 0° 15°

20 PIN PLASTIC (PDIP) PACKAGE DRAWING

E D SEATING PLANE e b A LA1 ∝TOP VIEW BOTTOM VIEW SIDE VIEW eA c

28 DS202F5

Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mismatch and are measured at the parting line, mold flash or protrusions shall not exceed 0.20 mm per side. 2. Dimension “b” does not include dambar protrusion /intrusion. Allowable dambar protrusion shall be 0.13 mm total in excess of “b” dimension at maximum material condition. Dambar intrusion shall not reduce dimension “b” by more than 0.07 mm at least material condition. 3. These dimensions apply to the fl at section of the lead between 0.10 and 0.25 mm from lead tips. INCHES MILLIMETERS NOTE DIM MIN MAX MIN MAX A -- 0.084 -- 2.13 A1 0.002 0.010 0.05 0.25 A2 0.064 0.074 1.62 1.88 b 0.009 0.015 0.22 0.38 2,3 D 0.272 0.295 6.90 7.50 1 E 0.291 0.323 7.40 8.20 E1 0.197 0.220 5.00 5.60 1 e 0.024 0.027 0.61 0.69 L 0.025 0.040 0.63 1.03 ∝ 0° 8° 0° 8°

20 PIN SSOP PACKAGE DRAWING

E N 1 23 e b2 A1 A2 A D SEATING PLANE E11 L SIDE VIEW END VIEW TOP VIEW

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Package Linearity Error (Max) Temperature CS5525-AS 20-pin SSOP ±0.003% -40 to +85 °C CS5525-ASZ (Lead Free) CS5526-BP 20-pin Plastic Dip (0.300”) ±0.0015%CS5526-BS 20-pin SSOP CS5526-BSZ (Lead Free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5525-AS 240 °C 2 365 Days CS5525-ASZ (Lead Free) 260 °C 3 7 Days CS5526-BP 260 °C 1 No Limit CS5526-BS 240 °C 2 365 Days CS5526-BSZ (Lead Free) 260 °C 3 7 Days

30 DS202F5

REVISION HISTORY

F4 JUN 2005 Added Lead-free device ordering information. F5 AUG 2005 Revised Lead-free device or dering information. Added MSL data. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. SPI is a trademark of Motorola, Inc. Microwire is a trademark of National Semiconductor Corporation.