CS5516 CIRRUS | Alldatasheet
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Technical content
Features
lOn-chip Instrumentation Amplifier lOn-chip Programmable Gain Amplifier lOn-Chip 4-Bit D/A For Offset Removal lDynamic Excitation Options lLinearity Error: ±0.0015% FS - 20-bit, No Missing Codes lCMRR at 50/60 Hz > 200 dB lSystem Calibration Capability with calibration read/write option l3-, 4-, or 5-wire Serial Communications Port lLow Power Consumption: 40 mW - 10 µW Standby Mode for Portable applications
Description
The CS5516 and CS5520 are complete solutions for dig- itizing low level signals from strain gauges, load cells, and pressure transducers. Any family of mV output transducers, including those requiring bridge excitation, can be interfaced directly to the CS5516 or CS5520. The devices offer an on-chip software programmable instru- mentation amplifier block, choice of DC or AC bridge excitation, and software selectable reference and signal demodulation. The CS5516 uses delta-sigma modulation to achieve 16-bit resolution at output word rates up to 60 Sps. The CS5520 achieves 20-bit resolution at output word rates up to 60 Sps. The CS5516 and CS5520 sample at a rate set by the user in the form of either an external CMOS clock or a crystal. On-chip digital filtering provides rejection of all frequencies above 12 Hz for a 4.096 MHz clock. The CS5516 and CS5520 include system calibration to null offset and gain errors in the input channel. The digi- tal values associated with the system calibration can be written to, or read from, the calibration RAM locations at any time via the serial communications port. The 4-bit DC offset D/A converter, in conjunction with digital cor- rection, is initially used to zero the input offset value.
ORDERING INFORMATION
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ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+, MDRV+ = 5V; VA-, VD- = -5V; VREF= 2.5V(external differential voltage across VREF+ and VREF-); fCLK = 4.9152 MHz; AC Excitation 300 Hz; Gain = 25; Bipolar Mode; Rsource = 300Ω with a 4.7nF to AGND at AIN (see Note 1); unless otherwise specified.) Parameter* Min Typ Max Units Specified Temperature Range -40 to +85 Accuracy Linearity Error 0.0015 0.003 ±%FS Differential Nonlinearity ±0.25 ±0.5 LSB16 Unipolar Gain Error (Note 2) ±31 ppm Bipolar Gain Error (Note 2) ±31 ppm Unipolar/Bipolar Gain Drift ppm/°C Unipolar Offset (Note 2) LSB16 Bipolar Offset (Note 2) LSB16 Offset Drift ±0.005 µV/°C Noise (Referred to Input) Gain = 25 (25 x 1) Gain = 50 (25 x 2) Gain = 100 (25 x 4) Gain = 200 (25 x 8) 250 200 150 150 nVrms nVrms nVrms nVrms Notes: 1. The AIN and VREF pins present a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both source resistance and shunt capacitance are therefore critical in determining the source impedance requirements of the CS5516 and CS5520 at these pins. 2. Applies after system calibration at the temperature of interest. Specifications are subject to change without notice. Unipolar Mode Bipolar Mode µV LSB’s % FS ppm FS LSB’s % FS ppm FS 0.4 0.26 0.0004 0.13 0.0002 0.76 0.50 0.0008 0.26 0.0004 1.52 1.00 0.0015 0.50 0.0008 3.04 2.00 0.0030 1.00 0.0015 6.08 4.00 0.0061 2.00 0.0030 VREF = 2.5V PGA gain = 1 CS5516; 16-Bit Unit Conversion Factors * Refer to the Specification Definitions immediately following the Pin Description Section. DS74F1 DS74F2
µV LSB’s % FS ppm FS LSB’s % FS ppm FS 0.025 0.26 0.0000238 0.25 0.13 0.0000119 0.125 0.047 0.50 0.0000477 0.50 0.26 0.0000238 0.25 0.095 1.00 0.0000954 1.0 0.50 0.0000477 0.50 0.190 2.00 0.0001907 2.0 1.00 0.0000954 1.0 0.380 4.00 0.0003814 4.0 2.00 0.0001907 2.0 VREF = 2.5V PGA gain = 1 CS5520; 20-Bit Unit Conversion Factors Specifications are subject to change without notice. * Refer to the Specification Definitions immediately following the Pin Description Section. ANALOG CHARACTERISTICS (continued) Parameter* Min Typ Max Units Specified Temperature Range -40 to +85 Accuracy Linearity Error 0.0007 0.0015 ±%FS Differential Nonlinearity (No Missing Codes) Bits Unipolar Gain Error (Note 2) ±24 ppm Bipolar Gain Error (Note 2) ±24 ppm Unipolar/Bipolar Gain Drift ppm/°C Unipolar Offset (Note 2) LSB20 Bipolar Offset (Note 2) LSB20 Offset Drift ±0.005 µV/°C Noise (Referred to Input) Gain = 25 (25 x 1) Gain = 50 (25 x 2) Gain = 100 (25 x 4) Gain = 200 (25 x 8) 250 200 150 150 nVrms nVrms nVrms nVrms DS74F1 DS74F2
ANALOG CHARACTERISTICS (continued) Parameter Min Typ Max Units Specified Temperature Range -40 to +85 Analog Input Analog Input Range Unipolar Bipolar 12.5, 25, 50, 100 mV mV Common Mode Rejection dc 50, 60 Hz 165 200 dB dB Input Capacitance pF Input Bias Current (Note 1) 100 pA Instrumentation Amplifier Gain Bandwidth 200 kHz Unity Gain Bandwidth MHz Output Slew Rate 1.5 V/µsec Noise @ 10 Hz BW 100 nVrms Power Supply Rejection @ 50/60 Hz (Note 3) 120 dB Common Mode Range (Note 4) V Chopping Frequency XIN/128 Hz Programmable Gain Amplifier Gain Tracking (Note 5) 4-Bit Offset Trim DAC Accuracy Voltage Reference Input Range (Note 6) 2.0 2.5 3.8 V Common Mode Rejection: dc 50, 60 Hz 200 dB Input Capacitance pF Input Bias Current (Note 1) nA Notes: 3. This includes the on-chip digital filtering. 4. The maximum magnitude of the differential input voltage, Vdiff(in) is determined by the following: Vdiff(in) < 300 mV - |Vcm/12.5 | and should never exceed 300mV. Vcm is the common mode voltage which is applied to the instrumentation amplifier inputs. The above equation should be used to calculate the allowable common mode voltage for a given differential voltage applied to the first gain stage inputs. This limit ensures that the instrumentation amplifier does not saturate. 5. Gain tracking accuracy can be significantly improved by uploading a calibrated gain word to the gain register for each PGA gain selection. 6. The common mode voltage on the Voltage Reference Input, plus the reference range, [(VREF+) - (VREF-)]/2, must not exceed ±3 volts. CS5516, CS5520 DS74F1 DS74F2
ANALOG CHARACTERISTICS (continued) Parameter Min Typ Max Units Modulator Differential Voltage Reference Nominal Output Voltage 3.75 V Initial Output Voltage Tolerance ±100 mV Temperature Coefficient 100 ppm/°C Line Regulation 0.5 mV/V Output Voltage Noise 0.1 to 15 Hz µVp-p Output Current Drive: Source Current Sink Current µA µA Power Supplies DC Power Supply Currents IA+ IA- ID+ ID- 2.7 -2.7 1.5 -0.6 3.5 -3.5 2.2 -0.8 mA mA mA mA Power Dissipation: (Note 7) Normal Operation Standby Mode 37.5 mW µW Power Supply Rejection: dc Positive Supplies dc Negative Supplies 100 dB dB System Calibration Specifications Positive Full Scale Calibration Range (Note 8) Unipolar Mode Bipolar Mode 0.8T 0.8T 1.2T 1.2T V V Maximum Ratiometric Offset Calibration Range (Note 8) Unipolar Mode Bipolar Mode -2T -2T +2T +2T V V Differential Input Voltage Range (Notes 4, 8, 9, 10) Unipolar Mode Bipolar Voffset + (1.2T) Voffset ± (1.2T) V V Notes: 7. All outputs unloaded. All inputs CMOS levels. 8. T=VREF/(Gx25), where T is the full scale span, where VREF is the differential voltage across VREF+ and VREF- in volts, and G is the gain setting of the second gain block. G can be set to 1, 2, 4, 8. This sets the overall gain to 25, 50, 100, 200. The gain can then be fine tuned by using the calibration of the full scale point. 9. When calibrated. 10. Voffset is the offset corrected by the offset calibration routine. Voffset may be as large as 2T. CS5516, CS5520 DS74F1 DS74F2
AIN and VREF Input Sampling Frequency fis fclk/128 Hz Modulator Sampling Frequency fs fclk/256 Hz Output Update Rate fout fclk/81,920 Sps Filter Corner Frequency f-3dB fclk/341,334 Hz Settling Time to ±0.0007% (FS Step) ts 6/fout s DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 5%; VA-, VD- = -5V ± 5%; DGND = 0) All measurements below are performed under static conditions. Parameter Symbol Min Typ Max Units High-Level Input Voltage: XIN All Pins Except XIN VIH VIH 4.5 2.0 V V Low-Level Input Voltage XIN All Pins Except XIN VIL VIL 0.5 0.8 V V High-Level Output Voltage (Note 11) VOH (VD+)-1.0 V Low-Level Output Voltage lout = 1.6mA VOL 0.4 V Input Leakage Current lin µA 3-State Leakage Current lOZ ±10 µA Digital Output Pin Capacitance Cout pF CS5516, CS5520 DS74F1 DS74F2
RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V, see Note 12.) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 5.5 -5.5 5.5 -5.5 V V V V Differential Analog Reference Voltage (VREF+) - (VREF-) 2.0 2.5 3.8 V Analog Input Voltage: (Note 13) Unipolar Bipolar VAIN VAIN V V Notes: 12. All voltages with respect to ground. 13. The CS5516 and CS5520 can accept input voltages up to +T in unipolar mode and -T to +T in bipolar mode where T=VREF/(Gx25). G is the gain setting at the second gain block. When the inputs exceed these values, the CS5516 and CS5520 will output positive full scale for any input above T, and negative full scale for inputs below AGND in unipolar and -T in bipolar mode. This applies when the analog input does not exceed ±2T overrange. ABSOLUTE MAXIMUM RATINGS* (AGND, DGND = 0V, all voltages with respect to ground.) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital (Note 14) Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- -0.3 -0.3 -0.3 +0.3 (VA+)+0.3 -5.5 5.5 -5.5 V V V V Input Current, Any Pin Except Supplies (Notes 15, 16) lin ±10 mA Analog Input Voltage AIN and VREF pins VINA (VA-)-0.3 (VA+)+0.3 V Digital Input Voltage VIND -0.3 (VD+)+0.3 V Ambient Operating Temperature TA -55 125 Storage Temperature Tstg -65 150 Notes: 14. No pin should go more positive than (VA+)+0.3V. VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V. 15. Applies to all pins including continuous overvoltage conditions at the analog input pins. 16. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is ± 50 mA. * WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. CS5516, CS5520 DS74F1 DS74F2
SID Write Timing (Not to Scale) SOD Read Timing (Not to Scale) SOD Read Timing with CS = 0 (Not to Scale) CS with Continuous SCLK (Not to Scale) CS5516, CS5520 DS74F1 DS74F2
SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 5%; VA-, VD- = -5V±5%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) Parameter Symbol Min Typ Max Units Master Clock Frequency: Internal Oscillator / External Clock XIN 1.0 4.096 5.0 MHz Master Clock Duty Cycle Rise Times Any Digital Input (Note 18) Any Digital Output trise 1.0 µs ns Fall Times Any Digital Input (Note 18) Any Digital Output tfall 1.0 µs ns Startup Power-on Reset Period tpor 100 ms Oscillator Start-up Time XTAL = 4.9152 MHz(Note 19) tost ms RST Pulse Width tres 1/XIN ns Serial Port Timing Serial Clock Frequency SCLK 2.4 MHz Serial Clock Pulse Width High Pulse Width Low 200 200 ns ns SID Write Timing CS Enable to Valid Latch Clock 150 ns Data Set-up Time prior to SCLK rising ns Data Hold Time After SCLK Rising ns SCLK Falling Prior to CS Disable ns SOD Read Timing CS to Data Valid 150 ns SCLK Falling to New Data Bit 170 ns SCLK Falling to SOD Hi-Z 200 ns DRDY Falling to Valid Data (CS = 0) t10 150 ns CS Rising to SOD Hi-Z t11 150 ns CS Disable Hold Time t12 ns CS Enable Set-up Time t13 150 ns CS Enable Hold Time t14 ns CS Disable Set-up Time t15 150 ns Notes: 18. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 19. Oscillator start-up time varies with crystal parameters. This specification does not apply when using an external clock source. CS5516, CS5520 DS74F1 DS74F2
amplifier, and a DAC for offset trimming. Figure 1. System Connection Diagram: AC Excitation Mode Using External Excitation
is the gain of the instrumentation amplifier. Figure 2. System Connection Diagram: DC Excitation Mode (EXC bit = 0), F1 = F0 = 0.
rial port is initialized into the command mode. illustrates the bits of the configuration register. cussed in various sections of this data sheet. Table 1. CS5516 and CS5520 Commands
2.A write to these bits does not change the register bit values. These bits are just a mirror of the DAC register contents. Table 2. Configuration Register
CS5516/CS5520 A/D converters, the devices must be reset to a known condition before proper operation can occur. The internal reset is applied after power is established and lasts for approximately 100 ms. The RST pin can also be used to establish a reset condition. The reset sig- nal should remain low for at least one XIN clock cycle to ensure adequate reset time. It is recom- mended that the RST pin be used to reset the converter if the power supplies rise very slowly or with poor startup characteristics. The RST signal can be generated by a microcontroller out- put, or by use of an R-C circuit. The reset function initializes the configuration register and all five of the calibration registers; and places the microcontroller in command mode ready to accept a command from the serial port. Whenever the device is reset the DRDY pin will be set to a logic 1 and the on-chip regis- ters are initialized to the following states: Configuration 000000(H) Calibration registers: DAC 000000(H) Gain 800000(H) AIN Ratiometric Offset 000000(H) AIN Non-ratiometric Offset 000000(H) VREF Non-ratiometric Offset 000000(H) CALIBRATION After the CS5516/20 is reset, the device is func- tional and can perform measurements without being calibrated. The converter will utilize the initialized values of the calibration registers to calculate output words. The converter uses the two outputs (AIN & VREF) of the dual channel converter along with the contents of the calibration registers to com- pute the conversion data word. The following equation indicates the computation. R0 = R4 [[ DAIN − R1 DVREF − R2] − R3] Where R0 is the output data, DAIN and DVREF are the digital output words from the AIN and VREF digital filter channels, and R1, R2, R3 and R4 are the contents of the following calibra- tion registers: R1 = AIN non-ratiometric offset R2 = VREF non-ratiometric offset R3 = AIN ratiometric offset R4 = Gain The computed output word, R0, is a two’s com- plement number. Calibration minimizes the errors in the converted output data. If calibration has not been per- formed, the measurements will include offset and gain errors of the entire system. The converter may be calibrated each time it is powered up, or calibration words from a pre- vious calibration may be uploaded into the appropriate calibration registers from some type of E2PROM by the system microcontroller. The converter uses five different registers to store specific calibration information. Each of the calibration registers stores information perti- nent to correcting a specific source of error associated with either the converter or with the input transducer and its wiring. The method by CS5516, CS5520 DS74F1 DS74F2
calibration step is completed. offset of the AIN channel should be calibrated. Table 3. CS5516/CS5520 Calibration Control non-ratiometric calibration. Figure 3. Non-ratiometric System Calibration using
the proper 24 bit calibration words in the VREF and AIN non-ratiometric registers. Note that the two non-ratiometric offsets can be calibrated si- multaneously or independently, but they must be calibrated prior to the other calibration steps if non-ratiometric offset calibration is to be used. If the effects of the non-ratiometric errors are not significant enough to affect the user application, they can be left uncalibrated (after a reset, the non-ratiometric offset registers will contain 000000(H)). Ratiometric Offset Once the non-ratiometric errors have been cali- brated, the ratiometric offset error of the AIN channel should be calibrated next. To perform this calibration step, a reference voltage must be applied to the VREF+ and VREF- pins. Then, place "zero" weight on the scale platform. This will result in an offset voltage into the converter which will represent the offset of the bridge, the wiring, and the AIN input of the converter itself. A configuration word with the EC and CC1 bits set to logic 1 is then written into the configura- tion register. During the ratiometric offset calibration of AIN the microcontroller first uses a successive approximation algorithm to com- pute the correct values for the DAC3-DAC0 bits of the DAC register. This accommodates any large offsets on the AIN input signal. Once the four DAC bits are computed, this amount of off- set is removed from the input signal. The microcontroller then computes the appropriate 24 bit number to place in the AIN ratiometric offset register to calibrate out the remaining off- set not removed by the DAC. Gain After the AIN ratiometric offset has been cali- brated, the next step is to perform a gain calibration. Gain calibration is performed with "full scale" weight on the scale platform. The EC and CC0 bits of the configuration register are set to logic 1. The gain calibration of the AIN channel is the final calibration step. After DRDY falls to signal the completion of this cali- bration step, the EC bit of the configuration register must be set back to logic 0 to terminate the calibration mode. Limitations in Calibration Range There are five calibration registers in the con- verter. There are two non-ratiometric offset calibration registers, one for the AIN input and one for the VREF input; one 4-bit offset trim DAC; one ratiometric offset calibration register for the AIN input; and one gain calibration reg- ister. After the non-ratiometric offsets are calibrated, an LSB in either of the 24-bit non-ra- tiometric calibration registers represents 2-23 proportion of an internally-scaled MDRV (Modulator Differential Reference Voltage). At the MDRV+ and MDRV- pins, the MDRV has a nominal value of 3.75 volts. This voltage is in- ternally scaled to a nominal 2.5 volts (never less than 2.4 volts) for use with the non-ratiometric calibration. The two non-ratiometric calibration words are stored in 2’s complement form with one count equal to slightly less than 300 nV at the input of the internal A/D converter. For the AIN channel this will be scaled down by the gain of the instrumentation amplifier (X25) and the PGA gain. For a PGA gain = 1, one count of a non-ratiometric register will represent slightly less than 12 nV. Non-ratiometric offset at the VREF input cannot exceed ± 2.4 volts to be within calibration range of the converter. Non- ratiometric offset to be calibrated by the AIN channel cannot exceed ± 2.4 volts divided by the channel gain. With a PGA gain = 1, the maxi- mum non-ratiometric offset which can be calibrated on the AIN channel cannot exceed ± 96 mV. When the ratiometric offset is calibrated, the 4- bit DAC coarsely trims offset from the analog signal. The ratiometric offset which remains is finely trimmed after the signal has been con- verted; using the contents of the ratiometric offset register for digital correction. The DAC CS5516, CS5520 DS74F1 DS74F2
bits can be manipulated by the user to add or subtract offset up to 200 percent of the nominal input signal. The AIN ratiometric offset register can be manipulated to add or subtract offset equal to the maximum differential input signal into the X25 amplifier. An LSB in the ratiomet- ric offset register represents 2-23 proportion of the voltage input across the VREF+ and VREF- pins at the internal input to the AIN channel A/D converter. This will be scaled down by the AIN channel gain when calculated relative to the instrumentation amplifier input. For example, with a VREF = 2.5 V, the PGA gain = 1, one count of the ratiometric offset register would represent about 12 nV at the instrumentation am- plifier input. The proportion remains ratiometric even if the VREF voltage should change. The 24-bit register content is stored in 2’s comple- ment form. Manipulation of the DAC or ratiometric offset register allows the user to shift the transfer func- tion to allow for load cell creep or load cell zero drift. The gain calibration is performed last. The con- tents of the gain register spans from 2-23 to 2 as shown in Table 4. After gain calibration has been performed, the numeric value in the gain register should not exceed the range of 0.8 to 1.2. The gain calibration range is ± 20 % of the nominal value of 1.0. The nominal value of 1.0 is for an input span dictated by the VREF volt- age, the PGA gain, and the X25 instrumentation gain. The converter may operate with gain slope factors from 0.5 to 2.0 (decimal), but when the slope exceeds 1.2 the converter output code computation may lack adequate resolution and result in missing codes in the transfer function. Internal circuitry may saturate for large signals which would calibrate to a gain factor less than 0.8. In a typical weigh scale application, the CS5516/CS5520 will be calibrated in combina- tion with a load cell at the factory. Once calibrated, the calibration words are off-loaded from the converter and stored in E2PROM. When powered-up in the field the calibration words are up-loaded into the appropriate regis- ters. This is viable because the AIN and VREF input to the converter are "chopper-stabilized" and maintain excellent stability when subjected to changes in temperature. Programmable Gain Amplifier The programmable gain amplifier inside the CS5516/20 offers gains of 1, 2, 4, and 8. This is in addition to the fixed gain of × 25 in the input instrumentation amplifier. The gain tracking of the PGA is about one percent between ranges. The user can remove this error by performing a gain calibration at the factory with a full scale signal on each range. The gain calibration word for each gain range can be off-loaded into E2PROM and uploaded into the gain register whenever a new gain setting is selected for the PGA. Gain stability over temperature for the converter itself is approximately 1 ppm/°C when the device is used ratiometrically. Serial Interface Modes The CS5516/20 support either 5, 4 or 3 pin se- rial interfacing. The SMODE pin sets the operating mode of the serial interface. With SMODE = 0, the device assumes the user is op- erating with either a 5 or 4 wire interface. The five wire mode includes SOD, SID, SCLK, DRDY, and CS. In the four wire mode, CS is connected to DGND as a logic 0. The user would then interface to the SOD, SID, SCLK, and DRDY pins. CS5516, CS5520 DS74F1 DS74F2
- A write to these bits does not change the register bit values.
The gain register span from 0 to (2-2-23). After Reset the MSB=1, all other bits are 0. Table 4. Calibration Registers
Reading a register in the converter requires a command word to be written to the SID pin. For example, to read the conversion data regis- ter, the following command sequence should be performed. First, the command word 88(H) would be issued to the port. In the 5 wire inter- face mode, this would involve activating CS low, followed by 8 SCLKs (note that SCLK must always start low and transition from low to high to latch the transmit data, and then back low again) to input the 8-bit command word. CS must be low for the serial port to recognize SCLKs during a write or a read, but it is actually the first rising SCLK during command time that gives the user control over the port. After writ- ing the command word, the user must pause and wait until the CS5520 presents the selected reg- ister data to the serial port. The DRDY signal will fall when the data is available. When read- ing the conversion data register, it may take up to 112,000 XIN clock cycles for DRDY to fall after the 88(H) command word is recognized. See Figure 4 for an illustration of command and data word timing. The conversion data register is actually the accu- mulator of the post-processor which computes the output data. At the end of each filter convo- lution cycle, the internal microcontroller checks to see if a read conversion data register com- mand has been interpreted. If so, it transfers the accumulator result to the serial port. Whenever registers other than the conversion data register are read, the DRDY pin will fall within 256 XIN clock cycles (62.5 µs with XIN = 4.096 MHz) after the command word is recognized. When DRDY falls, 24 SCLKs are then issued to the port to read the 24-bit output data word. DRDY will return high after all 24 bits have been clocked out. The SOD pin will be in a Hi-Z state whenever CS is high, or after all 24 output data bits have been clocked out of the port. The CS5516/20 is designed such that it can out- put conversion data words continuously, without issuing a new command word prior to each data read. Under the following circumstances, con- tinuous conversion data can be read from the port after issuing only one 88(H) command word. Once the command to read the conversion data register is issued, DRDY must be allowed to go low, after which 24 SCLKs are issued to read the data. This will cause DRDY to return high. The converter will continue to output conversion words at the update rate as long as a different command word is not started prior to DRDY falling again. The user is not required to read every output word to remain in the continuous update mode. DRDY will toggle high, and then low as each new output word becomes available. If a command word is issued immediately after a data word is read, the converter will end the read conversion mode. Figure 5 illustrates the con- tinuous data mode. The user should perform all data reads and com- mand writes within 51,000 XIN clock cycles after DRDY falls to avoid ambiguity as to who controls the serial port. If SMODE = 1 (tied to VD+), the interface oper- ates as a 3 wire interface using only SOD, SID, and SCLK. In the 3 wire mode CS must be tied to DGND. DRDY operates normally but is not used. Instead, the DRDY signal modifies the behavior of the SOD signal, allowing it to signal to the user when data is available. To read data from the converter requires a command word to be written to the SID pin. The SOD output is normally high (never Hi-Z). When output data is available, the SOD signal will go low. The user would then issue 8 SCLKs to the SCLK pin to clear this data ready signal. On the falling edge of the 8th SCLK the SOD pin will present the first bit of the 24-bit output word. 24 SCLKs are then issued to read the data. Then SOD will go high. SID should remain low whenever the CS5516, CS5520 DS74F1 DS74F2
8 SCLKs
24 SCLKs
8 SCLKs Clear DRDY
Figure 4. Command and Data Word Timing
burst one clock cycle per bit. sue one 88(H) command word to the converter. SID pin. Then issue a single 0 to the SID pin.
8 Data Bits
24 Data Bits
Figure 5. Continuous Read Conversion Data Mode (4 or 5 Wire)
CS5516 and at least 21 SCLKs for the CS5520. ones whenever an overrange condition exists. erroneously have its error flag bits set to "1". register written to a logic 1 and then back to 0. write the RF bit to the configuration register. flags under overrange conditions. Table 5. Output Coding for the CS5516/20 Converters.
The filter will start a new convolution on the next rising edge of the XIN clock after the 24th SCLK falls. Sleep Mode The CS5516/20 configuration register has an A/S bit which allows the users to put the device in a sleep condition to lower quiescent power. Upon reset the A/S bit device is set to a logic 0 which places the device in the ’awake’ condi- tion. Writing a 1 to the A/S bit will shutdown most of the chip, including the oscillator. It is desirable to use the following sequence when coming out of sleep. Write a logic 0 to the A/S bit of the configuration register. In the same configuration word write a logic 1 to the RF bit of the configuration register. Then wait until it is certain that the oscillator has started. After the oscillator has started or a clock present on the XIN pin, set the RF bit back to 0. The user should then wait at least 6 output word update periods before expecting a valid output data word. Noise Performance Typical noise performance for the converter is listed in the specification tables for each PGA gain. Figure 13 illustrates a noise histogram for 1000 output conversions from the CS5520. The data for the histogram was collected using the CDB5520 evaluation board; with VREF at 2.5 volts, PGA = 4, bipolar mode. The data shows the standard deviation of the data set is 3.2 LSBs. One LSB is equivalent to [VREF X 2(bi- polar)]/ [Inst amp gain X PGA gain X number of codes] or (2.5 X 2)/ (25 X 4 X 2E20) = 47.7 nV. One standard deviation is equivalent to rms if the data is Normal or Gaussian. The rms noise presented by the plot is 153 nV, which is in good agreement with the typical noise specifica- tion of 150 nV for a PGA gain of 4.
Applications
See the Application Notes section of the databook. Schematic & Layout Review Service Confirm Optimum Schematic & Layout Before Building Your Board. Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering. For Our Free Review Service Call Applications Engineering. C a l l : ( 5 1 2 ) 4 4 5 - 7 2 2 2 100 120 140 1 2 3 4 5 6 7 8 Figure 13. CS5520 Noise Histogram.
VD+ - Positive Digital Power, PIN 20. Positive digital supply voltage. Nominally +5 volts. VD- - Negative Digital Power, PIN 21. Negative digital supply voltage. Nominally -5 volts. DGND - Digital Ground, PIN 19. Digital ground. VA+ - Positive Analog Power, PIN 3. Positive analog supply voltage. Nominally +5 volts. VA- - Negative Analog Power, PIN 4. Negative analog supply voltage. Nominally -5 volts. AGND1, AGND2 - Analog Ground, PINS 5, 8. Analog ground. Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 22, 23 An internal gate is connected to these pins enabling the use of either a crystal or a ceramic resonator to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be input to the XIN pin as the master clock for the device. Modulator Diff. Voltage Ref + MDRV+ SMODE Serial Interface Mode Modulator Diff. Voltage Ref - MDRV- XOUT Crystal Out Positive Analog Power VA+ XIN Crystal In Negative Analog Power VA- VD- Negative Digital Power Analog Ground One AGND1 VD+ Positive Digital Power Analog In + AIN+ DGND Digital Ground Analog In - AIN- SOD Serial Output Data Analog Ground Two AGND2 SID Serial Input Data Voltage Ref In + VREF+ SCLK Serial Clock Input Voltage Ref In - VREF- DRDY Data Ready Bridge Excite 2 BX2 CS Chip Select Bridge Excite 1 BX1 RST Reset CS5516, CS5520 DS74F1 DS74F2
RST - Reset, PIN 13. Reset pin initializes all calibration registers to a known condition and places the serial port into the command mode. CS - Chip Select, PIN 14. An input which can be enabled by an external device to gain control over the serial port. When this pin is high, SOD is in a high impedance state if SMODE = 0. SCLK - Serial Data Clock, PIN 16. A clock signal at this pin determines the output rate of the data from the SOD pin and the input data rate on the SID pin. SID - Serial Input Data, PIN 17. This pin is used for inputting command and configuration words or inputting calibration words. Data is input at a rate determined by SCLK. SID is in a don’t care state when no data is being clocked in. SMODE - Serial Interface Mode, PIN 24. Selects the operating mode of the serial port. When low the serial port operates in the 5 or 4 wire interface mode. When high the chip will enter the 3 wire interface mode. Analog Inputs AIN+ and AIN- - Analog Inputs, PINS 6, 7. The analog input signals from the transducer. These are true differential inputs. VREF+ and VREF- - Voltage Reference Inputs, PINS 9,10. These are the differential analog reference voltage inputs. MDRV+ - Modulator Differential Voltage Reference, PIN 1. Positive terminal of the internal differential voltage reference which can be tied to the positive supply (VA+) or ground (AGND). MDRV- - Modulator Differential Voltage Reference, PIN 2. This is the -3.75V modulator differential voltage reference output and can be used to generate an analog reference. Note this is with reference to the MDRV+ pin. CS5516, CS5520 DS74F1 DS74F2
BX1 and BX2 - AC Bridge Excitation Signals, PINS 12, 11. These can be buffered to drive the transducer or used as synchronizing signals for a transducer drive circuit. BX1 and BX2 are 0 to +5V signals. DRDY - Data Ready, PIN 15. DRDY goes low every 81,920 cycles of XIN (when in read conversion data mode) to indicate that new data has been placed in the output port. DRDY goes high when all the serial port data is clocked out, when the serial port is being updated with new data, when a calibration is in progress, or when the device is in SLEEP. SOD - Serial Output Data, PIN 18. Data from the serial port will be output from this pin at a rate determined by SCLK . The data will either be conversion data, or, calibration values, dependent upon the command word that has been previously input on the SID pin. The SOD pin furnishes a high impedance output state when not transmitting data (SMODE = 0). ORDERING GUIDE Model Number Linearity Error (Max) Temperature Range Package CS5516-AP 0.003% -40°C to +85°C 24-pin 0.3" Plastic DIP CS5516-AS 0.003% -40°C to +85°C 24-pin 0.3" SOIC CS5520-BP 0.0015% -40°C to +85°C 24-pin 0.3" Plastic DIP CS5520-BS 0.0015% -40°C to +85°C 24-pin 0.3" SOIC CS5516, CS5520 DS74F1 DS74F2 ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Package Resolution Liearity Error Channels Temperature CS5516-AP 24-pin Plastic DIP
16 Bits
0.0030% -40 to +85 °C CS5516-AS 24-pin SOIC CS5516-ASZ (lead free) CS5520-BP 24-pin Plastic DIP
20 Bits
0.0015% CS5520-BS 24-pin SOIC CS5520-BSZ (lead free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5516-AP 260 °C No Limit CS5516-AS 240 °C
365 Days
CS5516-ASZ (lead free) 260 °C
7 Days
260 °C No Limit CS5520-BS 240 °C CS5520-BSZ (lead free) 260 °C
The deviation of a code from a straight line which extends between two fixed points on the A/D converter transfer function. In unipolar mode, the straight line extends from one point located 1⁄2 LSB below the first code transition, one count above all zeros; to the second point located 1⁄2 LSB beyond the code transition to all ones. In bipolar mode, the straight line extends from one point located 1⁄2 LSB beyond the code transition to all ones, passing through a point 1⁄2 LSB below code 8000(H) (16-bit); 80000(H) (20-bit); extending to beyond negative full scale. Units are in percent of full-scale. Differential Nonlinearity The deviation of a code’s width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition form the ideal [{(VREF+)-(VREF-)}-3⁄2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1⁄2 LSB above AGND) when in unipolar mode (BP/UP low). Units are in LSBs. Bipolar Offset AGND) when in bipolar mode (BP/UP high). Units are in LSBs. CS5516, CS5520 DS74F1 DS74F2 Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
Copyright Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CDB5516 CDB5520 CS5516 and CS5520 ADC Evaluation Board lRS232 Serial Communicationswith host PC lSupports either AC or DC bridge drive lOn-board bridge driver lSupports ratiometric or absolute measurements lEvaluation software included The CDB5516 and CDB5520 provide quick and easy evaluation of the CS5516 and CS5520 bridge transducer A/D converters. Direct connection of the bridge to the evaluation board is provided. The board also contains a microcontroller, with firmware which allows the board to be controlled via simple serial commands, using the RS232 communications port of a PC. I VREF+ VREF- AIN+ AIN- Clock Microcontroller RS232 Driver/ Receiver RS232 Connector BX1 BX2 +5V -5V +5V CS5516 CS5520 SCLK SID SOD Load Cell Bridge Excitation MAR ‘95 DS74DB# Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) http://www.cirrus.com CDB5516 CDB5520 CS5516 & CS5520 ADC Evaluation Boards SEP ‘05 DS74DB4
or ac excitation to the bridge.
25 Pin
Figure 2. Microcontroller and RS-232 Interface
R5, R7, C16, and C17 in some applications. perform the gain calibration step. Figure 6. Using Off-board Voltage Reference
Figure 8. CDB5520 Silkscreen
Figure 9. CDB5520 Top Ground Plane
Figure 10. CDB5520 Solder Side Trace Layer
Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.