CS5510

CS5510 CIRRUS | Alldatasheet

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zDelta-sigma Analog-to-digital Converter – Linearity Error: 0.0015% FS – Noise-free Resolution: Up to 17 Bits zDifferential Bipolar Analog Inputs zVREF Input Range from 250 mV to 5 V z50/60 Hz Simultaneous Rejection (CS5510/12) z16 to 326 Sps Output Word Rate zOn-chip Oscillator (CS5511/13) zPower Supply Configurations: – Multiple Dual-supply Arrangements zLow Power Consumption – Normal Mode, 2.5 mW – Sleep Mode, 10 µW zLow-cost, Compact, 8-pin Package zLead-free Device Package Options General Description The CS5510/11/12/13 are low-cost, easy-to-use, ∆Σ an- alog-to-digital converters (ADCs) which use charge- balance techniques to achieve 16-bit (CS5510/11) and 20-bit (CS5512/13) performance. The ADCs are avail- able in a space-efficient, 8-pin SOIC package and are optimized for measuring signals in weigh scale, process control, and other industrial applications. To accommodate these applications, the ADCs include a fourth-order ∆Σ modulator and a digital filter. When configured with an external master clock of 32.768 kHz, the filter in the CS5510/12 provides better than 80 dB of simultaneous 50 and 60 Hz line rejection, and outputs conversion words at 53.5 Sps. The CS5511/13 include an on-chip oscillator which eliminates the need for an ex- ternal clock source. Low-power, flexible supply configurations, compact pi- nout, and ease of use make these products ideal solutions for cost-conscience and space-constrained applications.

ORDERING INFORMATION

See page 23. AIN+ AIN- VREF Clock Gen. ~0.8X Differential 4th-order Delta-sigma Modulator Digital Filter Control Output SCLK SDO Logic Oscillator (CS5511/13 only) (CS5510/12 only) CS AUG ‘05 DS337F3

Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.

CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS (TA = 25° C; V+ = 5 V ±5%; V- = 0 V; VREF = 2.5 V (relative to V-); CS5510/12, SCLK = 32.768 kHz; CS5511/13, fosc = 64 kHz ±32 kHz; OWR (Output Word Rate) = 53.5 Sps for CS5510/12; OWR = 107 Sps ± 50% for CS5511/13) (See Note 1.) Notes: Specifications guaranteed by design, characterization, and/or test. Specification applies to the device only and does not include any effects by external parasitic thermocouples. Drift over specified temperature range after power-up at 25° C. Wideband noise aliased into the baseband. Referred to the input. Typical values shown for 25° C. For peak-to-peak noise multiply by 6.6. See the section of the data sheet which discusses Analog Input Models. For CS5511/13, OWR = 107 Sps ± 50%. Specifications are subject to change without notice. Parameter Min Typ Max Unit Accuracy Linearity Error (CS5510/11) ±0.0015 ±0.003 % FS Linearity Error (CS5512/13) ±0.0007 ±0.0015 % FS No Missing Codes (CS5510/11) Bits No Missing Codes (CS5512/13) Bits Bipolar Offset (CS5510/11) (Note 2) LSB16 Bipolar Offset (CS5512/13) (Note 2) ±40 ±100 LSB20 Offset Drift Over Temperature (Notes 2 and 3) nV/°C Gain Drift Over Temperature (Note 3) ppm/°C Analog Input Common Mode + Signal on AIN+ or AIN- Dual Supply V Input Range (Bipolar) |(AIN+ - AIN-)/(VREF - V-)| % VREF Common Mode Rejection dc 50, 60Hz (CS5510/12) 120 120 dB dB Input Capacitance pF CVF Current AIN+, AIN- (Note 6) nA Typical Noise (Notes 4, 5 and 7) Output Word Rate (Hz) -3 dB Filter Frequency (Hz) Noise (µV RMS) 53.5 12.5 7.5

ANALOG CHARACTERISTICS (Continued) Notes: VREF is referenced to V- and must be less than or equal to V+. Due to current through the CS pin, IV+ and IV- may not always be the same value. 10. All outputs unloaded. All inputs CMOS levels (> (V+ - 0.6 V) or < (V- + 0.6 V)). 11. CS must be inactive (logic high) during sleep to meet this power specification. DIGITAL CHARACTERISTICS (TA = 25° C; V+ = 5 V ±5%; V- = 0 V) (See Notes 1 and 12.) Notes: 12. All measurements performed under static conditions. 13. 14. The CS signal provides the sink current path for the SDO pin when CS is low. The external drive logic to CS, therefore, must be able to handle the logic-low current drive levels for all devices attached to SDO. The voltage specified for SDO is relative to CSLow. See Section 2.3.1, “Digital Logic Levels” and Figure 11 for more details. Parameter Min Typ Max Unit Voltage Reference Input Range {(VREF) - (V-)} (Note 8) 0.250 2.5 (V+) - (V-) V Input Capacitance pF CVF current nA Power Supplies Supply Voltages {(V+) - (V-)} 4.75 5.25 V DC Power Supply Currents (Note 9) IV+ CS5510 CS5511 CS5512 CS5513 IV- CS5510 CS5511 CS5512 CS5513 275 290 360 385 275 290 360 385 360 380 470 500 360 380 470 500 µA µA µA µA µA µA µA µA Power Consumption (Note 10) CS5510 CS5511 CS5512 CS5513 Sleep (Note 11) 1.4 1.5 1.8 1.9 1.9 2.0 2.5 2.7 mW mW mW mW µW Power Supply Rejection dc Positive Supply dc Negative Supply dB dB Parameter Symbol Min Typ Max Unit High-Level Input Voltage: CS and SCLK VIH V+ - 0.45 V Low-Level Input Voltage: (Note 13) CS SCLK CSLow VIL VL1 VL1 V V Input Current: (Note 14) CS ICS 1.0 mA High-Level Output Voltage: SDO, Isource = 5.0mA VOH (V+) - 0.6 V Low-Level Output Voltage: (Note 14) SDO, Isink = 1.0mA VOL (CSLow) + 0.6 V Input Leakage Current SCLK Iin ±0.015 ±10 µA 3-State Leakage Current SCLK IOZ ±10 µA

(V- = 0 V) (See Note 15.) Notes: 15. All voltages with respect to V-. 16. V+ and V- must satisfy 0.0V ≤ {(V+) - (V-)} ≤ +6.0 V. 17. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pins. 18. Transient current of up to 100 mA will not cause SCR latch-up. Maximum input current for a power supply pin is ±50 mA. 19. Total power dissipation, including all input currents and output currents. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Ratio Units Modulator Sampling Frequency CS5510/12 CS5511/13 fs fs SCLK/4 fosc/4 Hz Hz Output Word Rate CS5510/12 CS5511/13 OWR OWR SCLK/612 fosc/612 Sps Sps Filter Settling Time to 1/2 LSB (Full Scale Step) ts 4/OWR s Parameter Symbol Min Typ Max Unit DC Power Supplies (Note 16) Positive Negative -0.3 -6.0 +6.0 +0.3 V V Input Current, Any Pin Except Supplies (Notes 17 and 18) IIN ±10 mA Output Current IOUT ±25 mA Package Power Dissipation (Note 19) PDN 400 mW Analog Input Voltage AIN pins VINA (V-)+(-0.3) (V+)+0.3 V Digital Input Voltage VIND (V-)+(-0.3) (V+)+0.3 V Ambient Operating Temperature TA -40 +85 Storage Temperature Tstg -65 +150

SWITCHING CHARACTERISTICS - CS5510/12 (TA = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF) Notes: 20. Device parameters are specified with 32.768 kHz clock; however, clocks up to 130 kHz (CS5510) or 200 kHz (CS5512) can be used for increased throughput. Higher clock rates will result in degraded linearity specifications, as shown in Figures 14 and 15. 21. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. 22. On the CS5510/12, the serial clock input (SCLK) provides the master clock to operate the converter as well as the serial data clock used to read conversion data. If SCLK is held high (logic 1) for tSLP or longer, the CS5510/12 enters sleep. To exit from sleep mode, SCLK must be held low (logic 0) for tWAKE or longer. Parameter Symbol Min Typ Max Unit Master Clock Timing Master Clock Frequency (CS5510) (Note 20) SCLK 32.768 130 kHz Master Clock Frequency (CS5512) (Note 20) SCLK 32.768 200 kHz Master Clock Duty Cycle Rise Times (Note 21) CSB SCLK SDO trise 1.0 µs µs ns Fall Times (Note 21) CSB SCLK SDO tfall 1.0 µs µs ns Serial Port Timing Serial Clock Frequency (CS5510) (Note 22) SCLK 32.768 130 kHz Serial Clock Frequency (CS5512) (Note 22) SCLK 32.768 200 kHz SCLK High to Enter Sleep (Note 22) tSLP 200 2000 µs SCLK Low to Exit Sleep (Note 22) tWAKE µs Serial Clock Pulse Width High Pulse Width Low µs µs SDO Read Timing CS to Data Valid 150 ns SCLK Falling to New Data Bit 150 ns CS Rising to SDO Hi-Z 150 ns CS Falling to SCLK Rising t11 200 ns

SWITCHING CHARACTERISTICS - CS5511/13 (TA = 25° C; V+ = 5 V ±5%; V- = 0 V; Input Levels: Logic 0 = 0 V, Logic 1 = V+; CL = 50 pF) Notes: 23. The internal oscillator in the CS5511/13 provides the master clock for performing conversions. Data is retrieved from the serial port using the SCLK input pin. 24. The minimum SCLK rate for the CS5511/13 assumes that SCLK is logic 0 when idle. When data is being read from the ADC, SCLK must be burst at a minimum rate of 10 kHz and with a minimum of a 10 percent duty cycle. Rates slower than this can potentially put the ADC into sleep as the sleep mode is entered after SCLK is logic 1 for tSLP time. 25. On the CS5511/13, the serial clock (SCLK) is used to transfer data from the CS5511/13. If SCLK is held high (logic 1) for tSLP or longer, the CS5511/13 enters sleep mode. To exit from sleep mode, SCLK must be held low (logic 0) for tWAKE or longer. 26. Specified using 10% and 90% points on waveform of interest. Output loaded with 50 pF. Parameter Symbol Min Typ Max Unit Internal Oscillator Timing Internal Oscillator Frequency (Note 23) fosc 100 kHz Internal Oscillator Drift Over Temperature -0.02 %/°C Serial Port Timing Serial Clock Frequency (Note 24) SCLK MHz SCLK High to Enter Sleep (Notes 24 and 25) tSLP 200 2000 µs SCLK Low to Exit Sleep (Notes 24 and 25) tWAKE µs Rise Times (Note 26) CSB SCLK SDO trise 1.0 µs µs ns Fall Times (Note 26) CSB SCLK SDO tfall 1.0 µs µs ns Serial Clock Pulse Width High Pulse Width Low 200 200 ns ns SDO Read Timing CS to Data Valid 150 ns SCLK Falling to New Data Bit 150 ns CS Rising to SDO Hi-Z t10 150 ns CS Falling to SCLK Rising t11 200 ns

ing once a clock source is applied to the SCLK pin. again to signal that the conversion is complete.

24 SCLKs

Figure 16. Data Word Timing for the CS5510.

Figure 17. Data Word Timing for the CS5511. Figure 18. Data Word Timing for the CS5512. Figure 19. Data Word Timing for the CS5513.

words after the modulator becomes stable again. if any overrange condition occurs. Table 1. CS5512/13 Output Conversion Data Register Description (Flags + 20 bits). Table 2. CS5510/11 Output Conversion Data Register Description (Flags + 16 bits). Table 3. CS5510/11/12/13 Output Coding.

ter the step is applied will not be fully settled. a fully-settled result from the ADC. Figure 20. Digital Filter Response. Table 4. Digital Filter Response at 32.768 kHz.

priate time during the third conversion cycle to en- sure the maximum possible throughput. 2.6 Digital Off-chip System Calibration The CS5510/11/12/13 exhibit excellent linearity with low offset and gain drift, without the need for calibration. If precision voltage measurements are required by the system, however, software-based offset and gain calibration can be performed by the system. To perform a software offset calibration, the “zero- point” of the system should be established by ap- plying an input to the system equal to zero. Then, the user can obtain a conversion and store it in memory as the system’s zero point (ZP). This num- ber can then be used as the zero point for any sub- sequent conversion words. In the 20-bit devices (CS5512 and CS5513), multiple conversions can be averaged to arrive at a more accurate offset val- ue. In the 16-bit devices (CS5510 and CS5511), averaging may not be meaningful, because the noise will be below the size of one LSB when using nominal voltages for VREF (2.5 V). A software gain calibration can be performed by bringing the system to a known calibration Voltage value (Vcal) and acquiring a conversion (note that Vcal should be low enough to compensate for the possible gain error of the ADC). Multiple conver- sions can be averaged at this point to improve the accuracy of the calibration. The code obtained from this conversion is the real value (Cr) of the calibration Voltage input, and will differ from the ideal value. The ideal value for this conversion (Ci) will be equivalent to: 0x7FFF*Vcal/(0.80*Vref) for the CS5510/11, and 0x7FFFF*Vcal/(0.80*Vref) for the CS5512/13. The gain error (GE) is equal to: (Cr - ZP)/Ci. To correct for both offset and gain error in subsequent conversions, subtract the offset error, and then divide by the gain error. 2.7 Power Consumption, Sleep and Reset The CS5510/11/12/13 accommodates two power modes: normal and sleep. The normal mode is the default mode and is entered after power is estab- lished to the ADC. In normal mode, the ADCs typ- ically consumes 2.5 mW. Sleep is entered when the user leaves SCLK high for at least 200 µs. The ADCs are guaranteed to be in sleep after SCLK is high (logic 1) for 2 ms. The sleep mode reduces the consumed power to less than 10 µW when CS is high (logic 1). If CS is low (logic 0) at this time, the SDO drive logic will still be active, and the con- sumed sleep power will be greater. To exit sleep and return to normal mode, the user must return SCLK low for at least 10 µs. After a sleep is exited, the ADCs reset all their internal logic, including their digital filters, and begin performing conver- sions. Since the filters are reset, the first three con- version after returning to normal mode will not be fully settled. 2.8 PCB Layout The CS5510/11/12/13 should be placed entirely over the analog ground. Place the analog-digital plane split immediately adjacent to the digital pins of the chip.

1. PIN DESCRIPTIONS Control Pins and Serial Data I/O CS - Chip Select, Pin 4 CS is a dual function pin, which determines the state of SDO, as well as the digital logic-low output level. When CS is low, SDO will be active. When high, the SDO pin will output a high-impedance state. The logic-low level of SDO will match the active-low voltage on CS. SDO - Serial Data Output, Pin 8 SDO is the serial data output. It will output a high-impedance state if CS = 1. The logic-low level of SDO will match the active-low voltage on CS. SCLK - Serial Clock Input, Pin 5 SCLK is the serial bit-clock which controls the shifting of data from the ADCs. This input goes through a Schmitt trigger to allow for slow rise and fall time signals. If held high, the device will enter sleep mode. In the CS5510/12, this input is also used as a master clock source which determines conversion speeds and throughput. In the CS5511/13, SCLK is only used to read the conversion data and put the part in sleep mode. Measurement and Reference Inputs AIN+, AIN- - Differential Analog Input, Pins 2, 3 Differential input pins into the device VREF - Voltage Reference Input, Pin 1 Input Voltage which establishes the voltage reference, with respect to V-, for the on-chip modulator Power Supply Connections V+ - Positive Power, Pin 6 Positive supply voltage V- - Negative Supply, Pin 7 Negative supply voltage SDO SCLK CS AIN- AIN+ VREF

1. SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two end points of the A/D Converter transfer function. One end point is located 1/2 LSB below the first code transition and the other end point is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code's width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF) - (V-)} - 3/2 LSB]. Units are in LSBs. Bipolar Offset voltage on the AIN- pin). Units are in LSBs.LK

1. ORDERING INFORMATION ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020.

REVISION HISTORY

Linearity Error (Max) Temperature Range Package CS5510-AS External

16 Bits

±0.003% -40°C to +85°C 8-pin SOIC CS5510-ASZ (Lead Free) CS5511-AS Internal CS5511-ASZ (Lead Free) CS5512-BS External

20 Bits

±0.0015% CS5512-BSZ (Lead Free) CS5513-BS Internal CS5513-BSZ (Lead Free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5510-AS 240 °C

365 Days

CS5510-ASZ (Lead Free) 260 °C

7 Days

240 °C CS5511-ASZ (Lead Free) 260 °C 240 °C CS5512-BSZ (Lead Free) 260 °C 240 °C CS5513-BSZ (Lead Free) 260 °C Added lead-free device ordering information. AUG 2005 Updated lead-free device ordering information. Added MSL data.

1. PACKAGE DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A 0.076 0.080 0.084 1.93 2.03 2.13 0.004 0.007 0.010 0.10 0.175 0.25 b 0.013 0.016 0.020 0.33 0.406 0.51 C 0.006 0.008 0.010 0.15 0.20 0.25 D 0.206 0.208 0.210 5.23 5.28 5.33 E 0.204 0.208 0.212 5.18 5.28 5.38 e 0.040 0.050 0.060 1.02 1.27 1.52 H 0.302 0.310 0.318 7.67 7.88 8.08 L 0.019 0.025 0.030 0.48 0.64 0.76 EIAJ PACKAGE Controlling Dimension is Inches 8L SOIC (208 MIL BODY) PACKAGE DRAWING D H E e b A c L SEATING PLANE