CS5505 CIRRUS | Alldatasheet
Document overview
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Technical content
Features
lVery Low Power Consumption - Single supply +5 V operation: 1.7 mW - Dual supply ±5 V operation: 3.2 mW lOffers superior performance to VFCs and multi-slope integrating ADCs lDifferential Inputs - Single Channel (CS5507/8) and Four-Channel (CS5505/6) pseudo-differential versions lEither 5 V or 3.3 V Digital Interface lLinearity Error: lOutput update rates up to 100 Sps lFlexible Serial Port lPin-Selectable Unipolar/Bipolar Ranges
Description
The CS5505/6/7/8 are a family of low power CMOS A/D converters which are ideal for measuring low-frequency signals representing physical, chemical, and biological processes. The CS5507/8 have single-channel differential analog and reference inputs while the CS5505/6 have four pseudo-differential analog input channels. The CS5505/7 have a 16-bit output word. The CS5506/8 have a 20-bit output word.The CS5505/6/7/8 sample upon command up to 100 Sps. The on-chip digital filter offers superior line rejection at 50 and 60 Hz when the device is operated from a 32.768 kHz clock (output word rate = 20 Sps). The CS5505/6/7/8 include on-chip self-calibration cir- cuitry which can be initiated at any time or temperature to ensure minimum offset and full-scale errors. The CS5505/6/7/8 serial port offers two general-purpose modes for the direct interface to shift registers or syn- chronous serial ports of industry-standard microcontrollers.
ORDERING INFORMATION
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ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V(external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) CS5505/7-A CS5507-S Parameter* Min Typ Max Min Typ Max Units Specified Temperature Range -40 to +85 -55 to +125 Accuracy Linearity Error 0.0015 0.003 0.0015 0.003 ±%FS Differential Nonlinearity ±0.25 ±0.5 ±0.25 ±0.5 LSB16 Full Scale Error (Note 3) ±0.25 ±0.5 LSB16 Full Scale Drift (Note 4) ±0.5 LSB16 Unipolar Offset (Note 3) ±0.5 LSB16 Unipolar Offset Drift (Note 4) ±0.5 LSB16 Bipolar Offset (Note 3) ±0.25 ±0.5 LSB16 Bipolar Offset Drift (Note 4) ±0.25 ±0.5 LSB16 Noise (Referred to Output) 0.16 0.16 LSB- rms16 Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both source resistance and shunt capacitance are therefore critical in determining the CS5505/6/7/8’s source impedance requirements. For more information refer to the text section Analog Input Impedance Considerations. 2. Specifications guaranteed by design, characterization and/or test. 3. Applies after calibration at the temperature of interest. 4. Total drift over the specified temperature range since calibration at power-up at 25°C. Recalibration at any temperature will remove these errors. Specifications are subject to change without notice. * Refer to the Specification Definitions immediately following the Pin Description Section. Unipolar Mode Bipolar Mode mV LSB’s % FS ppm FS LSB’s % FS ppm FS 0.26 0.0004 0.13 0.0002 0.50 0.0008 0.26 0.0004 1.00 0.0015 0.50 0.0008 2.00 0.0030 1.00 0.0015 152 4.00 0.0061 2.00 0.0030 VREF = 2.5V CS5505/7; 16-Bit Unit Conversion Factors CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) CS5506/8-B CS5508-S Parameter* Min Typ Max Min Typ Max Units Specified Temperature Range -40 to +85 -55 to +125 Accuracy Linearity Error 0.0007 0.0015 0.0015 0.003 ±%FS Differential Nonlinearity (No Missing Codes) Bits Full Scale Error (Note 3) ±32 ±32 LSB20 Full Scale Drift (Note 4) ±32 LSB20 Unipolar Offset (Note 3) ±32 ±16 ±64 LSB20 Unipolar Offset Drift (Note 4) ±16 LSB20 Bipolar Offset (Note 3) ±16 ±32 LSB20 Bipolar Offset Drift (Note 4) LSB20 Noise (Referred to Output) 2.6 2.6 LSB- rms20 Unipolar Mode Bipolar Mode mV LSB’s % FS ppm FS LSB’s % FS ppm FS 0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12 1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24 2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47 4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95 9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91 VREF = 2.5V CS5506/8; 20-Bit Unit Conversion Factors DYNAMIC CHARACTERISTICS Parameter Symbol Ratio Units Modulator Sampling Frequency fs fclk/2 Hz Output Update Rate (CONV = 1) fout fclk/1622 Sps Filter Corner Frequency f-3dB fclk/1928 Hz Settling Time to 1⁄2 LSB (FS Step) ts 1/fout s CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VA- = -5V ± 10%; VD+ = 3.3V ± 5%; VREF+ = 2.5V (external); VREF- = 0V; fCLK = 32.768kHz; Bipolar Mode; Rsource = 1kΩ with a 10nF to AGND at AIN; Analog input channel AIN1+; AIN- = AGND; unless otherwise specified.) (Notes 1, 2) CS5505/7 CS5506/8 CS5507/8-S Parameter* Min Typ Max Min Typ Max Units Specified Temperature Range -40 to +85 -55 to +125 Analog Input Analog Input Range: Unipolar (VAIN+)-(VAIN-) Bipolar (Note 5) 0 to +2.5 ±2.5 0 to +2.5 ±2.5 Volts Volts Common Mode Rejection: dc 50, 60 Hz (Note 6) 120 105 120 105 dB dB Off Channel Isolation 120 120 dB Input Capacitance pF DC Bias Current (Note 1) nA Voltage Reference (Output) VREFOUT Voltage (VA+)-2.5 (VA+)-2.5 Volts VREFOUT Voltage Tolerance 4.0 4.0 VREFOUT Voltage Temperature Coefficient ppm/°C VREFOUT Line Regulation 1.5 1.5 mV/Volt VREFOUT Output Voltage Noise 0.1 to 10 Hz µVp-p VREFOUT: Source Current Sink Current µA µA Power Supplies DC Power Supply Currents: ITotal IAnalog IDigital 340 300 450 340 300 450 µA µA µA Power Dissipation: (Note 7) SLEEP inactive SLEEP active 3.2 4.5 3.2 4.5 mW µW Power Supply Rejection: Positive Supplies Negative Supplies dB dB Notes: 5. Common mode voltage may be at any value as long as AIN+ and AIN- remain within the VA+ and VA- supply voltages. 6. XIN = 32.768 kHz. Guaranteed by design and / or characterization. 7. All outputs unloaded. All inputs CMOS levels. SLEEP mode controlled by M/SLP pin. SLEEP active = M/SLP pin at (VD+)/2 input level. CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
5V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+VD+ = 5V ± 10%; VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2) Parameter Symbol Min Typ Max Units High-Level Input Voltage: XIN M/SLP All Pins Except XIN and M/SLP VIH VIH VIH 3.5 0.9VD+ 2.0 V V V Low-Level Input Voltage: XIN M/SLP All Pins Except XIN and M/SLP VIL VIL VIL 1.5 0.1VD+ 0.8 V V V M/SLP SLEEP Active Threshold (Note 8) VSLP 0.45VD+ 0.5VD+ 0.55VD+ V High-Level Output Voltage (Note 9) VOH (VD+)-1.0 V Low Level Output Voltage Iout = 1.6 mA VOL 0.4 V Input Leakage Current Iin µA 3-State Leakage Current IOZ ±10 µA Digital Output Pin Capacitance Cout pF Notes: 8. Under normal operation this pin should be tied to VD+ or DGND. Anytime the voltage on the M/SLP pin enters the SLEEP active threshold range the device will enter the power down condition. Returning to the active state requires elapse of the power-on reset period, the oscillator to start-up, and elapse of the wake-up period. 3.3V DIGITAL CHARACTERISTICS (TA = TMIN to TMAX; VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VA-= -5V ± 10%; DGND = 0.) All measurements below are performed under static conditions. (Note 2) Parameter Symbol Min Typ Max Units High-Level Input Voltage: XIN M/SLP All Pins Except XIN and M/SLP VIH VIH VIH 0.7VD+ 0.9VD+ 0.6VD+ V V V Low-Level Input Voltage: XIN M/SLP All Pins Except XIN and M/SLP VIL VIL VIL 0.3VD+ 0.1VD+ 0.16VD+ V V V M/SLP SLEEP Active Threshold (Note 8) VSLP 0.43VD+ 0.45VD+ 0.47VD+ V High-Level Output Voltage Iout = -400 µA VOH (VD+)-0.3 V Low Level Output Voltage Iout = 400 µA VOL 0.3 V Input Leakage Current Iin µA 3-State Leakage Current IOZ ±10 µA Digital Output Pin Capacitance Cout pF CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Symbol Min Typ Max Units Master Clock Frequency: Internal Oscillator: -A,B External Clock: XIN or fclk 30.0 30.0 32.768 32.768 53.0 34.0 163 kHz kHz kHz Master Clock Duty Cycle Rise Times: Any Digital Input (Note 10) Any Digital Output trise 1.0 µs ns Fall Times: Any Digital Input (Note 10) Any Digital Output tfall 1.0 µs ns Start-Up Power-On Reset Period (Note 11) tres ms Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu 500 ms Wake-up Period (Note 13) twup 1800/fclk s Calibration CONV Pulse Width (CAL = 1) (Note 14) tccw 100 ns CONV and CAL High to Start of Calibration tscl 2/fclk+200 ns Start of Calibration to End of Calibration tcal 3246/fclk s Conversion Set Up Time A0, A1 to CONV High tsac ns Hold Time A0, A1 after CONV High thca 100 ns CONV Pulse Width tcpw 100 ns CONV High to Start of Conversion tscn 2/fclk+200 ns Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk s Hold Time BP/UP stable after DRDY falls tbuh ns Start of Conversion to End of Conversion (Note 15) tcon 1624/fclk s Notes: 10. Specified using 10% and 90% points on waveform of interest. 11. An internal power-on-reset is activated whenever power is applied to the device, or when coming out of a SLEEP state. 12. Oscillator start-up time varies with the crystal parameters. This specification does not apply when using an external clock source. 13. The wake-up period begins once the oscillator starts; or when using an external fclk, after the power-on reset time elapses. 14. Calibration can also be initiated by pulsing CAL high while CONV=1. 15. Conversion time will be 1622/fclk if CONV remains high continuously. CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Symbol Min Typ Max Units Master Clock Frequency: Internal Oscillator: -A,B External Clock: XIN or fclk 30.0 30.0 32.768 32.768 53.0 34.0 163 kHz kHz kHz Master Clock Duty Cycle Rise Times: Any Digital Input (Note 10) Any Digital Output trise 1.0 µs ns Fall Times: Any Digital Input (Note 10) Any Digital Output tfall 1.0 µs ns Start-Up Power-On Reset Period (Note 11) tres ms Oscillator Start-up Time XTAL=32.768 kHz (Note 12) tosu 500 ms Wake-up Period (Note 13) twup 1800/fclk s Calibration CONV Pulse Width (CAL = 1) (Note 14) tccw 100 ns CONV and CAL High to Start of Calibration tscl 2/fclk+200 ns Start of Calibration to End of Calibration tcal 3246/fclk s Conversion Set Up Time A0, A1 to CONV High tsac ns Hold Time A0, A1 after CONV High thca 100 ns CONV Pulse Width tcpw 100 ns CONV High to Start of Conversion tscn 2/fclk+200 ns Set Up Time BP/UP stable prior to DRDY falling tbus 82/fclk s Hold Time BP/UP stable after DRDY falls tbuh ns Start of Conversion to End of Conversion (Note 15) tcon 1624/fclk s CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
5V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V ± 10%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Symbol Min Typ Max Units SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS = low) tcsd1 tdfd 2/fclk 2/fclk 3/fclk ns ns SDATA Delay Time: SCLK falling to next SDATA bit tdd1 250 ns SCLK Delay Time SDATA MSB bit to SCLK rising tcd1 1/fclk ns Serial Clock (Out) Pulse Width High Pulse Width Low tph1 tpl1 1/fclk 1/fclk ns ns Output Float Delay: CS high to output Hi-Z (Note 16) SCLK rising to SDATA Hi-Z tfd1 tfd2 1/fclk 2/fclk ns ns SEC Mode (M/SLP = DGND) Serial Clock (In) fsclk 2.5 MHz Serial Clock (In) Pulse Width High Pulse Width Low tph2 tpl2 200 200 ns ns Access Time: CS Low to data valid (Note 17) tcsd2 200 ns Maximum Delay time: (Note 18) SCLK falling to new SDATA bit tdd2 150 310 ns Output Float Delay: CS high to output Hi-Z (Note 16) SCLK falling to SDATA Hi-Z tfd3 tfd4 160 150 300 ns ns Notes: 16. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance. 17. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 2 clock cycles. The propagation delay time may be as great as 2 fclk cycles plus 200 ns. To guarantee proper clocking of SDATA when using asynchronous CS, SCLK(i) should not be taken high sooner than 2 fclk + 200 ns after CS goes low. 18. SDATA transitions on the falling edge of SCLK. Note that a rising SCLK must occur to enable the serial port shifting mechanism before falling edges can be recognized. CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
3.3V SWITCHING CHARACTERISTICS (TA = TMIN to TMAX VA+ = 5V ± 10%; VD+ = 3.3V ± 5%; VA- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF.) (Note 2) Parameter Symbol Min Typ Max Units SSC Mode (M/SLP = VD+) Access Time: CS Low to SDATA out (DRDY = low) DRDY falling to MSB (CS = low) tcsd1 tdfd 2/fclk 2/fclk 3/fclk ns ns SDATA Delay Time: SCLK falling to next SDATA bit tdd1 265 400 ns SCLK Delay Time SDATA MSB bit to SCLK rising tcd1 1/fclk ns Serial Clock (Out) Pulse Width High Pulse Width Low tph1 tpl1 1/fclk 1/fclk ns ns Output Float Delay: CS high to output Hi-Z (Note 16) SCLK rising to SDATA Hi-Z tfd1 tfd2 1/fclk 2/fclk ns ns SEC Mode (M/SLP = DGND) Serial Clock (In) fsclk 1.25 MHz Serial Clock (In) Pulse Width High Pulse Width Low tph2 tpl2 200 200 ns ns Access Time: CS Low to data valid (Note 17) tcsd2 100 200 ns Maximum Delay time: (Note 18) SCLK falling to new SDATA bit tdd2 400 600 ns Output Float Delay: CS high to output Hi-Z (Note 16) SCLK falling to SDATA Hi-Z tfd3 tfd4 320 150 500 ns ns CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
RECOMMENDED OPERATING CONDITIONS (DGND = 0V) (Note 19) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital (VA+)-(VA-) Positive Analog Negative Analog VD+ Vdiff VA+ VA- 3.15 4.5 4.5 5.0 5.0 -5.0 5.5 -5.5 V V V V Analog Reference Voltage (Note 20) (VREF+)-(VREF-) 1.0 2.5 3.6 V Analog Input Voltage: (Note 21) Unipolar Bipolar VAIN VAIN -((VREF+)-(VREF-)) (VREF+)-(VREF-) +((VREF+)-(VREF-)) V V Notes: 19. All voltages with respect to ground. 20. The CS5505/6/7/8 can be operated with a reference voltage as low as 100 mV; but with a corresponding reduction in noise-free resolution. The common mode voltage of the voltage reference may be any value as long as +VREF and -VREF remain inside the supply values of VA+ and VA-. 21. The CS5505/6/7/8 can accept input voltages up to the analog supplies (VA+ and VA-). In unipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative than 0 Volts. In bipolar mode the CS5505/6/7/8 will output all 1’s if the dc input magnitude ((AIN+)-(AIN-)) exceeds ((VREF+)-(VREF-)) and will output all 0’s if the input becomes more negative in magnitude than -((VREF+)-(VREF-)). ABSOLUTE MAXIMUM RATINGS* Parameter Symbol Min Typ Max Units DC Power Supplies: Digital Ground (Note 22) Positive Digital (Note 23) Positive Analog Negative Analog (VA+)-(VA-) (VA+)-(VD+) DGND VD+ VA+ VA- Vdiff1 Vdiff2 -0.3 -0.3 -0.3 +0.3 -0.3 -0.3 (VD+)-0.3 6.0 or VA+ 12.0 -6.0 12.0 12.0 V V V V V V Input Current, Any Pin Except Supplies (Notes 24, 25) Iin ±10 mA Analog Input Voltage AIN and VREF pins VINA (VA-)-0.3 (VA+)+0.3 V Digital Input Voltage VIND -0.3 (VD+)+0.3 V Ambient Operating Temperature TA -55 125 Storage Temperature Tstg -65 150 Notes: 22. No pin should go more positive than (VA+)+0.3V. 23. VD+ must always be less than (VA+)+0.3 V,and can never exceed 6.0V. 24. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin. 25. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is ± 50 mA. * WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
The CS5505/6/7/8 are very low power mono- lithic CMOS A/D converters designed specifically for measurement of dc signals. The CS5505/7 are 16-bit converters (a four channel and a single channel version). The CS5506/8 are 20-bit converters (a four channel and a single channel version). Each of the devices includes a delta-sigma charge-balance converter, a voltage reference, a calibration microcontroller with SRAM, a digital filter and a serial interface. The CS5505 and CS5506 include a four channel pseudo-differential (all four channels have the same reference measurement node) multiplexer. The CS5505/6/7/8 include an on-chip reference but can also utilize an off-chip reference for pre- cision applications. The CS5505/6/7/8 can be used to measure either unipolar or bipolar sig- nals. The devices use self-calibration to insure excellent offset and gain accuracy. The CS5505/6/7/8 are optimized to operate from a 32.768 kHz crystal but can be driven by an external clock whose frequency is between 30 kHz and 163 kHz. When the digital filter is operated with a 32.768 kHz clock, the filter has zeros precisely at 50 and 60 Hz line frequencies and multiples thereof. The CS5505/6/7/8 use a "start convert" com- mand to latch the input channel selection and to start a convolution cycle on the digital filter. Once the filter cycle is completed, the output port is updated. When operated with a 32.768 kHz clock the ADC converts and updates its output port at 20 samples/sec. The throughput rate per channel is the output update rate divided by the number of channels being multi- plexed. The output port includes a serial interface with two modes of operation. The CS5505/6/7/8 can operate from dual polar- ity power supplies (+5 and -5), from a single +5 volt supply, or with +10 volts on the analog and +5 on the digital. They can also operate with dual polarity (+5 and -5), or from a single +5 volt supply on the analog and + 3.3 on the digi- tal. THEORY OF OPERATION FOR THE CS5505/6/7/8 The front page of this data sheet illustrates the block diagram of the CS5505/6. Basic Converter Operation The CS5505/6/7/8 A/D converters have four op- erating states. These are start-up, calibration, conversion and sleep. When power is first ap- plied, the device enters the start-up state. The first step is a power-on reset delay of about 10 ms which resets all of the logic in the device. To proceed with start-up, the oscillator must then begin oscillating. After the power-on reset the device enters the wake-up period for 1800 clock cycles after clock is present. This allows the delta-sigma modulator and other circuitry (which are operating with very low currents) to reach a stable bias condition prior to entering into either the calibration or conversion states. During the 1800 cycle wake-up period, the de- vice can accept an input command. Execution of this command will not occur until the complete wake-up period elapses. If no command is given, the device enters the standby mode. Calibration After the initial application of power, the CS5505/6/7/8 must enter the calibration state prior to performing accurate conversions. During calibration, the chip executes a two-step process. The device first performs an offset calibration and then follows this with a gain calibration. The two calibration steps determine the zero ref- erence point and the full scale reference point of the converter’s transfer function. From these points it calibrates the zero point and a gain CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
digital codes when doing conversions. CAL and CONV pins are high at the same time. end of the 1800 clock cycle wake-up period. (static RAM) for use during conversion. are not important during calibrations. calibration has been completed. Table 1. Multiplexer Truth Table
form continuous conversions on one channel. The conversion time will be 1622 clock cycles. certainty as to when conversion actually begins. ing data from the serial port. VA+ pin and will track changes relative to VA+. pacitor is in place for stability. Figure 5. External Reference Connections
voltage between the VA+ and VA- supply rails. ternal voltage reference use, respectively. convert the input signal (XIN = 32.768 kHz). tude stays within the supply voltages. Note: VREF = (VREF+) - (VREF-); Table excludes common mode voltage on the signal and reference inputs. Table 2. Output Coding Figure 6. Internal Reference Connections
proper output codes during conversions. have no missing code performance to 16-bits. chopper-stabilized techniques to minimize drift. Figure 7. CS5505 Differential Nonlinearity plot.
nores the multiplexer switch resistance). sample each of the inputs (AIN+ and AIN-). the sample capacitor to settle to its final value. stray or additional capacitance at the input pin. The value of t is equal to 1/(2XIN). switched from the buffer output to the AIN pin. the buffer is 100 mV, which is the worst case. be reduced to yield a longer settling time. same structure as the AIN+ and AIN- inputs. Figure 8. Analog Input Model
external clock rates from 30 kHz to 163 kHz. the control logic used on the chip. Figure 12. Gate Oscillator and Control Logic
with other crystals in the range of 30 kHz to 53 kHz. Over the military temperature range (- 55 to +125 °C) the on-chip gate oscillator is designed to work only with a 32.768 kHz crys- tal. The chip will operate with external clock frequencies from 30 kHz to 163 kHz.over all temperature ranges. The 32.768 kHz crystal is normally specified as a time-keeping crystal with tight specifications for both initial frequency and for drift over temperature. To maintain excellent frequency stability, these crystals are specified only over limited operating temperature ranges (i.e. -10 to +60 °C) by the manufacturers. Appli- cations of these crystals with the CS5505/6/7/8 do not require tight initial tolerance or low tempco drift. Therefore, a lower cost crystal with looser initial tolerance and tempco will generally be adequate for use with the CS5505/6/7/8 con- verters. Also check with the manufacturer about wide temperature range application of their standard crystals. Generally, even those crystals specified for limited temperature range will op- erate over much larger ranges if frequency stability over temperature is not a requirement. The frequency stability can be as bad as ±3000 ppm over the operating temperature range and still be typically better than the line frequency (50 or 60 Hz) stability over cycle to cycle during the course of a day. There are crystals available for operation over the military temperature range (-55 to +125 °C). See the Appendix for suppliers of 32.768 kHz crystals. Serial Interface Logic The digital filter in the CS5505/6/7/8 takes 1624 clock cycles to compute an output word once a conversion begins. At the end of the conversion cycle, the filter will attempt to update the serial port. Two clock cycles prior to the update DRDY will go high. When DRDY goes high just prior to a port update it checks to see if the port is either empty or unselected (CS = 1). If the port is empty or unselected, the digital filter will update the port with a new output word. When new data is put into the port DRDY will go low. Data can be read from the serial port in either of two modes. The M/SLP pin determines which serial mode is selected. Serial port mode selec- tion is as follows: SSC (Synchronous Self-Clocking) mode; M/SLP = VD+, or SEC (Synchronous External Clocking) mode; M/SLP = DGND. Timing dia- grams which illustrate the SSC and SEC timing are in the tables section of this data sheet. Synchronous Self-Clocking Mode The serial port operates in the SSC mode when the M/SLP pin is connected to the VD+ pin on the part. In SSC mode the CS5505/6/7/8 fur- nishes both the serial output data (SDATA) and the serial clock (SCLK). When the serial port is updated at the end of a conversion, DRDY falls. If CS is low, the SDATA and SCLK pins will come out of the high impedance state two XIN clock cycles after DRDY falls. The MSB data bit will be presented for two cycles of XIN clock. The SCLK signal will rise in the middle of the MSB data bit. When SCLK then returns low the (MSB - 1) bit will appear. Subsequent data bits will be output on each falling edge of SCLK until the LSB data bit is output. After the LSB data bit is output, the SCLK will fall at which time both the SDATA and SCLK outputs will return to the high impedance output state. DRDY will return high at this time. If CS is taken low after DRDY falls, the MSB data bit will appear within two XIN clock cycles after CS is taken low. CS need not be held low for the entire data output. If CS is returned high during a data bit the port will complete the out- put of that bit and then go into the Hi-Z state. The port can be reselected any time prior to the completion of the next conversion (DRDY fall- ing) to allow the remaining data bits to be output. CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
than the voltage on any other pin of the device. To use the internal 2.5 volt reference see Figure 6. Figure 14. CS5505/6 System Connection Diagram Using External Reference, Single Supply
(1) To use the internal 2.5 volt reference see Figure 6. (2) VD+ must never exceed VA+. Examine power-up conditions. Figure 16. CS5505/6 System Connection Diagram Using External Reference, Call Applications Engineering. Call Applications Engineering.
PIN CONNECTIONS* CS5505/6 CS5507/8 MULTIPLEXER SELECTION INPUT MULTIPLEXER SELECTION INPUT CHIP SELECT CS DRDY DATA READY CONVERT CONV SDATA SERIAL DATA OUTPUT CALIBRATE CAL SCLK SERIAL CLOCK INPUT/OUTPUT CRYSTAL IN XIN VD+ POSITIVE DIGITAL POWER CRYSTAL OUT XOUT DGND DIGITAL GROUND SERIAL MODE/ SLEEP M/SLP VA- NEGATIVE ANALOG POWER BIPOLAR/UNIPOLAR BP/UP VA+ POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT AIN1+ VREFOUT VOLTAGE REFERENCE OUTPUT DIFFERENTIAL ANALOG INPUT AIN2+ VREF- VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG RETURN AIN- VREF+ VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT AIN3+ AIN4+ DIFFERENTIAL ANALOG INPUT CHIP SELECT CS DRDY DATA READY CONVERT CONV SDATA SERIAL DATA OUTPUT CALIBRATE CAL SCLK SERIAL CLOCK INPUT/OUTPUT CRYSTAL IN XIN VD+ POSITIVE DIGITAL POWER CRYSTAL OUT XOUT DGND DIGITAL GROUND SERIAL MODE/ SLEEP M/SLP VA- NEGATIVE ANALOG POWER BIPOLAR/UNIPOLAR BP/UP VA+ POSITIVE ANALOG POWER DIFFERENTIAL ANALOG INPUT AIN+ VREFOUT VOLTAGE REFERENCE OUTPUT NO CONNECTION NC VREF- VOLTAGE REFERENCE INPUT DIFFERENTIAL ANALOG INPUT AIN- VREF+ VOLTAGE REFERENCE INPUT *Pinout applies to both DIP and SOIC CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
Pin numbers for four channel devices are in parentheses. Clock Generator XIN; XOUT - Crystal In; Crystal Out, Pins 4 (5) and 5 (6). A gate inside the chip is connected to these pins and can be used with a crystal to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the device into a lower powered state (approximately 70% power reduction). Serial Output I/O M/SLP - Serial Interface Mode Select/ Sleep, Pin 6 (7). Dual function pin which selects the operating mode of the serial port and provides a very low power sleep function. When M/SLP is tied to the VD+ pin the serial port will operate in the Synchronous Self-Clocking (SSC) mode. When M/SLP is tied to the DGND pin the serial port will operate in the Synchronous External Clocking (SEC) mode. When the M/SLP pin is tied half way between VD+ and DGND the chip will enter into a very low powered sleep mode in which its calibration data will be maintained. CS - Chip Select, Pin 1 (2). This input allows an external device to access the serial port. DRDY - Data Ready, Pin 20 (23) Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new output word has been placed into the serial port. DRDY will return high after all data bits are shifted out of the serial port or two master clock cycles before new data becomes available if the CS pin is inactive (high). SDATA - Serial Data Output, Pin 19 (22). SDATA is the output pin of the serial output port. Data from this pin will be output at a rate determined by SCLK and in a format determined by the M/SLP pin. Data is output MSB first and advances to the next data bit on the falling edges of SCLK. SDATA will be in a high impedance state when not transmitting data. SCLK - Serial Clock Input/Output, Pin 18 (21). A clock signal on this pin determines the output rate of the data from the SDATA pin. The M/SLP pin determines whether SCLK is an input or and output. When used as an input, it must not be allowed to float. CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
CAL - Calibrate, Pin 3 (4). When taken high the same time that the CONV pin is taken high the converter will perform a self-calibration which includes calibration of the offset and gain scale factors in the converter. CONV - Convert, Pin 2 (3). The CONV pin initiates a calibration cycle if it is taken from low to high while the CAL pin is high, or it initiates a conversion if it is taken from low to high with the CAL pin low. CONV latches the multiplexer selection when it transitions from low to high on the multiple channel devices. If CONV is held high (CAL low) the converter will do continuous conversions. A0, A1 - Multiplexer Selection Inputs, Pins (1, 24). A0 and A1 select the input channel for conversion on the multi-channel input devices. A0 and A1 are latched when CONV transitions from low to high. These two inputs have pull-down resistors internal to the chip. BP/UP - Bipolar/Unipolar, Pin 7 (8). The BP/UP pin selects the conversion mode of the converter. When high the converter will convert bipolar input signals; when low it will convert unipolar input signals. Measurement and Reference Inputs AIN+, AIN-, (AIN1+, AIN2+, AIN3+, AIN4+, AIN-) - Differential Analog Inputs, Pins 8, 10 (9, 10, 12, 13, 11). AIN- in the CS5505/6 is a common measurement node for AIN1+, AIN2+, AIN3+ and AIN4+. VREF+, VREF- - Differential Voltage Reference Inputs, Pins 11, 12 (14, 15). A differential voltage reference on these pins operates as the voltage reference for the converter. The voltage between these pins can be any voltage between 1.0 and 3.6 volts. Voltage Reference VREFOUT - Voltage Reference Output, Pin 13 (16). The on-chip voltage reference is output from this pin. The voltage reference has a nominal magnitude of 2.5 volts and is referenced to the VA+ pin on the converter. Power Supply Connections VA+ - Positive Analog Power, Pin 14 (17). Positive analog supply voltage. Nominally +5 volts. VA- - Negative Analog Power, Pin 15 (18). Negative analog supply voltage. Nominally -5 volts when using dual polarity supplies; or 0 volts (tied to system analog ground) when using single supply operation. CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
VD+ - Positive Digital Power, Pin 17 (20). Positive digital supply voltage. Nominally +5 volts or 3.3 volts. DGND - Digital Ground, Pin 16 (19). Digital Ground. Other NC - No Connection, Pin 9. Pin should be left floating. SPECIFICATION DEFINITIONS Linearity Error The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Nonlinearity The deviation of a code’s width from the ideal width. Units in LSBs. Full Scale Error The deviation of the last code transition from the ideal [{(VREF+) - (VREF-)} - 3⁄2 LSB]. Units are in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1⁄2 LSB above the voltage on the AIN- pin.) when in unipolar mode (BP/UP low). Units are in LSBs. Bipolar Offset the voltage on the AIN- pin.) when in bipolar mode (BP/UP high). Units are in LSBs CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
# of Resolution Linearity Temperature Package Type Number Channels Error Range (°C) CS5505-AP 16-Bits 0.0030% -40 to +85 24-pin 0.3" Plastic DIP CS5505-AS 16-Bits 0.0030% -40 to +85 24-pin 0.3" SOIC CS5506-BP 20-Bits 0.0015% -40 to +85 24-pin 0.3" Plastic DIP CS5506-BS 20-Bits 0.0015% -40 to +85 24-pin 0.3" SOIC CS5507-AP 16-Bits 0.0030% -40 to +85 20-pin 0.3" Plastic DIP CS5507-AS 16-Bits 0.0030% -40 to +85 20-pin 0.3" SOIC CS5507-SD 16-Bits 0.0030% -55 to +125 20-pin 0.3" CerDIP CS5508-BP 20-Bits 0.0015% -40 to +85 20-pin 0.3" Plastic DIP CS5508-BS 20-Bits 0.0015% -40 to +85 20-pin 0.3" SOIC CS5508-SD 20-Bits 0.0030% -55 to +125 20-pin 0.3" CerDIP CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5 ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Package Resolution Liearity Error Channels Temperature CS5505-AP 24-pin Plastic DIP
16 Bits
0.0030% -40 to +85 °C CS5505-AS 24-pin SOIC CS5505-ASZ (lead free) CS5506-BP 24-pin Plastic DIP
20 Bits
0.0015% CS5506-BS 24-pin SOIC CS5506-BSZ (lead free) CS5507-AP 20-pin Plastic DIP 0.0030% CS5507-AS 20-pin SOIC CS5507-ASZ (lead free) CS5508-BP 20-pin Plastic DIP 0.0015% CS5508-BS 20-pin SOIC CS5508-BSZ (lead free) Model Number Peak Reflow Temp MSL Rating* Max Floor Life CS5505-AP 260 °C No Limit CS5505-AS 240 °C
365 Days
CS5505-ASZ (lead free) 260 °C
7 Days
260 °C No Limit CS5506-BS 240 °C CS5506-BSZ (lead free) 260 °C 260 °C No Limit CS5507-AS 240 °C CS5507-ASZ (lead free) 260 °C 260 °C No Limit CS5508-BS 240 °C CS5508-BSZ (lead free) 260 °C
The following companies provide 32.768 kHz crystals in many package varieties and temperature ranges. Fox Electronics
5570 Enterprise Parkway
Fort Meyers, FL 33905 (813) 693-0099 Micro Crystal Division / SMH
702 West Algonquin Road
Arlington Heights, IL 60005 (708) 806-1485 SaRonix
4010 Transport Street
Palo Alto, California 94303 (415) 856-6900 Statek
512 North Main
Orange, California 92668 (714) 639-7810 IQD Ltd. North Street Crewkerne Somerset TA18 7AK England 01460 77155 Mr. Pierre Hersberger Microcrystal/DIV. ETA S.A. Schild-Rust-Strasse 17 Grenchen CH-2540 Switzerland 065 53 05 57 Taiwan X’tal Corp. 5F. No. 16, Sec 2, Chung Yang S. RD. Reitou, Taipei, Taiwan R. O. C. Tel: 02-894-1202 Fax: 02-895-6207 Interquip Limited 24/F Million Fortune Industrial Centre 34-36 Chai Wan Kok Street, Tsuen Wan N T Tel: 4135515 Fax: 4137053 S& T Enterprises, Ltd. Rm 404 Blk B Sea View Estate North Point, Hong Kong Tel: 5784921 Fax: 8073126 Mr. Darren Mcleod Hy-Q International Pty. Ltd.
12 Rosella Road,
FRANKSON, 3199 Victoria, Australia Tel: 61-3-783 9611 Fax: 61-3-783 9703 CS5505/6/7/8 DS59F4 CS5505/6/7/8 DS59F5
REVISION HISTORY
Updated device ordering info. Updated legal notice. Added MSL data.. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.
- Notes • CS5505/6/7/8 DS59F5 - NOTES -
Copyright © Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CDB5505/6/7/8 Evaluation Board for CS5505/6/7/8 Series of ADC’s lOperation with on-board 32.768 kHz crystal or off-board clock source lJumper selectable: - SSC mode; SEC mode; Sleep lDIP Switch Selectable: - BP/UP mode; A0, & A1 channel selection lOn-board precision voltage reference lAccess to all digital control pins lOn-board patch area The CDB5505/5506/5507/5508 is a circuit board de- signed to provide quick evaluation of the CS5505/6/7/8 series of A/D converters. The board can be configured to evaluate the CS5505/6/7/8 in either SSC (Synchronous Self-Clocking) or SEC (Synchronous External-Clocking) serial port mode. The board allows access to all of the digital interface pins of the CS5505/6/7/8 chip. I AIN4+ AIN3+ AIN2+ AIN1+ AIN- +5V GND -5V CS5505/6/7/8 CLKIN VREF H E A D E R B U F F E R S MAR ‘95 DS59DB2 Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) http://www.cirrus.com CDB5505/6/7/8 Evaluation Board for CS5505/6/7/8 Series of ADCs AUG ‘05 DS59DB3
require a minimal amount of external circuitry. post is shorted to the GND binding post. the CS5505/6/7/8 A/D converter chip function. Figure 1 illustrates the schematic for the board. logic gate. See the schematic in Figure 1. 2B) to the bandgap IC are cut. for an explanation of these modes. buffer ICs for proper operation.
Figure 1. ADC Connections
2 LT1019
converter will convert continuously. placement (silkscreen) of the evaluation board. Figure 2. CS5505/6 and CS5507/8 Pin Layouts
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
Figure 4. Bottom Trace Layer (NOT TO SCALE)
Figure 5. Silk Screen Layer (NOT TO SCALE)
Updated legal notice. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives con- sent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROP- ERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DE- VICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICA- TIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners.