Logic IC

CS5503-BSZ

Cirrus Logic

The CS5501 and CS5503 are CMOS A/D converters ideal for measuring low-frequency signals representing physical, chemical, and biological processes. They utilize charge-balance techniques to…

Manufacturer: Cirrus Logic

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Technical content

Features

Monolithic CMOS ADC with Filtering - 6-pole, Low-pass Gaussian Filter Up to 4 kHz Output Word Rates - On Chip Self-calibration Circuitry - Linearity Error: ±0.0003% - Differential Nonlinearity: CS5501: 16-bit, No Missing Codes (DNL ±1/8 LSB) CS5503: 20-bit, No Missing Codes System Calibration Capability Flexible Serial Communications Port - Microcontroller-compatible Formats - 3-state Data and Clock Outputs - UART Format (CS5501 only) Pin-selectable Unipolar/Bipolar Ranges Low Power Consumption: 25 mW - 10 µW Sleep Mode for Portable Applications

Description

The CS5501 and CS5503 are CMOS A/D converters ideal for measuring low-frequency signals representing physical, chemical, and biological processes. They uti- lize charge-balance techniques to achieve 16-bit (CS5501) and 20-bit (CS5503) performance with up to 4 kSps word rates. The converters continuously sample at a rate set by the user in the form of either a CMOS clock or a crystal. On- chip digital filtering processes the data and updates the output register at up to a 4 kSps rate. The converters' low- pass, 6-pole Gaussian response filter is designed to al- low corner frequency settings from 0.1 Hz to 10 Hz in the CS5501 and 0.5 Hz to 10 Hz in the CS5503. Thus, each converter rejects 50 Hz and 60 Hz line frequencies as well as any noise at spurious frequencies. The CS5501 and CS5503 include on-chip self-calibra- tion circuitry which can be initiated at any time or temperature to insure offset and full-scale errors of typi- cally less than 1/2 LSB for the CS5501 and less than 4 LSB for the CS5503. The devices can also be applied in system calibration schemes to null offset and gain er- rors in the input channel. Each device's serial port offers two general purpose modes of operation for direct interface to shift registers or synchronous serial ports of industry-standard micro- controllers. In addition, the CS5501's serial port offers a third, UART-compatible mode of asynchronous communication.

ORDERING INFORMATION

See page 33. I Calibration CAL AIN AGND DGND BP/UPSLEEP SRAM SC1 SC2 Calibration Microcontroller Analog Modulator 6-Pole Gaussian Low-Pass Digital Filter Charge-Balanced A/D Converter Clock Generator Serial Interface Logic VA+ VA- VD+ VD- SDATA CLKOUTCLKIN DRDY CS MODESCLK VREF 10 SEP ‘04 DS31F4 Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) http://www.cirrus.com CS5501 CS5503 Non-aliasing, 16- & 20-bit A/D Converters I AUG ‘05 DS31F5 Charge-balanced A/D Converter Calibration SRAM Calibration Microcontroller 6-pole Gaussian Low-pass Digital Filter Analog Modulator Clock Generator Serial Interface Logic VREF BP/UP SLEEP AIN AGND DGND CAL VA+ VD+ VD- VA- SDATA DRDY CS MODE SCLK CLKIN CLKOUT SC1 SC2 CS5501 CS5503

CS5501 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 2.5V; CLKIN = 4.096MHz; Bipolar Mode; MODE = +5V; Rsource = 750Ω with a 1nF to AGND at AIN (see Note 1); Digital Inputs: Logic 0 = GND; Logic 1 = VD+; unless otherwise specified.) CS5501-A, B, C CS5501-S, T Parameter* Min Typ Max Min Typ Max Units Specified Temperature Range -40 to +85 -55 to +125 Accuracy Linearity Error -A, S -B, T 0.0015 0.0007 0.0003 0.003 0.0015 0.0012 0.0007 0.003 0.0015 ±%FS ±%FS ±%FS Differential Nonlinearity TMIN to TMAX ±1/8 ±1/2 ±1/8 ±1/2 LSB16 Full Scale Error (Note 2) ±0.13 ±0.5 ±0.13 ±0.5 LSB16 Full Scale Drift (Note 3) ±1.2 ±2.3 LSB16 Unipolar Offset (Note 2) ±0.25 ±0.25 LSB16 Unipolar Offset Drift (Note 3) ±4.2 +3.0 -25.0 LSB16 Bipolar Offset (Note 2) ±0.25 ±0.25 LSB16 Bipolar Offset Drift (Note 3) ±2.1 +1.5 -12.5 LSB16 Bipolar Negative Full Scale Error (Note 2) ±0.5 ±0.5 LSB16 Bipolar Negative Full Scale Drift (Note 3) ±0.6 ±1.2 LSB16 Noise (Referred to Output) LSBrms Notes: 1. The AIN pin presents a very high input resistance at dc and a minor dynamic load which scales to the master clock frequency. Both source resistance and shunt capacitance are therefore critical in determining the CS5501’s source impedance requirements. For more information refer the text section Analog Input Impedance Considerations. 2. Applies after calibration at the temperature of interest. 3. Total drift over the specified temperature range since calibration at power-up at 25°C (see Figure 11). This is guaranteed by design and /or characterization. Recalibration at any temperature will remove these errors. Unipolar Mode Bipolar Mode µV LSB’s %FS ppm FS LSB’s %FS ppm FS 0.26 0.0004 0.13 0.0002 0.50 0.0008 0.26 0.0004 1.00 0.0015 0.50 0.0008 2.00 0.0030 1.00 0.0015 152 4.00 0.0061 2.00 0.0030 CS5501 Unit Conversion Factors, VREF = 2.5V * Refer to the Specification Definitions immediately following the Pin Description Section. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

CS5503 ANALOG CHARACTERISTICS (TA = TMIN to TMAX; VA+, VD+ = 5V; VA-, VD- = -5V; VREF = 2.5V; CLKIN = 4.096MHz; Bipolar Mode; MODE = +5V; Rsource = 750. with a 1nF to AGND at AIN (see Note 1): unless otherwise specified.) CS5503-A, B, C CS5503-S, T Parameter* Min Typ Max Min Typ Max Units Specified Temperature Range -40 to +85 -55 to +125 Accuracy Linearity Error -A, S -B, T 0.0015 0.0007 0.0003 0.003 0.0015 0.0012 0.0007 0.003 TBD ±%FS ±%FS ±%FS Differential Nonlinearity T MIN to T MAX (Not Missing Codes) Bits Full Scale Error (Note 2) ±16 ±16 LSB20 Full Scale Error Drift (Note 3) ±19 ±37 LSB20 Unipolar Offset (Note 2) ±16 ±16 LSB20 Unipolar Offset Drift (Note 3) ±67 +48 -400 LSB20 Bipolar Offset (Note 2) ±16 ±16 LSB20 Bipolar Offset Drift (Note 3) ±34 +24 -200 LSB20 Bipolar Negative Full Scale Error (Note 2) ±32 ±32 LSB20 Bipolar Negative Full Scale Drift (Note 3) ±10 ±20 LSB20 Noise (Referred to Output) 1.6 1.6 LSBrms (20) Unipolar Mode Bipolar Mode . V LSB’s %FS ppm Fs LSB’s %FS ppm FS 0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12 1.192 0.50 0.0000477 0.47 0.26 0.0000238 0.24 2.384 1.00 0.0000954 0.95 0.50 0.0000477 0.47 4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95 9.537 4.000 0.0003814 3.81 2.00 0.0001907 1.91 CS5503 Unit Conversion Factors, VREF = 2.5V * Refer to the Specification Definitions immediately following the Pin Description Section. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

ANALOG CHARACTERISTICS (Continued) CS5501/3-A, B, C CS5501/3-S, T Parameter* Min Typ Max Min Typ Max Units Power Supplies DC Power Supply Currents IA+ IA- ID+ ID- (Note 4) Power Dissipation SLEEP High SLEEP Low (Note 4) 0.03 3.2 3.2 1.5 0.1 0.03 3.2 3.2 1.5 0.1 mA mA mA mA mW µW Power Supply Rejection Positive Supplies Negative Supplies (Note 5) dB dB Analog Input Analog Input Range Unipolar 0 to +2.5 0 to +2.5 V Bipolar ±2.5 ±2.5 V Input Capacitance pF DC Bias Current (Note 1) nA System Calibration Specifications Positive Full Scale Calibration Range VREF+0.1 VREF+0.1 V Positive Full Scale Input Overrange VREF+0.1 VREF+0.1 V Negative Full Scale Input Overrange -(VREF+0.1) -(VREF+0.1) V Maximum Offset Calibration Range (Notes 6, 7) Unipolar Mode Bipolar Mode -(VREF +0.1) -40%VREF to +40%VREF -(VREF +0.1) -40%VREF to +40%VREF V V Input Span (Note 8) 80% VREF 2VREF +0.2 80% VREF 2VREF +0.2 V Notes: 4. All outputs unloaded. 5. 0.1Hz to 10Hz. PSRR at 60 Hz will exceed 120 dB due to the benefit of the digital filter. 6. In unipolar mode the offset can have a negative value (-VREF) such that the unipolar mode can mimic bipolar mode operation. 7. The specifications for Input Overrange and for Input Span apply additional constraints on the offset calibration range. 8. For Unipolar mode, Input Span is the difference between full scale and zero scale. For Bipolar mode, Input Span is the difference between positive and negative full scale points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(VREF + 0.1). Specifications are subject to change without notice. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

s Sps Hz Settling Time to +0.0007% FS (FS Step) Sampling Frequency Output Update Rate Filter Corner Frequency CLKIN /1024 CLKIN /409,600 Ratio 506,880/CLKIN Continuous-Time Representation of 6-Pole Gaussian Filter where x = f/f-3dB, f-3dB = CLKIN/409,600, and f is the frequency of interest. S-Domain Pole/Zero Plot (Continuous-Time Representation) S1,2 = -1.4667 ± j1.8199 S3,4 = -1.7559 ± j1.0008 S5,6 = -1.8746 ± j0.32276 Frequency Response -j2 -j1 100 1000 Frequency in Hz -140 -120 -100 -80 -60 -40 -20 Output Amplitude in dB CLKIN = 2 MHz CLKIN = 1 MHz CLKIN = 4 MHz jω CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

DIGITAL CHARACTERISTICS (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%) Parameter Symbol Min Typ Max Units Calibration Memory Retention Power Supply Voltage (VD+ and VA+) VMR 2.0 V High-Level Input Voltage All Except CLKIN VIH 2.0 V High-Level Input Voltage CLKIN VIH 3.5 V Low-Level Input Voltage All Except CLKIN VIL 0.8 V Low-Level Input Voltage CLKIN VIL 1.5 V High-Level Output Voltage (Note 9) VOH (VD+)-1.0V V Low-Level Output Voltage Iout=1.6mA VOL 0.4 V Input Leakage Current Iin µA 3-State Leakage Current IOZ ±10 µA Digital Output Pin Capacitance Cout pF Notes: ABSOLUTE MAXIMUM RATINGS Parameter Symbol Min Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- -0.3 0.3 -0.3 0.3 (VA+)+0.3 -6.0 6.0 -6.0 V V V V Input Current, Any Pin Except Supplies (Notes 10, 11) Iin ±10 mA Analog Input Voltage (AIN and VREF pins) VINA (VA-)-0.3 (VA+)+0.3 V Digital Input Voltage VIND -0.3 (VA+)+0.3 V Ambient Operating Temperature TA -55 125 Storage Temperature Tstg -65 150 Notes: 10. Applies to all pins including continuous overvoltage conditions at the analog input (AIN) pin. 11. Transient currents of up to 100mA will not cause SCR latch-up. Maximum input current for a power supply pin is ± 50 mA. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

Notes: 14. CLKIN must be supplied whenever the CS5501 or CS5503 is not in SLEEP mode. If no clock is present when not in SLEEP mode, the device can draw higher current than specified and possibly become uncalibrated. 15. The CS5501/CS5503 is production tested at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz. 16. Specified using 10% and 90% points on waveform of interest. 17. In order to synchronize several CS5501’s or CS5503’s together using the SLEEP pin, this specification must be met. SWITCHING CHARACTERISTICS (TA = Tmin to Tmax; CLKIN=4.096 MHz; VA+, VD+ = 5V±10%; VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF; unless otherwise specified.) Parameter Symbol Min Typ Max Units Master Clock Frequency: Internal Gate Oscillator (See Table 1) Externally Supplied: (Note 14) Maximum Minimum (Note 15) CLKIN CLKIN CLKIN 200 200 4096 5000 5000 kHz kHz kHz CLKIN Duty Cycle Rise Times: Any Digital Input Any Digital Output (Note 16) trise trise 1.0 µs ns Fall Times: Any Digital Input Any Digital Output (Note 16) tfall tfall 1.0 µs ns Set Up Times: SC1, SC2 to CAL Low SLEEP High to CLKIN High (Note 17) tscs tsls 100 ns µs Hold Time: SC1, SC2 hold after CAL falls tsch 100 ns RECOMMENDED OPERATING CONDITIONS (AGND, DGND = 0V) (Note 12) Parameter Symbol Min Typ Max Units DC Power Supplies: Positive Digital Negative Digital Positive Analog Negative Analog VD+ VD- VA+ VA- 4.5 -4.5 4.5 -4.5 5.0 -5.0 5.0 -5.0 VA+ -5.5 5.5 -5.5 V V V V Analog Reference Voltage VREF 1.0 2.5 3.0 V Analog Input Voltage: (Note 13) Unipolar Bipolar VAIN VAIN AGND -VREF VREF VREF V V Notes: 12. All voltages with respect to ground. 13. The CS5501 and CS5503 can accept input voltages up to the analog supplies (VA+ and VA-). They will accurately convert and filter signals with noise excursions up to 100mV beyond |VREF|. After filtering, the devices will output all 1’s for any input above VREF and all 0’s for any input below AGND in unipolar mode and -VREF in bipolar mode. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

SWITCHING CHARACTERISTICS (continued) (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) Parameter Symbol Min Typ Max Units SSC Mode (Mode = VD+) Access Time CS Low to SDATA Out tcsd1 3/CLKIN ns SDATA Delay Time SCLK Falling to New SDATA bit tdd1 100 ns SCLK Delay Time SDATA MSB bit to SCLK Rising (at 4.096 MHz) tcd1 250 380 ns Serial Clock Pulse Width High (at 4.096 MHz) (Out) Pulse Width Low tph1 tpl1 240 730 300 790 ns Output Float Delay SCLK Rising to Hi-Z tfd2 1/CLKIN + 100 1/CLKIN + 200 ns Output Float Delay CS High to Output Hi-Z (Note 18) tfd1 4/CLKIN +200 ns SEC Mode (Mode = DGND) Serial Clock (In) fsclk dc 4.2 MHz Serial Clock (In) Pulse Width High Pulse Width Low tph2 tpl2 180 ns Access Time CS Low to Data Valid (Note 19) tcsd2 160 ns Maximum Data Delay Time (Note 20) SCLK Falling to New SDATA bit tdd2 150 ns Output Float Delay CS High to Output Hi-Z tfd3 250 ns Output Float Delay SCLK Falling to Output Hi-Z tfd4 100 200 ns Notes: 18. If CS is returned high before all data bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance. 19. If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for 4 clock cycles. The propagation delay time may be as great as 4 CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asychronous CS, SCLK(i) should not be taken high sooner than 4 CLKIN cycles plus 160ns after CS goes low. 20. SDATA transitions on the falling edge of SCLK(i). SDATA CS fd1 t Output Float Delay SSC Mode (Note 19) sls t CLKIN SLEEP Sleep Mode Timing for Synchronization VALID CAL SC1, SC2 scs t sch t Calibration Control Timing CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

t tph2 Hi-Z MSB MSB-1 fd3 t tcsd2 Hi-Z tpl2 tph2 dd2 t SDATA SCLK (i) DRDY CS SCLK (i) SDATA CS dd2 t t csd1 fd2 t t dd1 Hi-Z t ph1 tpl1 cd1 t Hi-Z Hi-Z Hi-Z MSB-2 LSB MSB MSB-1 SCLK (o) CLKIN SDATA CS SEC MODE Timing Relationships SSC MODE Timing Relationships CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

SWITCHING CHARACTERISTICS (continued) (TA = Tmin to Tmax; VA+, VD+ = 5V ± 10%; VA-, VD- = -5V ± 10%; Input Levels: Logic 0 = 0V, Logic 1 = VD+; CL = 50 pF) Parameter Symbol Min Typ Max Units AC Mode (Mode = VD-) CS5501 only Serial Clock (In) fsclk dc 4.2 MHz Serial Clock (In) Pulse Width High Pulse Width Low tph3 tpl3 180 ns ns Set-up Time CS Low to SCLK Falling tcss ns Maximum Data Delay Time SCLK Fall to New SDATA bit tdd3 180 ns Output Float Delay CS High to Output Hi-Z (Note 21) tfd5 100 200 ns Notes: 21. If CS is returned high after an 11-bit data packet is started, the SDATA output will continue to output data until the end of the second stop bit. At that time the SDATA output will go to high impedance. Low Byte STOP1 STOP2 t fd5 t pl3 Hi-Z Hi-Z BIT7 BIT6 BIT9 START t ph3 t dd3 High Byte SCLK(i) SDATA CS DRDY BIT8 t css AC MODE Timing Relationships (CS5501 only) CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

and serial communications port. ensure measurement accuracy.

The sample rate of the analog input signal.
The corner frequency of the on-chip digital
The output update rate of the serial output port.

son of the characteristics of these two filter types). Figure 1. Charge Balance (Delta-Sigma) A/D Converter

whenever the SLEEP is inactive (SLEEP = VD+). cause the device is built using dynamic logic. MSB first, at a SCLK output rate of CLKIN/4. will return high 1020 clock cycles after it falls. will not be transmitted during the window time. transmission to obtain all of the data bits.

4.096 MHz

3.579 MHz

2.000 MHz

1.0 MHz

2.0 MHz

Table 1. Resonator Loading Capacitors

4 kSps serial port update rate. SSC mode in only 1 of the 8 digital time periods in each filter cycle. Figure 4. Internal Timing

76 CLKIN cycles

Figure 5. Synchronous Self-Clocking (SSC) Mode Timing

high impedance state when SCLK goes low. CLKIN cycles plus 160 ns after CS is taken low. transitions positive to latch the MSB data bit. sent the MSB-1 data bit on its output. Figure 6. Synchronous External-Clocking (SEC) Mode Timing

provide data output in UART compatible format. impedance state after the second stop bit is output. all 22 bits have been clocked out of the port. rent 11-bit data packet will continue to be output. Figure 7. CS5501 Asynchronous (UART) Mode Timing

nitude of the voltages used in its feedback DAC. tain the same binary output code from the converter. scale" point must be presented to the modulator. Figure 8. CS5501 Differential Nonlinearity Plot

sequence (system offset and system gain) has been properly performed, additional offset calibra- tions can be performed by themselves to reposition the gain slope (the slope factor is not changed) to adjust its zero reference point to the new system zero reference value. A second system calibration mode is available which uses an input voltage for the zero scale calibration point, but uses the VREF voltage as the full scale calibration point. Whenever a system calibration mode is used, there are limits to the amount of offset and to the amount of span which can be accommodated. The range of input span which can be accommo- dated in either unipolar or bipolar mode is restricted to not less than 80% of the voltage on VREF and not more than 200% of (VREF + 0.1) V. The amount of offset which can be cali- brated depends upon whether unipolar or bipolar mode is being used. In unipolar mode the system calibration modes can handle offsets as positive as 20% of VREF (this is restricted by the minimum span requirement of 80% VREF) or as negative as -(VREF + 0.1) V. This capability enables the unipolar mode of the CS5501/CS5503 to be cali- brated to mimic bipolar mode operation. In the bipolar mode the system offset calibration range is restricted to a maximum of ±40% of VREF. It should be noted that the span restrictions limit the amount of offset which can be calibrated. The span range of the converter in bipolar mode extends an equidistance (+ and -) from the voltage used for the zero scale point. When the zero scale point is calibrated it must not cause either of the two endpoints of the bipolar transfer function to exceed the positive or the negative input over- range points (+(VREF + 0.1) V or - (VREF + 0.1) V). If the span range is set to a minimum (80% VREF) the offset voltage can move ±40% VREF without causing the end points of the trans- fer function to exceed the overrange points. Alternatively, if the span range is set to 200% of VREF, the input offset cannot move more than +0.1 or 0.1 V before an endpoint of the transfer function exceeds the input overrange limit. Initiating Calibration Table 2 illustrates the calibration modes available in the CS5501/CS5503. Not shown in the table is the function of the BP/UP pin which determines whether the converter is calibrated to measure bi- polar or unipolar signals. A calibration step is initiated by bringing the CAL pin (13) high for at least 4 CLKIN cycles to reset the part and then bringing CAL low. The states of SC1 (pin 4) and SC2 (pin 17) along with the BP/UP (pin 12) will determine the type of calibration to be performed. The SC1 and SC2 inputs are latched when CAL goes low. The BP/UP input is not latched and therefore must remain in a fixed state throughout the calibration and measurement cycles. Any time the state of the BP/UP pin is changed, a new cali- bration cycle must be performed to enable the CS5501/CS5503 to properly function in the new mode. When a calibration step is initiated, the DRDY signal will go high and remain high until the step is finished. Table 2 illustrates the number of clock cycles each calibration requires. Once a calibration step is initiated it must finish before a new calibration step can be executed. In the two step system calibration mode, the offset calibra- tion step must be initiated before initiating the gain calibration step. When a self-cal is completed DRDY falls and the output port is updated with a data word that repre- sents the analog input signal at the AIN pin. When a system calibration step is completed, DRDY will fall and the output port will be up- dated with the appropriate data value (zero scale point, or full scale point). In the system calibra- tion mode, the digital filter must settle before the output code will represent the value of the analog input signal. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

Figure 10. Calibration Equations point (in bipolar) it will output all zeroes. 100 mV may increase output noise. Table 3. Output Code Size After Calibration Table 4. Output Coding

on current limiting circuits. age on the sample capacitor to its final value. on the sample capacitor to settle to its final value. stray or additional capacitance at the input pin. The value of t is equal to 64/CLKIN. Figure 11. Analog Input Model

the buffer is 100 mV, which is the worst case.

4.096 MHz CLKIN, source resistances up to

comes the dominant source of offset drift. CS5501 and less than 40 LSBs for the CS5503 . perature to remove the effects of these errors. nificantly affected by temperature changes. Figure 12. Typical Self-Cal Bipolar Offset vs. Tem-

At the system level, the digital filter in the CS5501/CS5503 can be modeled exactly like an analog filter with a few minor differences. Digital filtering resides behind the A/D conver- sion and can thus reject noise injected during the conversion process (i.e. power supply rip- ple, voltage reference noise, or noise in the ADC itself). Analog filtering cannot. Also, since digital filtering resides behind the A/D converter, noise riding unfiltered on a near-full-scale input could potentially over- range the ADC. In contrast, analog filtering removes the noise before it ever reaches the converter. To address this issue, the CS5501/CS5503 each contain an analog modu- lator and digital filter which reserve headroom such that the device can process signals with 100mV "excursions" above full-scale and still output accurately converted and filtered data. Filtered input signals above full-scale still result in an output of all ones. The digital filter’s corner frequency occurs at CLKIN/409,600, where CLKIN is the master clock frequency. With a 4.096MHz clock, the filter corner is at 10Hz and the output register is updated at a 4kHz rate. CLKIN frequency can be reduced with a proportional reduction in the filter corner frequency and in the update rate to the out- put register. A plot of the filter response is shown in the specification tables section of this data sheet. Both the CS5501/CS5503 employ internal digi- tal filtering which creates a 6-pole Gaussian relationship. With the corner frequency set at 10Hz for minimized settling time, the CS5501/CS5503 offer approximately 55dB re- jection at 60Hz to signals coming into either the AIN or VREF pins. With a 5Hz cut-off, 60Hz rejection increases to more than 90dB. The digital filter (rather than the analog modula- tor) dominates the converters’ settling for step-function inputs. Figure 13 illustrates the set- tling characteristics of the filter. The vertical axis is normalized to the input step size. The horizon- tal axis is in filter cycles. With a full scale input step (2.5 V in unipolar mode) the output will ex- hibit an overshoot of about 0.25 LSB16 in the CS5501 and 4 LSB20 in the CS5503. (a) Settling Time Due to Input Step Change (b) Expanded Version of (a) Settling Accuracy 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 See (b) for expanded view Vertical scale normalized to input step size Filter Cycles (1024 CLKIN cycles) 100 150 200 250 300 350 400 450 500 1.00000381 0.99999850 Vertical scale normalized to input step size Settling response is monotonically increasing from zero to here, and then exhibits one overshoot and one undershoot as shown. Settling Accuracy 0.9999875 0.9999900 0.9999925 0.9999950 0.9999975 1.0000000 1.0000025 1.0000050 1.0000075 1.0000100 1.0000125 Filter Cycles (1024 CLKIN cycles) 500 530 560 590 620 650 680 710 740 CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

the 20-bit level in the CS5503). energy at multiples of the sampling rate. collected for post filtering. Table 5. Settling Time of the 6 Pole Low Pass Filter in

put which is transferred to the output data. connections to the CS5501/CS5503. the external reference just as the AIN pin does. ply 2.5 V for use with the CS5501/CS5503. ence voltage which is input into the VREF pin. their respective grounds using 0.1 µF capacitors. in Figure 15 eliminate this possibility. Figure 14. Voltage Reference Connections

CS5501/CS5503 or at integer multiples thereof. erations section of this data sheet.

0 VREF

Figure 15. Typical Connection Diagram

the CS5501/CS5503 is illustrated in Figure 15. supply voltage in the system. and the voltage reference stabilization time. quired to accommodate any self-heating effects. be lost whenever power is removed from the chip. Figure 16. Power-On Reset Circuitry

11 SLEEP

Figure 17. Example Calibration Memory Battery

to ensure that logic inputs are maintained at either VD+ ar DGND potential when SLEEP is low. Note that battery life could be shortened if the +5 V supply drops slowly during power-down. As the supply drops below the battery voltage but not yet below the logic threshold of the SLEEP pin, the battery will be supplying the CS5501/CS5503 at full power (typically 3 mA). Faster transitions at SLEEP can be triggered using a resistive divider or a simple resistor network to generate the SLEEP in- put from the +5 V supply. Output Loading Considerations To maximize performance of the CS5501/ CS5503, the output drive currents from the digital output lines should be minimized. Schematic & Layout Review Service CS5501 CS5503 DS31F5

CLKIN; CLKOUT -Clock In; Clock Out, Pins 3 and 2. A gate inside the CS5501/CS5503 is connected to these pins and can be used with a crystal or ceramic resonator to provide the master clock for the device. Alternatively, an external (CMOS compatible) clock can be input to the CLKIN pin as the master clock for the device. When not in SLEEP mode, a master clock (CLKIN) should be present at all times. Serial Output I/O MODE -Serial Interface Mode Select, Pin 1. Selects the operating mode of the serial port. If tied to VD- (-5V), the CS5501 will operate in the UART-compatible AC mode for Asynchronous Communication. The SCLK pin will operate as an input to set the data rate, and data will transmit formatted with one start and two stop bits. If MODE is tied to DGND, the CS5501/CS5503 will operate in the SEC (Synchronous External-Clocking) mode, with the SCLK pin operating as an input and the output appearing MSB-first. If MODE is tied to VD+ (+5V), the CS5501/CS5503 will operate in its SSC (Synchronous Self-Clocking) mode, with SCLK providing a serial clock output of CLKIN/4 (25% duty-cycle). DRDY -Data Ready, Pin 18. DRDY goes low every 1024 cycles of CLKIN to indicate that new data has been placed in the output port. DRDY goes high when all the serial port data is clocked out, when the serial port is being updated with new data, when a calibration is in progress, or when SLEEP is low. CS -Chip Select, Pin 16. An input which can be enabled by an external device to gain control over the serial port of the CS5501/CS5503. SERIAL INTERFACE MODE SELECT MODE SDATA SERIAL DATA OUTPUT CLOCK OUT CLKOUT SCLK SERIAL CLOCK INPUT/OUTPUT CLOCK IN CLKIN DRDY DATA READY SYSTEM CALIBRATION 1 SC1 SC2 SYSTEM CALIBRATION 2 DIGITAL GROUND DGND CS CHIP SELECT NEGATIVE DIGITAL POWER VD- VD+ POSITIVE DIGITAL POWER NEGATIVE ANALOG POWER VA- VA+ POSITIVE ANALOG POWER ANALOG GROUND AGND CAL CALIBRATE ANALOG IN AIN BP/UP BIPOLAR/UNIPOLAR SELECT VOLTAGE REFERENCE VREF SLEEP SLEEP * Pinout applies to both DIP and SOIC packages CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

SDATA -Serial Data Output, Pin 20. Data from the serial port will be output from this pin at a rate determined by SCLK and in a format determined by the MODE pin. It furnishes a high impedance output state when not transmitting data. SCLK -Serial Clock Input/Output, Pin 19. A clock signal at this pin determines the output rate of the data from the SDATA pin. The MODE pin determines whether the SCLK signal is an input or output. SCLK may provide a high impedance output when data is not being output from the SDATA pin. Calibration Control Inputs SC1; SC2 -System Calibration 1 and 2, Pins 4 and 17. Control inputs to the CS5501/CS5503’s calibration microcontroller for calibration. The state of SC1 and SC2 determine which of the calibration modes is selected for operation (see Table 2). BP/UP -Bipolar/Unipolar Select, Pin 12. Determines whether the CS5501/CS5503 will be calibrated to measure bipolar (BP/UP = VD+) or unipolar (BP/UP = DGND) input signals. Recalibration is necessary whenever the state of BP/UP is changed. CAL -Calibrate, Pin 13. If brought high for 4 clock cycles or more, the CS5501/CS5503 will reset and upon returning low a full calibration cycle will begin. The state of SC1, SC2, and BP/UP when CAL is brought low determines the type and length of calibration cycle initiated (see Table 2). Also, a single CAL signal can be used to strobe the CAL pins high on several CS5501/CS5503’s to synchronize their operation. Any spurious glitch on this pin may inadvertently place the chip in Calibration mode. Other Control Input SLEEP -Sleep, Pin 11. When brought low, the CS5501/CS5503 will enter a low-power state. When brought high again, the CS5501/CS5503 will resume operation without the need to recalibrate. After SLEEP goes high again, the device’s output will settle to within +0.0007% of the analog input value within 1.3/f-3dB, where f-3dB is the passband frequency. The SLEEP input can also be used to synchronize sampling and the output updates of several CS5501/CS5503’s. Analog Inputs VREF -Voltage Reference, Pin 10. Analog reference voltage input. AIN -Analog Input, Pin 9. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

VD+ -Positive Digital Power, Pin 15. Positive digital supply voltage. Nominally +5 volts. VD- -Negative Digital Power, Pin 6. Negative digital supply voltage. Nominally -5 volts. DGND -Digital Ground, Pin 5. Digital ground. VA+ -Positive Analog Power, Pin 14. Positive analog supply voltage. Nominally +5 volts. VA- -Negative Analog Power, Pin 7. Negative analog supply voltage. Nominally -5 volts. AGND -Analog Ground, Pin 8. Analog ground. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

The deviation of a code from a straight line which connects the two endpoints of the A/D Converter transfer function. One endpoint is located 1/2 LSB below the first code transition and the other endpoint is located 1/2 LSB beyond the code transition to all ones. Units in percent of full-scale. Differential Linearity The deviation of a code’s width from the ideal width. Units in LSB’s. Full-Scale Error The deviation of the last code transition from the ideal (VREF-3/2 LSB’s). Units in LSBs. Unipolar Offset The deviation of the first code transition from the ideal (1/2 LSB above AGND) when in unipolar mode (BP/UP low). Units in LSBs. Bipolar Offset below AGND) when in bipolar mode (BP/UP high). Units in LSBs. Bipolar Negative Full-Scale Error The deviation of the first code transition from the ideal when in bipolar mode (BP/UP high). The Ideal is defined as lying on a straight line which passes through the final and mid-scale code transitions. Units in LSBs. Positive Full-Scale Input Overrange The absolute maximum positive voltage allowed for either accurate system calibration or accurate conversions. Units in volts. Negative Full-Scale Input Overrange The absolute maximum negative voltage allowed for either accurate system calibration or accurate conversions. Units in volts. Offset Calibration Range The CS5501/CS5503 calibrate their offset to the voltage applied to the AIN pin when in system calibration mode. The first code transition defines Unipolar Offset when BP/UP is low and the mid-scale transition defines Bipolar Offset when BP/UP is high. The Offset Calibration Range specification indicates the range of voltages applied to AIN that the CS5501 or CS5503 can accept and still calibrate offset accurately. Units in volts. Input Span The voltages applied to the AIN pin in system-calibration schemes define the CS5501/CS5503 analog input range. The Input Span specification indicates the minimum and maximum input spans from zero-scale to full-scale in unipolar, or from positive full scale to negative full scale in bipolar, that the CS5501/CS5503 can accept and still calibrate gain accurately. Units in volts. CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. Model Package Resolution Throughput Linearity Temperature CS5501-BP 20-pin Plastic DIP 4 kSps 0.0015 -40 to +85 °C CS5501-BS 20-pin SOIC 16 Bits CS5501-BSZ (lead free) CS5503-BP 20-pin Plastic DIP

20 Bits

CS5503-BSZ (lead free) Model Peak Relfow Temp MSL Rating* Maximum Floor Life CS5501-BP 260 °C No Limit CS5501-BS 240 °C

365 Days

CS5501-BSZ (lead free) 260 °C

7 Days

260 °C No Limit CS5503-BS 240 °C CS5503-BSZ (lead free) 260 °C

APPENDIX A: APPLICATIONS Parallel Interface Figures A1 and A2 show two serial-to-parallel conversion circuits for interfacing the CS5501 in its SSC mode to 16- and 8-bit systems respec- tively. Each circuit includes an optional 74HCT74 flip-flop to latch DRDY and generate a level-sensitive interrupt. Both circuits require that the parallel read process be synchronized to the CS5501’s operation. That is, the system must not try to enable the regis- ters’ parallel output while they are accepting serial data from the CS5501. The CS5501’s DRDY falls just prior to serial data transmission and returns high as the last bit shifts out. There- fore, the DRDY pin can be polled for a rising transition directly, or it can be latched as a level- sensitive interrupt. With the CS input tied low the CS5501 will shift out every available sample (4kHz word rate with a 4MHz master clock). Lower output rates (and interrupt rates) can be generated by dividing down the DRDY output and applying it to CS. Totally asynchronous interfaces can be created using a Shift Data control signal from the system which enables the CS5501’s CS input and/or the shift registers’ S1 inputs. The DRDY output can then be used to disable serial data transmission once an output word has been fully registered. +5V +5V A OE2 OE1 PA PB PC PD PE PF PG PH 74HCT299 Q H A OE1 PA PB PC PD PE PF PG PH D10 D11 D12 D13 D14 D15 74HCT299 CS DRDY (For polling) MODE CS SDATA SCLK DRDY +5V D Q Q SET RESET INT 74HCT74 OE2 Only needed for interrupt driven systems CS5501 CS5503 Figure A1. 16-bit Parallel Interface CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

In such asynchronous configurations the CS5501 is operated much like a successive-approximation converter with a Convert signal and a subsequent read cycle. If it is required to latch the 16-bit data, then 2 74HC595 8-bit "shift register with latch" parts may be used instead of 74HC299’s. Serial Interfaces Figures A3 to A8 offer both the hardware and software interfaces to several industry-standard microcontrollers using the CS5501’s SEC and AC output modes. In each instance a system in- itialization routine is provided which configures the controller’s I/O ports to accept the CS5501’s serial data and clock outputs and/or generate its own serial clock. The routine also sets the CS5501 into a known state. For each interface, a second subroutine is also provided which will collect one complete 16-bit output word from the CS5501. Figure A5 illus- trates the detailed timing throughout the subroutine for one particular interface - the COPS family interface of Figure A4. Figure A2. 8-Bit Parallel Interface +5V +5V A OE2 OE1 74HCT299 Q H OE2 A OE1 D10 D11 D12 D13 D14 D15 74HCT299 PA PB PC PD PE PF PG PH PA PB PC PD PE PF PG PH DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 MODE CS SDATA SCLK DRDY +5V D Q Q SET RESET INT 74HCT74 Only needed for interrupt driven systems CS DRDY (For polling) CS5501 CS5503 CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

Notes: 1. CS5501 in Synchronous External Clocking mode. 2. COPS 444 max baud = 62.5 kbps. (Others = 500 kbps) 3. See timing diagram for detailed timing. Assumptions: 1. G0 used as CS. 2. Register 0 (upper four nibbles) used to store 16-bit word. Initial Code: SPINIT: OGI ; CS = 1, inactive; deselect CS5501 RC ; Reset carry, used in next XAS ; instruction to turn SK off Code to get word of data: SP_IN: LBI 0,12 ; Point to start of data ; storage location SC ; Set carry - enables SK in ; XAS instruction OGI ; CS = 0, active; select CS5501 LEI ; Shift register mode, S0 = 0 XAS ; Start clocking serial port NOP NOP ; Wait for (first) M.S. nibble GETNIB: NOP XAS ; Get nibble of data from SIO XIS ; Put nibble in memory, inc. pointer, JP GETNIB ; if overflow, jump around this inst. RC ; Reset carry - disables SK in XAS ; instruction XAS ; Bogus read - stops SK OGI ; CS = 1, inactive; deselect CS5501 RET Figure A4. COPS/CS5501 Interface CS5501 COPS 444 (All COPS) DI SK SDATA CS SCLK MODE CS5503 Notes: 1. CS5501 in Synchronous External Clocking mode. 2. Using 68HC11’s SPI port. (Can use SCI and CS5501’s Asynchronous mode.) 3. Maximum bit rate is 1.05 Mbps. Assumptions: 1. PA6 used as CS. 2. 68HC11 in single-chip mode. 3. Receive data via polling. 4. Normal equates for peripheral registers. 5. Data returned in register D. Initial Code: SPINIT: PSHA ; Store temporary copy of A LDAA #%x1xxxxxx ; Bit 6 = 1, all others are don’t cares STAA PORTA ; CS = 1, inactive; deselect CS5501 LDAA #$10 STAA SPCR ; Disable serial port LDAA #%xx0110xx ; SS-input, SCK-output, ; MOSI-output, MISO-input STAA DDRD ; Data direction register for port D LDAA #$50 ; Enable serial port, CMOS outputs, STAA SPCR ; master, highest clock rate (int. clk/2) LDAA SPSR LDAA SPDR ; Bogus read to clr port and SPIF flag PULA ; Restore A RTS Code to get word of data: SP_IN: LDAA #%x0xxxxxx STAA PORTA ; CS = 0, active; select CS5501 STAA SPDR ; Put data in serial port to start clk WAIT1: LDAA SPSR ; Get port status BPL WAIT1 ; If SPIF (MSB) 0, no data yet, wait LDAA SPDR ; Put most significant byte in A STAA SPDR ; Start serial port for second byte WAIT2: LDAB SPSR ; Get port status BPL WAIT2 ; If SPIF (MSB) 0, no data yet, wait LDAB #%x1xxxxxx STAB PORTA ; CS = 1, inactive; deselect CS5501 LDAB SPDR ; Put least significant byte in B RTS Figure A3. 68HC11/CS5501 Serial Interface CS5501 68HC11 (68HC05) MISO MODE SS +5V PA6 SCK SDATA CS SCLK CS5503 CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

Figure A5. Serial Timing Example - COPS SC OGI LEI XAS NOP NOP XAS XIS GDAT: LBI GETLP: NOP SCLK (SK) DATA (SI) CS (G0) Instruction SYNC (COPS internal) Shift in A SIO SCLK (SK) DATA (SI) CS (G0) Instruction SYNC (COPS internal) XAS XIS XAS XIS GETLP: NOP GETLP: NOP GETLP: NOP JP GETLP JP GETLP JP GETLP SCLK (SK) DATA (SI) CS (G0) Instruction SYNC (COPS internal) XAS XIS JP GETLP RC XAS OGI RET A SIO A SIO A SIO skip B10 B12 B11 B13 B14 B15 (MSB) HI-Z B10 HI-Z CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

Notes: 1. CS5501 in Synchronous External Clocking mode. 2. Interrupt driven I/O on 8051 (For polling, connect DRDY to another port pin). Assumptions: 1. INT1 external interrupt used. 2. Register bank 1, R6, R7 used to store data word, R7 MSbyte. 3. EA enabled elsewhere. Initial Code: CS EQU P1.1 SCLK EQU P1.2 DATA EQU P1.3 SPINIT: CLR EX1 ; Disable INT1 SETB IT1 ; Set INT1 for falling edge triggered SETB DATA ; Set DATA to be input pin SETB CS ; CS = 1; deselect CS5501 CLR SCLK ; SCLK low SETB EX1 ; Enable INT1 interrupt Code to get word of data: ORG 0003H LJMP GETWD ; Interrupt vector GETWD: PUSH PSW ; Save temp. copy PUSH A ; Save temp. copy MOV PSW,#08 ; Set register bank 1 active MOV R6,#8 ; number of bits in a byte CLR CS ; CS = 0; select CS5501 MSBYTE:SETB SCLK ; Toggle SCLK high MOV C,DATA ; Put bit of data into carry bit CLR SCLK ; Toggle SCLK low; next data bit RLC A ; Shift DATA bit into A register DJNZ R6,MSBYTE ; Dec. R6, if not 0, get another bit MOV R7,A ; Put MSbyte into R7 MOV R6,#8 ; Reset R6 to number of bits in byte LSBYTE:SETB SCLK ; Toggle SCLK high MOV C,DATA ; Put bit of data into carry bit CLR SCLK ; Toggle SCLK low; next data bit RLC A ; Shift DATA bit into A register DJNZ R6,LSBYTE ; Dec. R6, if not 0, get another bit MOV R6,A ; Put LSbyte into R6 SETB CS ; CS = 1; deselect CS5501 POP A ; Restore original value POP PSW ; Restore original value RETI Figure A6. MCS51 (8051) /CS5501 Serial Interface CS5501 MODE 8051 P1.1 P1.3 P1.2 INT1 CS SDATA SCLK DRDY Notes: 1. CS5501 in Asynchronous (UART-like) mode. 2. 8051 in mode 2, with OSC = 12 MHz, max baud = 375 kbps. Assumptions: 1. P1.2 (port 1, bit 2) used as CS. 2. Using serial port mode 2, Baud rate = OSC/32. (Assumptions cont.) 3. Word received put in A (ACC) and B registers, A = MSbyte. 4. No error checking done. 5. Equates used for peripheral names. Initial Code: SPINIT: SETB SMOD ; Set SMOD = 1, baud = OSC/32 SETB P1.2 ; CS = 1, inactive MOV SCON,#1001000B ; Enable serial port mode 2, ; receiver enabled, transmitter disabled CLR ES ; Disable serial port interrupts (polling) RET Code to get word of data: SP_IN: CLR P1.2 ; CS = 0, active; select CS5501 JNB RI,$ ; Wait for first byte CLR RI MOV A,SBUF ; Put most significant byte in A JNB RI,$ ; wait for second byte CLR RI MOV B,SBUF ; Put least significant byte in B SETB P1.2 ; CS = 1, inactive; deselect CS5501 RET Figure A7. MCS51 (8051) /CS5501 UART Interface CS5501 RXD MODE 8051 -5V OSC P1.2 SDATA SCLK CS CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

Notes: 1. CS5501 in Asynchronous (UART-like) mode. 2. TMS70X2 in Isosynchronous mode. 3. TMS70X2 with 8 MHz master clock has max baud =1.0 Mbps. Assumptions: 1. A0 used as CS. 2. Receive data via polling. 3. Word received put in A and B upon return, A = MS byte. 4. No error checking done. 5. Normal equates for peripheral registers. Initial Code: SPINIT: DINT MOVP %1,ADDR ; A port is output MOVP %1,APORT ; A0 = 1, (CS is inactive) MOVP %0,P17 MOVP %>10,SCTLO ; Resets port errors MOVP %?x1x01101,SMODE ; Set port for Isosync, MOVP %?00x1110x,SCTLO ; 8 bits, no parity MOVP %07,T3DATA ; Max baud rate MOVP %?01000000,SCTL1 ; No multiprocessor; prescale = 4 MOVP %0,IOCNT1 ; Disable INT4 - will poll port PUSH A ; Store original MOVP RXBUF,A ; Bogus read to clr receiver port flag POP A ; Restore original EINT RET Code to get word of data: SP_IN: MOVP %0,APORT ; CS active, select CS5501 WAIT1 BTJZP %2,SSTAT,WAIT1 ; Wait to receive first byte MOVP RXBUF,A ; Put most significant byte in reg. A WAIT2 BTJZP %2,SSTAT,WAIT2 ; Wait to receive second byte MOVP RXBUF,B ; Put least significant byte in reg. B MOVP %1,APORT ; CS inactive, deselect CS5501 RET Figure A8. TMS70X2/CS5501 Serial Interface CS5501 RXD MODE TMS70X2 (TMS70CX2) -5V SCLK SDATA CS SCLK CS5501/CS5503 DS31F4 CS5501 CS5503 DS31F5

Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries (“Cirrus”) believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant infor mation to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPER TY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOM ER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks o service marks of their respective owners.

Copyright  Cirrus Logic, Inc. 1998 (All Rights Reserved) Cirrus Logic, Inc. Crystal Semiconductor Products Division P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.crystal.com CDB5501 CDB5503 CS5501/CS5503 Evaluation Board lOperation with on-board clock generator, on- board crystal, or an off-board clock source. lDIP switch selectable or micro port controllable: - Unipolar/Bipolar input range - Sleep Mode-All Cal Modes lOn-board Decimation Counter lMultiple Data Output Interface Options: - RS-232 (CS5501) - Parallel Port (CS5501) - Micro Port (CS5501 & CS5503) The CDB5501/CDB5503 is an evaluation board de- signed for maximum flexibility when evaluating the CS5501/CS5503 A/D converters. The board can easily be configured to evaluate all the features of the CS5501/CS5503, including changes in master clock rate, calibration modes, output decimation rates, and in- terface modes. The evaluation board interfaces with most microcontrol- lers and allows full control of the features of the CS5501 or CS5503. DIP switch selectable control is also avail- able in the event a microcontroller is not used. The evaluation board also offers computer data interfaces in- cluding RS-232 and parallel port outputs for evaluating the CS5501. All calibration modes are selectable including Self-Cal, System Offset Cal, and System Offset and System Gain Cal. A calibration can be initiated at any time by pressing the CAL pushbutton switch. I CLKIN AIN Divider OSC VREF Decimation Counter Parallel Port Header Micro Port Header RS-232 Port Sub D GND-5 CS5501/ CS5503 MAR ‘95 DS31DB3 Copyright © Cirrus Logic, Inc. 2005 (All Rights Reserved) http://www.cirrus.com CDB5501 CDB5503 CS5501 & CS5503 Evaluation Boards I AUG ‘05 DS31DB4

The CDB5501/CDB5503 evaluation board pro- vides maximum flexibility for controlling and interfacing to the CS5501/CS5503 A/D convert- ers. The CS5501 or the CS5503 require a minimal amount of external circuitry. The devices can op- erate with a crystal (or ceramic resonator) and a voltage reference. The evaluation board includes several clock source options, a 2.5 volt trimmable reference, and circuitry to support several data interface schemes. The board operates from +5 and -5 volt power supplies. Evaluation Board Overview The CDB5501/CDB5503 evaluation board in- cludes extensive support circuitry to aid evaluation of the CS5501/CS5503. The support circuitry includes the following sections: A clock generator which has an on-board oscillator and counter divider IC. A 2.5 volt trimmable voltage reference. A Decimation Counter. A parallel output port (for CS5501 only). An RS-232 interface (for CS5501 only). A micro port (for CS5501 or CS5503). DIP switch and CAL pushbutton. Clock Generator The CS5501/CS5503 can operate off its on-chip oscillator or an off-chip clock source. The evalu- ation board includes a 4.9152 MHz gate oscillator and counter-divider chain as the primary clock source for the CS5501/CS5503. The counter-di- vider outputs offer several jumper-selectable frequencies as clock inputs to the CS5501/CS5503. The 4.9152 MHz crystal fre- quency was chosen to allow the counter-divider chain to also provide the common serial data rates (1200, 2400, 4800, etc.) when the CDB5501 evaluation board is configured to provide RS-232 data output. If a different operating frequency for the CS5501/CS5503 is desired, three options ex- ist. First, a BNC input is provided to allow an external CMOS (+5V) compatible clock to be used. Second, the crystal (Y1) in the on-board gate oscillator can be changed. Or, third, the on- chip oscillator of the CS5501/CS5503 can be used with a crystal connected in the Y2 position. 2. 5 Volt Reference A 2.5 volt (LT1019CN8-2.5) reference is pro- vided on the board. Potentiometer R9 allows the initial value of the reference to be accurately trimmed. Decimation Counter The CS5501/CS5503 updates its internal output register with a 16-bit word every 1024 clock cy- cles of the master clock. Each time the output register is updated the DRDY line goes low. Al- though output data is updated at a high rate it may be desirable in certain applications to acti- vate the CS to read the data at a much lower rate. A decimation counter is provided on the board for this purpose. The counter reduces the rate at which the CS line of the CS5501 is activated by only allowing CS to occur at a sub-multiple of the DRDY rate. Parallel Output Port (for CS5501 only) The output data from the CS5501/CS5503 is in serial form. Some applications may require the data to be read in parallel format. Therefore the evaluation board includes two 8-bit shift registers with three-state outputs. Data from the CS5501 is shifted into the registers and then read out in 16 bit parallel fashion. The parallel port comes set up for 16-bit parallel output but can be reconfig- ured to provide two 8-bit reads. The parallel port supports the CS5501 only, since the CS5503 out- puts 20-bit words. CDB5501/CDB5503 DS31DB3 CDB5501 CDB5503 DS31DB4

cludes an RS-232 driver and output connector. The CS5503 does not provide this output mode. CS5501/CS5503 on header connectors. require software control of all of these pins. the CS5501 is in the UART compatible mode. output data modes of the CS5503.

4.9152 MHz

Figure 1. Clock Generator

CS5501/CS5503 (shown in Figure 2). Figure 2. Decimation Counter / Microport

on the board for loading capacitors. be used to clock the data into an external register. chronous external-clocking mode is available. Table 2. Data Output Mode

2.4576 MHz

1.2288 MHz

Table 1. Clock Generator CLKIN Rate Selection (CLK/2n) with INT CLK on P1 selected.

Exceeds CLKIN Specifications of CS5501.

+ Exceeds CLKIN specifications of CS5503.

CS5501/CS5503 Data Output Mode Selection Connector P5 (see Figure 2) allows jumper selec- tion of any one of the three data output modes. These modes are: SSC (Synchronous Self-Clocking); SEC (Synchronous External Clocking); AC (Asynchronous Communication). (AC mode is available only in the CS5501) SSC (Synchronous Self-Clocking) Mode The SSC mode is designed for interface to those microcontrollers which allow external clocking of their serial inputs. The SSC mode also allows easy connection to serial-to-parallel conversion circuitry. In the SSC mode serial data and serial clock are output from the CS5501/CS5503 whenever the CS line is activated. As illustrated in Figure 2, all of the signals are available at connector P10. If the CS signal is to be controlled remotely the jumper on P9 should be placed in the NC (No Connection) position. This removes the Decima- tion Counter output from controlling the CS line. Data Output Interface: Parallel Port (for CS5501 evaluation only). Whenever the CS5501 is operated in the SSC mode the 16-bit output data is clocked into two 8-bit shift registers. The registers have three-state parallel outputs which are available at P7 (see Figure 3). A flip-flop (U8A) is used to signal the remote reading device whenever the registers are updated. The PDR (Parallel Data Ready) signal from the flip-flop is available on P7. The Q-bar output from the flip-flop locks out any further up- dates to the registers until their data is read and a DACK (Data ACKnowledge) signal is received from the remote device. Activation of the CS line determines the rate at which the CS5501 will attempt to update the out- put shift registers. Data will be shifted into the registers only if a DACK signal has occurred since the last update. The CS line can be controlled remotely at P10 or by the output of the Decimation Counter. If CS is controlled remotely, the Decimation divide jumper on P4 should be placed in the "0" posi- tion. This insures that the DCS signal will occur at the same rate CS is activated. The positive go- ing edge of DCS toggles the U8A flip-flop which signals an update to the parallel port. The parallel registers are set up to be read in 16- bit parallel fashion but can be configured to be read separately as two 8-bit bytes on an 8-bit bus. To configure the board for byte-wide reads, the byte-wide jumpers must be soldered in place. In addition, for proper "one byte at a time" address selection, a connection on the circuit board needs to be opened and a jumper wire soldered in the proper place to determine which register is to be read when A0 is a "1" and vice versa. See Figure 3 for schematic details. The evaluation board component layout diagram, Figure 7, indicates the location of the byte-wide jumpers and A0 address selection jumpers. After data is read from the registers a DACK (Data Acknowledge) signal is required from the off-board controller to reset flip-flop U8A. This enables the registers to accept data input once again. The DRB and CSB signals on connector P10 should be used to monitor and control the CS5501 output to the serial to parallel conversion registers. Be aware that an arbitrarily timed DACK signal may cause the output data regis- ters to be enabled in the middle of an output word if the CS signal to the CS5501 is not properly sequenced. This will result in incorrect data in the output registers. If the Decimation Counter is used to control the output of the CS5501 (Jumper on P9 in the DC position), the CSB signal on P10 can be moni- CDB5501/CDB5503 DS31DB3 CDB5501 CDB5503 DS31DB4

Figure 3. 16-Bit Parallel Port

clock from the microcontroller. sary to operate in the SEC mode. controller full control over the signals on P10. data bits, and two stop bits each. the SCI input at connector P10 (see Figure 2). The jumper on P11 must be in the NC position.

4.9152 MHz oscillator is selected as the input to

Table 3. On-Board Baud Rate Generator Baud Rate Clock Divider (CLK/2n) with INT CLK on P1 selected. On-Board Baud Rate Clock Input to CS5501/CS5503 SCLK Input.

swing is reduced below the EIA specified limits. Table 4. Decimation Counter Control Figure 4. RS-232 Port

the selected output activates CS low once again. the CAL signal is available on connector P8. connector P8 is implemented. reference output to a precise value. the CS5501/CS5503 will output all "0’s". Table 5. DIP Switch Selections Table 6. Calibration Mode Table Figure 5. DIP Switch / Header Control Pin Selection

cess current into the pin can damage the device. Figure 6. Voltage Reference / Analog Input

Oscilloscope Monitoring of SDATA The output data from either the CS5501 or the CS5503 can be observed on a dual trace oscillo- scope with the following hook-up. Set the evaluation board to operate in the SSC mode. Connect scope probes to TP9 (SCLK) and TP10 (SDATA). Use a third probe connected to TP8 (DRDY) to provide the external trigger input to the scope (use falling edge of DRDY to trigger). With proper horizontal sweep, the SDATA output bits from the A/D converter can be observed. Note that if the input voltage to the CS5501 is adjusted to a mid-code value, the converter will remain stable on the same output code. This illus- trates the low noise level of the CS5501. The CS5503 will exhibit a few LSB’s of noise in its observed output in agreement with its noise speci- fications. Evaluation Board Component Layout and Design Considerations Figure 7 is a reproduction of the silkscreen com- ponent placement of the PC board. The evaluation board includes design features to insure proper performance from the A/D con- verter chip. Separate analog and digital ground planes have been used on the board to insure good noise immunity to digital system noise. Decoupling networks (R6, C7, and R7, C9 in Fig- ure 6) have been used to eliminate the possibility of noise on the power supplies on the digital sec- tion from affecting the analog part of the A/D converter chip. The RC network (R10, C16 and C19) on the output of the LT1019-2.5 reference may not be needed in all applications. It has been included to insure the best noise performance from the refer- ence . CDB5501/CDB5503 DS31DB3 CDB5501 CDB5503 DS31DB4

Figure 7. CDB5501/CDB5503 Component Layout

Product Information

CS5503-BSZ specifications and overview.

Summary

Non-aliasing, 16- & 20-bit A/D Converters

Description

The CS5501 and CS5503 are CMOS A/D converters ideal for measuring low-frequency signals representing physical, chemical, and biological processes. They utilize charge-balance techniques to achieve 16-bit (CS5501) and 20-bit (CS5503) performance with up to 4 kSpsword rates.

Source title CS5503-BSZ Datasheet(PDF) - Cirrus Logic

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