CS5480

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Document overview

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• PDF pages: 70

Technical content

Features

• Superior Analog Performance with Ultra-low Noise Level & High SNR
• Energy Measurement Accuracy of 0.1% over 4000:1 Dynamic Range
• Current RMS Measurement Accuracy of 0.1% over 1000:1 Dynamic Range
• 3 Independent 24-bit, 4 th-order, Delta-Sigma Modulators for Voltage and Current Measurements
• 3 Configurable Digital Outputs for Energy Pulses, Zero-crossing, or Energy Direction
• Supports Shunt Resistor, CT, & Rogowski Coil Current Sensors
• On-chip Measurements & Calculations: - Active, Reactive, and Apparent Power - RMS Voltage and Current - Power Factor and Line Frequency - Instantaneous Voltage, Current, and Power
• Overcurrent, Voltage Sag, and Voltage Swell Detection
• Ultra-fast On-chip Digital Calibration
• Internal Register Protection via Checksum and Write Protection
• UART/SPI™ Serial Interface
• On-chip Temperature Sensor
• On-chip Voltage Reference (25ppm / °C Typ.)
• Single 3.3V Power Supply
• Ultra-fine Phase Compensation
• Low Power Consumption: <13mW
• Power Supply Configurations GNDA = GNDD = 0V, VDDA = +3.3V
• 4mm x 4mm, 24-pin QFN Package

ORDERING INFORMATION

See Page 69.

Description

The CS5480 is a high-accuracy, three-channel, energy mea- surement analog front end. The CS5480 incorporates independent, 4th order, Delta-Sigma analog-to-digital converters for every channel, reference cir- cuitry, and the proven EXL signal processing core to provide active, reactive, and apparent energy measurement. In addi- tion, RMS and power factor calculations are available. Calculations are output via configurable energy pulse, or direct UART/SPI™ serial access to on-chip registers. Instantaneous current, voltage, and power measurements are also available over the serial port. Multiple serial options are offered to allow customer flexibility. The SPI provides higher speed, and the 2-wire UART mini mizes the cost of isolation where required. Three configurable digital outputs provide energy pulses, zero- crossing, energy direction, and interrupt functions. Interrupts can be generated for a variety of conditions including voltage sag or swell, overcurrent, and more. On-chip register integrity is assured via checksum and write protection. The CS5480 is designed to interface to a variety of voltage and current sen- sors including shun t resistors, current transformers, and Rogowski coils. On-chip functionality makes digital calibration simple and ul- tra-fast, minimizing the time required at the end of the customer production line. Performance across temperature is ensured with an on-chip voltage reference with very low drift. A single 3.3V power supply is required, and power consump- tion is very low at <13mW. To minimize space requirements, the CS5480 is offered in a low-cost, 4mm x 4mm 24-pin QFN package. VDDA GNDA TX / SDO RX / SDI UART/SPI Serial Interface Energy To Pulse Conversion RESET Calculation 4th Order  Modulator Digital Filter HPF Option DO1 DO2 Digital Filter 4th Order  Modulator HPF Option Temperature Sensor VREF + Voltage Reference VDDD VREF- System Clock IIN2+ IIN2- PGA IIN1+ IIN1- PGA 10x CS5480 GNDD CS SCLK SSEL DO3 VIN+ VIN- Clock Generator XIN XOUT MODE Digital Filter HPF Option 4th Order  Modulator MAR’13 DS980F3

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1. OVERVIEW The CS5480 is a CMOS power measurement integrated circuit that uses three  analog-to-digital converters to measure line voltage, two currents and temperature. It calculates active, reactive, and apparent power as well as RMS voltage and current and peak voltage and current. It handles other system-related functions, such as energy pulse generation, voltage sag and swell, overcurrent and zero-crossing detection, and line frequency measurement. The CS5480 is optimized to interface to current tr ansformers, shunt resistors, or Rogowski coils for current measurement and to resistive dividers or voltage transformers for voltage measurement. Two full-scale ranges are provided on the current inputs to accommodate different types of current sensors. The CS5480’s three differential inputs have a common-mode input range from analog ground (GNDA) to the positive analog supply (VDDA). An on-chip voltage reference (nominally 2.4 volts) is generated and provided at analog output, VREF±. Three digital outputs (DO1, DO2, and DO3) provide a variety of output signals, and depending on the mode selected, energy pulses, zero-crossings, or other choices. The CS5480 includes a UART/SPI™ serial host interface to an external microcontroller. The serial select (SSEL) pin is used to configure the serial port to be a SPI or UART. SPI signals include serial data input (SDI), serial data output (SDO), and serial clock (SCLK). UART signals include serial data input (RX) and serial data output (TX). A chip select (CS ) signal allows multiple CS5480s to share the same serial interface with the microcontroller.

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1. PIN DESCRIPTION Clock Generator Crystal In Crystal Out 1,24 XIN, XOUT — Connect to an external quartz crystal. Alternatively, an external clock can be supplied to the XIN pin to provide the system clock for the device. Digital Pins and Serial Data I/O Digital Outputs 13,14,15 DO1, DO2, DO3 — Configurable digital outputs for energy pulses, interrupt, tamper indication, energy direction, and zero-crossings. Reset 2 RESET — An active-low Schmitt-trigger input used to reset the chip. Serial Data I/O 16,17 TX/SDO, RX/SDI — UART/SPI serial data output/input. Serial Clock Input 18 SCLK — Serial clock for the SPI. Serial Mode Select 20 SSEL — Selects the type of the serial interface, UART or SPI™. Logic level one - UART selected. Logic level zero - SPI selected. Chip Select 19 CS — Chip select for the UART/SPI. Operating Mode Select 21 MODE — Connect to VDDA for proper operation. Analog Inputs/Outputs Voltage Input 5,6 VIN+, VIN- — Differential analog input for the voltage channel. Current Inputs 4,3,8,7 IIN1+, IIN1-, IIN2+, IIN2- — Differential analog inputs for the current channels. Voltage Reference 10,9 VREF+, VREF- — The internal voltage reference. A 0.1 µF bypass capacitor is required between these two pins. Power Supply Connections Internal Digital Supply 23 VDDD — Decoupling pin for the internal 1.8V di gital supply. A 0.1µF bypass capacitor is required between this pin and GNDD. Digital Ground 22 GNDD — Digital ground. Positive Analog Supply 12 VDDA — The positive 3.3V analog supply. Analog Ground 11 GNDA — Analog ground. Thermal Pad - No Electrical Connection. 9 10 11 12 192021222324 Top-Down (Through Package) View 24-Pin QFN Package XOUT VDDD GNDD MODE SSEL CS IIN2- IIN2+ VREF- VREF+ GNDA XIN RESET IIN1- IIN1+ VIN+ SCLK RX/SDI TX/SDO DO2 DO1 Thermal Pad VIN- VDDA DO3

2.1 Analog Pins

bypass capacitor should be placed.

2.1.1 Voltage Input

70.7% of maximum peak voltage.

2.1.2 Current1 and Current2 Inputs

70.7% of maximum peak voltage.

2.1.3 Voltage Reference

connected to the VREF pins.

2.1.4 Crystal Oscillator

2.2 Digital Pins

2.2.1 Reset Input

2.2.2 Digital Outputs

pulses, interrupt, zero-cross ings, or energy directions.

6.6.2 Configuration 1 (Config1) – Page 0, Address 1 on

2.2.3 UART/SPI™ Serial Interface

a host microcontroller and the CS5480. port is used as the serial interface. Figure 1. Oscillator Connections

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2.2.3.1 SPI

, SCLK, SDI, and SDO signals. more reliable SPI communication. SCLK is the serial clock input for the CS5480 SPI port. SDI is the serial data input to the CS5480. SDO is the serial data output from the CS5480. The CS5480 SPI transmits and receives data MSB first.

2.2.3.2 UART

) for connecting multiple devices. mode connections are shown in Figure 2. Figure 2. Multi-device UART Connections

1. Multi-device UART Timing on page15).

Figure 3. UART Serial Frame Format The maximum baud rate is 512K if MCLK is 4.096MHz.

2.2.4 MODE Pin

1. CHARACTERISTICS AND SPECIFICATIONS

Notes: 1. Specifications guaranteed by design and characterization. 4.096MHz; 3) System is calibrated.

1. Calculated using register values; N ≥4000.

• Energy error measured at system level using single energy pulse; where one energy pulse = 0.5Wh or 0.5Varh.
• I RMS error calculated using register values.
• VDDA = +3.3V; TA = 25°C; MCLK = 4.096MHz. Parameter Symbol Min Typ Max Unit Positive Analog Power Supply VDDA 3.0 3.3 3.6 V Specified Temperature Range T A -40 - +85 °C Parameter Symbol Min Typ Max Unit Active Energy All Gain Ranges (Note 1 and 2) Current Channel Input Signal Dynamic Range 4000:1 PAvg -± 0 . 1- % Reactive Energy All Gain Ranges (Note 1 and 2) Current Channel Input Signal Dynamic Range 4000:1 QAvg -± 0 . 1- % Apparent Power All Gain Ranges (Note 1 and 3) Current Channel Input Signal Dynamic Range 1000:1 S- ± 0 . 1 - % Current RMS All Gain Ranges (Note 1, 3, and 4) Current Channel Input Signal Dynamic Range 1000:1 IRMS -± 0 . 1- % Voltage RMS (Note 1 and 3) Voltage Channel Input Signal Dynamic Range 20:1 VRMS -± 0 . 1- % Power Factor All Gain Ranges (Note 1 and 3) Current Channel Input Signal Dynamic Range 1000:1 PF - ±0.1 - % -0.5 0.5 0 500 1000 1500 2000 2500 3000 3500 4000 4500 Percent Error (%) Current Dynamic Range (x : 1) Lagging PF = 0.5 Leading PF = 0.5 PF = 1

Figure 4. Active Energy Load Performance

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Figure 5. Reactive Energy Load Performance Figure 6. IRMS Load Performance

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C.
• VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V.
• MCLK = 4.096MHz. Parameter Symbol Min Typ Max Unit Analog Inputs (Current Channels) Common Mode Rejection (DC, 50, 60Hz) CMRR 80 - - dB Common Mode+Signal -0.25 - VDDA V Differential Full-scale Input Range (Gain = 10) [(IIN+) – (IIN-)] (Gain = 50) IIN - 250 mVP mVP Total Harmonic Distortion (Gain = 50) THD 90 100 - dB Signal-to-Noise Ratio (SNR) (Gain = 10) (Gain = 50) SNR - dB dB Crosstalk from Voltage Inputs at Full Scale (50, 60Hz) -- 1 1 5-d B Crosstalk from Current Input at Full Scale (50, 60Hz) -- 1 1 5-d B Input Capacitance IC - 27 - pF Effective Input Impedance EII 30 - - k  Offset Drift (Without the High-pass Filter) OD - 4.0 - µV/°C Noise (Referred to Input) (Gain = 10) (Gain = 50) NI 3.5 µVRMS µVRMS Power Supply Rejection Ratio (60Hz) (Note 7) (Gain = 10) (Gain = 50) PSRR 60 dB dB Analog Inputs (Voltage Channels) Common Mode Rejection (DC, 50, 60Hz) CMRR 80 - - dB Common Mode+Signal -0.25 - VDDA V Differential Full-scale Input Range [(VIN+) – (VIN-)] VIN - 250 - mV P Total Harmonic Distortion THD 80 88 - dB Signal-to-Noise Ratio (SNR) SNR - 73 - dB Crosstalk from Current Inputs at Full Scale Input Capacitance IC - 2.0 - pF Effective Input Impedance EII 2 - - M  Noise (Referred to Input) N V -4 0- µ V RMS Offset Drift (Without the High-pass Filter) OD - 16.0 - µV/°C Power Supply Rejection Ratio (60Hz) (Note 7) (Gain = 10x) PSRR 60 65 - dB Temperature Temperature Accuracy (Note 6) T- ± 5 - ° C

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Notes: 5. All outputs unloaded. All inputs CMOS level. 6. Temperature accuracy measured after calibration is performed. 7. Measurement method for PSRR: VDDA = +3.3V, a 150mV (zer o-to-peak) (60Hz) sine wave is imposed onto the +3.3V DC supply voltage at the VDDA pin. The “+” and “-” input pins of both input channels are shorted to GNDA. The CS5480 is then commanded to continuous conversion acquisition mode, and digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured in mV) that would need to be applied at the channel’s inputs in order to cause the same digital sinusoidal output. This voltage is then defined as Veq PSRR is (in dB): VOLTAGE REFERENCE Notes: 8. It is strongly recommended that no connection other than the required filter capacitor be made to VREF±. 9. The voltage at VREF± is measured across the temperature range. From these measurements the following formula is used to calculate the VREF temperature coefficient: 10. Specified at maximum recommended output of 1µA sourcing. VREF is a sensitive signal; the output of the VREF circuit has a high output impedance so that the 0.1µF reference capacitor provides attenuation even to low-frequency noise, such as 50Hz noise on the VREF output. Therefore VREF is intended for the CS5480 only and should not be connected to any external circuitry. The output impedance is sufficiently high that standard digital multimeters can significantly load this voltage. The accuracy of the metrology IC cannot be guaranteed when a multimeter or any component other than the 0.1µF capacitor is attached to VREF. If it is desired to measure VREF for any reason other than a very course indicator of VREF functionality, Cirrus recommends a very high input impedance multimeter such as the Keithley Model 2000 Digital Multimeter be used. Cirrus cannot guarantee the accuracy of the metrology with this meter connected to VREF. Power Supplies Power Supply Currents (Active State) IA+ (VDDA = +3.3V) PSCA - 3.9 - mA Power Consumption (Note 5) Active State (VDDA = +3.3V) Stand-by State PC - 12.9 4.5 mW mW Parameter Symbol Min Typ Max Unit Reference (Note 8) Output Voltage VREF +2.3 +2.4 +2.5 V Temperature Coefficient (Note 9) TCVREF -2 5- p p m / ° C Load Regulation (Note 10) VR -3 0- m V Parameter Symbol Min Typ Max Unit PSRR 20 150 Veq TCVREF VREF MAX VREF MIN– VREF AVG  1

• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C.
• VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V.
• MCLK = 4.096MHz. Notes: 11. All measurements perfo rmed under static conditions. 12. XOUT pin used for crystal only. Typical drive current<1mA. Parameter Symbol Min Typ Max Unit Master Clock Characteristics XIN Clock Frequency Internal Gate Oscillator MCLK 2.5 4.096 5 MHz XIN Clock Duty Cycle 40 - 60 % Filter Characteristics Phase Compensation Range (60Hz, OWR = 4000Hz) -10.79 - +10.79 ° Input Sampling Rate - MCLK/8 - Hz Digital Filter Output Word Rate (Both channels) OWR - MCLK/1024 - Hz High-pass Filter Corner Frequency -3dB -2 . 0 - H z Input/Output Characteristics High-level Input Voltage (All Pins) V IH 0.6(VDDA) - - V Low-level Input Voltage (All Pins) V IL -- 0 . 6 V High-level Output Voltage DO1-DO3, Iout =+ 1 0 m A (Note 12) All Other Outputs, I out =+ 5 m A VOH VDDA-0.3 VDDA-0.3 V V Low-level Output Voltage DO1-DO3, Iout =- 1 2 m A (Note 12) All Other Outputs, I out =- 5 m A VOL 0.5 0.5 V V Input Leakage Current I in -± 1 ± 1 0 µ A 3-state Leakage Current I OZ -- ± 1 0 µ A Digital Output Pin Capacitance C out -5 - p F

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• Min / Max characteristics and specifications are guaranteed over all Recommended Operating Conditions.
• Typical characteristics and specifications are measured at nominal supply voltages and TA = 25°C.
• VDDA = +3.3V ±10%; GNDA = GNDD = 0V. All voltages with respect to 0V.
• Logic Levels: Logic 0 = 0V, Logic 1 = VDDA. Notes: 13. Specified using 10% and 90% points on wa veform of interest. Output loaded with 50pF. 14. Oscillator start-up time varies with cryst al parameters. This specification does not apply when using an external clock source. 15. The maximum SCLK is 2 MHz during a byte transaction. T he minimum 1µs idle time is required on the SCLK between two consecutive bytes. Parameter Symbol Min Typ Max Unit Rise Times DO1-DO3 (Note 13) Any Digital Output Except DO1-DO3 trise - 1.0 µs ns Fall Times DO1-DO3 (Note 13) Any Digital Output Except DO1-DO3 tfall - 1.0 µs ns Start-up Oscillator Start-up Time XTAL = 4.096 MHz (Note 14) tost -6 0- m s SPI Timing Serial Clock Frequency (Note 15) SCLK - - 2 MHz Serial Clock Pulse Width High Pulse Width Low 200 200 ns ns CS Enable to SCLK Falling t 3 50 - - ns Data Set-up Time prior to SCLK Rising t 4 50 - - ns Data Hold Time After SCLK Rising t 5 100 - - ns SCLK Rising Prior to CS Disable t 6 1-- µ s SCLK Falling to New Data Bit t 7 -- 1 5 0 n s CS Rising to SDO Hi-Z t 8 -- 2 5 0 n s UART Timing CS Enable to RX START bit t 9 5-- n s STOP bit to CS Disable t10 1-- µ s CS Disable to TX IDLE Hold Time t 11 -- 2 5 0 n s

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Notes: 16. VDDA and GNDA must satisfy [(VDDA) – (GNDA)]  + 4.0V. 17. Applies to all pins, includi ng continuous overvoltage conditions at the analog input pins. 18. Transient current of up to 100 mA will not cause SCR latch-up. 19. Applies to all pins, except VREF± . 20. Total power dissipation, including all input currents and output currents. 21. Applies to all pins. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Parameter Symbol Min Typ Max Unit DC Power Supplies (Note 16) VDDA -0.3 - +4.0 V Input Current (Notes 17 and 18) IIN -- ± 1 0 m A Input Current for Power Supplies - - - ±50 - Output Current (Note 19) IOUT -- 1 0 0 m A Power Dissipation (Note 20) PD -- 5 0 0 m W Input Voltage (Note 21) VIN - 0.3 - (VDDA) + 0.3 V Junction-to-Ambient Thermal Impedance 2 Layer Board

4 Layer Board JA

°C/W °C/W Ambient Operating Temperature T A -4 0 - 8 5 ° C Storage Temperature T stg -6 5 - 1 5 0 ° C

two separate voltage digital signal paths (V1 and V2).

4.1 Analog-to-Digital Converters

range and simplifies anti-alias filter design.

4.2 Decimation Filters

passed through an IIR "anti-sinc" filter.

4.3 IIR Filters

Figure 9. Signal Flow for V1, I1, P1, Q1 Measurements Figure 10. Signal Flow for V2, I2, P2, and Q2 Measurements

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4.4 Phase Compensation

provide up to 1/OWR delay in the current channels. channel or up to 2/OWR delay in the voltage channel.

4.5 DC Offset and Gain Correction

DC offset and gain errors in the channel (see section 7. System Calibration on page 63 for more details).

4.6 High-pass and Phase Matching Filters

4.7 Digital Integrators

gain generated by the Rogowski coil current sensor.

6.6.3 Configuration 2 (Config2) – Page 16, Address 0 on

4.8 Low-rate Calculations

Figure 11. Low-rate Calculations

4.8.1 Fixed Number of Samples Averaging

N is the preset value in the SampleCount register and should not be set less than 100. By default, the Sample- Count is 4000. With MCLK = 4.096MHz, the averaging period is fixed at N/4000 = 1 second, regardless of the line frequency.

4.8.2 Line-cycle Synchronized Averaging

When operating in Line-cycle Synchronized Averaging mode, and when line frequency measurement is enabled (see section 5.4 Line Frequency Measurement on page 22), the CS5480 uses the voltage (V) channel zero crossings and measured line frequency to automatically adjust N such that the averaging period will be equal to the number of half line-cycles in the CycleCount register. For example, if the line frequency is 51Hz, and the CycleCount register is set to 100, N will be 4000 (100/2)/51 = 3921 during continuous conversion. N is self-adjusted according to the line frequency; therefore, the averaging period is always close to the whole number of half line-cycles, and the low-rate calculation result s will minimize ripple and maximize resolution, especially when the line frequency varies. Before starting a low-rate conversion in Line-cycle Synchronized Averaging mode, the SampleCount register should not be changed from its default value of 4000, and bit AFC of the Config2 register must be set. During continuous conversion, the host processor should not change the SampleCount register.

4.8.3 RMS Current and Voltage

The root mean square (RMS in Figure 11) calculations are performed on N instantaneous current and voltage samples using Equation 1:

4.8.4 Active Power

The instantaneous voltage and current samples are multiplied to obtain the instantaneous power ( P1, P2 ) (see Figures 9 and 11). The product is then averaged over N samples to compute active power ( P1 AVG, P2AVG).

4.8.5 Reactive Power

Instantaneous reactive power (Q1, Q2) are sample rate results obtained by multip lying instantaneous current (I1, I2) by instantaneous quadrature voltage (V1Q, V2Q), which are created by phase shifting the instantaneous voltage ( V1, V2) 90 degrees using first-order integrators (see Figures 9 and 11). The gain of these integrators is inversely related to line frequency, so their gain is corrected by the Epsilon register, which is based on line frequency. Reactive power (Q1 AVG, Q2AVG) is generated by integrating the instantaneous quadrature power over N samples.

4.8.6 Apparent Power

By default, the CS5480 calculates the apparent power (S1, S2) as the product of RMS voltage and current as shown in Equation 2: The CS5480 also provides an alternate apparent power calculation method, which uses real power ( P1AVG, P2AVG) and reactive power ( Q1AVG, Q2AVG) to calcu- late apparent power, as shown in Equation 3: The APCM bit in the Config2 register controls which method is used for apparent power calculation.

4.8.7 Peak Voltage and Current

Peak current ( I1PEAK, I2PEAK) and peak voltage (VPEAK) are calculated over N samples and recorded in the corresponding channel peak register documented in the register map. This peak value is updated every N samples.

4.8.8 Power Factor

Power factor (PF1, PF2) is active power divided by ap- parent power as shown in Equation 4. The sign of the power factor is determined by the active power.

4.9 Average Active Power Offset

The average active power offset registers, P1OFF (P2OFF), can be used to offset erroneous power sources resident in the system not originating from the power line. Residual power offsets are usually caused by crosstalk into current channels from voltage channels, or from ripple on the meter’s or chip’s power supply, or from inductance from a nearby transformer. IRMS In n0= N1– = VRMS Vn n0= N1– = [Eq. 1] SV RMS IRMS= [Eq. 2] SQ AVG

2 PAVG

2+= [Eq. 3] PF PACTIVE

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These offsets can be either positive or negative, indicating crosstalk coupling either in phase or out of phase with the applied voltage input. The power offset registers can compensate for either condition. To use this feature, measure the average power at no load. Take the measured result (from the P1 AVG (P2AVG) register), invert (negate) the value, and write it to the associated average active power offset register, OFF (P2OFF).

4.10 Average Reactive Power Offset

The average reactive power offset registers, Q1OFF (Q2OFF), can be used to offset erroneous power sources resident in the system not originating from the power line. Residual reactive power offsets are usually caused by crosstalk into current channels from voltage channels, or from ripple on the meter’s or chip’s power supply, or from inductance from a nearby transformer. These offsets can be either positive or negative, depending on the phase angle between the crosstalk coupling and the applied voltage. The reactive power offset registers can compensate for either condition. To use this feature, measure the average reactive power at no load. Take the measured result from the AVG (Q2AVG) register, invert (negate) the value and write it to the associated reactive power offset register, OFF (Q2OFF).

5.1 Power-on Reset

threshold for the master reset to be de-asserted. Each POR is divided into two blocks: rough and fine. prevents the reset signal from chattering. de-asserts the master reset. Table 1. POR Thresholds

5.2 Power Saving Modes

• Standby: Powers down all the ADCs, rough buffer, and the temperature sensor. Standby mode disables the system time calculations. Use the wake-up command to come out of standby mode.
• Wake-up: Clears the ADC power-down bits and starts the system time calculations. After any of these commands are completed, the DRDY bit is set in the Status0 register.

5.3 Zero-crossing Detection

Figure 12. Power-on Reset Timing

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5.4 Line Frequency Measurement

frequency out of the range of 40Hz to 75Hz. If |VPEAK| > VZXLEVEL, then voltage zero-crossing detection is enabled. If |IPEAK| > IZXLEVEL, then current zero-crossing detection is enabled. If |VPEAK| ” VZXLEVEL, then voltage zero-crossing detection is disabled. If |IPEAK| ” IZXLEVEL, then current zero-crossing detection is disabled. Figure 13. Zero-crossing Level and Zero-crossing Output on DOx

5.5 Meter Configuration Modes

for power calculations in each mode. Table 2. Meter Configuration Modes Figure 14. Channel Selection and Tamper Protection Flow

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5.6 Tamper Detection and Correction

5.6.1.2 Manual Channel Selection on page 25.

5.6.1 Anti-tampering on Current

5.6.1.1 Automatic Channel Selection

Automatic channel selection is standard in the CS5480. of the IVSP bit in the Config2 register.

• T h e P1AVG and P2AVG must meet the Channel Select Minimum Amplitude (IchanLEVEL). The highest channel is active, P1AVG in this example.
• Even when the active channel ( P1AVG) moves below the previously lower channel (P2AVG), the channel selection does not change.
• The new channel selection is only made when the difference between P1AVG and P2AVG is greater than 2% x P1AVG or P2AVG > P1AVG x IchanLEVEL (1.02). Channel Select Level (IchanLEVEL) 2% minimum difference Channel Select Level (IchanLEVEL) 2% minimum difference Channel Select Minimum Amplitude PMIN (IRMSMIN) P1AVG P2AVG 1 2 3 Channel 1 - Remains Active Channel 2 - ActiveChannel 1 - Active Automatic Channel Selection Region Disabled Automatic Channel Selection Region

Figure 15. Automatic Channel Selection

5.6.1.2 Manual Channel Selection

5.6.2 Anti-tampering on Voltage

5.7 Energy Pulse Generation

energy pulses to accumulate the energy (see Figure 16). Figure 16. Energy Pulse Generation and Digital Output Control

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1. Write to register PulseWidth (page 0, address 8) to
2. Write to register PulseRate (page 18, address 28) to

select the energy pulse rate.

1. Write to register PulseCtrl (page 0, address 9) to
2. Write ‘1’ to bit EPGx_ON of register Config1 (page 0,
3. Write bits DOxMODE[3:0] of register Config1 to

energy pulse generation block.

1. Send DSP instruction (0xD5) to begin continuous

5.7.1 Pulse Rate

and the Scale register contains the default value of 0.6.

• The pulse rate generated by full-scale (1.0decimal) power register: FOUT =( PulseRatex2000)/2 FREQ_RNG
• T h e PulseRate register value is: PulseRate = (FOUTx2FREQ_RNG)/2000 = 0.5925952 = 0x4BDA29

5.7.2 Pulse Width

Active-low = 250µs+( PulseWidth/64000).

5.8 Voltage Sag, Voltage Swell, and

rectified and compared to the associated level register . swell or overcurrent condition (see Figure 17). Figure 17. Sag, Swell, and Overcurrent Detect

5.9 Phase Sequence Detection

sequence detection is performed. from the CS5480 on phase A with the highest count.

5.10 Temperature Measurement

Figure 18. Phase Sequence A, B, C for Rising Edge Transition

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GAIN) and Temperature Offset (TOFF) registers. T updates every 2240 output word rate (OWR) samples.

5.11 Anti-Creep

register, then SSUM is forced to zero.

5.12 Register Protection

5.12.1 Write Protection

Registers Summary (Page 17) on page 35.

5.12.2 Register Checksum

compare it with the saved copy of the RegChk register. and calibrations into the CS5480 is necessary. Figure 19. Phase Sequence C, B, A for Rising Edge Transition

1. HOST COMMANDS AND REGISTERS

6.1 Host Commands

Table 3. Command Format

6.1.1 Memory Access Commands

address within the selected page.

6.1.1.1 Page Select

performed once the page has been selected. Figure 20. Byte Sequence for Page Select

6.1.1.2 Register Read

Figure 21. Byte Sequence for Register Read

6.1.1.3 Register Write

must be followed by 3 bytes of data. Figure 22. Byte Sequence for Register Write

6.1.2 Instructions

and initiate a new process in the CS5480. Figure 23. Byte Sequence for Instructions Table 4. Instruction Format

0 C4 C3 C2 C1 C0

1 C4 C3 C2 C1 C0

1 C4C3 0 0 1 I1

1 C4C3 0 1 0 V1

1 C4C3 0 1 1 I2

1 C4C3 1 0 0 V2

1 C4C3 1 1 0 All Four

SDI/RX DATA DATA DATAWrite Cmd .

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6.1.3 Checksum

preparation for the next transmission. Figure 24. Byte Sequence for Checksum

6.1.4 Serial Time Out

SDI/RX ChecksumPage Select Cmd. SDI/RX DATA DATA DATA CHECKSUMWrite Cmd .

6.2 Hardware Registers Summary (Page 0)

Address2 RA[5:0] Name Description1 DSP3 HOST 3 Default 0* 00 0000 Config0 Configuration 0 Y Y 0x C0 2000 1* 00 0001 Config1 Configuration 1 Y Y 0x 00 EEEE 2 00 0010 - Reserved - 3* 00 0011 Mask Interrupt Mask Y Y 0x 00 0000 4 00 0100 - Reserved - 5* 00 0101 PC Phase Compensation Control Y Y 0x 00 0000 6 00 0110 - Reserved - 7* 00 0111 SerialCtrl UART Control Y Y 0x 02 004D 8* 00 1000 PulseWidth Energy Pulse Width Y Y 0x 00 0001 9* 00 1001 PulseCtrl Energy Pulse Control Y Y 0x 00 0000 10 00 1010 - Reserved - 11 00 1011 - Reserved - 12 00 1100 - Reserved - 13 00 1101 - Reserved - 14 00 1110 - Reserved - 15 00 1111 - Reserved - 16 01 0000 - Reserved - 17 01 0001 - Reserved - 18 01 0010 - Reserved - 19 01 0011 - Reserved - 20 01 0100 - Reserved - 21 01 0101 - Reserved - 22 01 0110 - Reserved - 23 01 0111 Status0 Interrupt Status N N 0x 80 0000 24 01 1000 Status1 Chip Status 1 N N 0x 80 1800 25 01 1001 Status2 Chip Status 2 N N 0x 00 0000 26 01 1010 - Reserved - 27 01 1011 - Reserved - 28 01 1100 - Reserved - 29 01 1101 - Reserved - 30 01 1110 - Reserved - 31 01 1111 - Reserved - 32 10 0000 - Reserved - 33 10 0001 - Reserved - 34* 10 0010 RegLock Register Lock Control N N 0x 00 0000 35 10 0011 - Reserved - 36 10 0100 V1 PEAK V1 Peak Voltage N Y 0x 00 0000 37 10 0101 I1 PEAK I1 Peak Current N Y 0x 00 0000 38 10 0110 V2 PEAK V2 Peak Voltage N Y 0x 00 0000 39 10 0111 I2 PEAK I2 Peak Current N Y 0x 00 0000 40 10 1000 - Reserved - 41 10 1001 - Reserved - 42 10 1010 - Reserved - 43 10 1011 - Reserved - 44 10 1100 - Reserved - 45 10 1101 - Reserved - 46 10 1110 - Reserved - 47 10 1111 - Reserved - 48 11 0000 PSDC Phase Sequence Detection & Control N Y 0x 00 0000 49 11 0001 - Reserved - 50 11 0010 - Reserved -

32 DS980F3

NUM Num. Zero Crosses used for Line Freq. Y Y 0x 00 0064 56 11 1000 - Reserved - 57 11 1001 - Reserved - 58 11 1010 - Reserved - 59 11 1011 - Reserved - 60 11 1100 - Reserved - 61 11 1101 - Reserved - 62 11 1110 - Reserved - 63 11 1111 - Reserved - Notes: (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. (3) Registers that can be set to write protect from DSP and/or HOST.

6.3 Software Registers Summary (Page 16)

Address2 RA[5:0] Name Description1 DSP3 HOST 3 Default 0* 00 0000 Config2 Configuration 2 Y Y 0x 00 0200 1 00 0001 RegChk Register Checksum N Y 0x 00 0000 2 00 0010 I1 I1 Instantaneous Current N Y 0x 00 0000 3 00 0011 V1 V1 Instantaneous Voltage N Y 0x 00 0000 4 00 0100 P1 Instantaneous Power 1 N Y 0x 00 0000 5 00 0101 P1 AVG Active Power 1 N Y 0x 00 0000 6 00 0110 I1 RMS I1 RMS Current N Y 0x 00 0000 7 00 0111 V1 RMS V1 RMS Voltage N Y 0x 00 0000 8 00 1000 I2 I2 Instantaneous Current N Y 0x 00 0000 9 00 1001 V2 V2 Instantaneous Voltage N Y 0x 00 0000 10 00 1010 P2 Instantaneous Power 2 N Y 0x 00 0000 11 00 1011 P2 AVG Active Power 2 N Y 0x 00 0000 12 00 1100 I2 RMS I2 RMS Current N Y 0x 00 0000 13 00 1101 V2 RMS V2 RMS Voltage N Y 0x 00 0000 14 00 1110 Q1 AVG Reactive Power 1 N Y 0x 00 0000 15 00 1111 Q1 Instantaneous Reactive Power 1 N Y 0x 00 0000 16 01 0000 Q2 AVG Reactive Power 2 N Y 0x 00 0000 17 01 0001 Q2 Instantaneous Reactive Power 2 N Y 0x 00 0000 18 01 0010 - Reserved - 19 01 0011 - Reserved - 20 01 0100 S1 Apparent Power 1 N Y 0x 00 0000 21 01 0101 PF1 Power Factor 1 N Y 0x 00 0000 22 01 0110 - Reserved - 23 01 0111 - Reserved - 24 01 1000 S2 Apparent Power 2 N Y 0x 00 0000 25 01 1001 PF2 Power Factor 2 N Y 0x 00 0000 26 01 1010 - Reserved - 27 01 1011 T Temperature N Y 0x 00 0000 28 01 1100 - Reserved - 29 01 1101 P SUM Total Active Power N Y 0x 00 0000 30 01 1110 S SUM Total Apparent Power N Y 0x 00 0000 31 01 1111 Q SUM Total Reactive Power N Y 0x 00 0000 32* 10 0000 I1 DCOFF I1 DC Offset Y Y 0x 00 0000 33* 10 0001 I1 GAIN I1 Gain Y Y 0x 40 0000 34* 10 0010 V1 DCOFF V1 DC Offset Y Y 0x 00 0000 35* 10 0011 V1 GAIN V1 Gain Y Y 0x 40 0000 36* 10 0100 P1 OFF Average Active Power 1 Offset Y Y 0x 00 0000 37* 10 0101 I1 ACOFF I1 AC Offset Y Y 0x 00 0000 38* 10 0110 Q1 OFF Average Reactive Power 1 Offset Y Y 0x 00 0000 39* 10 0111 I2 DCOFF I2 DC Offset Y Y 0x 00 0000 40* 10 1000 I2 GAIN I2 Gain Y Y 0x 40 0000 41* 10 1001 V2 DCOFF V2 DC Offset Y Y 0x 00 0000 42* 10 1010 V2 GAIN V2 Gain Y Y 0x 40 0000 43* 10 1011 P2 OFF Average Active Power 2 Offset Y Y 0x 00 0000 44* 10 1100 I2 ACOFF I2 AC Offset Y Y 0x 00 0000 45* 10 1101 Q2 OFF Average Reactive Power 2 Offset Y Y 0x 00 0000 46 10 1110 - Reserved - 47 10 1111 - Reserved - 48 11 0000 - Reserved - 49 11 0001 Epsilon Ratio of Line to Sample Frequency N Y 0x 01 999A 50* 11 0010 Ichan LEVEL Automatic Channel Select Level Y Y 0x 82 8F5C

34 DS980F3

51** 11 0011 SampleCount Sample Count N Y 0x 00 0FA0 52 11 0100 - Reserved - 53 11 0101 - Reserved - 54* 11 0110 T GAIN Temperature Gain Y Y 0x 06 B716 55* 11 0111 T OFF Temperature Offset Y Y 0x D5 3998 56* 11 1000 P MIN(IRMSMIN) Channel Select Minimum Amplitude Y Y 0x 00 624D 57 11 1001 T SETTLE Filter Settling Time to Conv. Startup Y Y 0x 00 001E 58* 11 1010 Load MIN No Load Threshold Y Y 0x 00 0000 59* 11 1011 VF RMS Voltage Fixed RMS Reference Y Y 0x 5A 8279 60* 11 1100 SYS GAIN System Gain N Y 0x 50 0000 61 11 1101 Time System Time (in samples) N Y 0x 00 0000 62 11 1110 - Reserved - 63 11 1111 - Reserved - Notes: (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. ** When setting the AVG_MODE bit (AVG_MODE = ‘1’) in the Config2 register, the device will use the Line-cycle Synchronized Averaging mode and the CycleCount register will be includ- ed in the checksum. Otherwise the SampleCount register will be included. (3) Registers that can be set to write protect from DSP and/or HOST.

6.4 Software Registers Summary (Page 17)

Address2 RA[5:0] Name Description1 DSP3 HOST 3 Default 0* 00 0000 V1Sag DUR V1 Sag Duration Y Y 0x 00 0000 1* 00 0001 V1Sag LEVEL V1 Sag Level Y Y 0x 00 0000 2 00 0010 - Reserved - 3 00 0011 - Reserved - 4* 00 0100 I1Over DUR I1 Overcurrent Duration Y Y 0x 00 0000 5* 00 0101 I1Over LEVEL I1 Overcurrent Level Y Y 0x 7F FFFF 6 00 0110 - Reserved - 7 00 0111 - Reserved - 8* 00 1000 V2Sag DUR V2 Sag Duration Y Y 0x 00 0000 9* 00 1001 V2Sag LEVEL V2 Sag Level Y Y 0x 00 0000 10 00 1010 - Reserved - 11 00 1011 - Reserved - 12* 00 1100 I2Over DUR I2 Overcurrent Duration Y Y 0x 00 0000 13* 00 1101 I2Over LEVEL I2 Overcurrent Level Y Y 0x 7F FFFF 14 00 1110 - Reserved - 15 00 1111 - Reserved - 16 01 0000 - Reserved - 17 01 0001 - Reserved - 18 01 0010 - Reserved - 19 01 0011 - Reserved - 20 01 0100 - Reserved - 21 01 0101 - Reserved - 22 01 0110 - Reserved - 23 01 0111 - Reserved - 24 01 1000 - Reserved - 25 01 1001 - Reserved - 26 01 1010 - Reserved - 27 01 1011 - Reserved - 28 01 1100 - Reserved - 29 01 1101 - Reserved - 30 01 1110 - Reserved - 31 01 1111 - Reserved - Notes: (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. (3) Registers that can be set to write protect from DSP and/or HOST.

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6.5 Software Registers Summary (Page 18)

Address2 RA[5:0] Name Description1 DSP3 HOST 3 Default 24* 01 1000 IZX LEVEL Zero-Cross Threshold for I-Channel Y Y 0x 10 0000 25 01 1001 - Reserved - 26 01 1010 - Reserved - 27 01 1011 - Reserved - 28* 01 1100 PulseRate Energy Pulse Rate Y Y 0x 80 0000 29 01 1101 - Reserved - 30 01 1110 - Reserved - 31 01 1111 - Reserved - 32 10 0000 - Reserved - 33 10 0001 - Reserved - 34 10 0010 - Reserved - 35 10 0011 - Reserved - 36 10 0100 - Reserved - 37 10 0101 - Reserved - 38 10 0110 - Reserved - 39 10 0111 - Reserved - 40 10 1000 - Reserved - 41 10 1001 - Reserved - 42 10 1010 - Reserved - 43* 10 1011 INT GAIN Rogowski Coil Integrator Gain Y Y 0x 14 3958 44 10 1100 - Reserved - 45 10 1101 - Reserved - 46* 10 1110 V1Swell DUR V1 Swell Duration Y Y 0x 00 0000 47* 10 1111 V1Swell LEVEL V1 Swell Level Y Y 0x 7F FFFF 48 11 0000 - Reserved - 49 11 0001 - Reserved - 50* 11 0010 V2Swell DUR V2 Swell Duration Y Y 0x 00 0000 51* 11 0011 V2Swell LEVEL V2 Swell Level Y Y 0x 7F FFFF 52 11 0100 - Reserved - 53 11 0101 - Reserved - 54 11 0110 - Reserved - 55 11 0111 - Reserved - 56 11 1000 - Reserved - 57 11 1001 - Reserved - 58* 11 1010 VZX LEVEL Zero-Cross Threshold for V-Channel Y Y 0x 10 0000 59 11 1011 - Reserved - 60 11 1100 - Reserved - 61 11 1101 - Reserved - 62** 11 1110 CycleCount Line Cycle Count N Y 0x 00 0064 63* 11 1111 Scale I-Channel Gain Calibration Scale Value Y Y 0x 4C CCCC Notes: (1) Warning: Do not write to unpublished or reserved register locations. (2) * Registers with checksum protection. ** When setting the AVG_MODE bit (AVG_MODE = ‘1’) in the Config2 register, the device will use the Line-cycle Synchronized Averaging mode and the CycleCount register will be includ- ed in the checksum. Otherwise the SampleCount register will be included. (3) Registers that can be set to write protect from DSP and/or HOST.

6.6 Register Descriptions

1. “Default” = bit states after power-on or reset 23. DO NOT write a “1” to any unpublished regi ster bit or to a bit published as “0”. 24. DO NOT write a “0” to any bit published as “1”. 25. DO NOT write to any unpublished register address.

6.6.1 Configuration 0 (Config0) – Page 0, Address 0

Default = 0xC0 2000 [23:9] Reserved. INT_POL Interrupt Polarity. 0 = Active low (Default) 1 = Active high I2PGA[1:0] Select PGA gain for I2 channel. 00 = 10x gain (Default) 10 = 50x gain I1PGA[1:0] Select PGA gain for I1 channel. 00 = 10x gain (Default) 10 = 50x gain [3] Reserved. NO_OSC Disable crystal oscillator (m aking XIN a logic-level input). 0 = Crystal oscillator enabled (Default) 1 = Crystal oscillator disabled IZX_CH Select current channe l for zero-cross detect. 0 = Selects current channel 1 for zero-cross detect (Default) 1 = Selects current channel 2 for zero-cross detect [0] Reserved. 23 22 21 20 19 18 17 16 1100- - - - 15 14 13 12 11 10 9 8 -0100- - I N T _ P O L 765432 10 I2PGA[1] I2PGA[0] I1PGA[1] I1PGA[0] - NO_OSC IZX_CH -

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6.6.2 Configuration 1 (Config1) – Page 0, Address 1

Default = 0x00 EEEE [23] Reserved. EPG3_ON Enable EPG3 block. 0 = Disable energy pulse generation block 3 (Default) 1 = Enable energy pulse generation block 3 EPG2_ON Enable EPG2 block. 0 = Disable energy pulse generation block 2 (Default) 1 = Enable energy pulse generation block 2 EPG1_ON Enable EPG1 block. 0 = Disable energy pulse generation block 1 (Default) 1 = Enable energy pulse generation block 1 [19] Reserved. DO3_OD Allow the DO3 pin to be an open-drain output. 0 = Normal output (Default) 1 = Open-drain output DO2_OD Allow the DO2 pin to be an open-drain output. 0 = Normal output (Default) 1 = Open-drain output DO1_OD Allow the DO1 pin to be an open-drain output. 0 = Normal output (Default) 1 = Open-drain output [15:12] Reserved. DO3MODE[3:0] Output control for DO3 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Reserved 0100 = P1 sign 0101 = P2 sign 0110 = P SUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = Q SUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt 23 22 21 20 19 18 17 16

0 EPG3_ON EPG2_ON EPG1_ON 0 DO3_OD DO2_OD DO1_OD

1 1 1 0 DO3MODE[3] DO3MODE[2] DO3MODE[1] DO3MODE[0] 76543210 DO2MODE[3] DO2MODE[2] DO2MODE[ 1] DO2MODE[0] DO1MODE[3] DO1M ODE[2] DO1MODE[1] DO1MODE[0]

DO2MODE[3:0] Output control for DO2 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Reserved 0100 = P1 sign 0101 = P2 sign 0110 = P SUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = Q SUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt DO1MODE[3:0] Output control for DO1 pin. 0000 = Energy pulse generation block 1 (EPG1) output 0001 = Energy pulse generation block 2 (EPG2) output 0010 = Energy pulse generation block 3 (EPG3) output 0011 = Reserved 0100 = P1 sign 0101 = P2 sign 0110 = P SUM sign 0111 = Q1 sign 1000 = Q2 sign 1001 = Q SUM sign 1010 = Reserved 1011 = V1/V2 zero-crossing 1100 = I1/I2 zero-crossing 1101 = Reserved 1110 = Hi-Z, pin not driven (Default) 1111 = Interrupt

40 DS980F3

6.6.3 Configuration 2 (Config2) – Page 16, Address 0

Default = 0x00 0200 VFIX Use internal RMS voltage reference instea d of voltage input for average active power. 0 = Use voltage input. (Default) 1 = Use internal RMS voltage reference (VF RMS). POS Positive energy only. Suppress negative values in P1AVG and P2AVG. If a negative value is calculated, a zero result will be stored. 0 = Positive and negative energy (Default) 1 = Positive energy only ICHAN Chooses which current channel is used for the P SUM, QSUM, SSUM registers. Applicable only when MCFG[1:0] = 00 and IHOLD = 1. 0 = PSUM, QSUM, and SSUM registers are driven by current channel 1 (P1) (Default) 1 = PSUM, QSUM, and SSUM registers are driven by current channel 2 (P2). IHOLD IHOLD suspends automatic channel se lection for total power calculations. Applicable only when MCFG[1:0] = 00. 0 = Energy channel selected automatically by magnitude compare and on IVSP bit (Default) 1 = Energy channel selected by user and depend on ICHAN configuration Refer to Channel Select Level and Channel Select Minimum Amplitude registers (IchanLEVEL) and PMIN (IRMSMIN) for the magnitudes compared. IVSP Use IRMS results instead of PAVG for automatic energy channel selection. Applicable only when MCFG[1:0] = 00 and IHOLD = 0. 0 = Use P1AVG and P2AVG instead of I1RMS and I2RMS (Default) 1 = Use I1RMS and I2RMS instead of P1AVG and P2AVG MCFG[1:0] Meter Configuration bits are used to control how the meter interprets the current channels when calculating total power — independently or collectively. 00 = 1V, 1I + Neutral mode; PSUM =P 1AVG or P2AVG,Q SUM =Q 1AVG or Q2AVG,S SUM =S 1o rS 2 (Default) 01 = 1V, 2I mode; PSUM = (P1AVG+P2AVG)/2, QSUM=(Q1AVG+Q2AVG)/2, SSUM=(S1+S2)/2 10 = Reserved 11 = Reserved [16:15] Reserved. APCM Selects the apparent power calculation method. 0 = Vx RMS x IxRMS (Default) 1 = SQRT(PAVG 2 + QAVG [13] Reserved. ZX_LPF Enable LPF in zero-cross detect. 0 = LPF disabled (Default) 1 = LPF enabled AVG_MODE Select averaging mode for low-rate calculations. 0 = Use SampleCount (Default) 1 = Use CycleCount 23 22 21 20 19 18 17 16 VFIX POS ICHAN IHOLD IVSP MCFG[1] MCFG[0] - 15 14 13 12 11 10 9 8 - APCM - ZX_LPF AVG_MODE REG_CSUM_OFF AFC I2FLT[1] 76543 2 1 0 I2FLT[0] V2FLT[1] V2FLT[0] I1FLT[1] I1FLT[0] V1FLT[1] V1FLT[0] IIR_OFF

REG_CSUM_OFF Disable checksum on critical registers. 0 = Enable checksum on critical registers (Default) 1 = Disable checksum on critical registers AFC Enables automatic line frequency measurement which sets Epsilon every time a new line frequency measurement completes. Epsilon is used to control the gain of 90-degree phase shift integrator used in quadrature power calculations. 0 = Disable automatic line frequency measurement 1 = Enable automatic line frequency measurement (Default) I2FLT[1:0] Filter enable for current channel 2. 00 = No filter (Default) 01 = High-pass filter (HPF) on current channel 2 10 = Phase-matching filter (PMF) on current channel 2 11 = Rogowski coil integrator (INT) on current channel 2 V2FLT[1:0] Filter enable for voltage channel 2. 00 = No filter (Default) 01 = High-pass filter (HPF) on voltage channel 2 10 = Phase-matching filter (PMF) on voltage channel 2 11 = Reserved I1FLT[1:0] Filter enable for current channel 1. 00 = No filter (Default) 01 = High-pass filter (HPF) on current channel 1 10 = Phase-matching filter (PMF) on current channel 1 11 = Rogowski coil integrator (INT) on current channel 1 V1FLT[1:0] Filter enable for voltage channel 1. 00 = No filter (Default) 01 = High-pass filter (HPF) on voltage channel 1 10 = Phase-matching filter (PMF) on voltage channel 1 11 = Reserved IIR_OFF Bypass IIR filter. 0 = Do not bypass IIR filter (Default) 1 = Bypass IIR filter

42 DS980F3

6.6.4 Phase Compensation (PC) – Page 0, Address 5

Default = 0x00 0000 CPCC2[1:0] Coarse phase compensation control for I2 and V2. 00 = No extra delay 01 = 1 OWR delay in current channel 2 10 = 1 OWR delay in voltage channel 2 11 = 2 OWR delay in voltage channel 2 CPCC1[1:0] Coarse phase compensation control for I1 and V1. 00 = No extra delay 01 = 1 OWR delay in current channel 1 10 = 1 OWR delay in voltage channel 1 11 = 2 OWR delay in voltage channel 1 [19:18] Reserved. FPCC2[8:0] Fine phase compensation control for I2 and V2. Sets a delay in current, relative to voltage. Resolution: 0.008789° at 50Hz and 0.010547° at 60Hz (OWR = 4000) FPCC1[8:0] Fine phase compensation control for I1 and V1. Sets a delay in current, relative to voltage. Resolution: 0.008789° at 50Hz and 0.010547° at 60Hz (OWR = 4000)

6.6.5 UART Control (SerialCtrl) – Page 0, Address 7

Default = 0x02 004D [23:19] Reserved. RX_PU_OFF Disable the pull-up resistor on the RX input pin. 0 = Pull-up resistor enabled (Default) 1 = Pull-up resistor disabled RX_CSUM_OFF Disable the checksum on serial port data. 0 = Enable checksum 1 = Disable checksum (Default) [16] Reserved. BR[15:0] Baud rate (serial bit rate). BR[15:0] = Baud Ratex524288/MCLK 23 22 21 20 19 18 17 16 CPCC2[1] CPCC2[0] CPCC1[1] CPCC1[0] - - FPCC2[8] FPCC2[7] 15 14 13 12 11 10 9 8 FPCC2[6] FPCC2[5] FPCC2[4] FPCC2[3] FPCC2[2] FPCC2[1] FPCC2[0] FPCC1[8] 76543210 FPCC1[7] FPCC1[6] FPCC1[5] FPCC1[4] FPCC1[3] FPCC1[2] FPCC1[1] FPCC1[0] 23 22 21 20 19 18 17 16 - - - - - RX_PU_OFF RX_CSUM_OFF - 15 14 13 12 11 10 9 8 BR[15] BR[14] BR[13] BR[12] BR[11] BR[10] BR[9] BR[8] 765432 10 BR[7] BR[6] BR[5] BR[4] BR[3] BR[2] BR[1] BR[0]

6.6.6 Pulse Output Width (PulseWidth) – Page 0, Address 8

Default = 0x00 0001 (265.6µs at OWR = 4kHz) PulseWidth sets the energy pulse frequency range and the duration of energy pulses. The actual pulse duration is 250µs plus the contents of PulseWidth divided by 64,000. PulseWidth is an inte- ger in the range of 1 to 65,535. [23:20] Reserved. FREQ_RNG[3:0] Energy pulse ( PulseRate) frequency range for 0.1% resolution. 0000 = Freq. range: 2kHz–0.238Hz (Default) 0001 = Freq. range: 1kHz–0.1192Hz 0010 = Freq. range: 500Hz–0.0596Hz 0011 = Freq. range: 250Hz–0.0298Hz 0100 = Freq. range: 125Hz–0.0149Hz 0101 = Freq. range: 62.5Hz–0.00745Hz 0110 = Freq. range: 31.25Hz–0.003725Hz 0111 = Freq. range: 15.625Hz–0.0018626Hz 1000 = Freq. range: 7.8125Hz–0.000931323Hz 1001 = Freq. range: 3.90625Hz–0.000465661Hz 1010 = Reserved ... 1111 = Reserved PW[15:0] Energy Pulse Width.

6.6.7 Zero crossing Number (ZXNUM) – Page 0, Address 55

Default = 0x00 0064 (100) ZXNUM is the number of zero crossings used for line frequency measurement. It is an integer in the range of 1 to 8,388,607. Zero should not be used.

6.6.8 Energy Pulse Rate (PulseRate) – Page 18, Address 28

Default= 0x80 0000 PulseRate sets the full-scale frequency for the energy pulse outputs. For a 4kHz OWR rate, the maximum pulse rate is 2kHz. This is a two's complement value in the range of -1value1, with the binary point to the left of the MSB. Refer to section 5.5 Meter Configuration Modes on page 23 for more information. 23 22 21 20 19 18 17 16 - - - - FREQ_RNG[3] FREQ_RNG[2] FREQ_RNG[1] FREQ_RNG[0] 15 14 13 12 11 10 9 8 PW[15] PW[14] PW[13] PW[12] PW[11] PW[10] PW[9] PW[8] 76543210 PW[7] PW[6] PW[5] PW[4] PW[3] PW[2] PW[1] PW[0] MSB LSB MSB LSB

44 DS980F3

6.6.9 Pulse Output Control (PulseCtrl) – Page 0, Address 9

Default = 0x00 0000 This register controls the input to the energy pulse generation block (EPGx). [23:12] Reserved. EPGxIN[3:0] Selects the input to the energy pulse generation block (EPGx). 0000 = P1AVG (Default) 0001 = P2AVG 0010 = PSUM 0011 = Q1AVG 0100 = Q2AVG 0101 = QSUM 0110 = S1 0111 = S2 1000 = S SUM 1001 = Unused ... 1111 = Unused

6.6.10 Register Lock Control (RegLock) – Page 0, Address 34

Default = 0x00 0000 [23:13] Reserved. DSP_LCK[4:0] DSP_LCK[4:0] = 0x16 sets the DSP lockable registers to be write protected from the CS5480 internal calculation engine. Writing 0x09 unlocks the registers. [7:5] Reserved. HOST_LCK[4:0] HOST_LCK[4:0] = 0x16 sets all the registers except RegLock, Status0, Status1, and Status2 to be write protected from the serial interface. Writing 0x09 unlocks the registers. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 - - - - EPG3IN[3] EPG3IN[ 2] EPG3IN[1] EPG3IN[0] 76543210 EPG2IN[3] EPG2IN[2] EPG2IN[1] EPG2IN[ 0] EPG1IN[3] EPG1IN[2] EPG1IN[1] EPG1IN[0] 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 - - - DSP_LCK[4] DSP_LCK[3] DSP _LCK[2] DSP_LCK[1] DSP_LCK[0] 76543210 - - - HOST_LCK[4] HOST_LCK[3] HOST _LCK[2] HOST_LCK[1] HOST_LCK[0]

6.6.11 Phase Sequence Detection and Control (PSDC) – Page 0, Address 48

Default = 0x00 0000 DONE Indicates valid count va lues reside in PSCNT[6:0]. 0 = Invalid values in PSCNT[6:0]. (Default) 1 = Valid values in PSCNT[6:0]. PSCNT[6:0] Registers the number of OWR samples fr om the start time to the time when the next zero crossing is detected. [15:6] Reserved. DIR Set the zero-crossing edge dire ction which will stop PSCNT count. 0 = Stop count at negative to positive zero-crossing - Rising Edge. (Default) 1 = Stop count at positive to negative zero-crossing - Falling Edge. CODE[4:0] Write 10110 to this location to enable the phase sequence detection.

6.6.12 Checksum of Critical Registers (RegChk) – Page 16, Address 1

Default = 0x00 0000 This register contains the checksum of critical registers. 23 22 21 20 19 18 17 16 DONE PSCNT[6] PSCNT[5] PSCNT[4] PSC NT[3] PSCNT[2] PSCNT[1] PSCNT[0] 15 14 13 12 11 10 9 8 765432 10 - - DIR CODE[4] CODE[3] CODE[2] CODE[1] CODE[0] MSB LSB

46 DS980F3

6.6.13 Interrupt Status (Status0) – Page 0, Address 23

Default = 0x80 0000 The Status0 register indicates a variety of conditions within the chip. Writing a one to a Status0 register bit will clear that bit. Writing a ‘0’ to any bit has no effect. DRDY Data Ready. During conversion, this bit indicates that low-rate results have been updated. It indicates completion of other host instruction and the reset sequence. CRDY Conversion Ready. Indicates that sample rate (output word rate) results have been updated. WOF Watchdog timer overflow. [20:19] Reserved. MIPS MIPS overflow. Sets when the calculation engine has not completed processing a sample before the next one arrives. V2SWELL (V1SWELL)V2 (V1) swell event detected. P2OR (P1OR) Power out of range. Sets when the measured power would cause the P2 (P1) register to overflow. I2OR (I1OR) Power out of range. Sets when the measured current would cause the I2 (I1) register to overflow. V2OR (V1OR) Voltage out of range. Sets when the measured current would cause the V2 (V1) register to overflow. I2OC (I1OC) I2 (I1) overcurrent. V2SAG (V1SAG) V2 (V1) sag event detected. TUP Temperature updated. Indicates when the Temperature register (T) has been updated. FUP Frequency updated. Indicates the Epsilon register has been updated. IC Invalid command has been received. RX_CSUM_ERR Received data checksum error. Sets to ‘1’ automatically if checksum error is detected on serial port received data. [1] Reserved. RX_TO SDI/RX time out. Sets to ‘1’ automatically when SDI/RX time out occurs. 23 22 21 20 19 18 17 16 DRDY CRDY WOF - - MIPS V2SWELL V1SWELL 15 14 13 12 11 10 9 8 P2OR P1OR I2OR I1OR V2OR V1OR I2OC I1OC 76543 2 1 0 V2SAG V1SAG TUP FUP IC RX_CSUM_ERR - RX_TO

6.6.14 Interrupt Mask (Mask) – Page 0, Address 3

Default = 0x00 0000 The Mask register is used to control the activation of the INT pin. Writing a '1' to a Mask register bit will allow the corresponding Status0 register bit to activate the INT pin when set. [23:0] Enable/disable (mask) interrupts. 0 = Interrupt disabled (Default) 1 = Interrupt enabled

6.6.15 Chip Status 1 (Status1) – Page 0, Address 24

Default = 0x80 1800 This register indicates a variety of conditions within the chip. [23:16] Reserved. LCOM[7:0] Indicates the value of the last serial command executed. [7:4] Reserved. TOD Modulator oscillation has been detected in the temperature ADC. VOD Modulator oscillation has be en detected in the voltage ADC. I2OD (I1OD) Modulator oscillati on has been detected in the current2 (current1) ADC. 23 22 21 20 19 18 17 16 DRDY CRDY WOF - - MIPS V2SWELL V1SWELL 15 14 13 12 11 10 9 8 P2OR P1OR I2OR I1OR V2OR V1OR I2OC I1OC 76543 2 1 0 V2SAG V1SAG TUP FUP IC RX_CSUM_ERR - RX_TO 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 LCOM[7] LCOM[6] LCOM[5] LCOM[4] LCOM[3] LCOM[2] LCOM[1] LCOM[0] 76543210 - - - - TOD VOD I2OD I1OD

48 DS980F3

6.6.16 Chip Status 2 (Status2) – Page 0, Address 25

Default = 0x00 0000 This register indicates a variety of conditions within the chip. [23:6] Reserved. QSUM_SIGN Indicates the sign of the value contained in QSUM. 0 = positive value 1 = negative value Q2_SIGN Indicates the sign of the value contained in Q2 AVG. 0 = positive value 1 = negative value Q1_SIGN Indicates the sign of the value contained in Q1 AVG. 0 = positive value 1 = negative value PSUM_SIGN Indicates the sign of the value contained in P SUM. 0 = positive value 1 = negative value P2_SIGN Indicates the sign of the value contained in P2 AVG. 0 = positive value 1 = negative value P1_SIGN Indicates the sign of the value contained in P1 AVG. 0 = positive value 1 = negative value

6.6.17 Line to Sample Frequency Ratio (Epsilon) – Page 16, Address 49

Default = 0x01 999A (0.0125 or 50Hz/4.0kHz) Epsilon is the ratio of the input line frequency to the OWR. It can either be written by the application program or calculated automatically from the line frequency (from the voltage channel 1 input) using the AFC bit in the Config2 register. It is a two's complement value in the range of -1.0 value1.0, with the binary point to the right of the MSB. Negative values are not used. 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 76543210 - - QSUM_SIGN Q2_SIGN Q1_SIGN PSUM_SIGN P2_SIGN P1_SIGN MSB LSB

6.6.18 Automatic Channel Select Level (IchanLEVEL ) – Page 16, Address 50

Default = 0x82 8F5C (1.02 or 2% minimum difference) Sets the hysteresis level for automatic energy channel selection. The channel select level register sets the hysteresis level for automatic energy channel selection. If the most-positive value of P1 AVG and P2AVG (I1RMS and I2RMS) is greater than IchanLEVEL multiplied by the least-positive value, and is also greater than IchanMIN, the channel associated with the most-positive value will be used. If not, the previous channel selection will remain. The value in this register is an unsigned fixed-point value in the range of 0 value2.0, with the binary point to the right of the MSB. A value of 1.0 or less indicates no hysteresis will be used.

6.6.19 Current Channel Minimum Amplitude (PMIN (IRMSMIN)) – Page 16, Address 56

Default = 0x00 624D (0.003) Sets the minimum level for automatic energy channel selection. The PMIN (IRMSMIN) register sets the minimum level for automatic energy channel selection. If the most-pos- itive values of P1AVG (or I1RMS) register and P2AVG (or I2RMS) register is less than PMIN (IRMSMIN), the pre- vious channel selection will remain in use. It is a two's complement value in the range of -1.0 value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.20 No Load Threshold (LoadMIN) – Page 16, Address 58

Default = 0x00 0000 LoadMIN is used to set the no-load threshold for the anti-creep function. When the magnitudes of PSUM and QSUM are less than LoadMIN, PSUM and QSUM are forced to zero. When the magnitude of SSUM is less than LoadMIN, SSUM is forced to zero. LoadMIN is a two’s complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used. MSB LSB MSB LSB MSB LSB

50 DS980F3

6.6.21 Voltage Fixed RMS Reference (VFRMS) – Page 16, Address 59

Default = 0x5A 8279 (0.7071068) The VFRMS register contains the internal RMS reference used when voltage input tampering is detected by the application program. The application may choose to set the VFIX bit in the Config2 register to force full-scale energy accumulation at the VFRMS level. This register holds two's complement value in the range of 0.0  value <1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.22 Sample Count (SampleCount) – Page 16, Address 51

Default = 0x00 0FA0 (4000) Determines the number of OWR samples to use in calculating low-rate results. SampleCount (N) is an integer in the range of 100 to 8,388,607. Values less than 100 should not be used.

6.6.23 Cycle Count (CycleCount) – Page 18, Address 62

Default = 0x00 0064 (100) Determines the number of half-line cycles to use in calculating low-rate results when the CS5480 is in Line-cy- cle Synchronized Averaging mode. CycleCount is an integer in the range of 1 to 8,388,607. Zero should not be used.

6.6.24 Filter Settling Time for Conversion Startup (TSETTLE) – Page 16, Address 57

Default = 0x00 001E (30) Sets the number of OWR samples that will be used to allow filters to settle at the beginning of Conversion and Calibration commands. This is an integer in the range of 0 to 16,777,215 samples. MSB LSB MSB LSB MSB LSB MSB LSB

6.6.25 System Gain (SysGAIN) – Page 16, Address 60

Default = 0x50 0000 (1.25) System Gain (SysGAIN) is applied to all channels. By default, SysGAIN = 1.25, but can be finely adjusted to compensate for voltage reference error. It is a two's complement value in the range of -2.0value2.0, with the binary point to the right of the second MSB. Values should be kept within 5% of 1.25.

6.6.26 Rogowski Coil Integrator Gain (IntGAIN) – Page 18, Address 43

Default = 0x14 3958 Gain for the Rogowski coil integrator. This must be programmed accordingly for 50Hz and 60Hz (0.158 for 50Hz, 0.1875 for 60Hz). This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.27 System Time (Time) – Page 16, Address 61

Default = 0x00 0000 System Time (Time) is measured in OWR samples. This is an unsigned integer in the range of 0 to 16,777,215 samples. At OWR = 4.0kHz, OWR will overflow every 1 hour, 9 minutes, and 54 seconds. Time can be used by the application to manage real-time events.

6.6.28 Voltage 1 Sag Duration (V1SagDUR) – Page 17, Address 0

Default = 0x00 0000 Voltage 1 Sag Duration, V1SagDUR, determines the count of OWR samples utilized to determine a sag event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. MSB LSB MSB LSB MSB LSB MSB LSB

52 DS980F3

6.6.29 Voltage 1 Sag Level (V1SagLEVEL) – Page 17, Address 1

Default = 0x00 0000 Voltage 1 Sag Level, V1SagLEVEL, establishes a threshold at which a sag event is triggered. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.30 Current 1 Overcurrent Duration (I1OverDUR) – Page 17, Address 4

Default = 0x00 0000 Current 1 Overcurrent Duration, I1OverDUR, determines the count of OWR samples utilized to determine an overcurrent event. This integer is in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

6.6.31 Current 1 Overcurrent Level (I1OverLEVEL) – Page 17, Address 5

Default = 0x7F FFFF Current 1 Overcurrent Level, I1OverLEVEL, establishes a threshold at which an overcurrent event is triggered. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.32 Voltage 2 Sag Duration (V2SagDUR) – Page 17, Address 8

Default = 0x00 0000 Voltage 2 Sag Duration, V2SagDUR, determines the count of OWR samples utilized to determine a sag event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

6.6.33 Voltage 2 Sag Level (V2SagLEVEL) – Page 17, Address 9

Default = 0x00 0000 Voltage 2 Sag Level, V2SagLEVEL, establishes a threshold at which a sag event is triggered. This is a two’s complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

6.6.34 Current 2 Overcurrent Duration (I2OverDUR) – Page 17, Address 12

Default = 0x00 0000 Current 2 Overcurrent Duration, I2OverDUR, determines the count of OWR samples utilized to determine an overcurrent event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

6.6.35 Current 2 Overcurrent Level (I2OverLEVEL) – Page 17, Address 13

Default = 0x7F FFFF Current 2 Overcurrent Level, I2OverLEVEL, establishes a threshold at which an overcurrent event is triggered. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.36 Voltage 1 Swell Duration (V1SwellDUR) – Page 18, Address 46

Default = 0x00 0000 Voltage 1 Swell Duration, V1SwellDUR, determines the count of OWR samples utilized to determine a swell event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature.

6.6.37 Voltage 1 Swell Level (V1SwellLEVEL) – Page 18, Address 47

Default = 0x7F FFFF Voltage 1 Swell Level, V1SwellLEVEL, establishes a threshold at which a swell event is triggered. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.38 Voltage 2 Swell Duration (V2SwellDUR) – Page 18, Address 50

Default = 0x00 0000 Voltage 2 Swell Duration, V2SwellDUR, determines the count of OWR samples utilized to determine a swell event. These are integers in the range of 0 to 8,388,607 samples. A value of zero disables the feature. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

54 DS980F3

6.6.39 Voltage 2 Swell Level (V2SwellLEVEL) – Page 18, Address 51

Default = 0x7F FFFF Voltage 2 Swell Level, V2SwellLEVEL, establishes a threshold at which a swell event is triggered. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.40 Instantaneous Current 1 (I1) – Page 16, Address 2

Default = 0x00 0000 I1 contains instantaneous current measurements for current channel 1. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.41 Instantaneous Voltage 1 (V1) – Page 16, Address 3

Default = 0x00 0000 V1 contains instantaneous voltage measurements for voltage channel 1. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.42 Instantaneous Active Power 1 (P1) – Page 16, Address 4

Default = 0x00 0000 P1 contains instantaneous power measurements for current and voltage channels 1. Values in registers I1 and V1 are multiplied to generate this value. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.43 Active Power 1 (P1AVG) – Page 16, Address 5

Default = 0x00 0000 Instantaneous power is averaged over each low-rate interval (SampleCount samples) and then added with power offset (P1OFF) to compute active power (P1AVG). This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

6.6.44 RMS Current 1 (I1RMS) – Page 16, Address 6

Default = 0x00 0000 I1RMS contains the root mean square (RMS) values of I1, calculated during each low-rate interval. This is an unsigned value in the range of 0 value1.0, with the binary point to the left of the MSB.

6.6.45 RMS Voltage 1 (V1RMS) – Page 16, Address 7

Default = 0x00 0000 V1RMS contains the root mean square (RMS) value of V1, calculated during each low-rate interval. This is an unsigned value in the range of 0 value1.0, with the binary point to the left of the MSB.

6.6.46 Instantaneous Current 2 (I2) – Page 16, Address 8

Default = 0x00 0000 I2 contains instantaneous current measurements for current channel 2. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.47 Instantaneous Voltage 2 (V2) – Page 16, Address 9

Default = 0x00 0000 V2 contains instantaneous voltage measurements for voltage channel 1. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.48 Instantaneous Active Power 2 (P2) – Page 16, Address 10

Default = 0x00 0000 P2 contains instantaneous power measurements for current and voltage channels 2. Values in registers I2 and V are multiplied to generate this value. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

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6.6.49 Active Power 2 (P2AVG) – Page 16, Address 11

Default = 0x00 0000 Instantaneous power is averaged over each low-rate interval (SampleCount samples) to compute active pow- er (P2AVG). This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.50 RMS Current 2 (I2RMS) – Page 16, Address 12

Default = 0x00 0000 I2RMS contains the root mean square (RMS) value of I2, calculated during each low-rate interval. This is an unsigned value in the range of 0 value1.0, with the binary point to the left of the MSB.

6.6.51 RMS Voltage 2 (V2RMS) – Page 16, Address 13

Default = 0x00 0000 V2RMS contains the root mean square (RMS) value of V2, calculated during each low-rate interval. This is an unsigned value in the range of 0 value1.0, with the binary point to the left of the MSB.

6.6.52 Reactive Power 1 (Q1Avg) – Page 16, Address 14

Default = 0x00 0000 Reactive power 1 (Q1AVG) is Q1 averaged over each low-rate interval (SampleCount samples) and corrected by Q1OFF. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.53 Instantaneous Quadrature Power 1 (Q1) – Page 16, Address 15

Default = 0x00 0000 Instantaneous quadrature power, Q1, the product of V1 shifted 90 degrees and I1. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

6.6.54 Reactive Power 2 (Q2Avg) – Page 16, Address 16

Default = 0x00 0000 Reactive power 2 (Q2AVG) is Q2 averaged over each low-rate interval (SampleCount samples). This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.55 Instantaneous Quadrature Power 2 (Q2) – Page 16, Address 17

Default = 0x00 0000 Instantaneous quadrature power, Q2, the product of V2 shifted 90 degrees and I2. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.56 Peak Current 1 (I1PEAK) – Page 0, Address 37

Default = 0x00 0000 Peak Current 1 (I1PEAK) contains the value of the instantaneous current 1 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.57 Peak Voltage 1 (V1PEAK) – Page 0, Address 36

Default = 0x00 0000 Peak voltage 1 (V1PEAK) contains the value of the instantaneous voltage 1 sample with the greatest magni- tude detected during the last low-rate interval. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.58 Apparent Power 1 (S1) – Page 16, Address 20

Default = 0x00 0000 Apparent power 1 (S1) is the product of V1RMS and I1RMS or SQRT(P1AVG 2 + Q1AVG 2). This is an unsigned value in the range of 0 value1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

58 DS980F3

6.6.59 Power Factor 1 (PF1) – Page 16, Address 21

Default = 0x00 0000 Power factor 1 (PF1) is calculated by dividing active power 1 (P1AVG) by apparent power 1 (S1). The sign is determined by the active power (P1AVG) sign. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.60 Peak Current 2 (I2PEAK) – Page 0, Address 39

Default = 0x00 0000 Peak current, I2PEAK, contains the value of the instantaneous current 2 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.61 Peak Voltage 2 (V2PEAK) – Page 0, Address 38

Default = 0x00 0000 Peak voltage, V2PEAK, contains the value of the instantaneous voltage 2 sample with the greatest magnitude detected during the last low-rate interval. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.62 Apparent Power 2 (S2) – Page 16, Address 24

Default = 0x00 0000 Apparent power 2 (S2) is the product of V2RMS and I2RMS or SQRT(P2AVG 2 + Q2AVG 2). This is an unsigned value in the range of 0 value1.0, with the binary point to the right of the MSB.

6.6.63 Power Factor 2 (PF2) – Page 16, Address 25

Default = 0x00 0000 Power factor 2 (PF2) is calculated by dividing active power 2 (P2AVG) by apparent power 2 (S2). The sign is determined by the active power (P2AVG) sign. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

6.6.64 Temperature (T) – Page 16, Address 27

Default = 0x00 0000 T contains results from the on-chip temperature measurement. By default, T uses the Celsius scale, and is a two's complement value in the range of -128.0 value128.0 (°C), with the binary point to the right of bit 16. Negative values are not used. T can be rescaled by the application using the TGAIN and TOFF registers.

6.6.65 Total Active Power (PSUM) – Page 16, Address 29

Default = 0x00 0000 PSUM =P 1AVG+P2AVG if MCFG[1:0] = 01 PSUM =P 1AVG or P2AVG if MCFG[1:0] = 00 This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.66 Total Apparent Power (SSUM) – Page 16, Address 30

Default = 0x00 0000 SSUM = S1+S2 if MCFG[1:0] = 01 SSUM = S1 or S2 if MCFG[1:0] = 00 This is an unsigned value in the range of 0 value1.0, with the binary point to the right of the MSB.

6.6.67 Total Reactive Power (QSUM) – Page 16, Address 31

Default = 0x00 0000 QSUM =Q 1AVG+Q2AVG if MCFG[1:0] = 01 QSUM =Q 1AVG or Q2AVG if MCFG[1:0] = 00 This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB

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6.6.68 DC Offset for Current (I1DCOFF , I2DCOFF) – Page 16, Address 32, 39

Default = 0x00 0000 DC offset registers I1DCOFF and I2DCOFF are initialized to zero on reset. During DC offset calibration, selected registers are written with the inverse of the DC offset measured. The application program can also write the DC offset register values. These are two's complement values in the range of -1.0value1.0, with the binary point to the right of the MSB.

6.6.69 DC Offset for Voltage (V1DCOFF , V2DCOFF) – Page 16, Address 34, 41

Default = 0x00 0000 DC offset registers V1DCOFF and V2DCOFF are initialized to zero on reset. During DC offset calibration, select- ed registers are written with the inverse of the DC offset measured. The application program can also write the DC offset register values. These are two's complement values in the range of -1.0 value1.0, with the binary point to the right of the MSB.

6.6.70 Gain for Current (I1GAIN, I2GAIN) – Page 16, Address 33, 40

Default = 0x40 0000 (1.0) Gain registers I1GAIN and I2GAIN are initialized to 1.0 on reset. During gain calibration, selected registers are written with the multiplicative inverse of the gain measured. These are unsigned, fixed-point values in the range of 0value4.0, with the binary point to the right of the second MSB.

6.6.71 Gain for Voltage (V1GAIN, V2GAIN) – Page 16, Address 35, 42

Default = 0x40 0000 (1.0) Gain registers V1GAIN and V2GAIN are initialized to 1.0 on reset. During gain calibration, selected register are written with the multiplicative inverse of the gain measured. These are unsigned fixed-point values in the range of 0value4.0, with the binary point to the right of the second MSB.

6.6.72 Average Active Power Offset (P1OFF, P2OFF) – Page 16, Address 36, 43

Default = 0x00 0000 Average Active Power offset P1OFF (P2OFF) is added to averaged power to yield P1AVG (P2AVG) register re- sults. It can be used to reduce systematic energy errors. These are two's complement values in the range of -1.0value 1.0, with the binary point to the right of the MSB. MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

6.6.73 Average Reactive Power Offset (Q1OFF , Q2OFF) – Page 16, Address 38, 45

Default = 0x00 0000 Average Reactive Power Offset (Q1OFF , Q2OFF) is added to averaged reactive power to yield Q1AVG (Q2AVG) register results. It can be used to reduce systematic energy errors. These are two's complement val- ues in the range of -1.0value 1.0, with the binary point to the right of the MSB.

6.6.74 AC Offset for Current (I1ACOFF, I2ACOFF ) – Page 16, Address 37, 44

Default = 0x00 0000 AC offset registers I1ACOFF and I2ACOFF are initialized to zero on reset. They are used to reduce systematic errors in the RMS results. These are unsigned values in the range of 0  value  1.0, with the binary point to the left of the MSB.

6.6.75 Temperature Gain (TGAIN) – Page 16, Address 54

Default = 0x 06 B716 Register TGAIN is used to scale the Temperature register (T), and is an unsigned fixed-point value in the range of 0.0value256.0, with the binary point to the right of bit 16. Register T can be rescaled by the application using the TGAIN and TOFF registers. Refer to section 7.3 Tem- perature Sensor Calibration on page 65 for more information.

6.6.76 Temperature Offset (TOFF) – Page 16, Address 55

Default = 0x D5 3998 Register TOFF is used to offset the Temperature register (T), and is a two's complement value in the range of -128.0value128.0 (°C), with the binary point to the right of bit 16. Register T can be rescaled by the application using the TGAIN and TOFF registers. Refer to section 7.3 Tem- perature Sensor Calibration on page 65 for more information. MSB LSB MSB LSB MSB LSB MSB LSB

62 DS980F3

6.6.77 Calibration Scale (Scale) – Page18, Address 63

Default = 0x4C CCCC (0.6) The Scale register is used in the gain calibration to set the level of calibrated results of I-channel RMS. During gain calibration, the IxRMS results register is divided into the Scale register. The quotient is put into the IxGAIN register. This is a two's complement value in the range of -1.0value1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.78 V-channel Zero-crossing Threshold (VZXLEVEL) – Page 18, Address 58

Default = 0x10 0000 (0.125) VZXLEVEL is the level that the peak instantaneous voltage must exceed for the zero-crossing detection to function. This is a two's complement value in the range of -1.0value<1.0, with the binary point to the right of the MSB. Negative values are not used.

6.6.79 I-channel Zero-crossing Threshold (IZXLEVEL) – Page 18, Address 24

Default = 0x10 0000 (0.125) IZXLEVEL is the level that the peak instantaneous current must exceed for the zero-crossing detection to func- tion. This is a two's complement value in the range of -1.0value<1.0, with the binary point to the right of the MSB. Negative values are not used. MSB LSB MSB LSB MSB LSB

measurements over the full load range.

7.1 Calibration in General

can be applied to the current RMS calculation. The data flow of the calibration is shown in Figure 25. the results of the RMS current calculation. the accuracy of calibration results tends to increase.

7.1.1 Offset Calibration

inputs IIN1± (IIN2±) of the CS5480 should be 0V.

7.1.1.1 DC Offset Calibration

subsequent conversions, removing the offset. will be removed by the high-pass filter.

7.1.1.2 Current Channel AC Offset Calibration

Figure 25. Calibration Data Flow

64 DS980F3

The AC offset register for the channel being calibrated should first be cleared prior to performing the calibration. The high-pass filter should be enabled if AC offset calibration is used. It is recommended that T SETTLE be set to 2000ms before performing an AC offset calibration. Note that the AC offset register holds the square of RMS value measured during calibration. Therefore, it can hold a maximum RMS noise of . This is the maximum RMS noise that AC offset correction can remove.

7.1.2 Gain Calibration

Prior to executing the gain calibration command, gain registers for any path to be calibrated ( Vx GAIN, IxGAIN) should be set to 1.0, and TSETTLE should be set to 2000 ms. For gain calibration, a reference signal must be applied to the meter. Du ring gain calibration, the voltage RMS result register (Vx RMS) is divided into 0.6, and the current RMS result register ( IxRMS) is divided into the Scale register. The quotient is put into the associated gain register. The gain calibration algorithm attempts to adjust the gain register ( Vx GAIN, IxGAIN) such that the voltage RMS result register ( VxRMS) equals 0.6, and the current RMS result register ( IxRMS) equal the Scale register. Note that for the gain calibration, there are some limitations on choosing the reference level and the Scale register value. Using a reference or a scale that is too large or too small can cause register overflow during calibration or later during normal operation. Either condition can set Status register bits I1OR (I2OR), or VOR. The maximum value that the gain register can attain is four. Using inappr opriate reference levels or scale values may also cause the CS5480 to attempt to set the gain register higher than four, therefore the gain calibration result will be invalid. The Scale register is 0.6 by default. The maximum voltage (U MAX Volts) and current (I MAX Amps) of the meter should be used as the reference signal level if the Scale register is 0.6. After gain calibration, 0.6 of the Vx RMS ( IxRMS) register represents U MAX Volts (I MAX Amps) for the line voltage (load current); 0.36 of the PAVG, QAVG, or Sx register represents U MAX×IMAX Watts, Vars, or VAs for the active, reactive, or apparent power. If the calibration is performed with U MAX Volts and ICAL Amps and I CAL<IMAX, the Scale register needs to be scaled down to 0.6×I CAL/IMAX before performing gain calibration. After gain calibration, 0.6 of the VxRMS register represents U MAX Volts, 0.6 x I CAL/IMAX of the IxRMS register represents I CAL Amps, and 0.36 × ICAL/IMAX of the PxAVG, QxAVG, or Sx register represents UMAX xI CAL Watts, Vars, or VAs.

7.1.3 Calibration Order

1) If the HPF option is enabled, then any DC compo- nent that may be present in the selected signal chan- nel will be removed, and a DC offset calibration is not required. However, if the HPF option is disabled, the DC offset calibration should be performed. When using high-pass filters, it is recommended that the DC offset register for the corresponding channel be set to 0. Before performing DC offset calibration, the DC offset register should be set to zero, and the corresponding gain register should be set to one. 2) If there is an AC offset in the Ix RMS calculation, the AC offset calibration should be performed on the cur- rent channel. Before performing AC offset calibra- tion, the AC offset register should be set to zero. It is recommended that T SETTLE be set to 2000ms before performing an AC offset calibration. 3) Perform the gain calibration. 4) If an AC offset calibration was performed (step 2), then the AC offset may need to be adjusted to com- pensate for the change in gain (step 3). This can be accomplished by restoring zero to the AC offset reg- ister and then perform an AC offset calibration. The adjustment could also be done by multiplying the AC offset register value that was calculated in step 2 by the gain calculated in step 3 and updating the AC off- set register with the product.

7.2 Phase Compensation

A phase compensation mechanism is provided to adjust for meter-to-meter variation in signal path delays. Phase offset between a voltage channel and its corresponding current channel can be calculated by using the power factor ( PF1, PF2 ) register after a conversion. 1) Apply a reference voltage and current with a lagging power factor to the meter. The reference current waveform should lag the voltage with a 60° phase shift. 2) Start continuous conversion. 3) Accumulate multiple readings of the PF1 or PF2 register. 4) Calculate the average power factor, PF avg. 5) Calculate phase offset = arccos(PF avg) - 60°. 0xFFFFFF

• The phase offset is more than 1 output word rate (OWR) sample.
• More delay is needed on the voltage channel. The compensation resolution is 0.008789° at 50Hz and 0.010547° at 60Hz at an OWR of 4000Hz.

7.3 Temperature Sensor Calibration

7.3.1 Temperature Offset and Gain Calibration

and intercept (b) can be obtained. Figure 26. T Register vs. Force Temp

66 DS980F3

1. BASIC APPLICATION CIRCUITS

1 Voltage and 2 Current

Figure 27. Typical Single-phase 3-Wire Connection

1 Voltage, 1 Line Current,

Figure 28. Typical Single-phase 2-Wire Connection

68 DS980F3

1. PACKAGE DIMENSIONS mm inch Dimension MIN NOM MAX MIN NOM MAX A3 0.20 REF 0.008 REF D 4.00 BSC 0.157 BSC e 0.50 BSC 0.020 BSC E 4.00 BSC 0.157 BSC aaa 0.15 0.006 bbb 0.10 0.004 ddd 0.05 0.002 eee 0.08 0.003

24 QFN (4mmX4mm BODY with EXPOSED PAD) PACKAGE DRAWING

Notes: 1. Controlling dimensions are in millimeters. 2. Dimensions and tolerances per ASME Y14.5M. 3. This drawing conforms to JE DEC outline MO-220, variation VGGD-6 with the exception of fea- tures D2 and E2, which are per supplier designations. 4. Recommended reflow profile is per JEDEC/IPC J-STD-020.

1. ORDERING INFORMATION 11. ENVIRONMENTAL, MANUFACTURING, AND HANDLING INFORMATION * MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD-020. 12. REVISION HISTORY Ordering Number Container Temperature Package CS5480-INZ Bulk -40 to +85 °C 24-pin QFN, Lead (Pb) Free CS5480-INZR Tape & Reel Part Number Peak Reflow Temp MSL Rating* Max Floor Life CS5480-INZ 260 °C 3 7 Days Revision Date Changes PP1 APR 2012 Preliminary release. F1 APR 2012 Edited for content and clarity. F2 JUN 2012 Updated ordering information. F3 MAR 2013 Clarified context.

70 DS980F3

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